JP4655257B2 - 2-terminal pair isolator - Google Patents

2-terminal pair isolator Download PDF

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JP4655257B2
JP4655257B2 JP2001233692A JP2001233692A JP4655257B2 JP 4655257 B2 JP4655257 B2 JP 4655257B2 JP 2001233692 A JP2001233692 A JP 2001233692A JP 2001233692 A JP2001233692 A JP 2001233692A JP 4655257 B2 JP4655257 B2 JP 4655257B2
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degrees
terminal pair
input
center
isolator
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JP2003046307A (en
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茂 武田
行範 有田
紳一朗 竹内
靖 岸本
伸二 山本
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Hitachi Metals Ltd
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Hitachi Metals Ltd
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Priority to JP2001233692A priority Critical patent/JP4655257B2/en
Priority to EP02007190A priority patent/EP1246292A3/en
Priority to US10/108,360 priority patent/US6940360B2/en
Priority to KR1020020017614A priority patent/KR100862962B1/en
Priority to CNB021272492A priority patent/CN1301567C/en
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【0001】
【発明の属する技術分野】
本発明は、高周波用アイソレータ、特に逆方向損失及び挿入損失が広帯域特性を有する2端子対アイソレータの分野に関するものである。
【0002】
【従来の技術】
現在の高周波用アイソレータの技術状況としては、3端子対接合型サーキュレータの一つの端子を整合インピーダンスで終端したものが一般的である。この接合型サーキュレータは、2種類の形式、すなわち分布定数型サーキュレータと集中定数型サーキュレータに分類される。サーキュレータは電気的特性が非可逆的であり、その構造はフェライト薄板に垂直に磁界を印加して、このフェライト薄板の中心近傍に導体を近接したものを基本としている。前者の分布定数型はフェライト薄板の寸法が、取り扱っているフェライト薄板中を伝わる高周波の波長の1/4以上の場合に、後者の集中定数型は1/8以下の場合にそれぞれ使い分けられる。当然のことながら、集中定数型の方が小型化に適する。
【0003】
図8に、3端子対集中定数型サーキュレータの原理を利用した、現在携帯電話等で用いられているアイソレータの概略構造図と概略回路図を示す。フェライト薄板Gはガーネット型フェライトよりなり、この上面に3本の中心導体L1、L2、L3が120度の角度間隔で配されている。それぞれの中心導体の一端は端子対▲1▼▲2▼▲3▼の入出力線路となり、他端は地導体となる共通部GRに接続される。整合用コンデンサーC1、C2、C3がそれぞれ中心導体L1、L2、L3の一端と共通部GRの間に並列接続される。また、アイソレータを実現するためエネルギー吸収用抵抗素子Rが端子対▲3▼と共通部GRの間に取り付けられている。フェライト薄板Gの主面にほぼ垂直な静磁界が印加されるように永久磁石が装荷されているが、図面では省略してある。静磁界の方向と強さ、および中心導体L1、L2、L3の形状と大きさと、三つの整合用コンデンサーC1、C2、C3の静電容量を慎重に調整することにより、図8の構造で所望の周波数fo(以後中心周波数という)でサーキュレータとして動作する。すなわち、端子対▲1▼から入力した高周波は端子対▲2▼に、端子対▲2▼から入った高周波は端子対▲3▼に少ない損失で伝わる。反対方向には伝わらない。端子対▲3▼に抵抗素子Rが接続されているとそこでほとんどのエネルギーが吸収され、端子対▲2▼から端子対▲1▼に高周波はほとんど伝播しない状態が実現する。すなわち一方向のみの伝播を助け、逆方向のそれは阻止する素子であるアイソレータを実現できる。
この様な図8の構造を有するアイソレータは挿入損失が小さく、その帯域幅も広いという利点を持っていたが、部品点数が多く、薄型化、小型化には限界があるという欠点を持っていた。
【0004】
また他の例として、図7に示すような2端子対集中定数型アイソレータ(特開昭52-134349号、特開昭53-129561号)がある。この2端子対集中定数型アイソレータは、直交している2本の中心導体L1、L2しか必要なく、また、整合用コンデンサーもC1、C2の二つでよく、極めて簡単な構造を有する。また、この構造は、2本の中心導体が直交していることから、中心周波数近傍(これを帯域内と呼ぶことにする)から離れて、すなわち帯域外で正しいアイソレータ動作が成立しなくなっても、高い減衰量が得られるという利点があると指摘されていた。本構造の大きな特徴は、エネルギー吸収用抵抗素子Rの二つの端子が、中心導体L1、L2の一端にそれぞれ接続されていることである。中心導体L1、L2の他端は地導体である共通部GRに接続されている。この構造は、図8の構造と比較して分かるように、中心導体の数が1本、整合用コンデンサーが1個、少ないことが特徴であり、高周波アイソレータの小型化、薄型化にとっては極めて好都合である。
【0005】
【発明が解決しようとする課題】
しかし、図7に示した2端子対集中定数型アイソレータの構造は、これまで本格的に実用化されることはなかった。その理由は、確かに逆方向損失の帯域幅が広いということはあるが、挿入損失の帯域幅が狭いという欠点を有していたからである。それに伴い挿入損失そのものの値が、図8の3端子対アイソレータの構造に比較して、それほど小さくならないということである。
一つの例として、前記帯域幅を広げようとする場合には、静磁界を弱くすることにより、規格化動作磁界σ(後述)を小さくすることが考えられる。しかしながら、このようにすると、磁気的損失が大きくなり、その結果挿入損失の増大を招く。また、3端子対サーキュレータのようにその動作原理がそれほど細かく検討されていなかったというのも一つの理由である。
【0006】
そこで本発明の発明者等は、図7の2端子対集中定数型アイソレータの回路解析ができる独自の回路シミュレータを開発し、それに基づきいろいろな基本的知見を得ることができた。以下、回路解析に基づき、図7の2端子対集中定数型アイソレータの動作原理について簡単に述べる。
端子対▲1▼から入った高周波は中心導体L1に電流を流し、フェライト薄板Gを励起する。フェライト薄板Gは永久磁石でその主面方向に磁化されており、直交している中心導体L2に結合する高周波磁界成分が発生する。これは、マイクロ波帯におけるフェライトの強磁性共鳴効果によるものである。この効果がなければ、中心導体L2にエネルギーが伝播することはない。整合用コンデンサーC1、C2は中心導体L1、L2とそれぞれペアとなって中心周波数foで共振する並列共振回路を構成している。ここで注目すべきことは、伝播する場合の位相変化である。すなわち、端子対▲1▼から端子対▲2▼にエネルギーが伝わる場合、入出力間の位相差は0度であり、入力と出力で振幅が同じであれば、抵抗素子Rに電流は流れない。逆に端子対▲2▼から端子対▲1▼にエネルギーが伝わる場合は、その位相差はちょうど180度となる。このときには抵抗素子Rに大きな電流が流れ、エネルギーが抵抗素子で消費される。すなわち、端子対▲2▼から端子対▲1▼にはエネルギーが伝わりにくくなるのである。
【0007】
しかし、この現象は理想的な場合である。実際には、第1と第2の中心導体間の線間容量が存在するし、また、抵抗素子と直列に寄生インダクタンスが存在する。このような寄生素子が存在した場合には、上に述べたような動作は期待できない。そこで、本発明者等は、第1の中心導体L1の中心軸と、第2の中心導体L2の中心軸とが交差してなす交差角度φを変化させた場合に、これらの線間容量や寄生インダクタンスを補償する方法を独自開発の回路シミュレータで検討した。本件については米国特許(US patent 4,210,886)ですでに論じられている。しかし、その理論的背景が不明確であり、到達した結論が必ずしも実用性を加味して、最適角度を求めたものではなかった。
そこで本発明は、独自開発した回路シミュレータにより、2端子対集中定数型アイソレータの回路特性を詳細に再吟味することにより、第1の中心導体L1と第2の中心導体L2の交差角度φと、更には第1の中心導体L1と第2の中心導体L2の間に接続される付属回路(例えば図4の回路の場合はCw)の最適条件を求め、構造が簡単で、小型・薄型化であるだけでなく、挿入損失の帯域幅が広帯域である低損失な極めて実用上有効な2端子対アイソレータを提供することを目的としている。
【0008】
【課題を解決するための手段】
本発明は、第1、第2の中心導体を互いに電気的に絶縁状態で交差するように、静磁界が印加されたフェライトの中央近傍に配接する2端子対アイソレータであって、前記第1、第2の中心導体の一端はそれぞれ第1、第2の入出力端子となり、他端は共通部に接続され、前記第1の入出力端子と前記共通部の間には第1の整合用コンデンサーが接続され、前記第2の入出力端子と前記共通端子の間には第2の整合用コンデンサーが接続され、前記第1、第2の入出力端子間に抵抗素子が接続され、前記第1の中心導体の中心軸と前記第2の中心導体の中心軸との交差角度が40度から80度の範囲にある2端子対アイソレータである。
本発明においては、前記抵抗素子と並列に第3のコンデンサーを接続するのが好ましい。また、前記第3のコンデンサーの静電容量は前記第1の整合用コンデンサー、及び第2の整合用コンデンサーの静電容量よりも小さい。
本発明において、前記抵抗素子と並列にインダクターを接続するのも好ましい。また、本発明において、前記抵抗素子と直列にインダクターを接続するもの好ましい。そして、本発明の2端子対アイソレータの前記共通部は地導体に接続される。
【0009】
【発明の実施の形態】
以下本発明の形態について添付図面に基づいて説明する。図4は本発明の基本となった2端子対アイソレータの等価回路図である。図7に示した従来技術の2端子対アイソレータと異なる点は、第1、第2に中心導体の交差角度が変化できること、その交差角度φの効果を補償するために新たに、抵抗素子Rと並列に第3のコンデンサーCwを接続したことである。
図1(a),(b),(c)は、中心周波数foを1000[MHz]とし、図4の等価回路が理想的な回路であると仮定して、独自に開発した回路シミュレータを用いて計算した、2端子対アイソレータのSパラメータの周波数特性を示す。ここでいう理想的な回路とは、二つの中心導体L1,L2の間の結合が完全であることを意味している。図中には、三つの代表的角度φ=60[度]、φ=90[度]、φ=120[度]についての計算結果を示す。このときに用いたパラメータは、特性インピーダンスZo=50[Ω]、空芯インダクタンスK=1[nH]、フェライト薄板の飽和磁化4πMs=900[G]、抵抗素子の抵抗値がR=50[Ω]である。また、計算した周波数範囲は、中心周波数foに対して±10%の900[MHz]〜1100[MHz]とした。
【0010】
付属回路素子である第3のコンデンサーCwは、従来技術のφ=90[度]では、当然Cw=0である。φ=60[度]とすると、Cw=7.85[pF]となり、φ=120[度]では、Cw=−7.85[pF]となった。Cwがマイナスということは、この部分がコンデンサーではなく、インダクターであることを意味する。この点については、後で詳細に説明する。
【0011】
図1(a)は、反射損失S11の周波数特性を示す。この図から分かるように、φ=90[度]を基準にして、これよりφが小さい場合は反射損失S11の帯域幅が広がり、φがこれより大きくなると急速に帯域幅が狭くなる。ここで、S11が20[dB]を切る周波数幅を中心周波数foで割り算した値を、比帯域幅W(S11)[%]で表す。
図1(b)は、挿入損失S21の周波数特性を示す。この図から分かるように、φ=90[度]を基準にして、これよりφが小さい場合はS21の帯域幅が広がり、φがこれより大きくなると急速に帯域幅が狭くなる。ここで、900[MHz]での反射損失S11の値を挿入損失の帯域幅に関係すると考えて、IL[dB](at 0.9fo)として定義する。図中△印で示した。ILが小さいということは挿入損失の帯域幅が広いことに相当し、逆は大きいことは狭いことに相当する。
以上、図1(a),(b)において、φ=60[度]で反射損失と挿入損失の帯域幅が広がるという結果が本発明の着眼点である。
図1(c)は、同じ条件で計算した逆方向損失の周波数特性を示す。φ=90[度]のときは、図示された0.9fo〜1.1fo(900MHz〜1100MHz)の周波数範囲内では、45[dB]以上という高い逆方向損失特性を示すが、φがこれより大きくなっても小さくなっても逆方向損失は劣化する。特にφがφ=90[度]より小さい場合にその劣化の程度が大きくなる。ここで、逆方向損失の帯域幅に関係する量IS[dB](at 0.96fo)を定義する。すなわちこれは、0.96fo(図では960MHz)での逆方向損失の値である。図中△印で示した。ISが大きいということは逆方向損失の帯域幅が広いことに相当し、逆は小さいことは狭いことに相当する。
【0012】
図2は、本発明の原理と範囲を示すために、二つの中心導体の交差角度φを40[度]〜140[度]の広い範囲で変化させた場合の、各付属パラメータの変化を示す。ここで第1の整合用コンデンサーと第2の整合用コンデンサーの値は同じとし、C(=C1=C2)で表している。φが90[度]より小さい場合は、第3のコンデンサーCwが次第に増加してゆく。丁度φ=60[度]なると、第3のコンデンサーCwと第1の整合用コンデンサーと第2の整合用コンデンサーCは一致し、両方とも7.85[pF]となる。Cは減少傾向にあるが60[度]以下ではほぼ一定となる。抵抗素子Rは50[Ω]と一定である。
逆に、φが90[度]より大きい場合は、第1、第2の整合用コンデンサーCの容量はφが大きくなると急速に大きくなる。一方、第3のコンデンサーCwはマイナスとなり、その絶対値はφが大きくなるにつれて大きくなる。これは図中細かい点線で示されている。Cwの絶対値の曲線は、φ=90[度]を中心に左右対称となる。実際にマイナスの容量を持つコンデンサーが存在しないので、これは等価的にインダクターLpとして表示することができる。この場合の等価回路を図5に示した。
すなわちφが90[度]より大きい場合は、抵抗素子Rに並列にインダクターLpが必要となる。しかし、この等価回路は余り実際的ではない。というのは、実用的には90[度]付近の振る舞いが重要であるので、この部分を詳細に論じたいのであるが、φ=90[度]でLpは無限大となるからである。これを避けるためには、図6のように、抵抗素子Rsに直列にインダクターLsを挿入した回路が実際的である。なぜなら、φを大きい状態から90[度]に近づけていった場合、Ls=0[nH]、Rs=50[Ω]に漸近するので、連続性があるからである。
【0013】
図2の右半分のグラフに、φ>90[度]でのLsとRsの変化を示す。φが大きくなるにつれて、Rsは急激にゼロに近づくが、Lsは115[度]で最大値をとる。それよりも角度が大きくなると次第にLsは単調に減少してゆく。
図3は、上述の条件のもとで計算した、アイソレータ特性の角度依存性を示す。挿入損失S11の帯域幅を示すIL(at 0.9fo)は、φが90[度]より小さくなると減少し、φ=60[度]で最小値をとる。逆に、90[度]より大きくなると、IL(at 0.9fo)は急速に大きくなる。また、静磁界の強さを示す規格化動作磁界σは、90[度]で最小となり、これより角度が大きくとも小さくとも大きくなる。ここで、規格化動作磁界σとは、フェライト薄板の内部磁界Hiを、中心周波数foでの強磁性共鳴磁界Hres(=2πfo/γ)で割り算したもので、無次元数である。γは磁気回転率と呼ばれる定数である。また、反射損失S11が20[dB]を切る帯域幅W(S11)は、φが小さくなると大きくなり、約φ=60[度]で最大値7.6[%]をとる。φが90[度]より大きくなると、W(S11)は単調に減少してゆく。
【0014】
一方、逆方向損失の帯域幅を示すIS(at 0.96fo)は、φ=90[度]で55dBという最大値を示し、これより角度が大きくとも小さくとも減少してゆく。特に、φ<90[度]では単調に減少し、φ=40[度]で10[dB]を切るようになる。一方、φ>90[度]では、減少はするものの、30[dB]程度の高い減衰量を示す。
さて、第3図、第4図から実用上有効な結果をまとめると次のようになる。
(1)低挿入損失を重視する場合は、φ<90[度]の範囲が望ましい。
(2)逆方向損失を重視する場合は、φ=90[度]が望ましい。
(3)挿入損失の帯域幅及び反射損失の帯域幅が一番広くなるのは約φ=60[度]である。
(4)実上用許容できるIS(at 0.96fo)=10[dB]を切るのは、φが40[度]以下の場合である。
【0015】
次に、上記の結果から本発明の請求範囲を規定する考え方について述べたい。
すなわち、本発明者はφ=60[度]において、極めて挿入損失の帯域幅が広くなり、かつ逆方向損失も充分実用的であることを始めて理論的に明らかにした。本発明の基本となる考え方は単にφ=60[度]だけにとどまるものではない。すなわち、逆方向損失の帯域幅を示すIS(at 0.96fo)が10dBを切る40[度]においても本発明の趣旨は変わらない。ただし、これよりφが小さくなるとIS(at 0.96fo)が小さくなりすぎ実用に耐えなくなる。このことから、φ=40[度]を本発明の請求範囲の下限と規定した。また、φ=80[度]では、従来技術のφ=90[度]に比較すると、挿入損失の帯域幅IL(at 0.9fo)および反射損失の帯域幅W(S11)がかなり改善されている。したがって、φ=80[度]においても本発明の趣旨が充分に生きている。ただし、これよりφが大きくなると、IS(at 0.96fo)が増加し、従来技術との差異が不明確となる。このことから、φ=80[度]を本発明の上限と規定した。
【0016】
さて、本発明の基本となった図4の等価回路には、明確に第3のコンデンサーCwが記載されている。ここで、第3のコンデンサーCwは、第1,第2の中心導体の交差確度φ=40[度]では、Cwの容量はCよりかなり大きいものが必要であり、φ=80[度]では、Cwはかなり小さいものでよい。
また、このCwは必ずしも必要でないときがある。というのは、二つの中心導体L1,L2はフェライト薄板Gの中心近傍で交差しており、その際、薄い絶縁シートで電気的に絶縁されている。実際にはその間に線間容量が存在する。この線間容量は等価回路的には図4のCwと全く同じように動作するからである。この線間容量を巧みに利用すれば第3のコンデンサーCwがなくとも本発明の効果は実現できる。
この線間容量の存在により、第3のコンデンサーCwは第1、第2のコンデンサーCより実用上は小さいことが多い。
またこの線間容量が大きすぎ、角度φの効果を補償するために必要なCwの量を超えてしまう場合もある。この行き過ぎを補償するために、抵抗素子Rに並列にインダクターLpを接続すればよい。
抵抗素子Rとそれに並列接続されるインダクターLpの回路は、抵抗素子Rsと直列インダクターLsでも代替できる。
【0017】
【発明の効果】
以上の説明から明らかなように、本発明の2端子対アイソレータによれば、2本の中心導体のみの構成で構造が簡単で、小型・薄型化であるだけでなく、挿入損失の帯域幅が広帯域である低損失な2端子対アイソレータを提供できる。
【図面の簡単な説明】
【図1】 (a)本発明の効果を示す2端子対アイソレータの反射損失の周波数特性図、 (b)本発明の効果を示す2端子対アイソレータの挿入損失の周波数特性図、 (c)本発明の効果を示す2端子対アイソレータの逆方向損失の周波数特性図。
【図2】本発明の効果を実現するための、2端子対アイソレータの付属回路パラメータの角度依存性。
【図3】本発明の効果を説明するための2端子対アイソレータ特性の角度依存性。
【図4】本発明の対象とした2端子対アイソレータの等価回路。
【図5】本発明の効果を説明する2端子対アイソレータの等価回路。
【図6】本発明の効果を説明する2端子対アイソレータの等価回路。
【図7】従来技術の2端子対アイソレータの等価回路。
【図8】従来技術の3端子対サーキュレータに基づいたアイソレータの等価回路。
【符号の説明】
▲1▼▲2▼▲3▼ 入出力端子対
C1,C2,C3 整合用コンデンサー
G フェライト薄板
L1,L2,L3 中心導体
GR 地導体
R 抵抗素子
φ 第1の中心導体と第2の中心導体の交差角度
Cw 並列コンデンサー
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to the field of high-frequency isolators, particularly two-terminal pair isolators that have wideband characteristics of reverse loss and insertion loss.
[0002]
[Prior art]
As a current technical situation of high-frequency isolators, one terminal of a three-terminal pair junction circulator is generally terminated with a matching impedance. This junction type circulator is classified into two types, that is, a distributed constant type circulator and a lumped constant type circulator. The circulator has an irreversible electrical characteristic, and its structure is based on a structure in which a magnetic field is applied perpendicularly to the ferrite thin plate and a conductor is close to the center of the ferrite thin plate. The former distributed constant type is selectively used when the size of the ferrite thin plate is ¼ or more of the wavelength of the high frequency transmitted through the handled ferrite thin plate, and the latter lumped constant type is used when the size is 1/8 or less. As a matter of course, the lumped constant type is more suitable for downsizing.
[0003]
FIG. 8 shows a schematic structure diagram and a schematic circuit diagram of an isolator that is currently used in a mobile phone or the like using the principle of a three-terminal pair lumped constant type circulator. The ferrite thin plate G is made of garnet-type ferrite, and three central conductors L1, L2, and L3 are arranged on the upper surface at an angular interval of 120 degrees. One end of each center conductor is an input / output line of the terminal pair (1), (2), and (3), and the other end is connected to a common portion GR that is a ground conductor. Matching capacitors C1, C2, and C3 are connected in parallel between one end of each of the central conductors L1, L2, and L3 and the common portion GR. In order to realize an isolator, an energy absorbing resistor element R is attached between the terminal pair (3) and the common part GR. A permanent magnet is loaded so that a static magnetic field substantially perpendicular to the main surface of the ferrite thin plate G is applied, but it is omitted in the drawing. The structure shown in FIG. 8 is desired by carefully adjusting the direction and strength of the static magnetic field, the shape and size of the center conductors L1, L2, and L3, and the capacitance of the three matching capacitors C1, C2, and C3. Operates as a circulator at a frequency fo (hereinafter referred to as a center frequency). That is, the high frequency input from the terminal pair (1) is transmitted to the terminal pair (2), and the high frequency input from the terminal pair (2) is transmitted to the terminal pair (3) with little loss. It is not transmitted in the opposite direction. When the resistance element R is connected to the terminal pair {circle around (3)}, most energy is absorbed there, and a state is realized in which almost no high frequency propagates from the terminal pair {circle around (2)} to the terminal pair {circle around (1)}. That is, it is possible to realize an isolator which is an element that helps propagation in one direction and blocks it in the opposite direction.
The isolator having the structure shown in FIG. 8 has the advantage that the insertion loss is small and the bandwidth is wide. However, the isolator has the disadvantages that the number of parts is large and there is a limit to the reduction in thickness and size. .
[0004]
As another example, there are two-terminal pair lumped constant type isolators (Japanese Patent Laid-Open Nos. 52-134349 and 53-129561) as shown in FIG. This two-terminal-pair lumped constant type isolator requires only two center conductors L1 and L2 that are orthogonal to each other, and the matching capacitors need only be C1 and C2, and has a very simple structure. In addition, since the two central conductors are orthogonal to each other in this structure, even if the correct isolator operation is not established away from the vicinity of the center frequency (this will be referred to as in-band), that is, out of the band. It has been pointed out that there is an advantage that high attenuation can be obtained. A major feature of this structure is that the two terminals of the energy absorbing resistance element R are connected to one ends of the central conductors L1 and L2, respectively. The other ends of the center conductors L1 and L2 are connected to a common portion GR that is a ground conductor. As can be seen from the structure shown in FIG. 8, this structure is characterized by one central conductor and one matching capacitor, which is extremely convenient for miniaturization and thinning of high-frequency isolators. It is.
[0005]
[Problems to be solved by the invention]
However, the structure of the two-terminal-pair lumped constant isolator shown in FIG. 7 has not been put into practical use until now. The reason is that although the bandwidth of reverse loss is certainly wide, it has the disadvantage that the bandwidth of insertion loss is narrow. Accordingly, the value of the insertion loss itself is not so small as compared with the structure of the three-terminal pair isolator in FIG.
As one example, when trying to widen the bandwidth, it is conceivable to reduce the normalized operating magnetic field σ (described later) by weakening the static magnetic field. However, this increases the magnetic loss, resulting in an increase in insertion loss. Another reason is that the operating principle has not been studied so finely as in the case of a three-terminal pair circulator.
[0006]
Thus, the inventors of the present invention have developed an original circuit simulator capable of analyzing the circuit of the two-terminal pair lumped constant isolator shown in FIG. 7, and have obtained various basic knowledge based on the circuit simulator. The operation principle of the two-terminal pair lumped constant isolator shown in FIG. 7 is briefly described below based on circuit analysis.
The high frequency entered from the terminal pair (1) causes a current to flow through the central conductor L1 and excites the ferrite thin plate G. The ferrite thin plate G is a permanent magnet that is magnetized in the direction of its main surface, and generates a high-frequency magnetic field component that is coupled to the orthogonal central conductor L2. This is due to the ferromagnetic resonance effect of ferrite in the microwave band. Without this effect, energy will not propagate to the center conductor L2. The matching capacitors C1 and C2 constitute a parallel resonance circuit that resonates at the center frequency fo in pairs with the center conductors L1 and L2. What should be noted here is a phase change in the case of propagation. That is, when energy is transmitted from the terminal pair (1) to the terminal pair (2), the phase difference between the input and output is 0 degree, and if the amplitude is the same at the input and output, no current flows through the resistance element R. . Conversely, when energy is transmitted from the terminal pair (2) to the terminal pair (1), the phase difference is exactly 180 degrees. At this time, a large current flows through the resistance element R, and energy is consumed by the resistance element. That is, energy is not easily transmitted from the terminal pair (2) to the terminal pair (1).
[0007]
However, this phenomenon is an ideal case. In practice, there is a line capacitance between the first and second central conductors, and there is a parasitic inductance in series with the resistance element. When such a parasitic element exists, the operation described above cannot be expected. Therefore, the present inventors have changed the line capacitance or the line capacitance when the intersection angle φ formed by the intersection of the center axis of the first center conductor L1 and the center axis of the second center conductor L2 is changed. A method to compensate for the parasitic inductance was investigated using an originally developed circuit simulator. This case has already been discussed in US patent 4,210,886. However, the theoretical background is unclear, and the conclusion reached has not necessarily calculated the optimum angle with practicality taken into account.
Therefore, the present invention reexamines the circuit characteristics of the two-terminal pair lumped constant type isolator in detail by using a uniquely developed circuit simulator, thereby obtaining an intersection angle φ between the first center conductor L1 and the second center conductor L2, Furthermore, the optimum condition of the attached circuit (for example, Cw in the case of the circuit of FIG. 4) connected between the first center conductor L1 and the second center conductor L2 is obtained, the structure is simple, and the size and thickness are reduced. In addition to the above, it is an object of the present invention to provide a very practically effective two-terminal pair isolator having a low insertion loss and a wide insertion loss bandwidth.
[0008]
[Means for Solving the Problems]
The present invention is a two-terminal pair isolator arranged near the center of a ferrite to which a static magnetic field is applied so that the first and second central conductors intersect each other in an electrically insulated state. One end of the second central conductor serves as first and second input / output terminals, the other end is connected to a common portion, and a first matching capacitor is provided between the first input / output terminal and the common portion. Is connected, a second matching capacitor is connected between the second input / output terminal and the common terminal, a resistance element is connected between the first and second input / output terminals, and the first This is a two-terminal pair isolator in which the crossing angle between the central axis of the central conductor of the second conductor and the central axis of the second central conductor is in the range of 40 to 80 degrees.
In the present invention, it is preferable to connect a third capacitor in parallel with the resistance element. The capacitance of the third capacitor is smaller than the capacitances of the first matching capacitor and the second matching capacitor.
In the present invention, it is also preferable to connect an inductor in parallel with the resistance element. In the present invention, an inductor is preferably connected in series with the resistance element. The common portion of the two-terminal pair isolator according to the present invention is connected to a ground conductor.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 4 is an equivalent circuit diagram of a two-terminal pair isolator which is the basis of the present invention. 7 differs from the conventional two-terminal pair isolator shown in FIG. 7 in that the crossing angle of the central conductor can be changed first and second, and in order to compensate for the effect of the crossing angle φ, a resistance element R is newly added. The third capacitor Cw is connected in parallel.
1 (a), (b), and (c) use a circuit simulator that was originally developed on the assumption that the center frequency fo is 1000 [MHz] and the equivalent circuit of FIG. 4 is an ideal circuit. The frequency characteristic of the S parameter of the two-terminal pair isolator calculated by The ideal circuit here means that the coupling between the two central conductors L1, L2 is perfect. In the figure, calculation results for three typical angles φ = 60 [degrees], φ = 90 [degrees], and φ = 120 [degrees] are shown. The parameters used at this time were characteristic impedance Zo = 50 [Ω], air core inductance K = 1 [nH], saturation magnetization of ferrite thin plate 4πMs = 900 [G], and resistance value of resistance element R = 50 [Ω ]. The calculated frequency range was set to 900 [MHz] to 1100 [MHz] of ± 10% with respect to the center frequency fo.
[0010]
The third capacitor Cw, which is an attached circuit element, is naturally Cw = 0 when φ = 90 degrees in the prior art. When φ = 60 [degrees], Cw = 7.85 [pF], and when φ = 120 [degrees], Cw = −7.85 [pF]. A negative Cw means that this part is not a capacitor but an inductor. This point will be described in detail later.
[0011]
FIG. 1A shows the frequency characteristic of the reflection loss S11. As can be seen from this figure, with φ = 90 [degrees] as a reference, when φ is smaller than this, the bandwidth of the reflection loss S11 is widened, and when φ is larger than this, the bandwidth is rapidly narrowed. Here, a value obtained by dividing the frequency width at which S11 falls below 20 [dB] by the center frequency fo is represented by a specific bandwidth W (S11) [%].
FIG. 1B shows the frequency characteristics of the insertion loss S21. As can be seen from this figure, on the basis of φ = 90 [degrees], when φ is smaller than this, the bandwidth of S21 is widened, and when φ is larger than this, the bandwidth is rapidly narrowed. Here, assuming that the value of the reflection loss S11 at 900 [MHz] is related to the bandwidth of the insertion loss, it is defined as IL [dB] (at 0.9fo). Indicated by Δ in the figure. A small IL corresponds to a wide bandwidth for insertion loss, and vice versa.
As described above, in FIGS. 1 (a) and 1 (b), the result that the bandwidth of reflection loss and insertion loss is widened at φ = 60 degrees is the focus of the present invention.
FIG.1 (c) shows the frequency characteristic of the reverse loss calculated on the same conditions. When φ = 90 [degrees], it shows a high reverse loss characteristic of 45 [dB] or more in the frequency range of 0.9fo to 1.1fo (900MHz to 1100MHz) as shown, but φ is larger than this Even if it becomes smaller, the reverse loss deteriorates. In particular, when φ is smaller than φ = 90 [degrees], the degree of deterioration increases. Here, an amount IS [dB] (at 0.96 fo) related to the bandwidth of reverse loss is defined. That is, this is the reverse loss value at 0.96fo (960 MHz in the figure). Indicated by Δ in the figure. A large IS corresponds to a wide reverse loss bandwidth, and a small IS corresponds to a narrow bandwidth.
[0012]
FIG. 2 shows the change of each attached parameter when the crossing angle φ of the two central conductors is changed in a wide range of 40 [degrees] to 140 [degrees] in order to show the principle and range of the present invention. . Here, the first matching capacitor and the second matching capacitor have the same value, and are represented by C (= C1 = C2). When φ is smaller than 90 [degrees], the third capacitor Cw gradually increases. When just φ = 60 [degrees], the third capacitor Cw, the first matching capacitor, and the second matching capacitor C match, and both are 7.85 [pF]. C tends to decrease, but is almost constant below 60 [deg.]. The resistance element R is constant at 50 [Ω].
Conversely, when φ is greater than 90 degrees, the capacitance of the first and second matching capacitors C increases rapidly as φ increases. On the other hand, the third capacitor Cw becomes negative, and its absolute value increases as φ increases. This is indicated by a fine dotted line in the figure. The curve of the absolute value of Cw is symmetrical with respect to φ = 90 [degrees]. Since there is actually no capacitor with a negative capacity, this can be equivalently represented as an inductor Lp. An equivalent circuit in this case is shown in FIG.
That is, when φ is greater than 90 degrees, an inductor Lp is required in parallel with the resistance element R. However, this equivalent circuit is not very practical. This is because, in practice, the behavior around 90 [degrees] is important, so I would like to discuss this part in detail, but at φ = 90 [degrees], Lp becomes infinite. In order to avoid this, a circuit in which an inductor Ls is inserted in series with a resistance element Rs as shown in FIG. 6 is practical. This is because when φ is brought close to 90 [degrees] from a large state, it gradually approaches Ls = 0 [nH] and Rs = 50 [Ω], so that there is continuity.
[0013]
The graph on the right half of FIG. 2 shows changes in Ls and Rs when φ> 90 [degrees]. As φ increases, Rs suddenly approaches zero, but Ls takes a maximum value of 115 degrees. When the angle becomes larger than that, Ls gradually decreases monotonously.
FIG. 3 shows the angular dependence of isolator characteristics calculated under the above conditions. IL (at 0.9fo) indicating the bandwidth of the insertion loss S11 decreases when φ is smaller than 90 [degrees], and takes a minimum value when φ = 60 [degrees]. On the contrary, when it becomes larger than 90 [degree], IL (at 0.9fo) rapidly increases. In addition, the normalized operating magnetic field σ indicating the strength of the static magnetic field is minimum at 90 [degrees], and becomes larger when the angle is larger or smaller. Here, the normalized operating magnetic field σ is a dimensionless number obtained by dividing the internal magnetic field Hi of the ferrite thin plate by the ferromagnetic resonance magnetic field Hres (= 2πfo / γ) at the center frequency fo. γ is a constant called magnetic rotation rate. The bandwidth W (S11) at which the reflection loss S11 falls below 20 [dB] increases as φ decreases, and takes a maximum value of 7.6 [%] at approximately φ = 60 [degrees]. When φ becomes larger than 90 [degrees], W (S11) decreases monotonously.
[0014]
On the other hand, IS (at 0.96 fo) indicating the bandwidth of the reverse loss shows a maximum value of 55 dB at φ = 90 [degrees], and decreases at both larger and smaller angles. In particular, it decreases monotonously when φ <90 [degree], and drops below 10 [dB] when φ = 40 [degree]. On the other hand, when φ> 90 [degrees], although it decreases, it shows a high attenuation of about 30 [dB].
Now, the practically effective results from FIGS. 3 and 4 are summarized as follows.
(1) When low insertion loss is important, a range of φ <90 [degrees] is desirable.
(2) When the reverse loss is important, φ = 90 [degree] is desirable.
(3) The insertion loss bandwidth and the reflection loss bandwidth are the largest at about φ = 60 degrees.
(4) Actually acceptable IS (at 0.96fo) = 10 [dB] is cut when φ is 40 degrees or less.
[0015]
Next, the idea of defining the claims of the present invention from the above results will be described.
That is, the present inventor theoretically clarified for the first time that the insertion loss bandwidth is extremely wide and the reverse loss is sufficiently practical at φ = 60 degrees. The basic idea of the present invention is not limited to φ = 60 degrees. That is, the gist of the present invention does not change even when IS (at 0.96 fo) indicating the bandwidth of the reverse loss is 40 degrees which is less than 10 dB. However, if φ becomes smaller than this, IS (at 0.96fo) becomes too small to be practically usable. For this reason, φ = 40 [degrees] was defined as the lower limit of the claims of the present invention. In addition, at φ = 80 [degrees], the insertion loss bandwidth IL (at 0.9fo) and the reflection loss bandwidth W (S11) are significantly improved compared to the prior art φ = 90 [degrees]. . Therefore, the gist of the present invention is fully alive even at φ = 80 degrees. However, if φ becomes larger than this, IS (at 0.96fo) increases, and the difference from the prior art becomes unclear. Therefore, φ = 80 [degrees] was defined as the upper limit of the present invention.
[0016]
Now, the third capacitor Cw is clearly described in the equivalent circuit of FIG. 4 which is the basis of the present invention. Here, the third capacitor Cw requires that the capacitance of Cw is considerably larger than C when the crossing accuracy φ = 40 [degrees] of the first and second central conductors, and φ = 80 [degrees]. Cw can be quite small.
Also, this Cw is not always necessary. This is because the two central conductors L1 and L2 intersect each other in the vicinity of the center of the ferrite thin plate G, and are electrically insulated by a thin insulating sheet. There is actually a line capacitance between them. This is because the line capacitance operates in exactly the same way as Cw in FIG. By skillfully utilizing this line capacitance, the effect of the present invention can be realized without the third capacitor Cw.
Due to the presence of the line capacitance, the third capacitor Cw is often practically smaller than the first and second capacitors C.
Also, this line-to-line capacitance may be too large and exceed the amount of Cw necessary to compensate for the effect of angle φ. In order to compensate for this overshoot, an inductor Lp may be connected in parallel with the resistance element R.
The circuit of the resistor element R and the inductor Lp connected in parallel thereto can be replaced by the resistor element Rs and the series inductor Ls.
[0017]
【The invention's effect】
As is clear from the above description, according to the two-terminal pair isolator of the present invention, the structure is simple with only the two central conductors, and not only is the size and thickness reduced, but also the insertion loss bandwidth A low-loss two-terminal pair isolator having a wide band can be provided.
[Brief description of the drawings]
1A is a frequency characteristic diagram of reflection loss of a two-terminal pair isolator showing the effect of the present invention, FIG. 1B is a frequency characteristic diagram of insertion loss of a two-terminal pair isolator illustrating the effect of the present invention, and FIG. The frequency characteristic figure of the reverse loss of the 2 terminal pair isolator which shows the effect of invention.
FIG. 2 is an angle dependency of an attached circuit parameter of a two-terminal pair isolator for realizing the effect of the present invention.
FIG. 3 is an angle dependency of two-terminal-pair isolator characteristics for explaining the effect of the present invention.
FIG. 4 is an equivalent circuit of a two-terminal pair isolator which is a subject of the present invention.
FIG. 5 is an equivalent circuit of a two-terminal pair isolator illustrating the effect of the present invention.
FIG. 6 is an equivalent circuit of a two-terminal pair isolator for explaining the effect of the present invention.
FIG. 7 is an equivalent circuit of a conventional two-terminal pair isolator.
FIG. 8 is an equivalent circuit of an isolator based on a prior art three-terminal pair circulator.
[Explanation of symbols]
▲ 1 ▼ ▲ 2 ▼ ▲ 3 ▼ I / O terminal pair
C1, C2, C3 matching capacitors
G Ferrite sheet
L1, L2, L3 Center conductor
GR Ground conductor
R resistance element φ Intersection angle of first center conductor and second center conductor
Cw parallel capacitor

Claims (2)

第1、第2の中心導体を互いに電気的に絶縁状態で交差するように、静磁界が印加されたフェライトの中央近傍に配接する2端子対アイソレータであって、
前記第1、第2の中心導体の一端はそれぞれ第1、第2の入出力端子となり、他端は地導体となる共通部に接続され、前記第1の入出力端子と前記共通部の間には第1の整合用コンデンサーが接続され、前記第2の入出力端子と前記共通の間には第2の整合用コンデンサーが接続され、前記第1、第2の入出力端子間に抵抗素子が接続され、前記第1の中心導体の中心軸と前記第2の中心導体の中心軸との交差角度が40度から80度の範囲にあり、
前記抵抗素子と並列に第3のコンデンサーを接続し、
前記第3のコンデンサーの静電容量が、前記第1の整合用コンデンサーおよび第2の整合用コンデンサーの静電容量より小さいことを特徴とする端子対アイソレータ。
A two-terminal pair isolator arranged near the center of a ferrite to which a static magnetic field is applied so that the first and second central conductors intersect each other in an electrically insulated state;
One end of each of the first and second center conductors is a first and second input / output terminal, and the other end is connected to a common portion serving as a ground conductor, and between the first input / output terminal and the common portion. Is connected with a first matching capacitor, a second matching capacitor is connected between the second input / output terminal and the common portion , and a resistor is connected between the first and second input / output terminals. element is connected, Ri angle of intersection near the range of 80 degrees from 40 degrees with the central axis of said first central conductor center axis and the second center conductor,
A third capacitor connected in parallel with the resistive element;
The terminal pair isolator , wherein the capacitance of the third capacitor is smaller than the capacitance of the first matching capacitor and the second matching capacitor .
第1、第2の中心導体を互いに電気的に絶縁状態で交差するように、静磁界が印加されたフェライトの中央近傍に配接する2端子対アイソレータであって、A two-terminal pair isolator arranged near the center of a ferrite to which a static magnetic field is applied so that the first and second central conductors intersect each other in an electrically insulated state;
前記第1、第2の中心導体の一端はそれぞれ第1、第2の入出力端子となり、他端は地導体となる共通部に接続され、前記第1の入出力端子と前記共通部の間には第1の整合用コンデンサーが接続され、前記第2の入出力端子と前記共通部の間には第2の整合用コンデンサーが接続され、前記第1、第2の入出力端子間に抵抗素子が接続され、前記第1の中心導体の中心軸と前記第2の中心導体の中心軸との交差角度が40度から80度の範囲にあり、One end of each of the first and second center conductors is a first and second input / output terminal, and the other end is connected to a common portion serving as a ground conductor, and between the first input / output terminal and the common portion. Is connected with a first matching capacitor, a second matching capacitor is connected between the second input / output terminal and the common portion, and a resistor is connected between the first and second input / output terminals. Elements are connected, and an intersection angle between the central axis of the first central conductor and the central axis of the second central conductor is in the range of 40 degrees to 80 degrees,
前記抵抗素子と直列にインダクターを接続したことを特徴とする2端子対アイソレータ。A two-terminal pair isolator, wherein an inductor is connected in series with the resistance element.
JP2001233692A 2001-03-30 2001-08-01 2-terminal pair isolator Expired - Lifetime JP4655257B2 (en)

Priority Applications (5)

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JP2001233692A JP4655257B2 (en) 2001-08-01 2001-08-01 2-terminal pair isolator
EP02007190A EP1246292A3 (en) 2001-03-30 2002-03-28 Two-port isolator and method for evaluating it
US10/108,360 US6940360B2 (en) 2001-03-30 2002-03-29 Two-port isolator and method for evaluating it
KR1020020017614A KR100862962B1 (en) 2001-03-30 2002-03-30 Two-port isolator and method for evaluting it
CNB021272492A CN1301567C (en) 2001-03-30 2002-03-30 Two-terminal-pair isolator and its evaluating method

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JP2001233692A JP4655257B2 (en) 2001-08-01 2001-08-01 2-terminal pair isolator

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3979402B2 (en) * 2003-09-04 2007-09-19 株式会社村田製作所 Two-port isolator, characteristic adjustment method thereof, and communication device
US7532084B2 (en) 2007-08-31 2009-05-12 Murata Manufacturing Co., Ltd Nonreciprocal circuit element
WO2015093273A1 (en) 2013-12-18 2015-06-25 株式会社村田製作所 Non-reciprocal circuit element

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53129561A (en) * 1977-04-18 1978-11-11 Motorola Inc Improved wideeband isolator
US4210886A (en) * 1978-09-18 1980-07-01 Motorola, Inc. Isolator having reactive neutralizing means and predetermined angle between input-output windings
JPH11205016A (en) * 1998-01-19 1999-07-30 Murata Mfg Co Ltd Manufacture of isolator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53129561A (en) * 1977-04-18 1978-11-11 Motorola Inc Improved wideeband isolator
US4210886A (en) * 1978-09-18 1980-07-01 Motorola, Inc. Isolator having reactive neutralizing means and predetermined angle between input-output windings
JPH11205016A (en) * 1998-01-19 1999-07-30 Murata Mfg Co Ltd Manufacture of isolator

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