JP4651023B2 - Circuit simulation device - Google Patents

Description

  The present invention relates to a circuit simulation apparatus, and more particularly to a circuit simulation in logic verification of a semiconductor device including a PLL (Phase Locked Loop :) circuit.

  Various electronic devices currently on the market are equipped with semiconductor integrated circuits. The demand for higher operating speed is increasing year by year for semiconductor integrated circuits mounted on electronic devices. One technique for improving the operation speed is to mount a PLL circuit on a semiconductor integrated circuit. In a semiconductor integrated circuit equipped with a PLL circuit, the internal clock frequency is set to an integral multiple of the external clock to increase the operation speed.

  The semiconductor integrated circuit as described above has been developed through various processes. In semiconductor development, simulation techniques are used at various stages of development. In order for the simulation to be effective, it is necessary to construct the model appropriately. In a conventional simulation apparatus, when a semiconductor integrated circuit equipped with a PLL circuit is simulated, a simple logic simulation model (hereinafter referred to as a first conventional model) that directly outputs an input clock is used. Used as a simulation model.

  In response to the recent miniaturization and complexity of semiconductor integrated circuits, there has been a demand for a simulation apparatus and a simulation method capable of performing simulation with higher accuracy. For example, in an actual semiconductor integrated circuit, a stable input clock needs to be supplied to a PLL circuit to be mounted during a multiplication operation. When the actual input clock is stopped for some reason, a problem may occur in the actual operation of the semiconductor integrated circuit. For this reason, in the logic simulation stage, it may be required to predict the above-mentioned problem. However, in the first conventional model, even when the input clock is stopped for some reason, it is impossible to detect the state (the state where the input clock is stopped).

  As a technique for performing verification closer to an actual device as compared with the simulation corresponding to the first conventional model, a technique described in Patent Document 1 (Japanese Patent Laid-Open No. 2001-358581) is known. The technique described in Patent Document 1 includes a counter circuit in a logic simulation model, and outputs a normal waveform by resetting only at the time of normal input, and stops output when not reset. The technique of Patent Document 1 enables verification close to an actual device by reflecting an incorrect value input in a logic simulation result by this operation.

  Further, a logic simulation model (hereinafter referred to as a second conventional model) is known that has a configuration different from that of Patent Document 1 and can reproduce the operation of a PLL circuit closer to an actual device. FIG. 1 is a block diagram showing the configuration of the second conventional model 100 described above. Referring to FIG. 1, the second conventional model 100 includes a multiplication set value input terminal DIV, an input clock supply terminal 106, a multiplication clock output terminal OUT, a clock period measurement unit 101, a clock period variation detection unit 102, The multiplication waveform generation unit 103 and the error processing unit 104 are included.

  The clock cycle measuring unit 101 detects the input clock supplied via the input clock supply terminal 106 and calculates the difference between the previous change time of the input clock and the current time. The clock cycle variation detection unit 102 receives the cycle value of the input clock output from the clock cycle measurement unit 101, and compares the cycle value of the previous cycle with the cycle value of the current cycle. The multiplication waveform generation unit 103 receives the cycle value of the input clock output from the clock cycle measurement unit 101 and the multiplication setting input value supplied via the multiplication setting value input terminal DIV, and determines the output multiplication waveform cycle. . The error processing unit 104 performs error processing when the clock cycle variation detection unit 102 detects a cycle variation.

  As described above, in an actual PLL circuit, the input clock supplied during the multiplication operation needs to be stable without frequency fluctuation. In the logic simulation corresponding to the second conventional model 100, when the frequency of the input clock fluctuates, the multiplication operation on the simulation is stopped, and the fact that there was an illegal input is reflected in the simulation result.

  This simulation result can be obtained by executing a simulation using a logic simulator corresponding to the second conventional model (hereinafter referred to as a conventional simulator). The conventional simulator calculates events for each time using the connection information of the design circuit, the input pattern, and the logic simulation model of each cell as information. Here, the conventional simulator starts simulation execution in response to the supply of the input clock to the PLL circuit indicated by the second conventional model. The conventional simulator determines the output logic value of the PLL circuit by performing processing based on the description of the second conventional model.

  Here, the above operation will be specifically described with reference to the drawings. FIG. 2 is a flowchart showing the operation of the conventional simulator. In step S1, the conventional simulator monitors an input clock event and determines whether an event has occurred. If an event is detected as a result of the determination, the process proceeds to step S2, and if no event is detected, the process ends. In step S <b> 2, the clock cycle measurement unit 101 measures the cycle of the input clock and supplies the measurement result to the clock cycle variation detection unit 102. In step S3, the clock cycle fluctuation detection unit 102 compares the values of the previous cycle period and the current cycle cycle based on the measurement result supplied from the clock cycle measurement unit 101. judge. When an illegal input occurs, the clock cycle variation detection unit 102 notifies the error processing unit 104 to that effect, and the process proceeds to step S7. If unauthorized input has not occurred, the process proceeds to step S4. In step S7, the error processing unit 104 outputs an indefinite value and prohibits multiplication output.

  In step S4, the multiplied waveform generation unit 103 determines whether or not the multiplied waveform generation is completed. As a result of the determination, if the multiplied waveform generation is completed, the process ends. If not generated, the process proceeds to step S5. In step S <b> 5, the time determination unit included in the multiplied waveform generation unit 103 determines whether the current time has passed a lock-up time that is a specification indicating a period necessary for phase adjustment. If the lock-up time has elapsed, the process proceeds to step S6. In step S6, the multiplied waveform generation unit 103 starts outputting the multiplied waveform. The multiplied waveform generates an output waveform by inverting the output at regular intervals. In step S8, the output waveform generated by the multiplied waveform generation unit 103 is scheduled, and the process according to the input event ends.

  Here, the schedule is to generate an output value of the determined PLL as an event. This event propagates to cells after the PLL. The logic simulator corresponding to the second conventional model outputs an indefinite value from the PLL when an illegal input is made by this processing. Due to this operation, the cells after the PLL do not operate normally, and the simulation result is different from the expected operation. Therefore, the circuit designer can find out that the violation operation has occurred in the PLL.

  Hereinafter, the above-described operation will be described using a timing chart. FIG. 3 is a timing chart showing the operation of the conventional simulator. FIG. 3A shows the signal waveform of the input clock supplied to the input clock supply terminal 106. FIG. 3B shows the waveform of the output signal output from the multiplied clock output terminal OUT. It is assumed that the period of the input clock input to the input clock supply terminal 106 before this timing chart is stable at the period value T1. Further, it is assumed that the phase adjustment of the PLL is completed at time A1, and a stable multiplied waveform can be output.

  The PLL requires a phase adjustment period inside the PLL for the output of the multiplied waveform, and the output is not stable during the phase adjustment period, so the logic simulation model outputs indefinite. Therefore, after detecting the multiplied output mode change event, output of the multiplied waveform is started after a certain time.

  At time A1, an input clock event has occurred. Therefore, it is determined as YES in the above-described determination in step S1. In step S2, the period of the input clock is measured. In step S3, a frequency variation check is performed based on the measurement result. At time A1, both the previous cycle and the current cycle are the period value T1. Therefore, it is determined that there is no frequency variation, and the process proceeds to step S4. In step S4, the multiplied waveform generation at time A1 is not performed. Therefore, it is determined that the multiplied waveform is not generated, and the process proceeds to step S5. In step S5, since the current time has passed the lock-up time, it is determined YES and the process proceeds to step S6. In step S6, a multiplied waveform is generated, the process proceeds to step S8, the schedule is registered, and the process ends.

  Thereafter, since an event of the input clock occurs at time A2, YES is determined in step S1, and the process proceeds to step S2. In step S2, the period of the input clock is measured, and the measurement result is output. In step S3, at time A2, a frequency variation check is performed, and both the previous cycle and the current cycle have the period value T1. Therefore, it is determined as NO, and the process proceeds to step S4. In step S4, since the multiplied waveform has been generated, it is determined as NO, and the process ends. Thereafter, similar processing is repeated at time A3 and time A4.

  Since an input clock event occurs at time A5, it is determined YES in step S1, and the process proceeds to step S2. In step S2, the period of the input clock is measured, the measurement result is output, and the process proceeds to step S3.

  In step S3, a frequency variation check is performed. Referring to FIG. 3, the current cycle value is the cycle value T2 with respect to the cycle value T1 of the previous cycle. Since the clock cycle variation detector 102 detects the difference between the cycle value T1 and the cycle value T2, the clock cycle variation detector 102 determines that the frequency has fluctuated, and the process proceeds to step S7. In step S7, the error processing unit 104 performs error processing. Thereafter, the process proceeds to S8, the indeterminate value output is scheduled, and the process ends. In this operation, the frequency fluctuation can be detected as an illegal operation.

  A conventional simulator that performs simulation using the second conventional model is an event-driven logic simulator that is currently mainstream. In the event-driven method, a signal event is detected and a logic simulation model of each cell connected to a netlist is called. The logic simulator gives an event to a terminal of a cell logic simulation model, and performs operation processing and output value schedule according to the cell logic simulation model description. Thereafter, the next signal propagation is performed via the netlist. Therefore, when no event occurs, the simulator shifts to a standby state.

  The operation when the input clock signal supply is stopped in the conventional simulator will be described below. FIG. 4 is a timing chart showing the operation of the conventional simulator when the input clock signal supply is stopped.

  Referring to FIG. 4, the operation from time B1 to time B4 is the same as from time A1 to time A4 in FIG. As shown in FIG. 4, the signal supply of the input clock is stopped at time B4. If input clock input continues at a stable frequency, an event should occur in the input clock at time B5. However, when the supply of the input clock is stopped, the event itself for detecting the frequency fluctuation and determining the supply stop does not occur. Therefore, the output signal in the normal state is continuously output even after time B5.

JP 2001-358581 A

  As described above, in the logic simulation corresponding to the first conventional model, it is not possible to automatically verify whether or not the illegal input is generated at the time of logic verification, and there is a possibility that the illegal input is missed. This may lead to a malfunction that does not operate normally in the actual circuit.

  Also, with the technique of Patent Document 1, it is possible to temporarily detect an illegal value input and stop the output. In the technique of Patent Document 1, when the input subsequently returns to a normal value, the output immediately returns to the normal waveform output. If the input frequency fluctuates, it cannot be detected as an illegal input, and a normal waveform continues to be output. In other words, in the technique described in Patent Document 1, the unstable state of the output in the actual device may not be reflected in the logic simulation.

  Further, in a conventional simulator that performs a simulation corresponding to the second conventional model, information related to various timing checks is described in the logic simulation model based on the occurrence of an input event. In the conventional simulator, the check was performed according to the description. In the simulator language, the input signal pulse width check and cycle value check are prepared as functions as the timing check process related to input, and both are processed based on the input event. Although no function is prepared for the frequency fluctuation check, the input event is realized by describing a series of processes based on the input event as described above.

  However, the fact that the supply of the input clock is stopped means that there is no event that triggers the check, and therefore the check process is not executed. In an actual device, when a stable input clock is not input to the PLL circuit, the PLL circuit does not operate properly. Even in a logic simulation model, this input illegal operation must be detected. The problem to be solved by the present invention is to provide a check method that does not depend on an input event.

  The means for solving the problem will be described below using the numbers used in [Best Mode for Carrying Out the Invention]. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

In order to solve the above problems, a circuit simulation is executed by the following simulation program (24). The simulation program (24) includes a PLL (27) that outputs at least one output clock based on the input clock. A simulation program (24) for causing a computer (10) to execute an operation of a circuit (25) comprising a PLL model (30) (50) representing the PLL (27),
(A) reading circuit information related to the circuit and executing a simulation based on the circuit information;
(B) monitoring the supply of the input clock in the simulation and generating an expected clock for monitoring changes in the input clock in response to the start of supply of the input clock to the PLL model. Is preferably a simulation program (24) characterized in that the computer (10) is executed.

The simulation program may further include (c) a step of prohibiting output of the output clock from the PLL based on a comparison between the expected clock and the input clock. Here, the step (b) includes generating the clock having the same period as the input clock as the predicted clock, and whether the predicted clock and the input clock are synchronized with each other. Preferably, the method includes a step of determining whether or not is stopped.

  Further, in order to execute the simulation program, a logic simulation apparatus (10) that simulates the operation of the semiconductor integrated circuit (25) including the PLL circuit (27) is configured. The apparatus (10) includes a storage unit (7) that holds a simulation model (23) and a simulation program (24), and an arithmetic processing unit (4) that executes circuit simulation according to the procedure shown in the simulation program (24). ) Is preferable. Here, it is preferable that the simulation model (23) held in the storage unit (7) includes PLL circuit models (30) and (50) corresponding to the PLL circuit (27).

  The PLL circuit models (30) and (50) show an output clock generator (31) that generates an output clock in response to an input clock, and a clock monitor (32) that monitors the state of the input clock. It is preferable. The clock monitoring unit (32) generates an expected clock having the same cycle as the input clock, and monitors the change of the input clock based on the comparison between the expected clock and the input clock. Furthermore, it is preferable that the logic simulation device stop the generation of the output clock in the output clock generation unit based on the monitoring result of the clock monitoring unit.

According to the present invention, it is possible to provide a check method that does not depend on an input event.
Further, it is possible to provide a logic simulation model capable of verifying operations such as multiplication and skew adjustment with higher accuracy in the logic verification phase of circuit design.
In addition, in order to detect a problem in the design circuit at an early stage, a logic simulation model equipped with an illegal input detection function can be provided.

  The configuration and operation of the simulation apparatus of the present invention will be described below with reference to the drawings. In the development of semiconductor devices, CAD (Computer Aided Design) is used in various processes related to the design of a semiconductor device to be developed. Therefore, in this specification, the form for implementing this invention is demonstrated corresponding to the case where design, verification, optimization, etc. of a semiconductor are performed using CAD.

[First Embodiment]
FIG. 5 is a block diagram illustrating the configuration of the simulation apparatus of the present invention. As illustrated in FIG. 5, the simulation apparatus 10 according to the first embodiment includes an information processing apparatus 1, an input apparatus 2, and a display apparatus 3. 5, the information processing apparatus 1 includes a CPU (Central Processing Unit) 4, a memory 5, an input / output interface 6, and a mass storage device 7, which are buses. 8 is connected. The mass storage device 7 includes a data storage unit 11 and a program storage unit 12.

  The information processing apparatus 1 is a high-speed arithmetic processing apparatus typified by a personal computer or a workstation. The input device 2 is a man-machine interface having a function of inputting data to the information processing device 1, and representative examples thereof include a keyboard and a mouse. In the following embodiment, the case where the input device 2 is a keyboard will be described as an example. The display device 3 is a man-machine interface having a function of outputting the processing result of the information processing device 1 to the outside, and representative examples thereof include a CRT and a liquid crystal display. In the following embodiments, the case where the display device 3 is a display device will be described as an example, and a description will be given assuming that a layout verification result and the like are visually displayed.

  The CPU 4 is an arithmetic processing device that controls various devices provided in the simulation device 10 and processes data input to and output from the information processing device 1, and interprets and calculates data received from the input device 2 and the like. The calculation result is output by the display device 3 or the like. The memory 5 is a storage medium on which data can be written and read, and examples thereof include SDRAM and DDR-SDRAM. The input / output interface 6 is a device that controls data communication executed between the information processing device 1 and the input device 2 or the display device 3 described above. The large-capacity storage device 7 is a device used for recording a large amount of data on a storage medium. For example, an HDD (Hard Disk Drive) is exemplified as a representative example. As shown in FIG. 5, the mass storage device 7 includes a data storage unit 11 and a program storage unit 12.

  The data storage unit 11 indicates a storage area for storing data related to the present embodiment among various data held by the mass storage device 7. Similarly, the program storage unit 12 indicates a storage area for storing a computer program related to the operation of the present embodiment among various data held by the mass storage device 7. Hereinafter, detailed configurations of the data storage unit 11 and the program storage unit 12 will be described with reference to the drawings.

  FIG. 6 is a block diagram illustrating the configuration of the data storage unit 11. Referring to FIG. 6, the data storage unit 11 includes a net list 21, a library 22, and a simulation model 23. The net list 21 is data representing the connection state of the circuit. The library 22 holds frequently used function blocks and basic logic gate data as macro data. The simulation model 23 is a model used when a logic simulation program 24 described later is executed when predicting circuit characteristics using the simulation apparatus 10 of the present embodiment. FIG. 7 is a block diagram illustrating the configuration of the program storage unit 12. Referring to FIG. 7, the program storage unit 12 includes a logic simulation program 24. The logic simulation program 24 is a computer program showing a circuit simulation procedure to be executed by the simulation apparatus 10 of the present embodiment.

  FIG. 8 is a block diagram illustrating the configuration of a semiconductor device to be simulated in this embodiment. The simulation apparatus 10 of this embodiment can be applied to the simulation of a semiconductor device on which a PLL circuit is mounted. Referring to FIG. 8, a semiconductor device 25 to be simulated includes a signal processing unit 26 and a PLL circuit 27. The signal processing unit 26 is a circuit block that operates in synchronization with the clock output from the PLL circuit 27. As shown in FIG. 8, the PLL circuit generates the PLL circuit output clock by setting the internal clock frequency to an integral multiple of the external clock. In a semiconductor integrated circuit equipped with a PLL circuit, the operation speed is increased by operating with a clock output from the PLL circuit. The configuration of the semiconductor device 25 shown here does not limit the simulation target device in the present invention.

  FIG. 9 is a block diagram illustrating the configuration of the PLL circuit model according to the first embodiment. Referring to FIG. 9, the PLL circuit model 30 of this embodiment includes a multiplied clock generation unit 31 and a clock monitoring unit 32. The multiplied clock generator 31 is a functional block that generates a multiplied clock in response to an input clock. The clock monitoring unit 32 is a functional block that monitors the state of the input clock. The PLL circuit model 30 includes a multiplication set value input terminal 41, an input clock supply terminal 42, and a multiplication clock output terminal 43. A multiplication set value is supplied to the multiplication set value input terminal 41. An input clock is supplied to the input clock supply terminal 42. A multiplied clock is output from the multiplied clock output terminal 43.

  As shown in FIG. 9, the multiplied clock generation unit 31 includes a clock cycle measurement unit 33, a clock cycle change detection unit 34, a multiplied waveform generation unit 35, and an error processing unit 36. The clock cycle measuring unit 33 is a functional block that measures the cycle of the input clock in response to the input clock. An input clock is supplied to the clock period measurement unit 33 via an input clock supply terminal 42. The clock cycle measuring unit 33 calculates the difference between the previous change time of the input clock and the current time. For example, the rising time of the input clock is measured, and then the clock cycle is measured based on the difference from the rising time of the input clock. The clock cycle measuring unit 33 supplies a value indicating the measured cycle of the input clock to the clock cycle change detecting unit 34.

  The clock cycle change detection unit 34 compares the measured value of the input clock supplied from the clock cycle measuring unit 33 with the measured value of the input clock supplied one cycle before and determines whether or not the input clock is fluctuating. It is a functional block to be identified. When the cycle of the input clock fluctuates, the clock cycle change detection unit 34 notifies the error processing unit 36 (to be described later) to that effect.

  The multiplied waveform generation unit 35 multiplies the input clock by an integral multiple based on the multiplied waveform set value supplied from the multiplied set value input terminal 41 and the measured value of the cycle of the input clock output from the clock cycle measuring unit 33. It is a functional block that generates a cook. The error processing unit 36 multiplies in response to a notification that the input clock supplied from the clock cycle change detection unit 34 has changed or a notification that the input clock supplied from the clock monitoring unit 32 described later has stopped. This is a functional block that limits clock output.

  As shown in FIG. 9, the clock monitoring unit 32 includes an expected clock generation unit 37 and a clock comparison unit 38. The expected clock generation unit 37 is a functional block that generates an expected clock that changes in the same cycle as the measurement cycle output from the clock cycle measurement unit 33. The expected clock generation unit 37 is executed only for one clock cycle after the lockup time (the time until the waveform of the multiplied clock output from the multiplied waveform generating unit 35 becomes stable) has elapsed. The predicted clock generation unit 37 continuously outputs the clock having the cycle generated at this time as the predicted clock. The clock comparison unit 38 is a functional block that compares the input clock at that time with the supplied expected clock in response to an event of the expected clock generation. The simulation operation with the above configuration will be described below.

  FIG. 10 is a flowchart illustrating the operation of the first embodiment. The flowchart shown in FIG. 10 illustrates the operation of the above-described PLL circuit model 30 when a logic simulation of a semiconductor device is executed using the simulation apparatus 10 of the present embodiment. This operation is realized by the CPU 4 of the information processing apparatus 1 reading the logic simulation program 24 in the program storage unit 12 and operating the information processing apparatus 1 according to the procedure indicated by the logic simulation program 24. Referring to FIG. 10, the operation of the simulation apparatus 10 operates in the same procedure as that of the conventional simulator described above.

  In step S <b> 101, the clock cycle measurement unit 33 monitors the occurrence of an event of the input clock supplied via the input clock supply terminal 42. The clock cycle measuring unit 33 determines whether an event corresponding to the supply of the input clock has occurred based on the monitoring result. If the event is detected as a result of the determination, the process proceeds to step S102. If no event is detected, the process ends.

  In step S <b> 102, the clock cycle measurement unit 33 measures the cycle of the input clock and supplies the measurement result to the clock cycle change detection unit 34, the multiplied waveform generation unit 35, and the expected clock generation unit 37. Here, the clock cycle change detection unit 34 measures the cycle of the input clock every clock and outputs the measurement result.

  In step S103, the clock period change detection unit 34 compares the values of the previous cycle period and the current cycle period based on the measurement result supplied from the clock period measurement unit 33. judge. When an illegal input occurs, the clock cycle change detection unit 34 notifies the error processing unit 36 to that effect, and the process proceeds to step S105. If unauthorized input has not occurred, the process proceeds to step S104.

  In step S105, the error processing unit 36 outputs an indefinite value and prohibits multiplication output. In step S104, the multiplied waveform generation unit 35 determines whether or not the multiplied waveform generation is completed. As a result of the determination, if the multiplied waveform generation is completed, the process ends. If not, the process proceeds to step S106.

  In step S <b> 106, the multiplied waveform generation unit 35 determines whether or not the current time has passed a lock-up time that is a specification indicating a period necessary for phase adjustment, using a time determination unit provided therein. If the lock-up time has elapsed in the determination, the process proceeds to step S107.

  In step S107, the multiplied waveform generation unit 35 generates a multiplied clock by multiplying the frequency of the input clock by an integral multiple, and starts outputting the multiplied clock. Here, the multiplied clock generated by the multiplied waveform generator 35 has an output waveform generated by inverting the output at regular intervals.

  In step S108, the expected clock generation unit 37 inside the logic simulation model generates an expected clock that changes in the same cycle as the measurement cycle obtained in step S102. The operation of generating the expected clock is executed only once after the lock-up time (the time until the waveform of the multiplied clock output from the multiplied waveform generator 35 is stabilized) has elapsed. The predicted clock generation unit 37 continuously outputs a clock having the same cycle as the predicted clock generated at this time.

  In step S109, the output waveform generated by the multiplied waveform generator 35 is scheduled, and the process according to the input event ends. Here, the schedule is to generate the determined output value of the PLL circuit as an event. This event propagates to a cell provided in the subsequent stage of the PLL circuit. The simulation apparatus 10 according to the present embodiment performs the above-described processing, so that when an inappropriate signal is supplied as an input clock, the simulation apparatus 10 treats the input as an illegal input and outputs an indefinite value as a PLL circuit output. Since the indefinite value is output, the subsequent cell of the PLL circuit does not operate normally. Therefore, since a simulation result different from the expected operation is output, the circuit designer can find out that a violation operation has occurred in the PLL.

  The operation of the clock monitoring unit 32 will be described below with reference to the drawings. FIG. 11 is a flowchart illustrating the operation of the clock monitoring unit 32. Referring to FIG. 11, in step S201, the clock comparison unit 38 monitors whether or not the predicted clock generated by the predicted clock generation unit 37 is supplied. When the expected clock is supplied, the supplied clock is recognized as an event occurrence. When the clock comparison unit 38 detects an event of expected clock generation, the process proceeds to step S202. If no expected clock generation event is detected, the process ends.

  In step S202, the clock comparison unit 38 compares the input clock at that time with the expected clock to be supplied in response to the event of the expected clock generation. The clock comparison unit 38 detects whether or not the input clock is stopped based on the comparison. As a result of the comparison, if it is detected that the input clock is stopped, the process proceeds to step S203. If the stop of the input clock is not detected, the process ends.

  In step S203, the clock comparison unit 38 notifies the error processing unit 36 that the input clock is stopped. The error processing unit 36 inhibits the output of the multiplied clock supplied from the multiplied waveform generating unit 35 in response to the notification. Thereafter, the processing proceeds to step S204. In step S204, the output of the PLL circuit model 30 is scheduled and the process ends.

  At this time, the clock monitoring unit 32 generates a clock having the same frequency as that of the input clock input in the normal state and the same operation timing as an expected clock, separately from the input clock. Then, an event of the generated predicted clock is detected, and it is determined whether or not the predicted clock and the input clock are synchronized. Based on this determination, the clock comparison unit 38 of the clock monitoring unit 32 determines whether or not the input clock from the outside is stopped at the same time, and if it is stopped, the steady value is input from the input clock supply terminal 42. Suppose that the value is an illegal input.

  When the input clock is stopped by executing the simulation corresponding to the above-described operation, the input is treated as an illegal input, and the PLL circuit on the computer outputs an indefinite value as the output. Since the indefinite value is output, the subsequent cell of the PLL circuit does not operate normally. Therefore, since a simulation result different from the expected operation is output, the circuit designer can find out that a violation operation has occurred in the PLL.

  FIG. 12 is a timing chart illustrating the operation of this embodiment. FIG. 12A shows the operation waveform of the input clock supplied via the input clock supply terminal 42. FIG. 12B illustrates the waveform of the expected clock output from the expected clock generation unit 37 and supplied to the clock comparison unit 38. FIG. 12C illustrates the waveform of the multiplied clock output from the multiplied clock output terminal 43. In the operation described below, it is assumed that the lock-up time is reached at time t1.

  Referring to FIG. 12, an input clock event occurs at time t1. Therefore, the clock cycle measuring unit 33 measures the cycle of the input clock at time t1 and supplies the measurement result to the clock cycle change detecting unit 34. The clock cycle change detector 34 checks the frequency variation from time t0 to time t1. At this time, the period of the input clock in the previous cycle (before time t0) and the period of the input clock in the current cycle (from time t1 to time t2) are both times T1. Accordingly, in step S103 of the above-described flowchart, it is determined that the cycle has not fluctuated, and thereafter, it is determined whether a multiplied waveform is being generated.

  Referring to FIG. 12, at time t1, multiplication waveform generation is not performed. Therefore, at time t1, a process for generating a multiplied waveform is executed. As described above, since the lock-up time has elapsed at the current time t1, the multiplied waveform generation unit 35 generates a multiplied waveform, and the process proceeds to an expected clock generation operation. At this time, the expected clock generation unit 37 generates, as an internal event, an expected clock signal that operates in the same cycle as the cycle value observed by the multiplied clock generation unit 31.

  In response to the expected clock generation, the simulation apparatus 10 registers the schedule and ends. At this time, the clock comparison unit 38 detects the occurrence of an expected clock event and determines whether an input clock event has occurred in response to the expected clock event. At time t1, since the input clock is supplied without stopping, the process ends.

  Thereafter, at times t2 to t4, every time an event of the input clock occurs, a determination is made as to whether the period has changed and a determination as to whether a multiplied waveform is being generated. Since the multiplied waveform is generated at time t1, the multiplied clock generated at time t1 is continuously output from time t2 to time t4.

  Referring to (a) of FIG. 12, it is shown that the input clock is stopped at time t5. At this time, an expected clock is output from the expected clock generation unit 37. The clock comparison unit 38 compares the input clock with the expected clock in response to the occurrence of the expected clock event at time t5. Since the input clock is stopped, the clock comparison unit 38 notifies the error processing unit 36 to that effect. The error processing unit 36 performs error processing based on the notification of the stop of the input clock from the clock comparison unit 38. After executing the error process, the indefinite value output is scheduled and the process ends. In this operation, when the supply of the input clock is stopped, the supply stop can be detected as an illegal operation.

[Second Embodiment]
The second embodiment of the present invention will be described below. In the drawing used for the description of the second embodiment, the elements using the same reference numerals as those used in the first embodiment described above have the same configuration and operation as the components of the first embodiment. Therefore, detailed description thereof is omitted.

  FIG. 13 is a block diagram illustrating the configuration of the PLL circuit model 50 according to the second embodiment of the invention. Referring to FIG. 13, the PLL circuit model 50 in the second embodiment is similar to the PLL circuit model 30 in the first embodiment, and further includes a feedback clock cycle variation monitoring unit 51, a feedback clock monitoring unit 52, and a feedback clock supply terminal. 58. The feedback clock cycle fluctuation monitoring unit 51 is fed back the multiplied clock output from the multiplied clock output terminal 43 via the feedback clock supply terminal 58.

  The PLL circuit model 50 of the second embodiment has a feedback clock supply terminal 58 and feeds back the output signal of the PLL circuit model 50 via the CTS. Therefore, the PLL circuit model 50 has a PLL circuit with a phase adjustment function that can match the phases of the external input clock and the operation clock signal of the internal logic, and can be applied to logic simulation of a semiconductor device.

  As shown in FIG. 13, the feedback clock cycle variation monitoring unit 51 includes a feedback clock cycle measurement unit 53 and a feedback clock cycle change detection unit 54. The feedback clock monitoring unit 52 includes an expected feedback clock generation unit 55 and a feedback clock comparison unit 56.

  The feedback clock cycle measuring unit 53 is a functional block that measures the cycle of a multiplied clock (hereinafter referred to as feedback clock) supplied via the feedback clock supply terminal 58. The feedback clock cycle change detection unit 54 is a functional block that determines whether the cycle of the feedback clock is stable based on the measurement value of the feedback clock cycle supplied from the feedback clock cycle measurement unit 53.

  The expected feedback clock generation unit 55 generates an expected feedback clock based on the multiplied set value supplied via the multiplied set value input terminal 41 and the measured value of the input clock period output from the clock period measuring unit 33. It is a functional block. The feedback clock is a clock having the same cycle as the multiplied clock output from the multiplied clock output terminal 43. Therefore, the expected feedback clock generation unit 55 generates an expected feedback clock by the same operation as the multiplied waveform generation unit 35 that generates a multiplied clock.

  The feedback clock comparison unit 56 is a functional block that determines whether or not the expected feedback clock supplied from the expected feedback clock generation unit 55 is synchronized with the feedback clock supplied via the feedback clock supply terminal 58. The delay adding unit 57 is a functional block that generates a delay clock by executing predetermined arithmetic processing on the multiplied clock output from the multiplied waveform generating unit 35.

  The operation of the PLL circuit model 50 in the second embodiment will be described below with reference to the drawings. FIG. 14 is a flowchart illustrating the operation of the second embodiment. Referring to FIG. 14, the operations from step S101 to step S108 are the same as the operations of the first embodiment.

  In step S110 of FIG. 14, the output is output from the multiplied clock output terminal 43 based on the measurement period of the input clock supplied from the clock period measuring unit 33 and the multiplied set value supplied via the multiplied set value input terminal 41. A predicted feedback clock is generated by predicting a clock to which the multiplied clock is fed back. Here, the operation of measuring the period of the input clock is performed in the same manner as in the first embodiment.

  FIG. 15 is a flowchart illustrating the operation of the feedback clock cycle variation monitoring unit 51. Referring to FIG. 15, in step S301, the feedback clock period measurement unit 53 determines whether or not a feedback clock event has occurred. As a result of the determination, if it is detected that an event has occurred, the process proceeds to step S302. If no feedback clock event has occurred, the process ends. To do.

  In step S <b> 302, the feedback clock cycle measurement unit 53 measures the cycle of the feedback clock and supplies the measurement result to the feedback clock cycle change detection unit 54. In step S <b> 303, the feedback clock cycle change detection unit 54 monitors the fluctuation of the feedback clock cycle based on the measurement result supplied from the feedback clock cycle measurement unit 53. Here, when a change in the period of the feedback clock is detected, the feedback clock period change detecting unit 54 notifies the error processing unit 36 that the feedback clock is changing, and the process proceeds to step 304. If the feedback clock has not changed, the process ends.

  In step S <b> 304, the error processing unit 36 performs error processing based on the notification from the feedback clock cycle change detection unit 54. In response to the completion of the error processing in the error processing unit 36, the processing proceeds to step S305. In step S305, the output of the PLL circuit is scheduled and the process ends.

  FIG. 16 is a flowchart illustrating the operation of the feedback clock monitoring unit 52. Referring to FIG. 16, in step S <b> 401, the feedback clock comparison unit 56 determines whether or not an event for generating a predicted feedback clock has occurred based on the signal supplied from the predicted feedback clock generation unit 55. .

  When the event for generating the predicted feedback clock has occurred, the process proceeds to step S402. In step S <b> 402, the feedback clock comparison unit 56 determines whether or not the predicted feedback clock and the input feedback clock supplied via the feedback clock supply terminal 58 are synchronized. Based on the determination, the feedback clock comparison unit 56 determines whether or not the event for supplying the feedback clock is stopped. If no event has occurred, the feedback clock comparison unit 56 notifies the error processing unit 36 of the stoppage of the feedback clock, and the process proceeds to step S403. In step S403, the error processing unit 36 performs error processing based on the notification, and makes the output value of the PLL circuit model 50 undefined. After the error processing by the error processing unit 36, the process proceeds to step S404. In step S404, a schedule is made to make the output value of the PLL circuit model 50 indefinite, and the process ends.

  In a PLL with a phase adjustment function, it is necessary to input a stable clock for the feedback clock as well as the input clock. By generating an event of the predicted feedback clock signal from the frequency measurement result of the input clock and the multiplication setting value, and comparing it with the input feedback clock signal, it is possible to detect an illegal operation of the feedback loop. A plurality of embodiments can be executed in combination when there is no contradiction in the configuration and operation.

FIG. 1 is a block diagram showing a configuration of a conventional logic simulator. FIG. 2 is a flowchart showing the operation of a conventional logic simulator. FIG. 3 is a timing chart showing the operation of the conventional logic simulator. FIG. 4 is a timing chart showing the operation of the conventional logic simulator. FIG. 5 is a block diagram illustrating the configuration of the ethics simulation apparatus of the present invention. FIG. 6 is a block diagram illustrating the configuration of the data storage unit 11. FIG. 7 is a block diagram illustrating the configuration of the program storage unit 12. FIG. 8 is a block diagram illustrating the configuration of a semiconductor device on which a PLL circuit is mounted. FIG. 9 is a block diagram illustrating the configuration of the PLL circuit model according to the first embodiment. FIG. 10 is a flowchart illustrating the operation of the first embodiment. FIG. 11 is a flowchart illustrating the operation of the first embodiment. FIG. 12 is a timing chart illustrating the operation of the first embodiment. FIG. 13 is a block diagram illustrating the configuration of the second embodiment. FIG. 14 is a flowchart illustrating the operation of the second embodiment. FIG. 15 is a flowchart illustrating the operation of the second embodiment. FIG. 16 is a flowchart illustrating the operation of the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus 2 ... Input device 3 ... Display apparatus 4 ... CPU
DESCRIPTION OF SYMBOLS 5 ... Memory 6 ... Input / output interface 7 ... Mass storage device 8 ... Bus 10 ... Simulation device 11 ... Data storage unit 12 ... Program storage unit 21 ... Net list 22 ... Library 23 ... Simulation model 24 ... Logic simulation program 25 ... Semiconductor Device 26 ... Signal processing unit 27 ... PLL circuit 30 ... PLL circuit model 31 ... Multiplication clock generation unit 32 ... Clock monitoring unit 33 ... Clock cycle measurement unit 34 ... Clock cycle change detection unit 35 ... Multiplication waveform generation unit 36 ... Error processing unit 37 ... Expected clock generation unit 38 ... Clock comparison unit 41 ... Multiplication set value input terminal 42 ... Input clock supply terminal 43 ... Multiplication clock output terminal 50 ... PLL circuit model 51 ... Feedback clock cycle variation monitoring unit 52 ... Feedback clock monitoring unit 53 ... Feedback clock cycle measurement unit 54 ... Feedback clock cycle change detection unit 55 ... Expected feedback clock generation unit 56 ... Feedback clock comparison unit 57 ... Delay addition unit 58 ... Feedback clock supply terminal 100 ... Second conventional model 101 ... Clock cycle measurement Reference numeral 102: Clock cycle variation detection part 103: Multiplication waveform generation part 104 ... Error processing part 106 ... Input clock supply terminal DIV: Multiplication set value input terminal OUT: Multiplication clock output terminal

Claims (8)

A simulation program for causing a computer to execute an operation of a circuit including a PLL that outputs at least one output clock based on an input clock using a PLL model indicating the PLL,
(A) reading circuit information related to the circuit and executing a simulation based on the circuit information;
(B) monitoring the supply of the input clock in the simulation and generating an expected clock for monitoring the change of the input clock in response to the start of supply of the input clock to the PLL model ;
(C) prohibiting output of an output clock by the PLL based on a comparison between the expected clock and the input clock;
Comprising
The step (b)
Generating a clock having the same period as the input clock as the expected clock;
Determining whether the expected clock and the input clock are synchronized, and determining that the input clock is stopped when the predicted clock and the input clock are not synchronized;
Scheduling an indefinite value as the PLL circuit output based on determining that the input clock is stopped; and
including
Simulation program for causing execute METHODS into the computer. The simulation program according to claim 1 ,
The step (b)
Identifying a time when the input clock in the simulation is stable as a lockup time, and generating one clock having the same period as the period of the input clock at the lockup time;
A simulation program comprising: generating the predicted clock by repeatedly outputting the one clock. The simulation program according to claim 2 , further comprising:
(D) supplying a feedback clock obtained by feeding back an output clock output from the PLL to the PLL;
(E) generating a predicted feedback clock for determining whether or not the feedback clock has returned; and (f) outputting an output clock from the PLL based on a comparison between the predicted feedback clock and the feedback clock. A step to prohibit ,
The step (f)
Determining that the feedback clock is stopped when the predicted feedback clock and the input feedback clock are not synchronized;
Performing a schedule for making the output value of the PLL undefined when it is determined that the feedback clock is stopped;
Including simulation program. A logic simulation apparatus for simulating the operation of a semiconductor integrated circuit including a PLL circuit,
A storage unit that holds a simulation model and a simulation program, and the simulation model includes a PLL circuit model that is a simulation model corresponding to the PLL circuit;
An arithmetic processing unit that executes circuit simulation according to the procedure shown in the simulation program,
The PLL circuit model is:
An output clock generator for generating an output clock in response to an input clock;
A clock monitoring unit for monitoring the state of the input clock;
The clock monitoring unit
An expected clock generator that generates an expected clock having the same period as the input clock; and the expected clock and the input clock output from the expected clock generator, and the input clock and the expected clock are synchronized with each other. A clock comparison unit that determines whether or not the input clock and the input clock are stopped when the predicted clock and the input clock are not synchronized ;
Including
The output clock generator is
A logic simulation device that schedules an indefinite value as an output of a PLL circuit and stops generation of the output clock in the output clock generation unit based on the determination that the input clock is stopped in the clock monitoring unit . The logic simulation apparatus according to claim 4 ,
Prior Symbol expected clock generator, a logic simulation apparatus cycle of the output clock is in synchronization with the input clock stable time to generate the expected clock, and outputs the estimated clock continuously. The logic simulation apparatus according to claim 5 ,
The output clock generator is
A clock period measuring unit for measuring a clock period of the input clock;
Based on the clock cycle at the current time and the clock cycle at the past time, a change in the cycle of the input clock is detected, and an instruction to prohibit the generation of the output clock is issued when the cycle of the input clock changes. A clock cycle change detector;
A multiplying waveform generating unit that generates the output clock based on the clock period and the multiplying setting value;
An error processing unit that determines whether to output the output clock based on an instruction from the clock cycle change detection unit,
When the clock comparison unit determines that the input clock is stopped, it notifies the error processing unit that the input clock is stopped ,
The error processing unit
Said notification output from the clock comparator unit, or in response to at least one of the instruction outputted from said clock period change detection unit, prohibits output of the output clock output from the遁倍waveform generator Yes Logic simulation device. The logic simulation apparatus according to claim 6 , further comprising:
A feedback clock determination unit that receives a feedback clock to which the output clock is fed back and detects a change in the period of the feedback clock;
A feedback clock monitoring unit for monitoring whether or not the feedback clock is stopped;
The feedback clock determination unit
When the period of the feedback clock changes, the output clock generation unit is instructed to prohibit generation of the output clock,
The feedback clock monitoring unit
When generating an expected feedback clock synchronized with the feedback clock, detecting that the feedback clock is stopped based on a comparison between the predicted feedback clock and the feedback clock, and detecting a stop of the feedback clock And a logic simulation device that instructs the output clock generation unit to prohibit generation of the output clock. The logic simulation apparatus according to claim 7 , wherein
The feedback clock determination unit
A feedback clock period measuring unit for measuring the period of the feedback clock;
The feedback clock cycle measurement unit compares the cycle of the feedback clock measured at the current time with the cycle of the feedback clock measured at the past time, and changes the cycle of the feedback clock based on the comparison result. A feedback clock change detection unit for detecting,
The feedback clock monitoring unit
An expected feedback clock generating unit that generates the predicted feedback clock based on the multiplication setting value and a measured value of the period of the input clock output from the clock period measuring unit;
Based on the comparison between the expected feedback clock and the expected clock, it is detected whether the feedback clock is stopped, and when it is detected that the feedback clock is stopped, the quality clock generation unit A logic simulation device including an expected feedback clock comparison unit that instructs output prohibition of an output clock.

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