JP4641560B2 - Variable gain control circuit and receiver - Google Patents

Description

  The present invention relates to a variable gain control circuit and a receiving apparatus using the same.

FIG. 1 shows a configuration diagram of a direct conversion receiver used in a direct sequence code division multiple access (DS-CDMA) mobile communication system that performs AGC (Automatic Gain Control) control using a conventional analog voltage signal. In the figure, reference numeral 300 denotes an RF-IC including a baseband amplifier unit (variable gain amplifier) (the same applies to other figures).
.

  A signal received from an external antenna of a terminal device (hereinafter simply referred to as a terminal) is differentially amplified by a low noise amplifier 301 and divided into two. After the DC component is cut (C cut) by the capacitor, the orthogonal mixer 302 performs down conversion from the RF signal to the baseband signal at once. At this time, a signal obtained by distributing the local oscillation (LO) signal from the local oscillator 304 into the in-phase component and the quadrature component by the divider 303 is mixed with the RF signal, so that each baseband is in quadrature with the in-phase (I) component. A signal of component (Q) is generated. Each of these baseband signals is subjected to a low-pass filter (LPF) 305 to remove signal power of an interference wave such as an adjacent channel and extract only a desired wave signal. Next, the baseband signal is amplified by the baseband amplifier 306 whose gain is variably controlled by the analog voltage 309. The LPF 307 at the subsequent stage of the baseband amplifier 306 is a filter inserted so that the 50% roll-off characteristic downlink signal on the transmission side has a 100% roll-off characteristic as a total transfer function. After the S / N of the baseband signal is maximized by the LPF 307, the A / D converter 308 performs quantization and converts the analog signal into a digital signal. Here, the analog voltage signal 309 described above is also called an AGC signal, and is controlled from the baseband signal processing unit (not shown) side so that the baseband signal received by the A / D converter 308 always has an optimum dynamic range. Is done.

  However, in the AGC control performed by the analog voltage signal, the component variation and the temperature variation of the baseband amplifier 306 are large, and it is difficult to perform highly accurate AGC control. In particular, the amplitude deviation of the IQ signal affects the BER (Bit Error Rate) characteristic, so that variation is a big problem. In addition, since it is influenced by digital noise on the substrate, an RC LPF (not shown) is required at the AGC input terminal.

  Recently, attention has been paid to a method using a configuration using a PGA (Programmable Gain Amp, hereinafter abbreviated as PGA) that changes by 3-wire serial data setting, instead of the AGC control method using the analog voltage signal 309. Have been bathed. The three-line signals are Data, Clock, and Strobe. The data is serially shifted and fetched in synchronization with the Clock signal, and the fetched data is latched according to the Strobe signal. Since the PGA is digitally controlled, it is difficult to be affected by component variations and temperature variations, and gain settings for each IQ can be realized with high accuracy. High linearity of the baseband amplifier can be achieved by switching individual linear resistors.

JP 2001-36358 A

  As described above, the PGA system has a number of advantages as an AGC control method for a direct conversion receiver, but also has problems as described below.

  FIG. 2 shows a configuration diagram of a direct conversion receiver used in a DS-CDMA mobile communication system that performs AGC control using the PGA method.

  Instead of the AGC control method using the analog voltage signal 309, the 3-wire serial digital data 312 is set and decoded by the PGA control circuit 311 to switch the gain of the baseband amplifier 306 discretely. The DC offset canceller circuit 310 is a circuit that cancels the DC offset by detecting the DC component at the final stage of the baseband amplifier and applying negative feedback in an analog manner (see Patent Document 1). Although omitted in the block diagram of FIG. 1, the DC offset canceller circuit 310 is usually mounted on a direct conversion receiver that performs AGC control using the analog voltage signal described in FIG. 1. As described above, in the PGA system, the PGA control circuit 311 decodes the 3-wire serial digital data 312 and switches the gain of the baseband amplifier 306 discretely. Consider a case where 1 dB is increased from a certain gain to a certain gain.

  This will be briefly described in FIG. 3 for convenience. When the PGA data for the differential amplifier row constituting the baseband amplifier changes from “0111” to “1000”, the PGA control circuit 311 switches the first-stage amplifier, which has been off until now, from 0 dB to 20 dB, and the rest It is assumed that the three-stage amplifier is controlled to be −19 dB less than the current gain. Although the total gain (total gain) only increases by 1 dB after all, step-by-step DC offset occurs due to transistor pair variations by switching the gain discretely in this differential amplifier row. Although the magnitude of this DC offset varies depending on the manufacturing process, it is several mV or more in terms of input. For this reason, when the gain is largely switched in the first stage, a considerably large DC offset occurs in the last stage. This stepwise DC offset component due to gain switching has no effect even if C-cut is performed, and deteriorates the S / N as an interference component in the desired wave signal component.

  FIG. 4 shows how the stepped DC offset component interferes with the desired wave signal. As shown in the figure, the stepped DC offset component is the interference component in the portion where the wideband desired wave signal is hatched by Fourier transform.

  In the circuit of FIG. 2 described above, the DC offset canceller circuit 310 is mounted. However, because of the circuit configuration based on analog negative feedback, the IQ output at the final stage has a waveform as shown in FIG. The large glitch component at the time of gain switching shown in FIG. 5 saturates the A / D converter 308 in FIG. 2 and raises the moving average value for AGC control calculated from the received IQ signal. If the frequency of this glitch increases, it will eventually converge to the AGC value determined by the glitch value. As a result, the AGC control is not correctly performed on the regular reception signal, and the A / D converter 308 is set lower than the optimum level, and the reception characteristics are deteriorated due to the influence of quantization noise.

  In general, in an analog DC offset canceller circuit, the time for the DC level to converge is related to the cutoff frequency of the LPF when DC feedback is performed. If the cutoff frequency of the LPF is about 5 kHz, it takes about 100 μs or more for DC offset convergence. For this reason, recently, a method has been proposed in which, after setting the gain with the PGA, the cutoff frequency of the LPF is temporarily increased to, for example, about 100 k to 200 kHz for about 10 μs to accelerate the convergence of the DC offset. Further, as a countermeasure against a large glitch component that causes a malfunction in AGC control, a method of masking IQ signal data in the period of 10 μs at the output accompanying the above method so as not to generate a waveform as shown in FIG. Has also been proposed.

  On the other hand, the DS-CDMA system is currently standardized in the 3rd Generation Partnership Project (3GPP), and the specification defines a signal when the spreading factor (SF) = 4 as a downlink DPCH signal. Has been. In this case, since the data length of one symbol is slightly over about 1 μs, when the IQ signal is masked for 10 μs as described above, data of about 10 symbols is lost.

  The present invention solves the above-mentioned problems, and an object of the present invention is to provide a variable gain control circuit that performs AGC control of a variable gain amplifier including a plurality of amplifiers whose gains are discretely set by the PGA method. An object of the present invention is to provide a variable gain control circuit capable of reducing the influence of an interference component due to a DC offset generated at the time of gain switching, and a receiving apparatus using the variable gain control circuit.

  Another object of the present invention is to use a PGA system in a direct conversion receiver without missing symbol data when the spreading factor (SF = 4) is small as a downlink DPCH (Dedicated Physical CHannel) signal. Is to reduce the influence of interference components due to the DC offset generated at the time of gain switching, and to realize good reception characteristics.

  A variable gain control circuit according to the present invention is a level for detecting a current amplifier output level in a variable gain control circuit that performs AGC control of a variable gain amplifier composed of a plurality of amplifiers whose gains are discretely set by the PGA method. A detecting unit, a PGA control data table storing PGA data corresponding to a difference between a current amplifier output level and a predetermined amplifier output level, and the variable gain amplifier based on an output of the PGA control data table PGA data generating means for generating PGA data for controlling the gain of the amplifier, and an amplifier generated when discretely switching the gain of the variable gain amplifier from the currently set PGA data to the next scheduled PGA data DC offset cancel data corresponding to the output DC offset voltage is written in advance. A control unit that generates a corresponding DC offset cancellation data by referring to the DC offset cancellation table based on the C offset cancellation table, the currently set PGA data, and the next scheduled PGA data; Means for converting the DC offset cancel data into an analog voltage and adding it to the amplifier output.

  In this variable gain control circuit, the PGA data generation means refers to the PGA control data table to control the gain of the variable gain amplifier in accordance with the difference between the current amplifier level and a predetermined amplifier output level. Generate data. On the other hand, DC offset cancel data corresponding to the DC offset voltage of the amplifier output generated when discretely switching the gain of the variable gain amplifier from the currently set PGA data to the next scheduled PGA data is previously stored. Using the written DC offset cancel table, the control unit generates corresponding DC offset cancel data corresponding to the currently set PGA data and the next scheduled PGA data. The generated DC offset cancel data is converted into an analog voltage and added to the amplifier output.

  According to another aspect, the variable gain control circuit according to the present invention is a variable gain control circuit that performs AGC control of a variable gain amplifier including a plurality of amplifiers whose gains are discretely set by the PGA method. Level detection means for detecting the amplifier output level, gain control means for controlling the gain of the variable gain amplifier corresponding to the difference between the current amplifier output level and a predetermined amplifier output level, and currently set DC offset cancellation in which DC offset cancellation data corresponding to the DC offset voltage of the amplifier output generated when discretely switching the gain of the variable gain amplifier from PGA data to PGA data to be set next is written in advance. Based on the table and the currently set PGA data and the next scheduled PGA data Means for referring to a DC offset cancel table, generating corresponding DC offset cancel data, converting the DC offset cancel data into an analog voltage, and canceling the DC offset of the amplifier output. is there.

  With these configurations, the DC offset can be canceled digitally without using an analog DC offset cancel circuit. That is, a stepwise DC offset component generated when the gain of each stage of the amplifier is discretely switched greatly in the PGA variable gain amplifier can be canceled based on the DC offset cancel data.

  Another variable gain control circuit according to the present invention is a variable gain amplifier provided with an analog DC offset cancel circuit and a mask hold circuit that masks the output of the amplifier and holds the DC level. Is a variable gain control circuit that performs AGC control of a variable gain amplifier including a plurality of stages of amplifiers for which is set. In this variable gain amplifier, the PGA data generation means includes a level detection means for detecting a current amplifier output level, and a variable gain amplifier corresponding to a difference between the current amplifier output level and a predetermined amplifier output level. PGA data for controlling the gain and the operation of the mask hold circuit is generated. The control means includes a DC offset of the amplifier output generated when discretely switching the gain of the variable gain amplifier from the currently set PGA data to the next scheduled PGA data, and a predetermined threshold value. Based on the comparison result, whether or not mask processing by the mask hold circuit is necessary is determined, the timing is controlled so that the PGA data is switched at a predetermined timing, and the DC offset of the DC offset cancel circuit is determined based on the comparison result. The cancel operation is turned ON / OFF, and only when the DC offset exceeds a threshold value, the DC offset cancel circuit temporarily accelerates the convergence of the DC offset, and the amplifier output during the period is masked for a predetermined time. The PGA data generation means is controlled so as to perform the operation.

  In this configuration, when a large DC offset component is not generated, the mask hold circuit is turned off and an amplified signal is output as it is. Only when a large DC offset component is generated, convergence of the DC offset is accelerated and the amplifier output during this period is output. To mask. In this way, when this variable gain amplifier and variable gain control circuit are used in a receiving device, the frequency of reception data loss is reduced, and deterioration of the BER / BLER of the receiver as a whole is prevented. Can do.

  Still another variable gain control circuit according to the present invention is a variable gain control circuit that performs AGC control of a variable gain amplifier composed of a plurality of stages of amplifiers whose gains are discretely set by the PGA method. It is characterized in that the gain switching of each amplifier is controlled so that the gain switching of each stage amplifier has a hysteresis.

  By introducing hysteresis in the gain switching of each amplifier as described above, the point at which a stepped DC offset component is generated, that is, the frequency at which the gain of the variable gain amplifier is switched discretely is greatly reduced.

  In the variable gain control circuit in which the hysteresis control is introduced, it is desirable that the variable range of the amplifier in charge of the minimum variable range among a plurality of amplifiers of the variable gain amplifier is extended. Thereby, the total gain control accompanying the hysteresis control can be performed smoothly as in the conventional case.

  The present invention further provides a receiving apparatus using each of the variable gain control circuits described above.

  For example, one receiving apparatus according to the present invention is a receiving apparatus that performs PGA AGC control on a variable gain amplifier in a receiver used in a mobile communication system, and gains are discretely set by the PGA system. PGA data is stored corresponding to the difference between the current received signal level and a predetermined received signal level, a variable gain amplifier comprising a plurality of stages of amplifiers, a received signal level calculator for calculating the current received signal level DC offset voltage at the last stage of the variable gain amplifier that occurs when the gain is discretely switched from the currently set PGA data to the next scheduled PGA data. Refer to the DC offset cancellation table in which digital data corresponding to the above is written in advance and the PGA control data table. Generating PGA data for controlling a plurality of amplifiers of the variable gain amplifier, and generating a DC offset cancel data by referring to the DC offset cancel table; and analogizing the DC offset cancel data A D / A converter that converts the voltage into a voltage and adds it to the output of the variable gain amplifier.

  With this configuration, a stepwise DC offset component that degrades S / N, which occurs when the gain of each stage of the PGA variable gain amplifier composed of a plurality of stages switches discretely and greatly, is canceled. Can do.

  In the receiving apparatus, more specifically, the PGA control processing unit switches the PGA data at the head of the slot using the receiving slot timing obtained from the baseband signal processing unit separately provided in the receiving apparatus. Thus, when the received signal level calculator performs reception level averaging processing, the received signal level is taken in after a time that can be set by an arbitrary parameter.

  In one embodiment of the present invention, the PGA control processing unit sets a half value of the maximum gain of the variable gain amplifier as an initial value of the PGA data at power-on, and the PGA control data table and the DC offset cancellation table Are limited to a case where the gain increase value is half the maximum gain and a case where the gain of each stage of the amplifier is switched discretely and greatly by the variable gain amplifier. This reduces the table size.

  According to the present invention, in a variable gain control circuit that performs AGC control of a variable gain amplifier composed of a plurality of amplifiers whose gains are discretely set by the PGA method, the influence of a DC offset generated at the time of gain switching is reduced. be able to.

  In particular, when the present invention is applied to a receiving apparatus that performs gain switching using a PGA method for a variable gain amplifier in a receiver, when the gain of each stage of PGA, which has been a problem in the past, is switched discretely, S / It is possible to solve or alleviate the problem that a stepwise DC offset component that degrades N occurs and the large glitch component that occurs at that time causes a problem in the AGC control operation.

  Further, it is possible to eliminate or reduce the problem that a part of the symbol data of the downlink DPCH signal is lost when the spreading factor is small (SF = 4).

  As described above, by overcoming the drawbacks of the PGA system, the AGC control method of the direct conversion receiver used in the DS-CDMA mobile communication system is not easily affected by component variations and temperature variations. Advantages such as that each IQ gain setting can be realized with high accuracy can be fully utilized, and a receiver having good reception characteristics can be realized.

It is a block diagram of the direct conversion receiver used for the DS-CDMA system mobile communication system which performs AGC control with the conventional analog voltage signal. It is a block diagram of the direct conversion receiver used for the DS-CDMA system mobile communication system which performs AGC control by the conventional PGA system. It is explanatory drawing of the cause of DC offset generation | occurrence | production by the gain switch in a PGA system. It is explanatory drawing of the mechanism in which a step-like DC offset component interferes with a desired wave signal. It is explanatory drawing of the influence on IQ output waveform by the gain switching in a PGA system. It is a block diagram which shows the structure of the receiver at the time of using the PGA system direct conversion receiver in the DS-CDMA system mobile communication system based on the 1st Embodiment of this invention. It is a wave form diagram for demonstrating DC offset cancellation operation | movement in this invention. It is a graph which shows the relationship between the gain step at the time of gain switching, and DC offset maximum variation | change_quantity. It is a figure which shows the structural example of the PGA control data table shown in FIG. It is a figure which shows the structural example of the DC offset cancellation table shown in FIG. It is a figure which shows the other structural example of a DC offset cancellation table. It is a block diagram which shows the structure of the receiver which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structural example of the mask effective table in the 2nd Embodiment of this invention. It is a figure which shows the structural example of the PGA baseband amplifier part in the 3rd Embodiment of this invention. It is a graph which shows the mode of the gain switching of each stage of the baseband amplifier part by the conventional control method. It is a graph which shows the mode of the gain switching of each stage of the baseband amplifier part by the control method of the 3rd Embodiment of this invention.

<First Embodiment>
The principle of the first embodiment of the present invention is that an analog offset cancellation is performed by digitally canceling a stepped DC offset component generated by digitally setting a gain by the PGA method. This is based on the idea that the problem of operation can be solved and AGC control can be ideally realized.

  A first embodiment of the present invention will be described below with reference to the drawings.

  FIG. 6 is a block diagram showing a configuration of a receiving apparatus when a PGA direct conversion receiver is used in the DS-CDMA mobile communication system according to the first embodiment of the present invention. In FIG. 6, as described above in the prior art, the signal received from the external antenna of the terminal is differentially amplified by the low noise amplifier 301 and divided into two. After the DC component of the differentially amplified signal is cut into C, the quadrature mixer 302 down-converts the RF signal to the baseband signal all at once. At this time, since the LO signal from the local oscillator 304 is mixed with the signal obtained by dividing the LO signal into the in-phase component and the quadrature component by the divider 303, in-phase component and quadrature component signals are generated in the baseband, respectively. From these baseband signals, the LPF 305 removes the signal power of interference waves such as adjacent channels, and only the desired wave signal is extracted. Subsequently, the set 3-wire serial digital data 312 is decoded by the PGA control circuit 311, and the baseband signal is amplified by discretely switching the gain of the baseband amplifier 306. The LPF 307 is a filter inserted in order to make a 50% roll-off characteristic downlink signal on the transmission side have a 100% roll-off characteristic as a general transfer function. After the S / N of the baseband signal is maximized by the LPF 307, the A / D converter 308 performs quantization and converts the analog signal into a digital signal. This quantized signal is sent to the finger processing unit & path search unit 319 constituting the baseband signal processing unit, and is not described here, but is subjected to decoding processing including RAKE combining and error correction. To correctly demodulate the downlink signal from the base station.

  Here, the AGC control method using the PGA method in the present invention will be described in detail.

  The IQ baseband signal quantized by the A / D converter 308 is subjected to digital signal processing in the reception signal level calculator 314 in parallel with the processing in the finger processing unit & path search unit 319. When the received signal level calculator 314 calculates the received signal level, the received signal level calculator 314 performs an averaging process in order to remove the influence of the instantaneous change in the received envelope level that is Rayleigh distributed due to fading. At that time, the PGA control processing unit 315 performs the above processing with an averaging time that can be arbitrarily set using the averaging time as a parameter. The PGA control processing unit 315 can be configured by, for example, a digital signal processor (DSP). This parameter is set based on simulation or actual measurement data.

  The PGA control processing unit 315 compares a predetermined received signal level value with the current received level calculated by the received signal level calculator 314 so that the A / D converter 308 has an optimum input level. In accordance with the comparison result, the optimum PGA data is selected from the PGA control data table 317 and sent to the PGA data generator 318. The PGA data generator 318 adds other bits such as an address bit to the received data, and generates 3-wire serial digital data 312 to be supplied to the PGA control circuit 311.

  FIG. 9 shows a configuration example of the PGA control data table 317. This table predetermines PGA data to be adopted for the difference between the current value of the received signal level and the optimum value. Although the table values in the figure are shown as variables for convenience, they are actually specific numerical values (the same applies to other table figures described later).

  Here, when it is assumed that the maximum gain of the baseband amplifier 306 is 80 dB, the first AGC initial pull-in operation after power-on is considered. In this case, since an initial cell search operation is performed, it is necessary to be able to receive P-SCH, S-SCH, and P-CPICH that are always transmitted from the base station. The PGA control processing unit 315 sets 40 dB, which is half of the maximum gain of the baseband amplifier 306, as an initial value of the PGA data. At this time, if the received signal level calculated by the received signal level calculator 314 is larger than a predetermined value of the received signal level, the gain is decreased accordingly, and if smaller, the gain is increased accordingly.

  That is, the PGA data in the PGA control data table 317 can be limited to PGA data whose gain change amount corresponds to a half value (40 dB) of the maximum gain. On the other hand, in an actual mobile communication environment, the instantaneous reception level varies by nearly 20 to 30 dB due to Rayleigh fading, but as described above, the reception signal level calculator 314 performs an averaging process to remove this influence. So no problem.

  On the other hand, the DC offset cancellation table 316 is generated when the gain is discretely switched from the currently set PGA data to the next scheduled PGA data, as shown in FIG. Digital data corresponding to the DC offset voltage at the final stage is written in advance. Since the PGA control processing unit 315 recognizes both the currently set PGA data and the next set PGA data, the optimum DC offset cancel data is selected by referring to the DC offset cancel table 316. The data is sent to the D / A converter 313. The D / A converter 313 converts the DC offset cancel data into an analog voltage and adds it to the IQ output signal of the direct conversion receiver.

  Here, the PGA control processing unit 315 controls the timing so that the PGA data is switched at the head of the slot using the reception slot timing obtained from the finger processing unit & path search unit 319. However, since a series of operations of decoding the 3-wire serial digital data 312 by the PGA control circuit 311 and discretely switching the gain of the baseband amplifier 306 is performed by an analog circuit, the DC offset voltage generated at the IQ output is reduced. The timing is slightly different, and it is difficult to completely synchronize with the DC offset cancel voltage from the D / A converter 313. Therefore, a slight glitch component that cannot be canceled occurs. This can be solved by taking the received data as received data after several tens of ns so as not to include the glitch component when the received signal level calculator 314 performs reception level averaging processing. Even if a DPCH signal having a spreading factor (SF) = 4 is received, as described above, since the data length of one symbol is slightly over 1 μs, there is almost no loss of received data compared to the prior art. A stepwise DC offset component caused by the PGA method that degrades the S / N can be removed. It should be noted that the value of the elapsed time before the reception data capture start can be arbitrarily set as a parameter in the PGA control processing unit 315 in advance. FIG. 7 shows IQ output waveforms in the above series of operations.

  Again, the DC offset cancellation table 316 will be examined. As described above, the DC offset cancel table 316 indicates the DC offset voltage at the final stage that is generated when the gain is discretely switched from the currently set PGA data to the next scheduled PGA data. It is necessary to write corresponding digital data in advance. As the contents of this table, if all cases where arbitrary data of PGA changes to arbitrary data are written, the amount of data becomes considerable. Also, a considerable number of measurements are required to create the table. However, in practice, the amount of data that needs to be written in advance can be considerably reduced. This will be described below.

  As described above, a stepwise DC offset is generated due to the variation of transistor pairs in the differential amplifier row constituting the baseband amplifier. Therefore, as shown in the graph of FIG. 8, when the total gain decreases, the fluctuation amount of the DC offset voltage at the final stage hardly changes. That is, it is only necessary to consider the case where the total gain increases. Therefore, it is only necessary to write in the DC offset cancel table 316 of FIG. 10 when the next PGA data is larger than the current PGA data. As in the case of the PGA control data table 317, the PGA data to be written to the table can be limited to data corresponding to half the maximum gain (40 dB) at the maximum.

  FIG. 11 shows another configuration example of the DC offset cancellation table 316. In this example, the tables 316a and 316b are used together. As can be seen from the graph of FIG. 8, if the DC offset amount is determined according to the gain increase amount, the DC offset cancellation table 316a includes the current PGA data and the next PGA data as in the DC offset cancellation table 316 of FIG. Instead of referencing, it may be configured to refer to the difference between the current PGA data and the next PGA data. In this case, the number of entries in the table can be greatly reduced. However, there may be an exceptionally large DC offset in the combination of specific current PGA data and next PGA data although the number is small as described above. That is, in the method of decoding by the PGA control circuit 311 and switching the gain of the baseband amplifier 306 discretely, there is a case where a considerably large DC offset occurs in the final stage even when the gain is changed by 1 dB. This phenomenon occurs when the gain of each stage amplifier switches discretely and greatly in a PGA-type baseband amplifier section composed of a plurality of stages. For example, the first stage PGA amplifier in FIG. 3 switches from 0 dB to 20 dB. This is a phenomenon that occurs only in a limited case. This can be dealt with by a table 316b that separately defines offset cancellation amounts for such combinations. Such a combination of the specific current PGA data and the next PGA data and the DC offset amount at that time are known in advance and can be incorporated in the table 316b.

  As described above, the number of data to be written in advance in the DC offset cancellation table 316 can be considerably reduced as described above.

<Second Embodiment>
The second embodiment of the present invention has a problem that the conventional analog DC offset cancel operation has a problem with respect to the stepped DC offset component generated by setting the gain digitally by the PGA method. It proposes an appropriate coping method to solve.

  Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 12 is a block diagram showing a configuration of a receiving apparatus when a PGA direct conversion receiver is used in a DS-CDMA mobile communication system according to the second embodiment of the present invention. In FIG. 12, as described above in the prior art, the signal received from the external antenna of the terminal is differentially amplified by the low noise amplifier 301 and divided into two. After the DC component is C-cut, the orthogonal mixer 302 performs down-conversion from the RF signal to the baseband signal at once. At this time, since the LO signal from the local oscillator 304 is mixed with the signal obtained by dividing the LO signal into the in-phase component and the quadrature component by the divider 303, in-phase component and quadrature component signals are generated in the baseband, respectively. From these baseband signals, the LPF 305 removes signal power of interference waves such as adjacent channels, and extracts only the desired wave signal.

  Subsequently, the 3-wire serial digital data 312 is set, decoded by the PGA control circuit 311, and the baseband signal is amplified by discretely switching the gain of the baseband amplifier 306. The LPF 307 is a filter inserted in order to make a 50% roll-off characteristic downlink signal on the transmission side have a 100% roll-off characteristic as a total transfer function. After the S / N of the baseband signal is maximized by the LPF 307, the A / D converter 308 performs quantization and converts the analog signal into a digital signal. The quantized signal is sent to a finger processing unit & path search unit 319 that constitutes a baseband signal processing unit, and is not described here, but is subjected to decoding processing including RAKE combining and error correction. Correctly demodulate the downlink signal from the base station. Further, the quantized signal is subjected to digital signal processing in the reception signal level calculator 314 in parallel with the processing in the finger processing unit & path search unit 319. When the received signal level calculator 314 calculates the received signal level, the received signal level calculator 314 performs an averaging process in order to remove the influence of the instantaneous change in the received envelope level that is Rayleigh distributed due to fading. At that time, the PGA control processing unit 315 performs the above processing with an averaging time that can be arbitrarily set using the averaging time as a parameter. This parameter is set based on simulation or actual measurement data. The operations up to here are the same as those in the first embodiment. The 3-wire serial digital data 312 is generated by the PGA data generation unit 318 in response to an instruction from the PGA control processing unit 315. Also in the second embodiment, the PGA control data table 317 is used as in the first embodiment.

  The circuit shown in FIG. 12 has a DC offset canceller circuit 310 as in the prior art, and a mask hold circuit 320 at the subsequent stage of the baseband amplifier 306. The mask hold circuit 320 has a function of masking the IQ signal data output from the baseband amplifier 306 and holding the DC level.

  Here, the mechanism of the second embodiment will be described.

  The problem with the direct conversion receiver using the PGA method is that, as described above, the stepped DC offset component that degrades the S / N and the A / D converter 308 are saturated, causing a problem in the AGC control operation. It is a big glitch ingredient. On the other hand, as in the prior art, the cutoff frequency of the LPF is temporarily increased to, for example, about 100 k to 200 kHz for about 10 μs to accelerate the convergence of the DC offset, and the IQ signal data for this 10 μs period is output at the output. In the case of masking, there is a problem that the received data signal is missing when the spreading factor (SF) = 4. Therefore, in the second embodiment, when a large DC offset component that degrades the S / N is not generated, the mask hold circuit 320 is turned off and an IQ signal is output as it is, and a large DC offset component that degrades the S / N. As long as this occurs, the LPF cutoff frequency is temporarily increased to about 100 k to 200 kHz for about 10 μs as in the prior art to accelerate the convergence of the DC offset, and the IQ signal data for this 10 μs period is obtained. Mask on output. By doing so, the frequency of reception data loss is reduced, and the deterioration of the BER / BLER of the receiver as a total is prevented.

  As described above, a large stepwise DC offset occurs when the total gain increases, and when the gain of the amplifier at each stage is discrete in the PGA baseband amplifier section composed of a plurality of stages. This is a phenomenon that occurs only in a limited case, such as when a large switching occurs.

  Therefore, stepwise DC offset fluctuation data and the DC offset threshold value that degrades the S / N can be grasped by actually measuring in advance. Since the PGA control processing unit 315 recognizes both the currently set PGA data and the next set PGA data, a combination of the current PGA data and the next PGA data in which a DC offset exceeding such a threshold value occurs. Is stored in a mask validation table 321 as shown in FIG. When the PGA data is changed, the PGA control processing unit 315 refers to the mask validation table 321 to turn on / off the analog DC offset cancel operation of the related art, and at the PGA data generator 318, turns on / off the flag. Is added to generate 3-wire serial digital data 312. This 3-wire serial PGA data 312 is decoded by the PGA control circuit 311 mounted in the direct conversion receiver, and the mask processing is performed with the ON / OFF flag set to ON only in the case of the combination stored in the mask validation table 321. Is enabled, and for other combinations, the ON / OFF flag is turned OFF and the mask processing is disabled.

  Note that the DC offset cancel table 316 shown in FIG. 10 is used instead of the mask validation table 321, and the offset cancel amount (equivalent to the offset amount) obtained by the PGA control processing unit 315 by referring to the table is set as a threshold value. It may be determined whether mask processing is necessary or not. In this case, specifically, the analog DC offset cancel operation of the prior art is turned ON / OFF by the threshold determination in the PGA control processing unit 315, and the ON / OFF flag is set in the PGA data generator 318. In addition, PGA data is generated. Further, a flag value (1 or 0) is stored in advance in a table corresponding to the current PGA data and the next PGA data, and the PGA control processing unit 315 obtains the flag value by referring to this. Good. Further, the mask validation table 321 stores the combination of the current PGA data and the next PGA data when the mask is validated. Conversely, the mask invalidation table stores the combination of PGA data when the mask is invalidated. (Not shown). In this specification, the mask validation table and the mask invalidation table are collectively referred to as a mask table.

  In addition, since a large glitch component that causes a problem in the AGC control operation is usually generated with a large stepped DC offset, as described above, the cutoff frequency of the LPF is set to 100 k to about 10 μs as in the prior art. This can be dealt with by masking the IQ signal data during the period of 10 μs in the output while temporarily raising the DC offset to about 200 kHz.

<Third Embodiment>
Subsequently, a third embodiment of the present invention will be described. In the present embodiment, a mechanism for reducing the frequency at which a stepwise DC offset component, which is the original cause of deteriorating S / N, is introduced.

  The idea in the present embodiment is as follows. In the actual mobile communication environment, the frequency at which the total gain of the baseband amplifier unit greatly increases with one PGA data setting is frequently performed because the reception signal level calculator 314 performs the averaging process as described above. Does not happen. Therefore, what actually becomes a problem is a change of about several dB as a total gain. As a result, a stepwise DC offset component that degrades the S / N is generated because the gain of the amplifier at each stage is discrete in the PGA baseband amplifier unit configured as described above with reference to FIG. It is a case where it switches greatly.

  Therefore, the inventor of the present application does not switch the gains of the amplifiers in each stage until the gain change amount is larger than that in the conventional case when the total gain changes by about several dB. The present inventors have conceived of providing hysteresis characteristics at the point where the gains of the PGAs are discretely switched.

  FIG. 14 shows a configuration example of the PGA baseband amplifier unit in the third embodiment. In this example, it is assumed that the baseband amplifier unit is configured by a PGA including four stages of amplifiers, and the total gain range is 72 dB. For example, PGA1 has a discrete gain switch of 10/15/20 dB, PGA2 has a discrete gain switch of −20 / −10 / 1/10/15 dB, PGA3 has a gain switch of 1 to 24 dB in 1 dB steps, and PGA4 has a 1 Assume that discrete gain switching of / -14 / -1 / -15 / 9/4 dB is performed. In this case, according to the conventional control method, gain switching at each stage as shown in FIG. 15-A is performed in order to change the total gain from 0 dB to 72 dB with variable 1 dB steps. The horizontal axis of the graph in the figure is a control word corresponding to the PGA data, and here is in steps of 1 word 1 dB.

  Here, in the baseband amplifier 306, the gain range of the PGA 3 that switches in 1 dB steps is expanded by 6 dB to be expanded to 1 to 30 dB, and a hysteresis width of 6 dB is given to the point where the gain of the PGA in each stage is switched discretely. Also in this case, as shown in FIG. 15B, the total gain range is configured as a 1 dB step variable baseband amplifier unit as in FIG. 15-A. Hysteresis means that the path of gain switching control differs between forward and backward, and control is performed such that the path on the side that rejects changes from the current state as much as possible is taken. For example, in the example of PGA2, when the total gain is increased from the 0 dB side, the gain is conventionally switched from −20 dB to −10 dB at 12 dB. The gains of other PGAs 1, 3, and 4 are switched in conjunction with this. (Because PGA 3 is in charge of a change of 1 dB in the minimum unit, it is always changed when the total gain is changed.) The same applies to the change in the opposite direction. That is, for example, when the total gain decreases from 24 dB, the gain of all PGA switches at 12 dB. Therefore, when a relatively small change in the total gain occurs around 12 dB, gain switching of all stages frequently occurs. The same applies to the point of total gain in which other multiple stages are simultaneously switched.

  However, in the hysteresis control, considering the example of FIG. 15-B, when the total gain increases from the 0 dB side by over 12 dB, the gain switching of the PGAs 1, 2 and 4 is performed until the total gain reaches 18 dB due to the benefit of hysteresis. Does not happen. The gain increase (6 dB) during that period is handled by the PGA 3 whose gain change range is expanded. A large DC offset which causes a problem is not caused by a sequential 1 dB gain change of only PGA3. Of course, if the total gain further increases and exceeds 18 dB, the gain change of all stages occurs, but the frequency of the simultaneous change of a plurality of PGAs is reduced due to the margin of 6 dB. The same applies to reverse changes. For example, even if the total gain is reduced from 24 dB to 18 dB, the gain switching of the PGAs 1, 2, and 4 does not occur, and the gain switching of all stages occurs only when the gain falls below 12 dB.

  In this way, by introducing hysteresis in gain switching at each stage, a stepwise DC offset component that degrades S / N occurs, that is, the frequency at which the gain of the PGA is switched discretely is greatly reduced. . The setting of the hysteresis width of the PGA baseband amplifier unit is not limited to 6 dB, and can be set to an arbitrary value in advance by the PGA control processing unit 315. In the PGA data setting unit 318, as a setting parameter value It is transmitted as a 3-wire serial PGA data string 312. The PGA control circuit 311 can switch with the set hysteresis width when the gain of the baseband amplifier 306 is discretely switched by decoding this PGA data string and recognizing the parameter value. By executing the above operation, it is possible to reduce the frequency of occurrence of stepped DC offset components that degrade the original S / N.

  As described above, in the third embodiment, the deterioration of the BER / BLER of the receiver as a total is reduced by reducing the frequency at which a stepwise DC offset component that degrades the original S / N due to mask processing is generated. Can be prevented. This embodiment can be employed independently of the first and second embodiments described above, but can also be used in combination.

DESCRIPTION OF SYMBOLS 300 ... RF IC, 301 ... Low noise amplifier, 302 ... Quadrature mixer, 304 ... Local oscillator, 303 ... Divider, 306 ... Baseband amplifier, 308 ... A / D converter, 309 ... Analog voltage signal, 310 ... DC offset canceller circuit 311 ... Control circuit, 312 ... 3 line serial digital data, 313 ... Converter, 314 ... Received signal level calculator, 315 ... Control processing unit, 316, 316a, 316b ... DC offset cancel table, 316a ... Offset cancel table, 317 ... Control data table, 318 ... Data generator, 319 ... Finger processing unit & path search unit, 320 ... Mask hold circuit, 321 ... Mask validation table

Claims (10)

In a variable gain control circuit that performs AGC control of a variable gain amplifier composed of a plurality of amplifiers whose gains are discretely set by the PGA method,
Level detection means for detecting the current amplifier output level;
PGA data generating means for generating PGA data for controlling the gain of the variable gain amplifier based on a difference between a current amplifier output level and a predetermined amplifier output level;
DC offset cancel data corresponding to the DC offset voltage of the amplifier output generated when discretely switching the gain of the variable gain amplifier from the currently set PGA data to the next scheduled PGA data is written in advance. A DC offset cancellation table,
Control means for referring to the DC offset cancellation table based on the currently set PGA data and the next scheduled PGA data and generating corresponding DC offset cancellation data;
Means for converting the generated DC offset cancellation data into an analog voltage and adding it to the amplifier output;
Means for performing gain switching control of each stage amplifier so as to have hysteresis in each gain switching of the plurality of stage amplifiers of the variable gain amplifier ;
A variable gain control circuit comprising:   In a variable gain control circuit that performs AGC control of a variable gain amplifier composed of a plurality of amplifiers whose gains are discretely set by the PGA method,
  Level detection means for detecting the current amplifier output level;
  Gain control means for controlling the gain of the variable gain amplifier in response to a difference between a current amplifier output level and a predetermined amplifier output level;
  DC offset cancel data corresponding to the DC offset voltage of the amplifier output generated when discretely switching the gain of the variable gain amplifier from the currently set PGA data to the next scheduled PGA data is written in advance. A DC offset cancellation table,
  Based on the currently set PGA data and the next scheduled PGA data, the DC offset cancel table is referred to, corresponding DC offset cancel data is generated, and the DC offset cancel data is converted into an analog voltage. Means for canceling the DC offset of the amplifier output;
  Means for performing gain switching control of each stage amplifier so as to have hysteresis in each gain switching of the plurality of stage amplifiers of the variable gain amplifier;
  A variable gain control circuit comprising:   3. The variable gain control circuit according to claim 1, wherein a half value of the maximum gain of the variable gain amplifier is set as an initial value of the PGA data, and the maximum gain of the data written in the table in advance is set. A variable gain control circuit characterized in that the amount of change is limited to PGA data corresponding to half of the maximum gain.   3. The variable gain control circuit according to claim 1, wherein data written to the DC offset cancellation table is limited to data when a total gain of the variable gain amplifier increases. A variable gain amplifier composed of a plurality of amplifiers whose gains are discretely set by the PGA method;
A received signal level calculator for calculating the current received signal level;
DC offset cancel data corresponding to the DC offset voltage of the amplifier output generated when discretely switching the gain of the variable gain amplifier from the currently set PGA data to the next scheduled PGA data is written in advance. A DC offset cancellation table,
PGA data for controlling a plurality of amplifiers of the variable gain amplifier is generated according to a difference between a current received signal level and a predetermined received signal level, and DC offset cancellation is performed with reference to the DC offset cancellation table. Control means for generating data;
A D / A converter that converts the DC offset cancel data into an analog voltage and adds the analog voltage to the output of the variable gain amplifier;
The control means is a receiving device that performs gain switching control of each stage of the amplifier so that the gain switching of each of the plurality of stages of the variable gain amplifier has hysteresis.   6. The receiving device according to claim 5, wherein the control means uses a receiving slot timing obtained from a baseband signal processing unit separately provided in the receiving device, so that the PGA data is switched at the head of the slot. , And when the reception signal level calculator performs reception level averaging processing, the reception device captures the received data after a lapse of time that can be set by an arbitrary parameter in advance.   6. The receiving apparatus according to claim 5, wherein the control means compares a received signal level calculated by the received signal level calculator with a predetermined received signal level value, and corresponds to a difference between the levels. A gain PGA data value is selected from the PGA control data table, and digital data corresponding to the DC offset voltage at the final stage of the variable gain amplifier generated by the selected PGA control data is selected from the DC offset cancel table. A receiving device.   6. The receiving apparatus according to claim 5, wherein the control means sets a half value of the maximum gain of the variable gain amplifier as an initial value of the PGA data at power-on, and the PGA control data table and the DC offset cancellation The pre-written contents of the table should be limited to the case where the gain increase value is half of the maximum gain at the maximum and the case where the gain of each stage of the amplifier is switched discretely and greatly by the variable gain amplifier. A receiving device.   6. The receiving apparatus according to claim 5, wherein data to be written to the DC offset cancellation table is limited to data when a total gain of the variable gain amplifier is increased. 6. The receiving apparatus according to claim 5 , wherein the hysteresis width can be set to an arbitrary value in advance by the control means.

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