JP4640559B2

JP4640559B2 - Inverter device

Info

Publication number: JP4640559B2
Application number: JP2000388567A
Authority: JP
Inventors: 英史上田
Original assignee: Yaskawa Electric Corp
Current assignee: Yaskawa Electric Corp
Priority date: 2000-12-21
Filing date: 2000-12-21
Publication date: 2011-03-02
Anticipated expiration: 2020-12-21
Also published as: JP2002191179A

Description

【０００１】
【発明の属する技術分野】
本発明はインバータ装置の電流検出器に関するものであり、かつ被検出電流の流れる抵抗端子間電圧により電流検出を行う小型軽量のインバータ装置に関するものである。
【０００２】
【従来の技術】
図１１は特開平１０―１２３１８４による従来例である電流検出回路を示したものである。
図１１による従来例においては、第１のオペアンプＯＰ１の出力端子が第２のオペアンプＯＰ２の非反転入力端子に接続されているとともに、オペアンプＯＰ２の帰還回路には高耐圧のＰチャネルＭＯＳＦＥＴのゲート・ソースが直列に接続されている。また、オペアンプＯＰ１、ＯＰ２の駆動電源である正電源Ｖ＋の正極とＰチャネルＭＯＳＦＥＴのソースとの間には、抵抗Ｒ１０６が接続されている。なおＰチャネルＭＯＳＦＥＴのドレインとインバータの主回路直流電源の負極Ｎとの間には、前記同様に検出抵抗Ｒ１０７が接続されている。
この回路において、シャント抵抗Ｒｓの電圧はオペアンプＯＰ１により増幅され、そのオペアンプ出力電圧Ｖ１０５がオペアンプＯＰ２に入力される。オペアンプＯＰ２はボルテージフォロワであるため、抵抗Ｒ１０６に印加される電圧Ｖ１０６が次の数式で示される一定値になるようにＰチャネルＭＯＳＦＥＴのゲート電圧を調整する。
Ｖ１０６＝Ｒ１０６×ｉ１０２＝(Ｖ+)−Ｖ１０５
このとき、抵抗Ｒ１０７はＭＯＳＦＥＴを介して抵抗Ｒ１０６と直列に接続されているため、抵抗Ｒ１０７にも抵抗Ｒ１０６と同じ電流ｉ１０２が流れることとなり、その結果として相電流の検出電圧Ｖ１０４はＶ１０６と等しくなる。
つまりこの回路では相電流の検出電圧Ｖ１０４が、オペアンプＯＰ２によって以下の数式で示される一定値となるように調整されることとなり、このＶ１０４から逆算してＶ１０５が検出できることとなり、いいかえれば相電流が検出できることとなる。
Ｖ１０４（＝Ｖ１０６）＝Ｒ１０６×ｉ１０２＝(Ｖ+)−Ｖ１０５
またＩＧＢＴトランジスタＴ１およびＴ２のスイッチング動作に伴って抵抗Ｒ１０６と抵抗Ｒ１０７との間に発生する高電圧を、ＰチャネルパワーＭＯＳＦＥＴのドレイン・ソース間電圧として吸収することで、高電圧側からの電圧信号Ｖ１０５についてのアナログ電圧信号伝送を実現している。
【０００３】
【発明が解決しようとする課題】
図１１に示す従来例ではシャント抵抗Ｒｓにおいては、出力電流にシャント抵抗Ｒｓの抵抗端子間電圧を乗じた熱ロスが発生する。
このためインバータ装置の電力容量増加に伴い定格出力電流が大きくなれば同一の抵抗端子間電圧を得ようとした場合、シャント抵抗Ｒｓで発生する熱ロスが増加するので抵抗サイズを大型化する必要があり、インバータ装置小型化のネックとなる。
またシャント抵抗Ｒｓの抵抗値を十分小さくして抵抗の小型化を図れば抵抗端子間電圧が大きく低下するため、抵抗端子間電圧増幅用オペアンプの入力オフセットや入力バイアス電流等の影響で電流検出誤差が大きくなるという問題がある。
また小型抵抗を並列接続して抵抗全体の放熱面積を増やし全体抵抗値をも下げれば、抵抗端子間電圧をある程度小さくするだけで抵抗の小型化を図ることはできる。しかしこの場合にも検出電圧が小さくなった分だけ前記同様に検出誤差の影響は大きくなり、また並列接続ゆえに各抵抗を相互につなぐパターン抵抗分の影響が生じ検出誤差がさらに増加してしまうという問題もある。
本発明は、このような問題点を解決するためになされたものであり、大きな被検出電流に対しても誤差の少ない、しかも超小型の電流検出器を備えた超小型のインバータ装置を提供することにある。
【０００４】
【課題を解決するための手段】
上記問題を解決するため本発明は請求項１記載のように、半導体スイッチング素子と前記半導体スイッチング素子に逆並列接続される還流ダイオードとの並列接続体を２個直列接続してなる直列接続体と、前記並列接続体を2個直列接続した接続点がインバータ装置の出力端子に接続され、前記直列接続体を直流電源の正負極間に２個以上並列接続してなるインバータ装置において、２以上の抵抗を並列接続してなる第１の抵抗群であり、かつインバータ装置の出力電流が流れる前記第１の抵抗群と、インバータ装置の出力電流が前記第１の抵抗群を流れる際に前記並列接続された各抵抗の端子間に発生する各抵抗端子間電圧を増幅し、かつ各増幅値を加算して前記出力電流を検出する手段を備えたことを特徴とする。
【０００５】
また請求項２記載のように、半導体スイッチング素子と前記半導体スイッチング素子に逆並列接続される還流ダイオードとの並列接続体を２個直列接続してなる直列接続体と、前記並列接続体を2個直列接続した接続点がインバータ装置の出力端子に接続され、前記直列接続体を直流電源の正負極間に２個以上並列接続してなるインバータ装置において、前記直列接続体の前記接続点とインバータ装置の前記出力端子との間に挿入接続された第１の抵抗と、差動増幅器と、前記差動増幅器の負側入力端子と前記第１の抵抗の一方の側の端子との間に挿入接続された第４の抵抗と、前記差動増幅器の負側入力端子と出力端子との間に接続された第３の抵抗と、前記第１の抵抗のもう一方の側の端子と前記差動増幅器の正側入力端子との間に挿入接続された第２の抵抗と、基準電圧と、前記基準電圧と前記差動増幅器の正側入力端子との間に接続された第５の抵抗とからなる構成体と、前記構成体を２個以上有し、かつ各構成体中の第１の抵抗を互いに並列接続し、かつ各構成体中の差動増幅器各出力を加算する加算器とからなる電流検出手段を備えたことを特徴とする。
【０００６】
また請求項３記載のように、半導体スイッチング素子と前記半導体スイッチング素子に逆並列接続される還流ダイオードとの並列接続体を２個直列接続してなる直列接続体と、前記並列接続体を2個直列接続した接続点がインバータ装置の出力端子に接続され、前記直列接続体を直流電源の正負極間に２個以上並列接続してなるインバータ装置において、２以上の抵抗を並列接続してなる第１の抵抗群であり、かつ前記直列接続体の前記接続点とインバータ装置の出力端子との間に挿入接続された前記第１の抵抗群と、インバータ装置の出力電流が前記第１の抵抗群を流れる際に前記並列接続された各抵抗の端子間に発生する各抵抗端子間電圧を増幅し、かつ各増幅値を加算して前記出力電流を検出する手段を備えたことを特徴とする。
【０００７】
また請求項４記載のように、半導体スイッチング素子と前記半導体スイッチング素子に逆並列接続される還流ダイオードとの並列接続体を２個直列接続してなる直列接続体と、前記並列接続体を２個直列接続した接続点がインバータ装置の出力端子に接続され、前記直列接続体を直流電源の正負極間に２個以上並列接続してなるインバータ装置において、２以上の抵抗を並列接続してなる第１の抵抗群であり、かつ２個以上並列接続された前記直列接続体と前記直流電源の負極端子との間に挿入接続された前記第１の抵抗群と、インバータ装置の出力電流が前記第１の抵抗群を流れる際に前記並列接続された各抵抗の端子間に発生する各抵抗端子間電圧を増幅し、かつ各増幅値を加算して前記出力電流を検出する手段を備えたことを特徴とする。
また請求項５記載のように、半導体スイッチング素子と前記半導体スイッチング素子に逆並列接続される還流ダイオードとの並列接続体を２個直列接続してなる直列接続体と、前記並列接続体を２個直列接続した接続点がインバータ装置の出力端子に接続され、前記直列接続体を直流電源の正負極間に２個以上並列接続してなるインバータ装置において、２以上の抵抗を並列接続してなる第１の抵抗群であり、かつ２個以上並列接続された前記直列接続体と前記直流電源の正極側端子との間に挿入接続された前記第１の抵抗群と、インバータ装置の出力電流が前記第１の抵抗群を流れる際に前記並列接続された各抵抗の端子間に発生する各抵抗端子間電圧を増幅し、かつ各増幅値を加算して前記出力電流を検出する手段を備えたことを特徴とする。
また請求項６記載のように、前記インバータ装置において、２個以上並列接続された前記直列接続体と前記直流電源の負極側端子との間に前記第１の抵抗群を挿入接続し、かつ前記各直列接続体を構成する負極側並列接続体である半導体スイッチング素子および還流ダイオードと前記第１の抵抗群との接続点において還流ダイオードのみその接続を切り放し前記直流電源の負極側端子に接続したことを特徴とする。また請求項７のように、前記第１の抵抗群が電流を導通させる端子対と電圧信号を取り出す端子対とをもつ４端子構造一体型の抵抗としたことを特徴とする。
【０００８】
請求項１記載の構成において、インバータ装置の被検出電流は全て並列接続された第１の抵抗群を流れることとなる。ここで第１の抵抗群を構成する各抵抗はいずれも小型であり、そのために抵抗値も小さい。また一般的には全て同一抵抗が使用されている。各抵抗はプリント基板上に実装され、これら各抵抗の両側端子はプリント基板上の銅パターンにより同極側端子どうしがそれぞれ相互接続されている。銅パターンは小さなインピーダンスを有するが、第１の抵抗群の各抵抗値が小さいので前記銅パターンによるインピーダンスの影響は相対的に大きくなり検出誤差も増加する。
この影響を無くそうとすれば一般的には抵抗端子から直接に端子間電圧を検出すればよいのだが、複数抵抗が並列接続された場合では全抵抗の全体共通の直接端子というものは存在しないので抵抗端子から直接に端子間電圧を検出することはできず、従って検出した抵抗端子間電圧には必ず銅パターンによるインピーダンスの影響が含まれてしまうこととなる。
【０００９】
ところが請求項１記載の構成では並列接続された第１の抵抗群につき、各抵抗ごとにその端子から直接に端子間電圧を検出している。従って検出された抵抗端子間電圧には銅パターンによるインピーダンスの影響が含まれることはない。
例えば並列接続された第１の抵抗群が３個の抵抗による並列接続の場合、図７で示すように銅パターンによるインピーダンスの影響で各抵抗を流れる電流はそれぞれが異なった値となってしまう。ここで図８に示すように第１の抵抗群をそれぞれＲ１ａ，Ｒ１ｂ，Ｒ１ｃとし各抵抗を流れる電流をＩａ，Ｉｂ，Ｉｃとすると前記各抵抗の端子間電圧はＶａ（＝Ｒ１ａ×Ｉａ），Ｖｂ（＝Ｒ１ｂ×Ｉｂ），Ｖｃ（＝Ｒ１ｃ×Ｉｃ）となる。
【００１０】
またＲ１ａの両端子は第２の抵抗群の一つであるＲ２ａ，第４の抵抗群の一つであるＲ４ａを介してそれぞれ差動増幅器の正側入力端子および負側入力端子へと接続されており，同様にＲ１ｂの両端子はＲ２ｂ，Ｒ４ｂを介して，Ｒ１ｃの両端子はＲ２ｃ，Ｒ４ｃを介してそれぞれ差動増幅器の正負各入力端子に接続されている。また差動増幅器の正側入力端子は第５の抵抗Ｒ５を介して基準電圧となるグランドに接続され、負側入力端子は第３の抵抗Ｒ３を介して差動増幅器出力端子に接続されている。そしてＲ２ａ，Ｒ２ｂ，Ｒ２ｃ，Ｒ４ａ，Ｒ４ｂ，Ｒ４ｃは全て等しい抵抗値としており、またＲ３とＲ５の抵抗値も等しくしている。
Ｒ１ａとＲ２ａとの接続点では銅パターンのインピーダンスによりコモンモード電圧Ｖｃａが発生し、Ｒ１ａとＲ４ａとの接続点ではこのＶｃａに抵抗端子間電圧Ｖａを加えた電圧（Ｖｃａ＋Ｖａ）が発生している。同様にＲ１ｂとＲ２ｂとの接続点ではコモンモード電圧Ｖｃｂが発生し、Ｒ１ｂとＲ４ｂとの接続点ではこのＶｃｂに抵抗端子間電圧Ｖｂを加えた電圧（Ｖｃｂ＋Ｖｂ）が発生し、同じくＲ１ｃとＲ２ｃとの接続点ではコモンモード電圧Ｖｃｃが発生し、Ｒ１ｃとＲ４ｃとの接続点ではこのＶｃｃに抵抗端子間電圧Ｖｃを加えた電圧（Ｖｃｃ＋Ｖｃ）が発生している。
【００１１】
ここで差動増幅器の正負両入力端子電圧は等しくなるが、この入力端子電圧をＶｉｎとすると、Ｒ３を流れる電流（Ｉ３）は

となる。
【００１２】
この（１）式からわかるように、作動増幅器出力Ｖｏには銅パターンによるインピーダンスの影響をまったく含まない第１の抵抗群の端子間電圧のみが電圧増幅検出されることとなり、しかもその端子間電圧に関しては第１の抵抗群の全体並列抵抗値（＝Ｒ１ａ／３）に被検出電流を乗じた値ではなく、一つ相当の抵抗値（＝Ｒ１ａ）に被検出電流を乗じた端子間電圧となるので３倍もの端子間電圧を得ることが可能となる。従って銅パターンによる影響誤差がなく、また検出電圧も大きくとれるので差動増幅器の入力オフセット電圧等の影響をも低減した検出精度の高い電流検出器を構成することが可能となる。
【００１３】
請求項２記載の構成においても、インバータ装置の被検出電流は全て並列接続された第１の抵抗群を流れることになる。ここで第１の抵抗群を構成する各抵抗は前記同様いずれも小型であり、そのために抵抗値も小さい。また一般的には全て同一抵抗値となっている。また各抵抗はプリント基板上に実装され、これら各抵抗ごとにその両側端子と差動増幅器正負入力端子間には第２の抵抗および第４の抵抗がそれぞれ挿入接続されている。また各差動増幅器の正入力端子と基準電圧であるグランドとの間には第５の抵抗が接続され、各差動増幅器負入力端子と出力端子との間には第３の抵抗が接続されている。
ここで抵抗値において
Ｒ２＝Ｒ４
Ｒ３＝Ｒ５
とし第１の抵抗群のうち例えば抵抗Ｒ１ａを流れる電流をＩａとすれば、当該差動増幅器出力電圧（Ｖｏａ）は、
Ｖｏａ＝−Ｒ１ａ×Ｉａ×Ｒ３／Ｒ４
となる。そしてこのような構成が第１の抵抗群の各抵抗ごとにあり、各抵抗ごとに上記のような差動増幅器出力電圧を得られるので、これらを加算器により全て加え合わせればその出力であるＶｏは

となり、請求項１記載の場合と同様に抵抗の小型化、銅パターンの影響の削除、大きな抵抗端子間電圧を得ることができる。
【００１４】
請求項３記載の構成においては、被検出電流が流れる第１の抵抗群を並列接続により構成し、この各抵抗端子間電圧を増幅して、増幅された各抵抗端子間電圧を加算器により全て加え合わせたその合計値から電流検出を行うことにより、銅パターンの影響の削除、大きな端子間電圧を得ることによる増幅器等に内在する検出誤差の低減、および抵抗の小型化とをあわせて実現することができる。請求項４および請求項５記載の構成は、請求項３記載の構成における電流検出器の挿入位置を変更しただけのものであり、その検出原理および作用効果は前記と同様である。
【００１５】
また請求項６記載の構成は、請求項４記載の構成における電流検出器の挿入位置において、かつ直流電源の負極側に接続された半導体スイッチング素子と還流ダイオードとの並列接続体においてその還流ダイオードの接続位置を変更したものである。この構成は請求項４または請求項５記載の構成に比べ、インバータ装置の出力電力が小さい場合でも、第１の抵抗群を流れる被検出電流の導通時間幅を十分に確保できるという効果がある。また請求項１ないし請求項６記載のいずれの構成においても並列接続された第１の抵抗群の各抵抗に関し、被検出電流が流れる電流端子部と被検出電圧出力部とを別々に備えた４端子構造の抵抗（図９および図１０）を使用することで、抵抗をプリント基板に実装する際に電流端子部の半田接続で発生する誤差電圧の影響をも削除した検出誤差の極めて少ない電流検出器を構成できるという効果も期待できる。
【００１６】
【発明の実施の形態】
以下、本発明の第１の実施例を図１に基づいて説明する。１は商用交流電源、２〜７は全波整流ブリッジを構成する整流用ダイオード、８〜１３はインバータ主回路を構成するＩＧＢＴトランジスタ、１４〜１９は各ＩＧＢＴトランジスタ素子に逆並列接続される還流ダイオード、２０はＵ相電流を検出する電流検出器、２１はＶ相の電流検出器、２２はＷ相の電流検出器、２３はモータ、２４はオペアンプ、２５は直流電源、Ｒ１１、Ｒ１２、Ｒ１３はＵ相電流を分流する抵抗、Ｕ、Ｖ、Ｗはインバータ装置の各々の出力端子である。
次に動作を説明する。図１において、インバータのＵ相出力電流（以下これをＩｕとする）は抵抗値の小さい小型抵抗Ｒ１１、Ｒ１２，Ｒ１３を流れて外部負荷であるモータ２３へと供給される。この電流Ｉｕは、抵抗Ｒ１１、Ｒ１２，Ｒ１３とを分離分割して流れることとなるが、この各抵抗を流れる電流をそれぞれＩｕ１，Ｉｕ２，Ｉｕ３とすると各抵抗端子間にはこの電流に比例した端子間電圧がそれぞれに発生しており、また銅パターンによるインピーダンスの影響でコモンモード端子電圧Ｖｕ１，Ｖｕ２，Ｖｕ３もそれぞれ発生している。
従って、例えば抵抗Ｒ１１の両側端子では、それぞれにＶｕ１と（Ｖｕ１−Ｉｕ１×Ｒ１１）の端子電圧が発生していることとなる。
この端子電圧は抵抗Ｒ２１、抵抗Ｒ４１を介してそれぞれオペアンプ２４の正負入力端子に接続されている。同様に抵抗Ｒ１２の端子電圧は抵抗Ｒ２２、抵抗Ｒ４２を介して、抵抗Ｒ１３の端子電圧は抵抗Ｒ２３、抵抗Ｒ４３を介してそれぞれオペアンプ２４の正負入力端子に接続されている。
そして各抵抗の抵抗値を
Ｒ１１＝Ｒ１２＝Ｒ１３
Ｒ４１＝Ｒ４２＝Ｒ４３＝Ｒ２１＝Ｒ２２＝Ｒ２３
Ｒ３＝Ｒ５
に設定するとオペアンプ２４の出力電圧Ｖｕｏは

となるので、このＶｕｏにはプリント基板の銅パターンによるインピーダンスの影響を含まない抵抗の端子間電圧のみが増幅抽出され、この値から被検出電流Ｉｕを高精度で検出することが可能となる。
【００１７】
次に本発明の第２の実施例を図２に基づいて説明する。図２において、インバータのＵ相出力電流（以下これをＩｕとする）は抵抗値の小さい小型抵抗Ｒ１１、抵抗Ｒ１２，抵抗Ｒ１３を流れて外部負荷であるモータ２３へと供給される。この電流Ｉｕは、抵抗Ｒ１１、Ｒ１２，Ｒ１３とを分離分割して流れることとなるが、この各抵抗を流れる電流をそれぞれＩｕ１，Ｉｕ２，Ｉｕ３とすると各抵抗端子間にはこの電流に比例した端子間電圧がそれぞれに発生しており、また銅パターンによるインピーダンスの影響でコモンモード端子電圧Ｖｕ１，Ｖｕ２，Ｖｕ３もそれぞれ発生している。
従って例えば抵抗Ｒ１１の両側端子では、各々にＶｕ１と（Ｖｕ１−Ｉｕ１×Ｒ１１）の端子電圧とが発生していることとなる。
この端子電圧は抵抗Ｒ２１、抵抗Ｒ４１を介してそれぞれオペアンプ２６の正負入力端子に接続されている。同様に抵抗Ｒ１２の端子電圧は抵抗Ｒ２２、抵抗Ｒ４２を介してそれぞれオペアンプ２７の正負入力端子に、抵抗Ｒ１３の端子電圧は抵抗Ｒ２３、抵抗Ｒ４３を介してそれぞれオペアンプ２８の正負入力端子に接続されている。
【００１８】
そして各抵抗の抵抗値を
Ｒ１１＝Ｒ１２＝Ｒ１３
Ｒ４１＝Ｒ４２＝Ｒ４３＝Ｒ２１＝Ｒ２２＝Ｒ２３
Ｒ３１＝Ｒ３２＝Ｒ３３＝Ｒ５１＝Ｒ５２＝Ｒ５３
に設定するとオペアンプ２６、２７、２８の各出力電圧Ｖｏ１、Ｖｏ２，Ｖｏ３は

となる。さらに
Ｒ６１＝Ｒ６２＝Ｒ６３
と設定することで，オペアンプ２９によりこれらＶｏ１，Ｖｏ２，Ｖｏ３とを加算しその出力電圧Ｖｕｏとして

を得ることができる。
【００１９】
このＶｕｏにはプリント基板の銅パターン等による影響を含まない抵抗の端子間電圧のみが増幅抽出されることになり、しかも大きな端子間電圧を得ることができるので被検出電流Ｉｕを高精度で検出することが可能となる。
次に本発明の第３の実施例を図３に基づいて説明する。
これは第１の実施例である図１の構成に対し検出抵抗Ｒ１１，Ｒ１２，Ｒ１３の位置を直流電源の負極側に配置して被検出電流を変更しただけのものであり検出構成および効果は前記と同様である。
次に本発明の第４の実施例を図４に基づいて説明する。
これは第１の実施例である図１の構成に対し検出抵抗Ｒ１１，Ｒ１２，Ｒ１３の位置を直流電源の正極側に配置して被検出電流を変更しただけのものであり検出構成および効果は前記と同様である。
【００２０】
次に本発明の第５の実施例を図５に基づいて説明する。これは第２の実施例である図２の構成に対し検出抵抗Ｒ１１，Ｒ１２，Ｒ１３の位置を直流電源の負極側に配置して被検出電流を変更し、かつ加算器を第２の実施例におけるようなオペアンプではなくてＣＰＵ３０のＡ／Ｄ変換ポートからオペアンプ１、２、３の各出力電圧を取り込みＣＰＵ３０の内部で演算加算して電流検出を行う構成としている。
次に本発明の第６の実施例を図６に基づいて説明する。
これは第２の実施例である図２の構成に対し検出抵抗３１，３２，３３に４端子構造の抵抗（図９および図１０）を使用し、また検出抵抗３１、３２、３３の位置を直流電源の負極側に配置して被検出電流を変更し、かつ還流ダイオード１７、１８、１９のアノード側端子を直流電源の負極側に接続変更したものである。４端子構造の抵抗により、その電流端子部の半田接続で発生する当該部分のインピーダンスの影響を削除することができ、より精度の高い電流検出を行うことができる。またこの、電流を導通させる端子対と電圧信号を取り出す端子対とをもつ４端子構造一体型の抵抗は前記第１の実施例ないし第５の実施例においてもそのまま適用することが可能であり、この場合には前記同様にさらに精度の高い電流検出を行うことが可能となる。
【００２１】
【発明の効果】
以上述べたように本発明によれば、被検出大電流用の検出抵抗を並列接続された小型かつ抵抗値の小さな抵抗のみで構成でき、また検出用抵抗が並列接続でありながらプリント基板の銅パターンインピーダンスによる影響を含まない、従って抵抗の端子間電圧のみを増幅抽出でき、さらには小さな抵抗値でありながら大きな抵抗端子間電圧をも得ることができ、従って増幅器の入力オフセット電圧等の影響も低減できるという効果がある。すなわち大きな被検出電流に対しても誤差の少ない、しかも小型サイズの電流検出器を構成でき、超小型のインバータ装置を提供できる。
【図面の簡単な説明】
【図１】本発明の第１の実施例におけるインバータ装置の電流検出器の構成図を示したもの
【図２】本発明の第２の実施例におけるインバータ装置の電流検出器の構成図を示したもの
【図３】本発明の第３の実施例におけるインバータ装置の電流検出器の構成図を示したもの
【図４】本発明の第４の実施例におけるインバータ装置の電流検出器の構成図を示したもの
【図５】本発明の第５の実施例におけるインバータ装置の電流検出器の構成図を示したもの
【図６】本発明の第６の実施例におけるインバータ装置の電流検出器の構成図を示したもの
【図７】第１の抵抗群を並列接続した際におけるプリント基板の銅パターンの影響を示したもの
【図８】請求項１記載の構成における本発明の作用効果の説明用構成図を示したもの
【図９】電流端子部と検出電圧出力部とを別々に備えた４端子構造による抵抗の外観図を示したもの
【図１０】４端子構造による抵抗の内部回路図を示したもの
【図１１】従来例におけるインバータ装置の電流検出器の構成図を示したもの
【符号の説明】
１商用交流電源
２、３、４、５、６、７整流用ダイオード
８、９、１０、１１、１２、１３ＩＧＢＴトランジスタ
１４、１５、１６、１７、１８、１９還流ダイオード
２０、２１、２２電流検出器
２３モータ
２４、２６、２７、２８、２９オペアンプ
２５直流電源
３０ＣＰＵ
３１、３２、３３４端子構造の抵抗
Ｒ３、Ｒ５、Ｒ７、Ｒ８、Ｒ１１、Ｒ１２、Ｒ１３、Ｒ２１Ｒ、Ｒ２２、Ｒ２３抵抗
Ｒ３１、Ｒ３２、Ｒ３３、Ｒ４１、Ｒ４２、Ｒ４３、Ｒ５１、Ｒ５２、Ｒ５３、Ｒ６１、Ｒ６２、Ｒ６３抵抗
Ｒ１ａ、Ｒ１ｂ、Ｒ１ｃ並列接続された第１の抵抗群を構成する各抵抗
Ｒ２ａ、Ｒ４ａ、Ｒ２ｂ、Ｒ４ｂ、Ｒ２ｃ、Ｒ４ｃ抵抗
Ｚａ０、Ｚｂ０、Ｚｃ０、Ｚａ１、Ｚｂ１、Ｚｃ１プリント基板の銅パターンによるインピーダンス
Ｕインバータ装置のＵ相出力端子
Ｖインバータ装置のＶ相出力端子
Ｗインバータ装置のＷ相出力端子
Ｔ１、Ｔ２ＩＧＢＴトランジスタ
Ｔ４、Ｔ５、Ｔ６ＭＯＳＦＥＴ
Ｒ１０１、Ｒ１０２、Ｒ１０３、Ｒ１０４、Ｒ１０５、Ｒ１０６、Ｒ１０７抵抗
Ｒｓシャント抵抗
ＧＤＵ１、ＧＤＵ２ゲート駆動回路
ＯＰ１、ＯＰ２オペアンプ
１０１反転ゲート
１０２、１０３制御電源[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a current detector of an inverter device, and also relates to a small and light inverter device that performs current detection using a voltage between resistance terminals through which a current to be detected flows.
[0002]
[Prior art]
FIG. 11 shows a conventional current detection circuit according to Japanese Patent Laid-Open No. 10-123184.
In the conventional example shown in FIG. 11, the output terminal of the first operational amplifier OP1 is connected to the non-inverting input terminal of the second operational amplifier OP2, and the feedback circuit of the operational amplifier OP2 includes the gate and gate of a high breakdown voltage P-channel MOSFET. Sources are connected in series. A resistor R106 is connected between the positive electrode of the positive power supply V + that is the driving power supply for the operational amplifiers OP1 and OP2 and the source of the P-channel MOSFET. The detection resistor R107 is connected between the drain of the P-channel MOSFET and the negative electrode N of the main circuit DC power supply of the inverter in the same manner as described above.
In this circuit, the voltage of the shunt resistor Rs is amplified by the operational amplifier OP1, and the operational amplifier output voltage V105 is input to the operational amplifier OP2. Since the operational amplifier OP2 is a voltage follower, the gate voltage of the P-channel MOSFET is adjusted so that the voltage V106 applied to the resistor R106 becomes a constant value represented by the following equation.
V106 = R106 × i102 = (V +) − V105
At this time, since the resistor R107 is connected in series with the resistor R106 via the MOSFET, the same current i102 as the resistor R106 flows through the resistor R107. As a result, the detection voltage V104 of the phase current becomes equal to V106. .
In other words, in this circuit, the phase current detection voltage V104 is adjusted by the operational amplifier OP2 to be a constant value represented by the following formula, and V105 can be detected by calculating backward from this V104. It can be detected.
V104 (= V106) = R106 × i102 = (V +) − V105
Further, by absorbing the high voltage generated between the resistors R106 and R107 in association with the switching operation of the IGBT transistors T1 and T2 as the drain-source voltage of the P-channel power MOSFET, a voltage signal from the high voltage side is obtained. The analog voltage signal transmission for V105 is realized.
[0003]
[Problems to be solved by the invention]
In the conventional example shown in FIG. 11, in the shunt resistor Rs, a heat loss is generated by multiplying the output current by the voltage across the resistance terminals of the shunt resistor Rs.
For this reason, if the same rated voltage is obtained as the rated output current increases as the power capacity of the inverter device increases, the heat loss generated by the shunt resistor Rs increases, so the resistor size must be increased. Yes, it becomes a bottleneck in downsizing the inverter device.
In addition, if the resistance value of the shunt resistor Rs is made sufficiently small to reduce the resistance, the voltage between the resistance terminals is greatly reduced. Therefore, the current detection error is influenced by the input offset, input bias current, etc. of the operational amplifier for voltage amplification between the resistance terminals. There is a problem that becomes larger.
If a small resistor is connected in parallel to increase the heat radiation area of the entire resistor and lower the overall resistance value, it is possible to reduce the size of the resistor only by reducing the voltage between the resistance terminals to some extent. However, in this case as well, the influence of the detection error is increased as the detection voltage is reduced, and the effect of the pattern resistance that connects the resistors to each other due to the parallel connection is generated, and the detection error further increases. There is also a problem.
The present invention has been made to solve such a problem, and provides an ultra-small inverter device having a small-sized current detector with little error even for a large current to be detected. There is.
[0004]
[Means for Solving the Problems]
In order to solve the above problem, the present invention provides a serial connection body comprising two parallel connection bodies of a semiconductor switching element and a free-wheeling diode connected in reverse parallel to the semiconductor switching element. In the inverter apparatus in which two or more parallel connection bodies are connected in series, connected to the output terminal of the inverter apparatus, and two or more series connection bodies are connected in parallel between the positive and negative electrodes of the DC power supply . A first resistor group in which resistors are connected in parallel, and the first resistor group in which an output current of the inverter device flows, and the parallel connection when the output current of the inverter device flows in the first resistor group And a means for amplifying a voltage between the resistance terminals generated between the terminals of the resistors and adding the amplification values to detect the output current .
[0005]
Further, as in claim 2, a series connection body in which two parallel connection bodies of a semiconductor switching element and a free-wheeling diode connected in reverse parallel to the semiconductor switching element are connected in series, and two of the parallel connection bodies In the inverter device in which two or more series connection bodies are connected in parallel between the positive and negative electrodes of a DC power source, the connection points connected in series are connected to the output terminal of the inverter device, and the connection points of the series connection body and the inverter device A first resistor inserted between the output terminals of the differential amplifier, a differential amplifier, and a negative input terminal of the differential amplifier and a terminal on one side of the first resistor. A fourth resistor, a third resistor connected between a negative input terminal and an output terminal of the differential amplifier, a terminal on the other side of the first resistor, and the differential amplifier Inserted into the positive input terminal of A structure comprising a second resistor connected, a reference voltage, a fifth resistor connected between the reference voltage and the positive input terminal of the differential amplifier, and two of the structures And a current detection means including an adder for connecting the outputs of the differential amplifiers in each component and connecting the first resistors in each component in parallel with each other. .
[0006]
Further, according to a third aspect of the present invention, there are provided a series connection body formed by serially connecting two parallel connection bodies of a semiconductor switching element and a reflux diode connected in reverse parallel to the semiconductor switching element, and two parallel connection bodies. In an inverter device in which two or more series connection points are connected in parallel between the positive and negative electrodes of a DC power source, the connection point connected in series is connected to the output terminal of the inverter device, and two or more resistors are connected in parallel. The first resistor group that is inserted and connected between the connection point of the series connection body and the output terminal of the inverter device, and the output current of the inverter device is the first resistor group. Means for amplifying the voltage between the resistance terminals generated between the terminals of the resistors connected in parallel when flowing through the circuit, and adding the amplified values to detect the output current .
[0007]
Further, as in claim 4 , a series connection body formed by connecting two parallel connection bodies of a semiconductor switching element and a free-wheeling diode connected in reverse parallel to the semiconductor switching element, and two of the parallel connection bodies In an inverter device in which two or more series connection points are connected in parallel between the positive and negative electrodes of a DC power source, the connection point connected in series is connected to the output terminal of the inverter device, and two or more resistors are connected in parallel. The first resistor group inserted and connected between the series connection body connected in parallel with two or more and the negative terminal of the DC power source, and the output current of the inverter device is the first resistance group . And a means for amplifying a voltage between the resistance terminals generated between the terminals of the resistors connected in parallel when flowing through one resistance group, and adding the amplified values to detect the output current. Features The
Further, as in claim 5 , a series connection body formed by connecting two parallel connection bodies of a semiconductor switching element and a free-wheeling diode connected in reverse parallel to the semiconductor switching element, and two of the parallel connection bodies In an inverter device in which two or more series connection points are connected in parallel between the positive and negative electrodes of a DC power source, the connection point connected in series is connected to the output terminal of the inverter device, and two or more resistors are connected in parallel. 1 resistor group, and the first resistor group inserted and connected between the series connection body connected in parallel with two or more and the positive terminal of the DC power source, and the output current of the inverter device is Means for amplifying the voltage between the resistance terminals generated between the terminals of the resistors connected in parallel when flowing through the first resistance group, and adding the amplified values to detect the output current. With features To do.
Further, according to claim 6, in the inverter device, the first resistor group is inserted and connected between the series connection body connected in parallel with two or more and the negative electrode side terminal of the DC power source, and Only the free wheel diode is disconnected at the connection point between the semiconductor switching element and the free wheel diode, which are the negative electrode side parallel connected bodies constituting each series connection body, and the first resistor group, and is connected to the negative terminal of the DC power supply. It is characterized by. According to a seventh aspect of the present invention, the first resistor group is a four-terminal structure integrated resistor having a terminal pair for conducting current and a terminal pair for extracting a voltage signal.
[0008]
In the configuration according to claim 1, all the detected currents of the inverter device flow through the first resistor group connected in parallel. Here, each of the resistors constituting the first resistor group is small in size, and therefore has a small resistance value. In general, all the same resistors are used. Each resistor is mounted on a printed circuit board, and both terminals of each resistor are connected to each other on the same polarity side by a copper pattern on the printed circuit board. Although the copper pattern has a small impedance, since each resistance value of the first resistor group is small, the influence of the impedance by the copper pattern becomes relatively large, and the detection error also increases.
In order to eliminate this effect, it is generally sufficient to detect the voltage between the terminals directly from the resistance terminal. However, when multiple resistors are connected in parallel, there is no direct terminal common to all resistors. Therefore, the voltage between the terminals cannot be detected directly from the resistance terminal, and therefore, the detected voltage between the resistance terminals always includes the influence of the impedance due to the copper pattern.
[0009]
However, in the configuration of the first aspect, the inter-terminal voltage is detected directly from the terminal for each resistor for the first resistor group connected in parallel. Therefore, the detected voltage between the resistance terminals does not include the influence of impedance due to the copper pattern.
For example, when the first resistor group connected in parallel is a parallel connection of three resistors, the currents flowing through the resistors have different values due to the influence of the impedance due to the copper pattern, as shown in FIG. Here, as shown in FIG. 8, when the first resistor group is R1a, R1b, R1c, and the currents flowing through the resistors are Ia, Ib, Ic, the terminal voltage of each resistor is Va (= R1a × Ia), Vb (= R1b × Ib), Vc (= R1c × Ic).
[0010]
Both terminals of R1a are connected to the positive side input terminal and the negative side input terminal of the differential amplifier via R2a which is one of the second resistance group and R4a which is one of the fourth resistance group, respectively. Similarly, both terminals of R1b are connected to the positive and negative input terminals of the differential amplifier through R2b and R4b, and both terminals of R1c are connected through R2c and R4c, respectively. The positive input terminal of the differential amplifier is connected to the ground serving as the reference voltage via the fifth resistor R5, and the negative input terminal is connected to the differential amplifier output terminal via the third resistor R3. . R2a, R2b, R2c, R4a, R4b, and R4c all have the same resistance value, and the resistance values of R3 and R5 are also equal.
At the connection point between R1a and R2a, a common mode voltage Vca is generated due to the impedance of the copper pattern, and at the connection point between R1a and R4a, a voltage (Vca + Va) obtained by adding the resistance terminal voltage Va to this Vca is generated. Similarly, a common mode voltage Vcb is generated at the connection point between R1b and R2b, and a voltage (Vcb + Vb) obtained by adding the voltage Vb between the resistance terminals to Vcb is generated at the connection point between R1b and R4b. A common mode voltage Vcc is generated at the connection point of R1c and R4c, and a voltage (Vcc + Vc) obtained by adding the voltage Vc between the resistance terminals to Vcc is generated at the connection point of R1c and R4c.
[0011]
Here, the positive and negative input terminal voltages of the differential amplifier are equal, but if this input terminal voltage is Vin, the current (I3) flowing through R3 is

It becomes.
[0012]
As can be seen from the equation (1), only the voltage between the terminals of the first resistor group that does not include the influence of the impedance due to the copper pattern is detected in the operational amplifier output Vo, and the voltage between the terminals is detected. Is not the value obtained by multiplying the entire parallel resistance value (= R1a / 3) of the first resistor group by the detected current, but the terminal voltage obtained by multiplying the resistance value equivalent to one (= R1a) by the detected current. Therefore, it is possible to obtain a voltage between terminals that is three times as large. Therefore, there is no influence error due to the copper pattern, and the detection voltage can be increased. Therefore, it is possible to configure a current detector with high detection accuracy in which the influence of the input offset voltage of the differential amplifier is reduced.
[0013]
Also in the configuration of the second aspect, all the currents to be detected of the inverter device flow through the first resistor group connected in parallel. Here, each of the resistors constituting the first resistor group is small in size as described above, and therefore has a small resistance value. In general, they all have the same resistance value. Each resistor is mounted on a printed circuit board, and a second resistor and a fourth resistor are inserted and connected between the both side terminals and the differential amplifier positive / negative input terminal for each resistor. Further, a fifth resistor is connected between the positive input terminal of each differential amplifier and the ground which is the reference voltage, and a third resistor is connected between each negative input terminal of the differential amplifier and the output terminal. ing.
Here, in the resistance value, R2 = R4
R3 = R5
For example, if the current flowing through the resistor R1a in the first resistor group is Ia, the differential amplifier output voltage (Voa) is
Voa = −R1a × Ia × R3 / R4
It becomes. Such a configuration is provided for each resistor of the first resistor group, and the differential amplifier output voltage as described above can be obtained for each resistor. Therefore, if these are all added by an adder, the output is Vo. Is

Thus, similarly to the case of the first aspect, the resistance can be reduced, the influence of the copper pattern can be eliminated, and a large resistance terminal voltage can be obtained.
[0014]
According to the third aspect of the present invention, the first resistor group through which the current to be detected flows is configured by parallel connection, the voltage between the resistance terminals is amplified, and all the amplified voltage between the resistance terminals is all added by the adder. By performing current detection from the total value added together, it is possible to eliminate the influence of the copper pattern, reduce the detection error inherent in amplifiers by obtaining a large voltage between terminals, and reduce the resistance. be able to. The configurations according to claims 4 and 5 are obtained by changing the insertion position of the current detector in the configuration according to claim 3 , and the detection principle and operational effects are the same as described above.
[0015]
The structure of claim 6 wherein the of the freewheeling diode in parallel connection of the insertion position of the current detector in the configuration according to claim 4, and a semiconductor switching element connected to the negative electrode side of the DC power supply and a reflux diode The connection position is changed. This configuration has an effect that the conduction time width of the detected current flowing through the first resistor group can be sufficiently secured even when the output power of the inverter device is small, as compared with the configuration of the fourth or fifth aspect. Further, in each of the configurations of claims 1 to 6, each of the resistors of the first resistor group connected in parallel is provided with a current terminal portion through which a detected current flows and a detected voltage output portion separately provided. By using the resistor of the terminal structure (Fig. 9 and Fig. 10), current detection with extremely low detection error that eliminates the effect of error voltage generated by solder connection of the current terminal when mounting the resistor on the printed circuit board The effect that a vessel can be configured can also be expected.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIG. 1 is a commercial AC power source, 2 to 7 are rectifying diodes constituting a full-wave rectification bridge, 8 to 13 are IGBT transistors constituting an inverter main circuit, and 14 to 19 are free-wheeling diodes connected in reverse parallel to the respective IGBT transistor elements. , 20 is a current detector for detecting a U-phase current, 21 is a V-phase current detector, 22 is a W-phase current detector, 23 is a motor, 24 is an operational amplifier, 25 is a DC power supply, R11, R12, and R13 are Resistors U, V, and W for diverting the U-phase current are output terminals of the inverter device.
Next, the operation will be described. In FIG. 1, the U-phase output current of the inverter (hereinafter referred to as Iu) flows through small resistors R11, R12, R13 having small resistance values and is supplied to the motor 23 which is an external load. The current Iu flows separately from the resistors R11, R12, and R13. If the currents flowing through the resistors are Iu1, Iu2, and Iu3, terminals between the resistance terminals are proportional to the current. Inter-mode voltages are generated respectively, and common mode terminal voltages Vu1, Vu2, and Vu3 are also generated due to the influence of impedance due to the copper pattern.
Therefore, for example, terminal voltages Vu1 and (Vu1−Iu1 × R11) are generated at both terminals of the resistor R11.
This terminal voltage is connected to the positive and negative input terminals of the operational amplifier 24 through resistors R21 and R41, respectively. Similarly, the terminal voltage of the resistor R12 is connected to the positive and negative input terminals of the operational amplifier 24 via the resistors R22 and R42, and the terminal voltage of the resistor R13 is connected to the positive and negative input terminals of the operational amplifier 24 via the resistors R23 and R43, respectively.
And the resistance value of each resistor is R11 = R12 = R13
R41 = R42 = R43 = R21 = R22 = R23
R3 = R5
When set to, the output voltage Vuo of the operational amplifier 24 is

Therefore, in this Vuo, only the terminal voltage of the resistor not including the influence of the impedance due to the copper pattern of the printed circuit board is amplified and extracted, and the detected current Iu can be detected with high accuracy from this value.
[0017]
Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 2, the U-phase output current of the inverter (hereinafter referred to as Iu) flows through small resistors R11, R12, and R13 having small resistance values and is supplied to the motor 23 that is an external load. The current Iu flows separately from the resistors R11, R12, and R13. If the currents flowing through the resistors are Iu1, Iu2, and Iu3, terminals between the resistance terminals are proportional to the current. Inter-mode voltages are generated respectively, and common mode terminal voltages Vu1, Vu2, and Vu3 are also generated due to the influence of impedance due to the copper pattern.
Therefore, for example, Vu1 and (Vu1−Iu1 × R11) terminal voltages are generated at both terminals of the resistor R11.
This terminal voltage is connected to the positive and negative input terminals of the operational amplifier 26 via resistors R21 and R41, respectively. Similarly, the terminal voltage of the resistor R12 is connected to the positive / negative input terminal of the operational amplifier 27 via the resistors R22 and R42, and the terminal voltage of the resistor R13 is connected to the positive / negative input terminal of the operational amplifier 28 via the resistors R23 and R43, respectively. Yes.
[0018]
And the resistance value of each resistor is R11 = R12 = R13
R41 = R42 = R43 = R21 = R22 = R23
R31 = R32 = R33 = R51 = R52 = R53
When set to, the output voltages Vo1, Vo2, Vo3 of the

operational amplifiers

26, 27, 28 are

It becomes. Furthermore, R61 = R62 = R63
By setting these, the operational amplifier 29 adds these Vo1, Vo2, and Vo3 to obtain the output voltage Vuo.

Can be obtained.
[0019]
In this Vuo, only the voltage between the terminals of the resistor not affected by the copper pattern of the printed circuit board is amplified and extracted, and since a large voltage between the terminals can be obtained, the detected current Iu can be detected with high accuracy. It becomes possible to do.
Next, a third embodiment of the present invention will be described with reference to FIG.
This is the same as the first embodiment shown in FIG. 1, except that the detection resistors R11, R12, and R13 are arranged on the negative electrode side of the DC power supply and the detected current is changed. Same as above.
Next, a fourth embodiment of the present invention will be described with reference to FIG.
This is the same as the first embodiment shown in FIG. 1, except that the detection resistors R11, R12, and R13 are arranged on the positive electrode side of the DC power supply and the detected current is changed. Same as above.
[0020]
Next, a fifth embodiment of the present invention will be described with reference to FIG. This is different from the configuration of the second embodiment shown in FIG. 2 in that the positions of the detection resistors R11, R12, and R13 are arranged on the negative side of the DC power source to change the detected current, and the adder is used in the second embodiment. The output voltages of the

operational amplifiers

1, 2, and 3 are fetched from the A / D conversion port of the CPU 30 instead of the operational amplifiers in FIG.
Next, a sixth embodiment of the present invention will be described with reference to FIG.
This is because the resistance of the four-terminal structure (FIGS. 9 and 10) is used for the detection resistors 31, 32, and 33 with respect to the configuration of FIG. The current to be detected is changed by being arranged on the negative side of the DC power source, and the anode side terminals of the free-wheeling

diodes

17, 18, and 19 are connected to the negative side of the DC power source. Due to the resistance of the four-terminal structure, the influence of the impedance of the portion generated by the solder connection of the current terminal portion can be eliminated, and more accurate current detection can be performed. The four-terminal structure integrated resistor having a terminal pair for conducting current and a terminal pair for extracting a voltage signal can be applied as it is in the first to fifth embodiments. In this case, current detection with higher accuracy can be performed as described above.
[0021]
【The invention's effect】
As described above, according to the present invention, the detection resistor for a large current to be detected can be configured only by a small and small resistance value connected in parallel, and the copper of the printed circuit board can be formed while the detection resistor is connected in parallel. It does not include the effects of pattern impedance, so only the voltage between the terminals of the resistor can be amplified and extracted, and even with a small resistance value, a large voltage between the resistance terminals can be obtained. There is an effect that it can be reduced. That is, a small-sized current detector can be configured with little error even for a large current to be detected, and an ultra-small inverter device can be provided.
[Brief description of the drawings]
FIG. 1 shows a configuration diagram of a current detector of an inverter device in a first embodiment of the present invention. FIG. 2 shows a configuration diagram of a current detector of an inverter device in a second embodiment of the present invention. FIG. 3 is a diagram showing the configuration of the current detector of the inverter device according to the third embodiment of the present invention. FIG. 4 is a configuration diagram of the current detector of the inverter device according to the fourth embodiment of the present invention. FIG. 5 shows a configuration diagram of the current detector of the inverter device in the fifth embodiment of the present invention. FIG. 6 shows the configuration of the current detector of the inverter device in the sixth embodiment of the present invention. FIG. 7 shows the influence of the copper pattern of the printed circuit board when the first resistor group is connected in parallel. FIG. 8 is a diagram for explaining the effect of the present invention in the configuration according to claim 1. Fig. 9 shows the current configuration diagram. FIG. 10 shows an internal circuit diagram of a resistor having a four-terminal structure. FIG. 11 shows an inverter in a conventional example. A diagram showing the configuration of the current detector of the device.
1 Commercial

AC power supply

2, 3, 4, 5, 6, 7

Rectifier diodes

8, 9, 10, 11, 12, 13

IGBT transistors

14, 15, 16, 17, 18, 19 Free-wheeling

diodes

20, 21, 22 Current Detector 23

Motor

24, 26, 27, 28, 29 Operational amplifier 25 DC power supply 30 CPU
31, 32, 33 Four-terminal resistors R3, R5, R7, R8, R11, R12, R13, R21R, R22, R23 Resistors R31, R32, R33, R41, R42, R43, R51, R52, R53, R61, R62, R63 Resistors R1a, R1b, R1c Each resistor R2a, R4a, R2b, R4b, R2c, R4c constituting the first resistor group connected in parallel Resistance Za0, Zb0, Zc0, Za1, Zb1, Zc1 Printed circuit board copper Impedance U by pattern U phase output terminal V of inverter device V phase output terminal W of inverter device W phase output terminal T1, T2 IGBT transistors T4, T5, T6 MOSFET of inverter device
R101, R102, R103, R104, R105, R106, R107 Resistor Rs Shunt resistor GDU1, GDU2 Gate drive circuit OP1, OP2 Operational amplifier 101

Inverted gate

102, 103 Control power supply

Claims

A series connection body in which two parallel connection bodies of a semiconductor switching element and a free-wheeling diode connected in reverse parallel to the semiconductor switching element are connected in series, and a connection point in which the two parallel connection bodies are connected in series is an inverter device. In an inverter device connected to an output terminal and having two or more series-connected bodies connected in parallel between positive and negative electrodes of a DC power source,
A first resistor group in which two or more resistors are connected in parallel, and the first resistor group through which the output current of the inverter device flows;
When the output current of the inverter device flows through the first resistor group, the voltage between the resistance terminals generated between the terminals of the resistors connected in parallel is amplified, and the amplified values are added to obtain the output current. An inverter device comprising means for detecting.

A series connection body in which two parallel connection bodies of a semiconductor switching element and a free-wheeling diode connected in reverse parallel to the semiconductor switching element are connected in series, and a connection point in which the two parallel connection bodies are connected in series is an inverter device. In an inverter device connected to an output terminal and having two or more series-connected bodies connected in parallel between positive and negative electrodes of a DC power source,
A first resistor inserted and connected between the connection point of the series connection body and the output terminal of the inverter device; a differential amplifier; a negative input terminal of the differential amplifier; and the first resistor. A fourth resistor inserted and connected between the terminal on one side, a third resistor connected between the negative input terminal and the output terminal of the differential amplifier, and the first resistor. A second resistor inserted and connected between the other terminal and the positive input terminal of the differential amplifier; a reference voltage; and between the reference voltage and the positive input terminal of the differential amplifier. And a differential amplifier in each of the constituents having two or more of the constituents, the first resistors in the constituents being connected in parallel to each other. An inverter device comprising current detecting means comprising an adder for adding outputs.

A series connection body in which two parallel connection bodies of a semiconductor switching element and a free-wheeling diode connected in reverse parallel to the semiconductor switching element are connected in series, and a connection point in which the two parallel connection bodies are connected in series is an inverter device. In an inverter device connected to an output terminal and having two or more series-connected bodies connected in parallel between positive and negative electrodes of a DC power source,
A first resistor group formed by connecting two or more resistors in parallel, and the first resistor group inserted and connected between the connection point of the series connection body and the output terminal of the inverter device;
When the output current of the inverter device flows through the first resistor group, the voltage between the resistance terminals generated between the terminals of the resistors connected in parallel is amplified, and the amplified values are added to obtain the output current. An inverter device comprising means for detecting.

A series connection body in which two parallel connection bodies of a semiconductor switching element and a free-wheeling diode connected in reverse parallel to the semiconductor switching element are connected in series, and a connection point in which the two parallel connection bodies are connected in series is an inverter device. In an inverter device connected to an output terminal and having two or more series-connected bodies connected in parallel between positive and negative electrodes of a DC power source ,
The first resistor, which is a first resistor group formed by connecting two or more resistors in parallel, and inserted and connected between the series connection body connected in parallel with two or more resistors and the negative terminal of the DC power supply Group ,
When the output current of the inverter device flows through the first resistor group, the voltage between the resistance terminals generated between the terminals of the resistors connected in parallel is amplified, and the amplified values are added to obtain the output current. An inverter device comprising means for detecting .

A series connection body in which two parallel connection bodies of a semiconductor switching element and a free-wheeling diode connected in reverse parallel to the semiconductor switching element are connected in series, and a connection point in which the two parallel connection bodies are connected in series is an inverter device. In an inverter device connected to an output terminal and having two or more series-connected bodies connected in parallel between positive and negative electrodes of a DC power source ,
The first resistor group is formed by connecting two or more resistors in parallel, and the first resistor is inserted and connected between the series connection body connected in parallel to two or more resistors and the positive terminal of the DC power supply. Resistance group ,
When the output current of the inverter device flows through the first resistor group, the voltage between the resistance terminals generated between the terminals of the resistors connected in parallel is amplified, and the amplified values are added to obtain the output current. An inverter device comprising means for detecting .

Only the freewheeling diode is disconnected at the connection point between the semiconductor switching element and the freewheeling diode, which are the negative electrode side parallel connected bodies constituting each series connection body, and the first resistor group, and is connected to the negative electrode side terminal of the DC power supply. The inverter device according to claim 4.

7. Each of the resistors connected in parallel constituting the first resistor group is a four-terminal structure-integrated resistor having a terminal pair for conducting current and a terminal pair for extracting a voltage signal. Inverter device.