JP4640434B2 - Digital camera - Google Patents

Description

  It is an object of the present invention to provide a digital camera with improved image signal processing time by efficient image memory control.

  When taking still images or movies with a digital camera, CCD data capture processing, separation processing into luminance and color difference signals (Y / C separation processing), display processing on the LCD monitor, JPEG compression processing, recording media In each signal processing such as recording processing, it is common to perform processing by temporarily storing data generated between each signal processing in an image memory.

  In conventional digital cameras, these processes are performed in synchronization with CCD data output because the access speed of the image memory is insufficient or it is complicated to process memory accesses generated by multiple image processes in parallel. Priority is given to the acquisition of CCD data that must be completed within a predetermined period of time, and the CCD data for one screen is imported to the image memory, and then Y / C separation processing for one screen is performed for one screen. The Y color difference signal was taken into the image memory, and then monitor display processing, JPEG compression processing, recording processing to external media, etc. were performed. Therefore, there has been a problem that it takes a long time for signal processing as a total.

The digital camera of the present invention includes an imaging circuit for digitizing the output of the imaging device, a first buffer memory for temporarily storing a video signal stored in the memory, and a digitization temporarily stored in the first buffer memory . Y / C separation processing means for processing the recorded video signal in synchronization with the output of the image sensor, a second buffer memory for temporarily storing the video signal stored in the memory, and a temporary storage in the second buffer memory Compression processing means for processing the stored digitized video signal without synchronizing with the output of the imaging device, a memory, and the Y / C separation from the access request to the memory issued from the compression processing means and a arbiter to prioritize access request to the memory issued from the processing unit, the capacity of the first buffer memory, said second buffer memory Smaller than the capacity, characterized in that.

  By the means as described above, the present invention realizes parallel processing of a plurality of signal processing by efficient memory control, and shortens the shooting interval, high-speed continuous shooting function, and liquid crystal monitor of shooting data by improving the signal processing time. A digital camera with improved display speed can be provided.

  Thus, according to the digital camera of the present invention, as described above, the digital camera of the present invention realizes parallel processing of a plurality of signal processes by efficient memory control, and improves the signal processing time. We provide digital cameras that improve shooting interval reduction, high-speed continuous shooting function, and display speed of shooting data on the LCD monitor.

(Specific embodiment)
(Embodiment 1)
This embodiment realizes parallel processing of multiple signal processing through efficient memory control, shortens the shooting interval, improves high-speed continuous shooting function, and displays the shooting data on the LCD monitor by improving the signal processing time This is to realize a digital camera with improved performance.

  Embodiment 1 of the present invention will be described below with reference to the drawings.

  FIG. 1 is a configuration diagram of a digital camera according to Embodiment 1 of the present invention.

  In FIG. 1, reference numeral 101 denotes an image pickup circuit that digitizes the output of the image pickup element, and reference numeral 102 denotes a plurality of signal processing circuits that need to write or read data in the main memory. 103 is an arbiter that arbitrates memory access requests from the signal processing circuit 102, 104 is a memory control circuit that relays memory access from the signal processing circuit 102, 105 is a main memory, and 106 is for image data. It is a recording medium for storing an image file finally generated after signal processing.

  110 is a memory access request signal from the plurality of signal processing circuits 102, and 111 is a memory access permission signal from the arbiter 103. Reference numeral 112 denotes a memory address to the main memory output from each signal processing circuit of the plurality of signal processing circuits 102. Reference numeral 113 denotes a data transfer between the main memory 105 and the plurality of signal processing circuits 102 via the memory control circuit. It is.

  A memory access switching signal 114 is switched by the memory control circuit 104 so that data can be transferred between the signal processing circuit to which the memory access permission is given from the arbiter 103 and the main memory. Reference numeral 115 denotes a memory address given from the memory control circuit 104 to the main memory 105, 116 denotes data transfer between the memory control circuit 104 and the main memory 105, and 117 denotes a command given from the memory control circuit 117 to the main memory 105.

  Arbiter 103 outputs an access permission signal to the signal processing circuit in response to a memory access request signal from a plurality of signal processing circuits 102, and the signal processing circuit that has received the access accesses the main memory via the memory control circuit It has become.

  FIG. 2 shows the configuration of the arbiter 103 in FIG.

  In the arbiter 103, the priority determination circuit 201 issues an access permission signal to the memory access request signal having the highest priority among the plurality of signal processing circuits 102 in accordance with a predetermined priority order. The selected signal processing circuit performs memory access via the memory control circuit.

  As described above, the memory access request is integrated and controlled by the arbiter 103, so that the main memory can be easily controlled without having a plurality of memory control means for one main memory, and simultaneously from a plurality of signal processing circuits. Even when a memory access or request occurs, it is possible to give priority to signal processing with high priority.

  The memory access performed by the signal processing circuit selected by the access permission signal is a predetermined period, and the arbiter 103 sends the access permission signal according to the request signal having the highest priority at that time. Output.

  In this way, by switching the memory access in a short time cycle of a certain time, the main memory is not accessed for a long time by one signal processing, so that the memory access of the signal processing with a low priority may be waited for a long time. Therefore, it is possible to process a plurality of signal processing without failing.

  FIG. 3 shows the configuration of the memory control circuit 104.

  In FIG. 3, reference numeral 301 denotes a memory address switching processing circuit, which is configured to switch the memory address from the signal processing circuit to which access permission is given by the arbiter to the main memory. A memory data switching processing circuit 302 is a circuit that performs data exchange processing between the main memory and a signal processing circuit to which access permission is given by an arbiter. A memory command generation circuit 303 is a circuit that switches depending on whether a signal processing circuit to which access permission is given by an arbiter performs a write process or a read process. The memory control circuit 104 is configured to switch so that a signal processing circuit permitted to access the memory can access the main memory by a memory access switching signal output from the arbiter 103.

  FIG. 4 shows the configuration of each signal processing circuit in the plurality of signal processing circuits 102. In FIG. 4, 401 is a signal processing unit, 402 is a buffer memory, 403 is a buffer memory control circuit, and 404 is a memory address generation circuit.

  In FIG. 4, when each signal processing circuit in the plurality of signal processing circuits 102 relays the memory control circuit 104 and performs a process of writing to the main memory, the data after the signal processing in the signal processing unit 401 is temporarily stored. When the data stored in the buffer memory 402 exceeds a certain amount, the buffer memory control circuit 403 outputs an access request signal to the arbiter 103. When an access request is accepted by the arbiter and memory access is permitted, the memory address for reading data from the buffer memory and writing data to the main memory is output.

  In this way, when the unprocessed data on the buffer memory falls below a certain amount, or when the processed data on the buffer memory exceeds a certain amount, the memory access request signal is output to acquire the access right. In addition, the signal processing circuit needs the signal on the buffer memory by fetching the data required by the signal processing circuit from the main memory or discharging the processed data on the buffer memory to the main memory. Since a state where there is data and there is room for storing signal-processed data is automatically maintained, it is possible to perform signal processing continuously even during a period when memory access is not being performed.

  In FIG. 4, when each signal processing circuit in the plurality of signal processing circuits 102 relays the memory control circuit 104 and performs processing for reading data from the main memory, the data read from the main memory is temporarily stored in the buffer memory. The buffer memory control circuit 403 outputs an access request signal to the arbiter 103 when the data in the buffer memory 402 falls below a certain amount. When an access request is accepted by the arbiter and memory access is permitted, the memory address for writing data to the buffer memory and reading data from the main memory is output.

  When there is a memory access request from a plurality of signal processing circuits at the same time, the priority order is determined by giving a higher order to signal processing that needs to be completed within a certain time, and allowing memory access delays. For processing, a lower rank is given.

  In this way, the signal processing circuit that needs to finish memory access within a certain time can be processed so as not to fail, and memory access with lower priority is accepted during idle time when memory access with higher priority is not accessed. Therefore, it is possible to eliminate the idle time of memory access and perform a plurality of efficient signal processing in parallel.

  If the buffer memory 402 of the signal processing circuit 102 is sufficiently large, signal processing will not stop even if memory access is intermittent, but having more buffer memory than necessary increases the cost of the signal processing circuit. Therefore, optimization of capacity is necessary.

  Therefore, in the case of memory access related to signal processing in which two or more simultaneously generated memory access requests need to be completed within a certain time, or in memory access related to signal processing in which delay of memory access is allowed, unit time An upper rank is given to a signal processing circuit having a larger amount of data accessed within, and a lower rank is assigned to a signal processing having a smaller amount of data accessed within a unit time.

  In this way, in the memory access waiting time during the synchronization, the signal processing circuit having a larger amount of data accessed within the unit time requires a larger buffer capacity, so that the amount of data accessed within the unit time is larger. By giving higher ranks to many signal processing circuits, the capacity of the buffer memory can be suppressed.

  Also, memory access requests from a plurality of signal processing circuits 102 are generated at the same time, and the signal processing circuit with the highest priority level accesses the memory, and then the memory access is performed in descending order of priority. When each signal processing circuit accesses the memory once before the low signal processing circuit accesses the memory, the maximum value of the time from when the memory access request is issued until the memory access permission is given, that is, the maximum waiting time Time is proportional to the rank given to the signal processing circuit. In order to keep the signal processing circuit operating throughout the entire period, the buffer memory needs to store data processed by the signal processing circuit during the maximum waiting time. It is necessary to provide a capacity proportional to the product of the speed and the order given to the signal processing circuit.

  Thus, the capacity of the buffer memory included in the signal processing circuit can be minimized.

  A control method when a plurality of memory access requests are actually generated will be described with reference to FIG. 5 when a memory access request is simultaneously generated from the signal processing circuit A 1021, the signal processing circuit B 1022, and the signal processing circuit C 1023. The memory access requests generated from the signal processing circuit A 1021, the signal processing circuit B 1022, and the signal processing circuit C 1023 are referred to as a request A, a request B, and a request C, respectively. Here, T is a memory access time performed by the signal processing circuit selected by one memory access permission signal, and data processing amounts per unit time of the signal processing circuit A 1021, the signal processing circuit B 1022, and the signal processing circuit C 1023 are respectively shown. , K, L, M, and N is the processing speed of the main memory.

  Here, as a condition for performing the above three signal processes without failure, a processing speed of the main memory that satisfies K + L + M <N is required. In order to simplify the description, it is assumed that the signal processing circuit A 1021, the signal processing circuit B 1022, and the signal processing circuit C 1023 perform writing processing to the main memory, respectively, and the amount of data that the main memory processes in the T period, that is, When N × T is stored in the buffer memory, a memory access request is issued to the arbiter. Here, the memory access requests from the signal processing circuits A1021, B1022, and C1023 are referred to as request A, request B, and request C, respectively, and the priority order is request A, request B, and request C. Suppose they are given in order.

  FIG. 5 shows the relationship between the memory access request, the memory access permission, and the data access to the main memory under such conditions. In FIG. 5, the priority order is determined first at t = 0, and thereafter the priority order is determined every T period. Further, at t = t0 in FIG. 5, since the N × T data amount is accumulated in the buffer memories on the signal processing circuit A1021, the signal processing circuit B1022, and the signal processing circuit C1023, it is assumed that a memory access request is issued simultaneously. In FIG. 5, the case of K = 4, L = 2, M = 1, and N = 8 will be described for the sake of simplicity, but the present invention is not limited to this.

  At t = T, request A, request B, and request C are generated.In this case, request A with the highest priority is accepted, and the access permission signal to request A becomes HI. The signal processing circuit A 1021 performs a data writing process on the main memory. When the access permission signal of request A becomes HI, immediately after request A is dropped to LO. Since the request A is accepted at t = T, the data amount of N × T is accumulated in the buffer memory on the signal processing circuit A 1021 from t = t0 to N / K × T = 8 / 4T = Request A is issued at the timing of t = t1 when 2T has elapsed.

  At t = 2T, request B and request C are generated. In this case, request B with the highest priority is accepted, the access permission signal to request B becomes HI, and the signal processing circuit B1022 performs a data write process to the main memory. When the access permission signal of request A becomes HI, immediately after, request B is dropped to LO. Since the request B is accepted at t = 2T, the data amount of N × T is accumulated in the buffer memory on the signal processing circuit B1022 from t = t0 to N / L × T = 8 / 2T = Request 4 is issued at the timing of t = t2 when 4T has elapsed.

  At time t = 3T, request A and request C are generated. In this case, request A having the highest priority is accepted, the access permission signal to request A becomes HI, and the signal processing circuit A1021 performs a data write process to the main memory. When the access permission signal of request A becomes HI, immediately after request A is dropped to LO. Since the request A has been accepted at t = 3T, the N × T data amount is accumulated in the buffer memory on the signal processing circuit A 1021 from t = t0 to N / K × T + t1 = 8 / Request A is issued at the timing of t = t2 when 4T + 2T = 4T has elapsed.

  At time t = 4T, only the request C is generated. In this case, the request C is accepted, the access permission signal to the request C becomes HI, and the signal processing circuit C1023 performs a data write process to the main memory. I do. When the access permission signal of request C becomes HI, request C is dropped to LO immediately after. Since the request C is accepted at t = 4T, the N × T data amount is accumulated in the buffer memory on the signal processing circuit C1023 from t = t0 to N / M × T = 8 / 1T = Request C is issued at the timing of t = t4 when 8T has elapsed.

  At t = 5T, request A and request B are generated. In this case, request A with the highest priority is accepted, and the access permission signal to request A becomes HI, and the signal processing circuit A1021 performs a data write process to the main memory. When the access permission signal of request A becomes HI, immediately after request A is dropped to LO. Since the request B is accepted at t = 5T, the N × T data amount is accumulated in the buffer memory on the signal processing circuit A 1021 because t = t0 to N / K × T + t2 = 8 / The request A is issued at the timing of t = t3 when 4T + 4T = 6T has elapsed.

  At t = 6T, only the request B is generated. In this case, the request B is accepted, the access permission signal to the request B becomes HI, and the signal processing circuit B1022 performs a data write process to the main memory. I do. When the access permission signal for request B becomes HI, immediately after request B is dropped to LO. Since the request B is accepted at t = 6T, the data amount of N × T is accumulated in the buffer memory on the signal processing circuit A 1022 from t = t0 to N / L × T + t2 = 8 / Request B is issued at the timing of t = t4 when 2T + 4T = 8T has elapsed.

  At time t = 7T, only the request A is generated. In this case, the request A is accepted, the access permission signal to the request A becomes HI, and the signal processing circuit A1021 performs a data write process to the main memory. I do. When the access permission signal of request A becomes HI, immediately after request A is dropped to LO. Since the request A is accepted at t = 7T, the N × T data amount is accumulated in the buffer memory on the signal processing circuit A 1021 because t = t0 to N / K × T + t3 = 8 / Request A is issued at the timing of t = t4 when 4T + 6T = 8T has elapsed.

  Since no requests A, B, and C are generated at t = 8T, the main memory does not perform data transfer processing with any signal processing circuit in this case.

  Since request A, request B, and request C are issued simultaneously at t = t4, priority determination at t = 9T is exactly the same as at t = T. Repeat data transfer with memory.

  By performing control with the above-described configuration, parallel processing of a plurality of signal processes can be realized by efficient memory control without causing failure in signal processing of the three circuits.

  In the above description, the signal processing circuit A1021, the signal processing circuit B1022, and the signal processing circuit C1023 have been described. However, the present invention is not limited thereto, and the signal processing circuit A1021, the signal processing circuit B1022, and the signal processing circuit C1023 In addition to the memory access request, there is a request from a plurality of signal processing circuits with low priority, and the data processing amount per unit time other than the signal processing of the signal processing circuit A 1021, the signal processing circuit B 1022, and the signal processing circuit C 1023 is If P and K + L + M + P <N are satisfied, the plurality of signal processes can be processed in parallel.

  FIG. 6 shows a configuration at the time of high-speed continuous shooting in the digital camera of the first embodiment. 601 to 608 in FIG. 6 correspond to the plurality of signal processing circuits 102 in FIG. 1, and 601 is a CCD data processing circuit that writes imaging data digitized by the imaging circuit 101 to the main memory. 602 is a Y / C separation processing circuit that reads data written by the CCD data processing circuit 601 from the main memory and separates it into a luminance signal and a color difference signal (hereinafter referred to as Y / C separation); A recording Y / C generation processing circuit for writing Y / C data for recording, which is obtained by converting the number of pixels converted for Y / C separation in the C separation processing circuit 602 into the main memory, into a main memory. A display Y / C generation processing circuit for writing display Y / C data obtained by converting the number of pixels of the signal Y / C separated by the Y / C separation processing circuit 602 into a main memory for liquid crystal display, 605 is Y / C for display The display data read processing circuit 604 that reads the display Y / C data subjected to the write processing by the generation processing circuit 604 from the main memory and displays it on the liquid crystal, and 606 performs the write processing by the recording Y / C generation processing circuit 603. The recording Y / C data is read from the main memory, and a compression processing circuit that performs compression processing. 607 is a code data processing circuit that writes the code data generated by the compression processing circuit 606 into the main memory. Reference numeral 608 denotes a media recording processing circuit that reads data written by the code data processing circuit 607 from the main memory and performs recording processing on a recording medium.

  Hereinafter, the operation in the high-speed continuous shooting mode will be described with reference to the timing chart of FIG.

  In the period (1) in FIG. 7, the CCD performs the first frame imaging. The readout method when outputting the imaged signal from the CCD is by frame readout. First, during the period (2), the first field signal corresponding to the odd line on the CCD is output, converted into a digital signal, and then the CCD. The data is input to the data processing circuit 601 and the data is written into the main memory. During this period, the memory access request output from each of the signal processing circuits 601 to 608 is only from the CCD data processing circuit 601, and the main memory is exclusively used to perform the writing process.

  Here, if the signal processing speed per unit time in the CCD data processing circuit 601 in the period (1) is a and the signal processing speed per unit time in the main memory is N, if a <N, There will be no failure in the processing in the period 1).

  In the period (2) in FIG. 7, the second field signal corresponding to the even lines on the CCD is output, converted into a digital signal, input to the CCD data processing circuit 601, and then in the Y / C separation processing circuit 602. Y / C separation processing is performed using the first field signal read from the main memory and the second field signal output from the CCD data processing circuit 601. In parallel, the processing in the recording Y / C generation processing circuit 603, the display Y / C generation processing circuit 604, the compression processing circuit 606, the code data processing circuit 607, and the code data processing circuit 608 described above is performed in parallel. And do it.

  In the period (2), priorities are determined for the memory access requests to the main memory generated simultaneously from the signal processing circuits, and memory access permission is given to the signal processing with the highest priority. Each signal processing of the Y / C separation processing circuit 602, the recording Y / C generation processing circuit 603, and the display Y / C generation processing circuit 604 needs to be completed within the period of (2) in accordance with the vertical synchronizing signal of the CCD. Therefore, the priority is set high, and the signal processing of the compression processing circuit 606, the code data processing circuit 607, and the media recording processing circuit 608 is allowed to be delayed because memory access delay is allowed.

  Here, in the period (2), the Y / C separation processing circuit 602, the recording Y / C generation processing circuit 603, the display Y / C generation processing circuit 604, the compression processing circuit 606, the code data processing circuit 607, and the media recording If the signal processing speed per unit time in each signal processing of the processing circuit 608 is b, c, d, e, f, g, and the signal processing speed per unit time of the main memory is N, then b + c + d + e + If f + g <N, the processing in the period (2) will not fail.

  In the period of (3) in FIG. 7, the CCD starts exposure of the second frame, and in parallel with the exposure of the second frame, the display data read processing circuit 605 reads the display Y / C data from the main memory. Processing to be displayed and processing by the compression processing circuit 606, the code data processing circuit 607, and the media recording processing circuit 608 are continued from the period (2).

  Here, assuming that the signal processing speed per unit time in the display data read processing circuit 605 in the period (3) is h and the signal processing speed per unit time of the main memory is N, e + f + g If + h <N, the process in the period (3) will not fail.

  Next, after the exposure of the second frame is completed, the video signal of the second frame from the CCD is read out from the frame. First, a field signal corresponding to an odd line on the CCD is input from the imaging circuit to the CCD data processing circuit 601 and the data Is written into the main memory. At the same time, the display data reading processing circuit 605, compression processing circuit 606, code data processing circuit 607, and media recording processing circuit 608 continue processing from (3).

  In the period (4), if a + e + f + g + h <N, the process in the period (4) will not fail.

  In the period (5), as in the period (2), the second field signal corresponding to the even lines on the CCD is output, and the Y / C separation processing 602 and the recording Y / C generation processing circuit in the second frame are output. The display Y / C reading process and the media recording process for the first frame are continued from 603, the display Y / C generation processing circuit 604, the compression processing circuit 606, the code data processing circuit 607, and (4).

  If b + c + d + e + f + g + h <N in the period of (5), the process in the period of (5) will not fail.

  After the period of (5), the exposure operation for the third frame is performed, but since the exposure of the third frame is started, (2), (3), and (4) are repeated, and thus the description thereof is omitted.

  By performing the above processing during continuous shooting, multiple signal processing can be executed in parallel, and the high-speed continuous shooting can be realized at the same speed as the CCD drive speed by eliminating the main memory access idle time. .

  According to the first embodiment of the present invention as described above, the CCD data processing, the Y / C separation processing, the recording Y / C generation processing, the display Y / C generation processing, and the display that need to be completed within a predetermined time. Signal processing that gives higher priority to signal processing for Y / C read processing and allows delays in compression processing, code data processing, and recording media recording processing during periods when the signal processing circuit with higher priority is not accessed The digital camera that realizes parallel processing of multiple signal processing and shortens the shooting interval, high-speed continuous shooting function, display speed of shooting data on the LCD monitor, etc. by improving the signal processing time Can be built.

(Embodiment 2)
The second embodiment realizes parallel processing of a plurality of signal processing by efficient memory control, and shortens the shooting interval, high-speed continuous shooting function, and displays the shooting data on the liquid crystal monitor by improving the signal processing time. The present invention realizes a digital camera that improves the speed and the response speed of the operation.

  The second embodiment of the present invention will be described below with reference to FIG.

  FIG. 8 is a block diagram of a digital camera according to Embodiment 2 of the present invention. In FIG. 8, reference numeral 101 denotes an image pickup circuit that digitizes the output of the image pickup element, and reference numeral 102 denotes a plurality of signal processing circuits that need to write or read data in the main memory.

  103 is an arbiter that arbitrates memory access requests from the signal processing circuit 102, 104 is a memory control circuit that relays memory access from the signal processing circuit 102, 105 is a main memory, and 106 is for image data. It is a recording medium for storing an image file finally generated after signal processing.

  110 is a memory access request signal from the plurality of signal processing circuits 102, and 111 is a memory access permission signal from the arbiter 103. Reference numeral 112 denotes a memory address to the main memory output from each signal processing circuit of the plurality of signal processing circuits 102. Reference numeral 113 denotes a data transfer between the main memory 105 and the plurality of signal processing circuits 102 via the memory control circuit. It is. A memory access switching signal 114 is switched by the memory control circuit 104 so that data can be transferred between the signal processing circuit to which the memory access permission is given from the arbiter 103 and the main memory.

  Reference numeral 115 denotes a memory address given from the memory control circuit 104 to the main memory 105, 116 denotes data transfer between the memory control circuit 104 and the main memory 105, and 117 denotes a command given from the memory control circuit 117 to the main memory 105.

  A microcomputer 118 accepts user operations and operates the signal processing circuits A, B, C to n, and also operates display data on the main memory to display a response screen corresponding to the user operations on the liquid crystal display. indicate. The arbiter 119 outputs an access permission signal to the signal processing circuit in response to the memory access request signals from the plurality of signal processing circuits 102 and the microcomputer, and the signal processing circuit that has received the access accesses the main memory via the memory control circuit. It is configured to do.

  FIG. 9 shows the configuration of the arbiter 119 in FIG. The arbiter includes a priority determination circuit and a counter. The priority determination circuit issues an access permission signal to the memory access request signal having the highest priority among the plurality of signal processing circuits 102 and the microcomputer according to a predetermined priority, and permits access until the counter indicates 0. Hold the signal. If the priority determination circuit outputs an access permission signal when the counter is 0, the counter is loaded with a predetermined value for each access permission signal, and thereafter counts down every clock until reaching 0. The priority determination circuit issues a new access permission signal in response to the memory access request signal with the highest priority when the counter reaches zero. According to this configuration, if the value loaded by the counter is increased, access permission is given for a long time, and if the value loaded by the counter is reduced, access permission is given only for a short time.

  In FIG. 8, in order to operate a plurality of signal processing circuits in parallel, the length of one access permission signal is lengthened to suppress the frequency of giving a memory address to the memory and switching the data bus transfer direction. It is desirable that the ratio of time required for these is smaller than the time required for data transfer. On the other hand, since the microcomputer accesses the main memory in units of a short time, even if access permission is granted for a long time, it is only useless, and it may put pressure on the operation margin of other signal processing circuits that require memory access. Absent.

  However, for a signal processing circuit that requires continuous access for a long time, the duration of the access permission signal is lengthened by setting a large value to be loaded by the counter in FIG. 9, and only a short time access is required. By setting the value loaded by the counter to be small for the microcomputer, the access permission assignment can be optimized by shortening the duration of the access permission signal.

  In addition, a technique for optimizing the length of access permission time is disclosed. By reducing the frequency of giving memory addresses to the memory and switching the transfer direction of the data bus as described above, the time ratio required for these is reduced, and the time ratio for data transfer between the microcomputer and the signal processing circuit is reduced. However, in order to perform data transfer continuously for a certain period of time, the signal processing circuit must have a buffer memory that is proportional to the time for data transfer. This will increase costs. Therefore, according to claim 9 of the present invention, a fixed amount of time is determined to determine the amount of data accessed by each signal processing circuit, and each signal processing circuit has a buffer memory having a capacity proportional to the amount of data, The arbiter sets a counter so as to issue an access permission signal having a time proportional to the data amount. In this case, since the arbiter only needs to grant access permission to each signal processing circuit once within a fixed time, the number of times the access permission signal is switched is minimum, and the access permission time is the maximum according to the buffer capacity of each signal processing circuit. Therefore, the loss time associated with switching of the access permission signal can be minimized while the buffer memory capacity is limited. In this way, the length of the access permission time can be optimized.

  According to the second embodiment of the present invention as described above, if the time of the access permission signal to be assigned to the microcomputer is set short, even if the priority of the microcomputer is increased, the time to wait for access of other signal processing circuits is little. Since it does not increase, the access time can be shortened by giving priority to the access from the microcomputer to the main memory. As a result, the response to the user's operation is reflected in the display data on the main memory in a shorter time, and the user's feeling of use becomes better.

(Embodiment 3)
The third embodiment realizes parallel processing of a plurality of signal processing by efficient memory control, and shortens the shooting interval, high-speed continuous shooting function, and display of shooting data on the liquid crystal monitor by improving the signal processing time. A digital camera with improved speed and the like is realized.

  The third embodiment of the present invention will be described below with reference to the drawings. FIG. 10 is a block diagram of a digital camera according to Embodiment 3 of the present invention.

  In FIG. 10, reference numeral 101 denotes an image pickup circuit that digitizes the output of the image pickup element, and reference numeral 102 denotes a plurality of signal processing circuits that need to write or read data in the main memory. 103 is an arbiter that arbitrates memory access requests from the signal processing circuit 102, 104 is a memory control circuit that relays memory access from the signal processing circuit 102, 105 is a main memory, and 106 is imaging data. This is a recording medium that stores an image file that is finally generated after the signal processing for.

  121 is a first memory access request signal from the signal processing circuit 102, 121 is a second memory access request signal from the signal processing circuit 102, and 111 is a memory access permission signal from the arbiter 103. Reference numeral 112 denotes a memory address to the main memory output from each signal processing circuit of the plurality of signal processing circuits 102. Reference numeral 113 denotes a data transfer between the main memory 105 and the plurality of signal processing circuits 102 via the memory control circuit. It is. A memory access switching signal 114 is switched by the memory control circuit 104 so that data can be transferred between the signal processing circuit to which the memory access permission is given from the arbiter 103 and the main memory.

  Reference numeral 115 denotes a memory address given from the memory control circuit 104 to the main memory 105, 116 denotes data transfer between the memory control circuit 104 and the main memory 105, and 117 denotes a command given from the memory control circuit 117 to the main memory 105. Reference numeral 1024 denotes a signal processing circuit D having two memory access requests.

  Here, it is assumed that a certain signal processing circuit D1024 in the signal processing circuit 102 intermittently outputs a large amount of data, and the signal processing circuit D1024 has only one memory access request signal. If a high priority is given, the signal processing circuit D1024 will continue to issue a memory access request signal until the buffer memory is empty, and the signal processing circuit with a lower priority may not be able to access the memory during that time. Yes, and conversely, if the signal processing circuit D1024 is given a lower priority than the other signal processing circuits, there is no guarantee that the memory access permission signal can be secured for the time necessary for transferring a large amount of data. The data not yet transferred from the main memory to the main memory exceeds the buffer memory capacity (data overflow Over), there is a possibility that data of the signal processing unprocessed transferred from main memory to the signal processing circuit is in a state that does not exist in the buffer memory (data underflow).

  A technique for eliminating such a dilemma is disclosed. In the signal processing circuit, the circuit that outputs the memory access request signal has two threshold values and two memory access request outputs, and the first memory access request signal while there is data exceeding the first threshold value in the buffer memory. The arbiter 103 gives a lower rank to the first memory access request signal 1101 and gives a memory access permission signal only when there is no other access request. When the signal processing circuit starts outputting data and the amount of data exceeds the second threshold without interrupting the memory access of the circuit, the second memory access request signal 1101 is issued, and the arbiter 103 uses the second memory For access request signals, memory access permission is given priority over other signal processing circuits. It is possible to avoid data overflow by reducing the amount of data on the memory below the second threshold. While the second memory access request signal is issued, other access requests are not accepted, but the data amount of the buffer memory is rapidly consumed because the signal processing circuit D1024 continuously takes the memory access right. Since the period during which the second memory access request signal is output can be suppressed to a short time, there is no practical problem.

  According to the third embodiment of the present invention as described above, by using two memory access request signals having different priorities, a period during which no other signal processing circuit accesses the memory due to a low priority access request signal is made effective. It is possible to transfer data by using it, and to ensure that data overflow or data underflow is avoided by a high priority access request signal, whereby an efficient and highly reliable memory system can be constructed.

1 is a block diagram showing a configuration of a digital camera according to Embodiment 1 of the present invention. The block diagram which shows the structure of the arbiter circuit of Embodiment 1 A block diagram showing a configuration of a memory control circuit according to the first embodiment. The block diagram which shows the structure of the signal processing circuit of Embodiment 1 Timing chart showing timing of data access with main memory of the first embodiment FIG. 2 is a block diagram showing the configuration of a digital camera equipped with the continuous shooting function according to the first embodiment. Timing chart showing timing in continuous shooting mode of the first embodiment FIG. 3 is a block diagram showing a configuration of a digital camera according to a second embodiment of the present invention. The block diagram which shows the structure of the arbiter circuit of Embodiment 2 of this invention. FIG. 3 is a block diagram showing the configuration of a digital camera according to Embodiment 3 of the present invention.

Claims (1)

Imaging means for capturing a subject image and generating a video signal;
A memory for storing a video signal based on the generated video signal;
A first buffer memory for temporarily storing the video signal stored in the memory;
The first facilities in synchronization with the processing to the operation timing of the imaging unit with respect temporarily stored video signal in the buffer memory Sutame, a Y / C separation means for issuing an access request to said memory,
A second buffer memory for temporarily storing the video signal stored in the memory;
Wherein the second facilities the process without synchronism with the operation timing of the imaging unit with respect temporarily stored video signal in the buffer memory Sutame, a compression processing means for issuing an access request to said memory,
An arbiter that prioritizes an access request to the memory issued from the Y / C separation processing means over an access request to the memory issued from the compression processing means ;
With
The capacity of the first buffer memory is smaller than the capacity of the second buffer memory,
A digital camera characterized by that.

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