JP4636267B2 - Encoding device and encoding bit rate switching method - Google Patents

Description

  The present invention relates to an encoding device capable of changing an encoding bit rate, and more particularly to control of data delay when changing the encoding bit rate in the encoding device.

  In an apparatus that transmits video and audio as a digital signal, video and audio are encoded (see Patent Document 1). For example, in the case of voice, the voice data per unit time is set as one frame, the voice data is encoded in units of frames, and the encoded data is packetized and transmitted. The video is processed in the same manner.

  In this type of encoding apparatus, the encoding bit rate is not necessarily fixed, and may be changed during the encoding of video and audio. When the encoding bit rate is changed, video and audio may be temporarily interrupted at the boundary.

  This interruption of video and audio is not preferable for the user. Therefore, it is desired to prevent or reduce the interruption of video and audio. That is, it is desired to prevent or reduce the interruption of the sound output from the decoding unit in the device that receives the encoded sound data.

  Therefore, conventionally, by reducing the usable buffer size of the buffer for temporarily storing the video and audio data encoded by the encoding unit, the difference in delay time before and after switching the encoding bit rate is eliminated or There was a way to make it smaller.

  Further, when switching the encoding bit rate, it is preferable not to cause the buffer of the decoding unit to fail, that is, to prevent overflow or underflow. Therefore, the data in the buffer that temporarily stores the data from the encoding unit is liquidated while preventing the buffer of the decoding unit from failing. Here, “clearing” refers to sending data from the buffer, whereby the data storage state before switching can be shifted to the data storage state after switching.

When reducing the amount of data stored in the buffer, encoding is performed so as to suppress the amount of data generated by encoding during the settlement period.
JP 2004-140505 A

  In the conventional apparatus, the sound quality is deteriorated by reducing the size of the buffer for temporarily storing the encoded data or reducing the amount of the encoded data generated in the encoding unit.

  An object of the present invention is to provide an encoding device that reduces sound interruption and deterioration in sound quality when switching the encoding bit rate.

In order to achieve the above object, the encoding apparatus of the present invention provides:
An encoding device capable of switching an encoding bit rate with a change in delay time,
An encoding unit that encodes input data for each frame and switches an encoding bit rate according to a request;
A packetizing unit for generating a packet including the frame encoded by the encoding unit;
The packet generated by the packetizer is delayed by a predetermined delay time depending on the difference between the write position indicated by the write pointer and the read position indicated by the read pointer, and the coding bit rate is switched. When the packet length information of the packet being written is changed to the notified and changed packet length, the packet is corrected to a complete packet. A delay buffer that discards, inserts invalid data between the last packet before switching and the first packet after switching, and starts writing after switching from the notified first writing pointer after switching;
At the time of switching the coding bit rate, from the information about the delay time before switching, the information about the delay time after switching, and the start position of the packet in the middle of writing, the first write pointer after the switching, and the writing It obtains the modified packet length in the middle of the packet, a delay buffer control unit and a first write pointer and said modified packet length after the switching notifying the delay buffer,
have.

  According to the present invention, sound interruption at the time of switching the encoding bit rate is reduced, and deterioration of sound quality is prevented.

  Embodiments for carrying out the present invention will be described in detail with reference to the drawings. In this embodiment, MPEG2-AAC (Advanced Audio Coding) audio coding is exemplified.

  FIG. 1 is a block diagram showing the configuration of the encoding apparatus of the present embodiment. Referring to FIG. 1, the encoding apparatus according to the present embodiment includes an encoding unit 11, an encoding buffer 12, a packetizing unit 13, a delay buffer 14, and a delay buffer control unit 15.

  The encoding unit 11 uses the audio baseband signal per unit time as one ADTS (Audio Data Transport Stream) frame, and performs MPEG2-AAC encoding in units of frames. The encoding bit rate can be switched, and when switching is requested, the encoding unit 11 switches the encoding bit rate. The encoding unit 11 sends ES (Elementary Stream) data E1 for each ADTS frame obtained by encoding to the encoding buffer 12. ES data is a data stream composed of a plurality of ES frames.

  The encoding buffer 12 temporarily stores the ES data E1 from the encoding unit 11 and then sends the ES data E1 to the packetizing unit 13 as ES data E2.

  The packetizing unit 13 packetizes the ES data E2 from the encoding buffer 12 with a designated packet length, and sends the obtained PES (Packetized Elementary Stream) data P1 to the delay buffer 14. PES data is a stream of data composed of a plurality of PES packets.

  The delay buffer 14 temporarily stores the PES data P1 from the packetizing unit 13 for a specified delay time using a write pointer and a read pointer having a difference corresponding to the specified delay time, and then outputs the PES data as output PES data. Output. Here, the delay time is a time for delaying data in the delay buffer 14, and is changed when the coding bit rate is switched. Further, the delay buffer 14 notifies the delay buffer control unit 15 of the write pointer position, the read pointer position, and the latest PES header position as the current state information.

  When the coding bit rate is switched, the delay buffer control unit 15 notifies the delay buffer 14 of the correction information. The correction information from the delay buffer control unit 15 includes information on the position of the write pointer after switching and the value of the packet length added to the last PES header before switching.

  When the correction information is notified from the delay buffer control unit 15, the delay buffer 14 corrects the position of the write pointer and the packet length value of the last PES header before switching based on the notification information. In addition, the delay buffer 14 adds an appropriate PES header to the first PES packet after switching. Furthermore, the delay buffer 14 inserts invalid data if there is an interval between the last PES header before switching and the first PES header after switching. Further, when the ES data overflows to correct the delay time between the last PES header before switching and the first PES header after switching, the delay buffer 14 discards the overflowing ES data.

  Since the delay time is changed when the encoding bit rate is switched, the pointer of the delay buffer 14 needs to be changed. Further, in response to switching in the middle of the PES packet, the PES packet up to the middle is converted into one complete PES packet. By rewriting the packet length in the header of the PES packet up to the middle to the packet length added to the last PES header before switching included in this correction information, the PES packet up to the middle is converted into a completed PES packet. Can be converted.

  For the remaining ES frames converted into complete PES packets, the delay buffer 14 writes to the head of the next PES packet if writing is possible in relation to the position of the write pointer after switching, and writing is not possible. Discard if possible.

  As a result, incomplete PES packets can be prevented from being discarded, sound interruption can be prevented when the delay time is increased, and sound interruption can be reduced even when the delay time is reduced.

  When the coding bit rate is switched, the delay buffer control unit 15 uses the post-switching delay time given as the delay instruction information and the values of the write pointer and the read pointer notified from the delay buffer 14. Then, the value of the write pointer after switching is obtained. Further, the delay buffer control unit 15 obtains a packet length in which one PES packet is obtained from the position of the latest PES header notified from the delay buffer 14 to the last ES data frame before switching. This packet length is the packet length of the last PES header before switching. Then, the delay buffer control unit 15 notifies the delay buffer 14 of the position of the write pointer after switching and the packet length of the last PES packet before switching.

  FIG. 2 is a diagram illustrating an example of PES data. As shown in FIG. 2, the PES data is a data stream composed of a plurality of PES packets. The PES packet includes a PES header and a plurality of ES frames. The PES header has a PES packet length field (not shown), in which the PES packet length from the PES header to the last ES frame is described. In the example of FIG. 2, there is no interval between the PES packet and the PES packet, but there may be an interval. In that case, the interval becomes invalid data.

  As described above, the delay time is changed by switching the coding bit rate, but there are cases where the delay time becomes longer or shorter. The operation of the encoding apparatus differs depending on whether the delay time is long or short.

  When the delay time becomes long, it is necessary to increase the difference between the write pointer and the read pointer. Conversely, when the delay time is shortened, it is necessary to reduce the difference between the write pointer and the read pointer.

  FIG. 3 is a diagram for explaining a change in the state of the delay buffer 14 when the difference between the write pointer and the read pointer is increased. 3A shows the state of the delay buffer 14 before switching, and FIG. 3B shows the state of the delay buffer 14 after switching.

  At the time of switching, the delay buffer control unit 15 calculates a pointer position difference X1 from the current write pointer position A1 and the read pointer position B1 notified from the delay buffer 14.

  Further, the delay buffer control unit 15 obtains the difference X2 in the pointer position after switching from the delay time after switching input as the delay instruction information.

  Further, the delay buffer control unit 15 determines the position A3 of the first write pointer after switching from the current reading pointer position B1 and the difference X2 between the pointer positions after switching.

  In order to set the delay time to X2, the delay buffer 14 inserts the invalid data M1 from the write pointers A1 to A2, and writes the PES header H2 and the ES frame F1 from A2 to A3. In addition, the packet length value included in the header H1 of the last PES packet before switching is corrected to a value up to A1 to form one complete packet up to the break of ES data.

  FIG. 4 is a diagram showing PES data output from the delay buffer 14 by the switching shown in FIG. In this example, the packetizing unit 13 generates a PES packet including the ES frames 4 to 6 after the PES packet including the ES frames 1 to 3 and sends the PES packet to the delay buffer 14. However, in the middle of the PES packet including the ES frames 4 to 6, an instruction to change the delay time by switching the coding bit rate is given. Therefore, the delay buffer control unit 15 completes the ES frame 4 and the ES frame 5 as one PES packet, and corrects the delay time between the PES packets including the next ES frames 6 to 8. At that time, the delay buffer 14 inserts invalid data between the PES packet including the ES frame 4 and the ES frame 5 and the PES packet including the ES frames 6 to 8.

  FIG. 5 is a diagram for explaining a change in the state of the delay buffer 14 when the difference between the write pointer and the read pointer is reduced. 5A shows the state of the delay buffer 14 before switching, FIG. 5B shows the state of the delay buffer 14 in the middle of switching, and FIG. 5C shows the state of the delay buffer 14 after switching. .

  At the time of switching, the delay buffer control unit 15 calculates a pointer position difference X3 from the current write pointer position A4 and the read pointer position B2 notified from the delay buffer.

  Further, the delay buffer control unit 15 obtains the pointer position difference X4 after switching from the switching delay time given as the delay instruction information. Then, the delay buffer control unit 15 determines the position A6 of the first write pointer after switching so that the head A5 of the first PES packet after switching is after A4, and the position of A6 and the position of the pointer after switching are determined. From the difference X4, a predetermined position B3 of the read pointer and the number of frames until the read pointer reaches B3 from B2 are determined.

  The writing is stopped by stopping the encoding unit 11 until the reading pointer comes from B2 to B3. When the stop of writing is continued and the position of the read pointer comes to B3 while maintaining the write pointer at A4 (the state of FIG. 5B), the delay buffer 14 moves the position of the write pointer from A4 to A6.

  Therefore, the delay buffer 14 inserts invalid data M2 from the write pointers A4 to A5, and writes the PES header H4 and the ES frame F2 from A5 to A6 (state shown in FIG. 5C). Further, the packet length value included in the PES header H3 of the last PES packet before switching is corrected to A4, and the ES data break is made one complete PES packet.

  FIG. 6 is a diagram showing PES data output from the delay buffer 14 by the switching shown in FIG. In this example, the packetizing unit 13 generates a PES packet including the ES frame 4 to the ES frame 6 after the PES packet including the ES frame 1 to the ES frame 3 and sends the PES packet to the delay buffer 14. However, in the middle of the PES packet including the ES frame 4 to the ES frame 6, the change of the delay time by switching the coding bit rate is instructed. Therefore, the delay buffer control unit 15 completes the ES frame 4 and the ES frame 5 as one PES packet, and corrects the delay time after that. At that time, the ES frames 6 to 9 overflow and are discarded. The delay buffer 14 inserts invalid data between the PES packet including the ES frame 4 and the ES frame 5 and the PES packet including the ES frames 10 to 12.

  As described above, in the present embodiment, the encoding unit 11 switches the encoding bit rate when the encoding bit rate is switched. Further, the delay buffer control unit 15 obtains information about the pointer of the delay buffer after switching and the packet length of the PES packet to be changed at the time of switching, and notifies the delay buffer 14 of the information. The delay buffer 14 is completed by rewriting the packet length in the header of the PES packet in the middle before switching based on the notification from the delay buffer control unit 15, and changes the pointer position difference to change the operation after switching. To start. Therefore, according to the present embodiment, it is possible to prevent an intermediate PES packet from being discarded in an incomplete state at the time of switching, and to perform switching without reducing the buffer size or the data amount. Sound interruption at the time of bit rate switching is reduced, and deterioration of sound quality is prevented.

  In the present embodiment, the bit rate switching for audio encoding is exemplified, but the present invention is not limited to this, and may be bit rate switching for video encoding as another example.

It is a block diagram which shows the structure of the encoding apparatus of this embodiment. It is a figure which shows the example of PES data. It is a figure for demonstrating the change of the state of the delay buffer 14 when enlarging the difference of a write pointer and a read pointer. It is a figure which shows the PES data output from the delay buffer 14 by the switching shown in FIG. It is a figure for demonstrating the change of the state of the delay buffer 14 when making the difference of a write pointer and a read pointer small. It is a figure which shows the PES data output from the delay buffer 14 by the switching shown in FIG.

Explanation of symbols

11 Encoding unit 12 Encoding buffer 13 Packetization unit 14 Delay buffer 15 Delay buffer control unit E1, E2 ES data P1 PES data

Claims (8)

An encoding device capable of switching an encoding bit rate with a change in delay time,
An encoding unit that encodes input data for each frame and switches an encoding bit rate according to a request;
A packetizing unit for generating a packet including the frame encoded by the encoding unit;
The packet generated by the packetizer is delayed by a predetermined delay time depending on the difference between the write position indicated by the write pointer and the read position indicated by the read pointer, and the coding bit rate is switched. When the packet length information of the packet being written is changed to the notified and changed packet length, the packet is corrected to a complete packet. A delay buffer that discards, inserts invalid data between the last packet before switching and the first packet after switching, and starts writing after switching from the notified first writing pointer after switching;
At the time of switching the coding bit rate, from the information about the delay time before switching, the information about the delay time after switching, and the start position of the packet in the middle of writing, the first write pointer after the switching, and the writing It obtains the modified packet length in the middle of the packet, a delay buffer control unit and a first write pointer and said modified packet length after the switching notifying the delay buffer,
An encoding device. When the delay time increases due to the switching of the encoding bit rate, the delay buffer control unit determines whether the pointers for writing and reading before switching are based on the current write pointer position and read pointer position in the delay buffer. The position difference is calculated, the difference between the position of the write and read pointers after switching is obtained from the given delay time after switching, and the position of the current read pointer and the position of the write and read pointers after the switching The encoding apparatus according to claim 1, wherein the position of the first write pointer after the switching is determined from the difference and notified to the delay buffer. The delay buffer control unit, when the delay time by the switching of the coding bit rate is decreased from the position of the read pointer of the current write pointer in the delay buffer before switching the writing and the reading pointer The position difference is calculated, the position difference between the write and read pointers after switching is obtained from the given delay time after switching, and the head of the first packet after switching is after the current write pointer. Determining the position of the first write pointer after the switching, determining the predetermined position of the read pointer from the position of the first writing pointer after the switching and the difference between the position of the writing and reading pointer after the switching Instruct the delay buffer,
The delay buffer stops writing until a read pointer reaches the predetermined position, and moves the write pointer to the position of the first write pointer after the switching when the read pointer reaches the predetermined position. 2. The encoding device according to 2.   The encoding device according to any one of claims 1 to 3, wherein at least one of an audio signal and a video signal is encoded. A coding bit rate switching method for switching a coding bit rate accompanied by a change in delay time,
The input data is encoded for each frame, a packet including the encoded frame is generated, and the packet is subjected to a predetermined delay time depending on the difference between the write position indicated by the write pointer and the read position indicated by the read pointer. Only delayed
At the time of switching the coding bit rate, from the information about the delay time before switching, the information about the delay time after switching, and the start position of the packet in the middle of writing, the first write pointer after the switching, and the writing Find the changed packet length of the midway packet,
Modify the packet length information of the packet in the middle of writing to the completed packet by changing to the changed packet length,
If there is a frame that overflows due to the delay time change, discard the frame, insert invalid data if necessary between the last packet before switching and the first packet after switching,
Start writing after switching from the first writing pointer after switching,
Encoding bit rate switching method. When the delay time increases due to the switching of the encoding bit rate, the difference between the position of the writing and reading pointer before switching is calculated from the current writing pointer position and the reading pointer position, and the given switching is performed. The difference between the pointer position for writing and reading after switching is obtained from the later delay time, and the first position after switching is calculated from the position of the current reading pointer and the position of the writing and reading pointer after switching. 6. The encoding bit rate switching method according to claim 5, wherein the position of the write pointer is determined. When the delay time is reduced by switching the coding bit rate, the difference between the write and read pointer positions before switching is calculated from the current write pointer position and read pointer position, and the given switch The difference between the positions of the write and read pointers after switching is obtained from the later delay time, and the position of the first write pointer after switching is such that the head of the first packet after switching is after the current write pointer. Determine the predetermined position of the read pointer from the position of the first write pointer after the switching and the difference between the position of the write and read pointer after the switching, and stop writing until the read pointer reaches the predetermined position When the read pointer is at the predetermined position, the write point The move to the position of the first write pointer after the switching, the coding bit rate switching method according to claim 5 or 6.   The coding bit rate switching method according to any one of claims 5 to 7, wherein the coding bit rate of at least one of an audio signal and a video signal is switched.

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