JP4624127B2 - Charge pump circuit - Google Patents

Description

  The present invention relates to a charge pump circuit including a charge transfer switching element and a pumping capacitor.

  In general charge pump circuits, a plurality of charge transfer switching elements are connected in series, and a pumping capacitor is connected to the connection node of these switching elements to form a multi-stage pumping packet. The input voltage applied to the element is boosted or lowered. When VDD is an input voltage and Vout is an output voltage, the output voltage Vout is represented by (N + 1) × VDD in an N-stage charge pump circuit. However, the voltage loss of the switching element is ignored.

  FIG. 6 is a circuit diagram of a two-stage charge pump circuit. This charge pump circuit includes first, second, and third switching elements SW1, SW2, and SW3 connected in series between an input terminal Pin and an output terminal Pout, and a first switching element SW1 and a second switching element. A first capacitor C1 having one terminal connected to the first connection node A with the element SW2, and a first clock driver DRV1 that supplies the first clock CK1 to the other terminal of the first capacitor C1. A second capacitor C2 having one terminal connected to the second connection node B of the second switching element SW2 and the third switching element SW3, and a second terminal connected to the other terminal of the second capacitor C2. And a second clock driver DRV2 that outputs a second clock CK2 (clock having a phase opposite to that of the first clock CK1). Here, when the charge pump circuit is integrated, MOS transistors or bipolar transistors are used as the switching elements SW1, SW2, and SW3.

  The power supply voltage of the first and second clock drivers DRV1, DRV2 is VDD, and this power supply voltage VDD is applied to the input terminal Pin. Further, a smoothing output capacitor Cout is connected to the output terminal Pout.

  Next, the steady-state operation of the above-described charge pump circuit will be described with reference to the operation timing charts of FIGS. The charge pump circuit has two operation modes, mode A and mode B, as shown in FIG. 6A and 6B show the ON / OFF states of the first to third switching elements SW1 to SW3 and the level states of the first clock CK1 and the second clock CK2, respectively, in the mode A and mode B periods. Show.

  In mode A, the first clock CK1 is set to the ground voltage (GND), and the second clock CK2 is set to the high level (VDD). Further, the first switching element SW1 and the third switching element SW3 are turned on, and the second switching element SW2 is turned off. As a result, the voltage of the first node A is VDD, and the voltage of the second node B is 3VDD.

  In the next mode B, the first clock CK1 is set to the high level (VDD), and the second clock CK2 is set to the ground voltage (GND). Further, the first and third switching elements SW1 and SW3 are turned off, and the second switching element SW2 is turned on. As a result, the voltage at the first node A and the second node B becomes 2VDD, and the output voltage Vout becomes 3VDD.

As described above, by alternately repeating the above-described two operations of the mode A and the mode B, it is possible to obtain the output voltage Vout = 3VDD boosted three times at the output terminal Pout.
FIG. 8 is a circuit diagram of a three-stage charge pump circuit.

  The charge pump circuit includes first, second, third, and fourth switching elements SW1, SW2, SW3, and SW4 connected in series between an input terminal Pin and an output terminal Pout, and a first switching element SW1. And a first capacitor C1 having one terminal connected to a first connection node A between the second switching element SW2 and a first clock CK1 that supplies the first clock CK1 to the other terminal of the first capacitor C1. One clock driver DRV1, a second capacitor C2 having one terminal connected to a second connection node B of the second switching element SW2 and the third switching element SW3, and the second capacitor C2. A second clock driver DRV2 that outputs a second clock CK2 (clock having a phase opposite to that of the first clock CK1) to the other terminal; A third capacitor C3 having one terminal connected to the third connection node C of the switching element SW3 and the fourth switching element SW4, and a third clock CK3 ( A third clock driver DRV3 that outputs a clock in phase with the first clock CK1.

  The power supply voltage of the first, second and third clock drivers DRV1, DRV2 and DRV3 is VDD, and the power supply voltage VDD is applied to the input terminal Pin. A smoothing output capacitor Cout is connected to the output terminal Pout.

  Next, the steady state operation of the above-described three-stage charge pump circuit will be described with reference to FIG. 8 and the operation timing chart of FIG. This charge pump circuit has two operation modes, mode A and mode B. FIGS. 8A and 8B show the on / off states of the first to fourth switching elements SW1 to SW4 in the period of mode A and mode B, the first clock CK1, the second clock CK2, and the third, respectively. The level state of the clock CK3 is shown.

  In mode A, the first clock CK1 and the third clock CK3 are set to the ground voltage (GND), and the second clock CK2 is set to the high level (VDD). Further, the first and third switching elements SW1 and SW3 are turned on, and the second and fourth switching elements SW2 and SW4 are turned off. As a result, the voltage of the first node A becomes VDD, and the voltages of the second node B and the third node C become 3VDD.

  In the next mode B, the first clock CK1 and the third clock CK3 are set to the high level (VDD), and the second clock CK2 is set to the ground voltage (GND). Further, the first and third switching elements SW1 and SW3 are turned off, and the second and fourth switching elements SW2 and SW4 are turned on. As a result, the voltages of the first node A and the second node B are 2VDD, and the third node C and the output voltage Vout are 4VDD.

As described above, by alternately repeating the two operations of the mode A and the mode B, it is possible to obtain the output voltage Vout = 4VDD boosted four times at the output terminal Pout.
JP 2001-211637 A

  When stepping up or down using a charge pump circuit, the switching element needs to have a withstand voltage (voltage applied to both ends when the switching element is off). In the conventional two-stage charge pump circuit described above, SW1 and SW3 have a VDD breakdown voltage, but SW2 requires a high breakdown voltage characteristic of 2VDD breakdown voltage. In the above-described conventional three-stage charge pump circuit, SW1 and SW4 have a VDD breakdown voltage, but SW2 and SW3 require a high breakdown voltage characteristic of 2VDD breakdown.

  However, in general, an element having a high withstand voltage has inferior current driving capability. Therefore, the area of such an element (SW2 in the above-described conventional two-stage charge pump circuit and SW2 and SW3 in the above-described conventional three-stage charge pump circuit). Therefore, there is a problem that the chip size of the IC is increased and the cost is increased.

The present invention has been made in view of the above problems, and its main features are as follows. That is, the charge pump circuit of the present invention includes a first switching element, a second switching element, a third switching element connected in series between an input terminal and an output terminal, and the first switching element and the second switching element. A first capacitor having one terminal connected to a first connection node; a first clock driver that outputs a first clock to the other terminal of the first capacitor; and the second switching element; A second capacitor having one terminal connected to a second connection node with the third switching element; a second clock driver for outputting a second clock to the other terminal of the second capacitor; The first and second clocks are set to a first level, the first switching element is turned on, and the second and third switching elements are turned off. Next, the first clock is changed to a second level, the first switching element is turned off, the second switching element is turned on, and then the first clock is changed to the first level. While maintaining the level, the second clock is changed to the second level, the third switching element is turned on, and the first and second switching elements are turned off.
Further, a power supply voltage is applied to the input terminal.
Further, the first level is a ground voltage, and the second level is the power supply voltage.
The first, second, and third switching elements are formed of MOS transistors or bipolar transistors.

  According to the present invention, in the charge pump circuit, the voltage applied to all the switching elements can be suppressed, and the withstand voltage can be suppressed low, so that each switching element exhibits a high current driving capability and can be boosted or stepped down. Can be performed. Since the chip size of the IC is reduced, it is suitable for downsizing and the cost can be kept low.

  Next, embodiments of the charge pump circuit of the present invention will be described with reference to the drawings. First, a first embodiment of the present invention will be described with reference to FIG. 1 and FIG.

  In the first embodiment, the present invention is applied to a two-stage charge pump circuit. As shown in FIG. 1, the charge pump circuit includes first, second, and third switching elements SW1, SW2, and SW3 connected in series between an input terminal Pin and an output terminal Pout, and a first switching element. The first capacitor C1 having one terminal connected to the first connection node A of the element SW1 and the second switching element SW2, and the first clock CKa is output to the other terminal of the first capacitor C1 The first clock driver DRVA, the second capacitor C2 having one terminal connected to the second connection node B of the second switching element SW2 and the third switching element SW3, and the second capacitor A second clock driver DRVB that outputs a second clock CKb is provided at the other terminal of C2. The power supply voltage VDD (for example, +5 V) is applied to the input terminal Pin. A smoothing output capacitor Cout is connected to the output terminal Pout.

  Next, the steady-state operation of the above-described charge pump circuit will be described with reference to the operation timing charts of FIGS. The charge pump circuit normally employs only two operation modes such as mode A and mode B as described in the conventional example. However, the charge pump circuit according to the first embodiment of the present invention has the mode There are three operation modes: A, mode B, and mode C. Here, the mode means the clock level of the first and second clocks CKa and CKb and the pattern of the on / off operation of the switching elements SW1, SW2 and SW3. FIGS. 1A, 1B, and 1C show the on / off states of the first, second, and third switching elements SW1, SW2, and SW3 during the modes A, B, and C, respectively. The level states of the clock CKa and the second clock CKb are shown.

  As shown in FIG. 1A, in mode A, the first and second clocks CKa and CKb are set to a first level, for example, the ground voltage (GND), and the first switching element SW1 is turned on. The second and third switching elements SW2 and SW3 are turned off. As a result, the voltage of the first node A becomes VDD. Here, since the charge pump circuit of the present embodiment forms a loop of mode A, mode B, and mode C as will be described later, a voltage is applied to the second node B in mode A, The voltage is 2VDD.

  Next, as shown in FIG. 1B, in mode B, the second clock CKb is maintained at the ground voltage (GND), and the first clock CKa is set to the second level, for example, the power supply voltage (VDD). At the same time, the second switching element SW2 is turned on, and the first and third switching elements SW1 and SW3 are turned off. Then, when the first clock CKa changes from the ground voltage (GND) to the power supply voltage (VDD), the voltage at the first node A rises from VDD to 2VDD due to the coupling effect of the first capacitor C1. Note that since the second switching element SW2 is on, the voltage of the second node B is also 2VDD.

  Next, as shown in FIG. 1C, in mode C, the first clock CKa is maintained at VDD, the second clock CKb is changed from the ground voltage (GND) to the power supply voltage (VDD), and The third switching element SW3 is turned on, and the first and second switching elements SW1 and SW2 are turned off. Then, when the second clock CKb changes from the ground voltage (GND) to the power supply voltage (VDD), the voltage of the second node B rises from 2VDD to 3VDD due to the coupling effect of the second capacitor C2. Since the third switching element SW3 is on, the output voltage Vout is 3VDD.

  Next, return to mode A. That is, the first clock CKa and the second clock CKb fall to the ground voltage (GND). Also, the first switching element SW1 is turned on, and the second and third switching elements SW2 and SW3 are turned off. As a result, the voltage at the first node A returns to VDD. The voltage of the second node B decreases to 2VDD due to the coupling effect of the second capacitor C2 as the second clock CKb decreases from VDD to GND.

  Thus, in mode A, mode B, and mode C, the switching elements are turned on in order from the first to the third as shown in FIGS. 1A, 1B, and 1C, and the other switching elements are In addition to turning off, the levels of the first and second clocks CKa and CKb are sequentially changed from the ground voltage (GND) to the power supply voltage (VDD) as shown in FIG.

  By repeating the operations of the modes A, B, and C in this order, an output voltage Vout = 3VDD that is three times boosted to the output terminal Pout can be obtained.

  As described above, in the first embodiment, the first clock driver DRVA and the second clock driver DRVB change in three modes such as mode A, mode B, and mode C, and the switching element SW2 When 2 is off, a voltage of 2VDD is not applied to both ends of the switching element SW2. Therefore, according to the charge pump circuit according to the present embodiment, the voltage applied to each switching element is suppressed, the conventional 2VDD breakdown voltage element as described above is not required, and all switching elements are configured by the VDD breakdown voltage element. can do.

  Next, a second embodiment of the present invention will be described with reference to the operation timing charts of FIG. 3, FIG. 4, and FIG.

  In the second embodiment, the present invention is applied to a three-stage charge pump circuit. As shown in FIG. 3, the charge pump circuit includes first, second, third, and fourth switching elements SW1, SW2, SW3, SW4 connected in series between an input terminal Pin and an output terminal Pout. , A first capacitor C1 having one terminal connected to the first connection node A of the first switching element SW1 and the second switching element SW2, and a first terminal connected to the other terminal of the first capacitor C1. A first clock driver DRVA that supplies a second clock CKa, a second capacitor C2 having one terminal connected to a second connection node B of the second switching element SW2 and the third switching element SW3, A second clock driver DRVB for supplying a second clock CKb to the other terminal of the second capacitor C2, a third switching element SW3, A third capacitor C3 having one terminal connected to a third connection node C to the fourth switching element SW4, and a third capacitor CKc for supplying a third clock CKc to the other terminal of the third capacitor C3. And a clock driver DRVC.

  The power supply voltage VDD (for example, +5 V) is applied to the input terminal Pin. A smoothing output capacitor Cout is connected to the output terminal Pout.

  Next, the steady-state operation of the above-described charge pump circuit will be described with reference to the operation timing charts of FIG. 3, FIG. 4, and FIG. The charge pump circuit normally employs only two operation modes such as mode A and mode B as described in the conventional example. However, the charge pump circuit according to the second embodiment of the present invention is There are four operation modes, A, mode B, mode C, and mode D.

  Here, the mode refers to the clock level of the first, second, and third clocks CKa, CKb, and CKc and the on / off operation of the first, second, third, and fourth switching elements SW1, SW2, SW3, and SW4. It shall mean a pattern. FIGS. 3A and 3B show the first, second, third and fourth switching elements SW1 in the period of mode A, mode B, mode C and mode D, respectively. , SW2, SW3, SW4, and the level states of the first clock CKa, the second clock CKb, and the third clock CKc.

  As shown in FIG. 3A, in mode A, the first, second, and third clocks CKa, CKb, and CKc are set to a first level, for example, the ground voltage (GND), and the first switching is performed. The element SW1 is turned on, and the second, third, and fourth switching elements SW2, SW3, and SW4 are turned off. As a result, the voltage of the first node A becomes the same VDD as the input voltage. Here, since the charge pump circuit of this embodiment forms a loop of mode A, mode B, mode C, and mode D as will be described later, a voltage is applied to the second node B in mode A. The voltage is VDD, and similarly, a voltage is applied to the third node C, and the voltage is 3VDD.

  Next, as shown in FIG. 3B, in the mode B, the second and third clocks CKb and CKc are maintained at the ground voltage (GND), and the first clock CKa is set to the second level, for example, the power supply. While changing the voltage (VDD), the second switching element SW2 is turned on, and the first, third, and fourth switching elements SW1, SW3, and SW4 are turned off. Then, when the first clock CKa changes from the ground voltage (GND) to the power supply voltage (VDD), the voltage at the first node A rises from VDD to 2VDD due to the coupling effect of the first capacitor C1. Note that since the second switching element SW2 is on, the voltage of the second node B is also 2VDD.

  Next, as shown in FIG. 4A, in mode C, the first clock CKa is maintained at VDD, the second clock CKb is changed from the ground voltage (GND) to the power supply voltage (VDD), and The third switching element SW3 is turned on, and the first, second, and fourth switching elements SW1, SW2, and SW4 are turned off. Then, when the second clock CKb changes from the ground voltage (GND) to the power supply voltage (VDD), the voltage of the second node B rises from 2VDD to 3VDD due to the coupling effect of the second capacitor C2. Since the third switching element SW3 is on, the voltage at the third node C is also 3VDD. Note that the third clock CKc is maintained at the ground voltage (GND).

  Next, as shown in FIG. 4B, in mode D, the first and second clocks CKa and CKb are maintained at VDD, and the third clock CKc is changed from the ground voltage (GND) to the power supply voltage (VDD). And the fourth switching element SW4 is turned on, and the first, second, and third switching elements SW1, SW2, and SW3 are turned off. Then, when the third clock CKc changes from the ground voltage (GND) to the power supply voltage (VDD), the voltage of the third node C increases from 3VDD to 4VDD due to the coupling effect of the third capacitor C3. Since the fourth switching element SW4 is on, the output voltage Vout is 4VDD.

  Next, return to mode A. That is, the first clock CKa, the second clock CKb, and the third clock CKc drop to the ground voltage (GND). Also, the first switching element SW1 is turned on, and the second, third, and fourth switching elements SW2, SW3, and SW4 are turned off. As a result, the voltage at the first node A returns to VDD. Then, the voltage of the second node B decreases to 2VDD due to the coupling effect of the second capacitor C2 when the second clock CKb decreases from VDD to GND. Then, the voltage of the third node C decreases to 3VDD due to the coupling effect of the third capacitor C3 when the third clock CKc decreases from VDD to GND.

  Thus, in mode A, mode B, mode C, and mode D, the switching elements are arranged in order from first to fourth as shown in FIGS. 3 (a), 3 (b), 4 (a), 4 (b). The other switching elements are turned off, and the levels of the first, second, and third clocks CKa, CKb, and CKc are changed in order from the ground voltage (GND) to the power supply voltage (VDD) as shown in FIG. To change.

  By repeating the operations of the modes A, B, C, and D in this order, the output voltage Vout = 4VDD boosted four times to the output terminal Pout can be obtained.

  As described above, in the second embodiment, the first clock driver DRVA, the second clock driver DRVB, and the third clock driver DRVC have different changes, that is, mode A, mode B, mode C, and mode D, respectively. Thus, four modes are changed, and when the second and third switching elements SW2 and SW3 are turned off, a voltage of 2VDD is not applied to both ends of the switching elements SW2 and SW3. Therefore, the conventional 2VDD breakdown voltage element as described above is not necessary, and all the switching elements can be configured with VDD breakdown voltage elements.

  As described above, according to the embodiment of the present invention, the voltage applied to all the switching elements can be kept low in the charge pump circuit, so that a switching element with a high withstand voltage is not required and all the switching elements are low. It can be composed of a withstand voltage element. Accordingly, each switching element exhibits a high current driving capability, and can perform step-up or step-down. Since the chip size of the IC is reduced, it is suitable for downsizing and the cost can be kept low.

  Although the embodiment has described the charge pump circuit that outputs boosted voltages of 3VDD and 4VDD, it can be similarly applied to a multistage charge pump circuit that outputs a boosted voltage of 5VDD or more.

  The present invention can be applied not only to a charge pump circuit that outputs a boosted voltage, but also to a circuit that outputs a stepped down voltage such as -2 times and -3 times, and a multistage charge pump circuit.

  In the present embodiment, the clock level is changed to the ground voltage (GND) or the power supply voltage (VDD). However, the present invention is not limited to this, and other voltages may be used as necessary.

  When the charge pump circuit according to the present invention is integrated into an IC, a MOS transistor or a bipolar transistor can be used as the switching element.

1 is a circuit diagram of a charge pump circuit according to a first embodiment of the present invention. FIG. 3 is an operation timing chart of the charge pump circuit according to the first embodiment of the present invention. FIG. 4 is a circuit diagram of a charge pump circuit according to a second embodiment of the present invention. FIG. 4 is a circuit diagram of a charge pump circuit according to a second embodiment of the present invention. It is an operation | movement timing diagram of the charge pump circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram of the charge pump circuit of a prior art example. It is an operation | movement timing diagram of the charge pump circuit of a prior art example. It is a circuit diagram of the charge pump circuit of a prior art example. It is an operation | movement timing diagram of the charge pump circuit of a prior art example.

Explanation of symbols

SW1 First switching element SW2 Second switching element SW3 Third switching element SW4 Fourth switching element C1 First capacitor C2 Second capacitor C3 Third capacitor C4 Fourth capacitor Cout Output capacitor
DRVA first clock driver DRVB second clock driver DRVC third clock driver CKa first clock CKb second clock CKc third clock Vin input voltage Vout output voltage VDD power supply voltage GND ground voltage
DRV1 first clock driver DRV2 second clock driver DRV3 third clock driver CK1 first clock CK2 second clock CK3 third clock

Claims (4)

First, second, and third switching elements connected in series between an input terminal and an output terminal;
A first capacitor having one terminal connected to a first connection node between the first switching element and the second switching element;
A first clock driver for outputting a first clock to the other terminal of the first capacitor;
A second capacitor having one terminal connected to a second connection node between the second switching element and the third switching element;
A second clock driver that outputs a second clock to the other terminal of the second capacitor;
Setting the first and second clocks to a first level, turning on the first switching element, turning off the second and third switching elements;
Next, the first clock is changed to a second level, the first switching element is turned off, the second switching element is turned on,
Next, while maintaining the first clock at the first level, the second clock is changed to the second level, the third switching element is turned on, and the first and second A charge pump circuit characterized by turning off a switching element. The charge pump circuit according to claim 1, wherein a power supply voltage is applied to the input terminal. 3. The charge pump circuit according to claim 2, wherein the first level is a ground voltage, and the second level is the power supply voltage. 4. The charge pump circuit according to claim 1, wherein the first, second, and third switching elements are configured by MOS transistors or bipolar transistors. 5.

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