JP4621013B2 - Inverter control device - Google Patents

Description

  The present invention relates to an inverter control device that performs pulse width modulation.

  As this type of inverter, for example, there is a grid-connected inverter that converts the output of a DC power source into AC power and supplies it to a commercial AC power source. Examples of the grid interconnection inverter include a single-phase voltage source inverter and a three-phase voltage source inverter as shown in FIGS.

  For example, in the single-phase voltage source inverter of FIG. 11A, an upper arm 101 in which a switching element (semiconductor element such as IGBT or MOSFET) S1 and a diode d1 are connected in parallel, and a lower arm having the same configuration as the upper arm 101 are provided. 102, the upper arm 103 and the lower arm 104 having the same configuration as the upper arm 101 are connected in series, and the upper and lower arms 101, 102 and the upper and lower arms 103, 104 are connected in parallel. A DC power source 105 is connected to the upper ends of the upper arms 101 and 103 and the lower ends of the lower arms 102 and 104, and from the midpoints of the upper and lower arms 101 and 102 and the midpoints of the upper and lower arms 103 and 104 via the inductor 106. The output current is is output, and the output current iss is supplied to the commercial AC power supply 108 via a low-pass filter (LPF) 107 including a capacitor C and an inductor L.

  As an example of the operation of the single-phase voltage source inverter having such a configuration, the switching elements S1, S4 of the upper and lower arms 101, 104 and the switching elements S2, S3 of the upper and lower arms 102, 103 are synchronized with a carrier signal of several tens of kHz. There is a method of turning on and off alternately. As a result, the output current is is controlled to generate an AC output current is whose frequency is sufficiently lower than that of the carrier signal, and the LPF 107 removes the harmonic component from the AC output current is and does not include the harmonic component. The AC output current iss is supplied to the commercial AC power supply 108.

  In addition, a dead time is set between the switching element S1 of the upper arm 101 and the switching element S2 of the lower arm 102 so that the switching elements S1 and S2 are not simultaneously turned on. ing. Similarly, in the upper and lower arms 103 and 104, both switching elements S3 and S4 are simultaneously turned on during a period in which the switching element S3 of the upper arm 103 is turned on and a period in which the switching element S4 of the lower arm 104 is turned on. A dead time is set for not.

  Since this dead time takes time for the switching element to become completely non-conductive even if the command to the switching element is switched from on to off, for example, the command to the switching element S1 of the upper arm 101 is turned off. Then, if the command to the switching element S2 of the lower arm 102 is immediately turned on, or turned on in the reverse order and then immediately turned off, the switching elements S1 and S2 connected in series are instantaneously conducted, Since both ends of the DC power supply 105 are short-circuited, the setting is made to prevent this short-circuit.

  However, the setting of this dead time causes an inconvenience that an error occurs in the inverter output voltage vB and the AC output current is is distorted.

For this reason, for example, in Patent Document 1, a voltage command value and a compensation voltage of the inverter output voltage vB are generated based on the command value of the output current, the compensation voltage is added to the voltage command value, and the inverter is based on this sum. The switching timing of the switching elements is controlled, thereby reducing an error in the inverter output voltage vB due to dead time. Further, when the output current command value is near 0, the error of the inverter output voltage vB is small. Therefore, the compensation voltage is set to 0 or a value near 0 so that the output is hardly compensated.
JP-A-6-62580

  However, Patent Document 1 requires complicated calculation processing such as obtaining a compensation voltage based on the command value of the output current or adding the compensation voltage to the voltage command value, and the circuit configuration for this calculation processing is also complicated. There was a problem of becoming.

  Therefore, the present invention has been made in view of the above-described conventional problems, and an object thereof is to provide an inverter control device that does not require complicated arithmetic processing.

In order to solve the above-described problems, the present invention connects a plurality of upper and lower arms connected in parallel by connecting upper and lower arms in which switching elements (semiconductor elements such as IGBTs and MOSFETs) are inserted in series. A first operation for connecting the power supply to both ends of the upper and lower arms of each group and taking out the output from the midpoint of the upper and lower arms of each group, and turning on the switching element of the upper arm that supplies the output current flowing to the positive polarity side. The mode period and the second operation mode period in which the switching element of the lower arm that supplies the output current flowing to the negative polarity side is turned on are alternately repeated, and all upper and lower arms are interposed between the first operation mode period and the second operation mode period. In the inverter control device for setting the dead time for turning off the switching element, the carrier signal is compared with the first and second arm command values different from each other, and the carrier When the signal becomes less than the first arm command value, the first operation mode period is set. When the carrier signal exceeds the second arm command value, the second operation mode period is set. Timing setting means for setting the dead time when it is between the second arm command values, and the output current from the middle point of each of the upper and lower arms of the inverter is near 0, more positive than near 0, and near 0 And a timing setting unit that determines whether the output current is in the vicinity of 0 when the determination unit determines that the output current is near zero. Is decreased by Δv and the second arm command value is increased by Δv. When the determination means determines that the output current is on the positive polarity side, the second arm command value is increased by 2Δv over one period of the carrier signal. When the output means determines that the output current is on the negative polarity side, the first arm command value is decreased by 2Δv over one period of the carrier signal, the dead time setting timing is changed, and before and after the dead time The first operation mode period and the second operation mode period are reciprocally expanded and contracted .

  Further, in the present invention, the judging means is configured such that the output current is near 0 based on the comparison result between the value corresponding to the output current level from the midpoint of each arm of the inverter and two different threshold values. It is determined whether it is on the positive polarity side or the negative polarity side from the vicinity of 0, and each threshold value is changed according to the condition of the inverter.

Furthermore, the present invention further includes connecting upper and lower arms each having a switching element (semiconductor element such as IGBT or MOSFET) connected in series, connecting a plurality of sets of upper and lower arms in parallel, and connecting a DC power supply to each group. A first operation mode period in which an output is taken out from the middle point of each pair of upper and lower arms, and an upper arm switching element for passing an output current flowing to the positive polarity side is turned on, and The second operation mode period for turning on the lower arm switching element for flowing the output current flowing to the negative polarity side is alternately repeated, and the switching elements of all the upper and lower arms are switched between the first operation mode period and the second operation mode period. In the inverter control device for setting the dead time to be turned off, the carrier signal is compared with the first and second arm command values different from each other, and the carrier signal is the first arm. When the carrier signal becomes less than the command value, the first operation mode period is set, when the carrier signal exceeds the second arm command value, the second operation mode period is set, and the carrier signal is the first and second arm command values. The timing setting means for setting the dead time when the output current is between ON and OFF of each upper and lower arm of the inverter, and the output current from the middle point of each upper and lower arm when OFF and ON is on the positive side or the negative side A timing setting unit that determines whether the output current flows to the positive polarity side when the determination unit determines that the output current flows to the positive polarity side. When the second arm command value is increased by 2Δv over the carrier signal half cycle including the timing, and the determination means determines that the output current flows to the negative polarity side, the ON → OFF or OFF → Decrease the first arm command value by 2Δv over the carrier signal half cycle including the ON switching timing, change the dead time setting timing, the first operation mode period and the second operation mode period before and after the dead time Has changed .

  According to the present invention as described above, it is determined whether the output current from the midpoint of each arm of the inverter is in the vicinity of 0, the positive side from the vicinity of 0, or the negative side from the vicinity of 0, Based on the determination result, the dead time setting timing is changed, and accordingly, the ON period and the OFF period of each switching element before and after the dead time are reciprocally expanded and contracted.

  Here, when the output current is close to 0, the error of the inverter output voltage vB decreases, so that the waveform distortion of the output current decreases. Therefore, there is almost no need to compensate the inverter output voltage vB. Further, depending on whether the output current is on the positive polarity side near 0 or on the negative polarity side near 0, the path of the current flowing in the upper and lower arms changes before or after the dead time, so that the inverter output voltage vB The output voltage error causes distortion of the output current waveform.

  On the other hand, if the dead time setting timing is changed and the ON and OFF periods of each switching element before and after the dead time are reciprocally expanded and contracted, the current path of each upper and lower arm before and after the dead time changes and the inverter output The voltage vB changes.

  Therefore, as in the present invention, the dead time setting timing is changed based on the determination result of the output current from the middle point of each arm of the inverter, and the ON period and the OFF period of each switching element before and after the dead time are contradictory. If the current path of the upper and lower arms before and after the dead time is changed, the error of the inverter output voltage vB can be reduced and the waveform distortion of the output current can be compensated.

  In addition, since complicated calculation processing is not required for the determination relating to the output current and the change of the dead time, the circuit configuration is simple.

  For example, a value corresponding to the output current level is compared with two different threshold values, and if the output current level is between the threshold values, it is determined that the output current is near 0, and the output current level is If it is on the positive polarity side from each threshold, it is determined that the output current is on the positive polarity side near the zero, and if the output current level is on the negative polarity side from each threshold, the output current is zero. What is necessary is just to determine that it exists in the negative polarity side rather than the vicinity. Further, since the waveform of the output current varies depending on the state of the inverter, each threshold value may be changed according to the operation state of the inverter. As a result, the error of the inverter output voltage vB can be compensated, and therefore the waveform distortion of the output current can be compensated more accurately.

  According to another aspect of the present invention, the polarity of the output current from the middle point of each arm of the inverter when each of the upper and lower arms is turned on → off and turned off → on is determined, and the dead time is set based on the determination result. The timing is changed, and accordingly, the ON period and OFF period of each switching element before and after the dead time are changed.

  Strictly speaking, in the present invention, the output current waveform distortion occurs because the voltage pulse of the inverter output voltage vB is not centrally arranged in each switching period when the output current is near zero. For this reason, the dead time setting timing is changed according to the polarity of the output current from the middle point of each inverter arm when the upper and lower arms are turned on → off and off → on as in the present invention. If the on and off periods of the switching elements before and after are changed and the current path of the upper and lower arms before and after the dead time is changed, the voltage of the inverter output voltage vB regardless of whether it is near zero or not. Since the pulse is centrally arranged in each switching period, the waveform distortion of the output current is compensated, and more accurate compensation is possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a circuit diagram schematically showing a control device for a grid-connected inverter according to a first embodiment of the present invention. The grid interconnection inverter 1 includes a single-phase voltage source inverter unit 2 and a control unit 3. The single-phase voltage source inverter unit 2 converts the DC power of the DC power source 4 into an AC output current is and supplies the output current is to the commercial AC power source 5. Further, the control unit 3 performs pulse width modulation on the single-phase voltage source inverter unit 2 to match the frequency and phase of the AC output current is with the frequency and phase of the AC voltage of the commercial AC power supply 2, or to adjust the output current is to the output current is. The included harmonics are reduced to bring the output current is closer to a sine waveform.

  In the single-phase voltage source inverter unit 2, the upper arm 11 and the lower arm 12 into which the respective switching elements S1 and S2 are inserted are connected in series, and the upper arm 13 and the lower arm into which the respective switching elements S3 and S4 are inserted. 14 are connected in series, and the upper and lower arms 11 and 12 and the upper and lower arms 13 and 14 are connected in parallel. The DC power source 4 is connected to the upper ends of the upper arms 11 and 13 and the lower ends of the lower arms 12 and 14, and the midpoints of the upper and lower arms 11 and 12 and the midpoints of the upper and lower arms 13 and 14 are passed through the inductor 15. The output current is is output, and this output current is is supplied to the commercial AC power supply 5.

  The control unit 3 receives a carrier signal Ch of several tens of kHz, and in synchronization with the carrier signal Ch, the switching elements S1, S4 of the upper and lower arms 11, 14 and the switching elements S2, S3 of the upper and lower arms 12, 13 Are turned on reciprocally, or the switching elements S1 to S4 of all the upper and lower arms 11 to 14 are turned off to form the AC output current is.

  Here, the carrier signal Ch is a triangular wave of tens of kHz as shown in FIG. The control unit 3 receives not only the carrier signal Ch but also an output voltage command value PV and an output current command value PI that respectively indicate the output voltage vB and the output current is of the inverter unit 2, and the output voltage command value PV The first arm command value A1 and the second arm command value A2 are set with reference to the carrier signal Ch, the carrier signal Ch is compared with the first and second arm command values A1 and A2, and each of the upper and lower arms is based on the comparison result. The switching elements S1 to S4 of 11 to 14 are on / off controlled to form an AC output current is.

  For example, as shown in FIG. 2B, the first and second arm command values A1 and A2 are set by adding or subtracting a constant voltage width Δv to the output voltage command value PV. In this case, since the level vC of the carrier signal Ch is larger than the second arm command value A2 (vC> A2) in the period T2 immediately before the time point t01, the switching elements S1 and S4 of the upper and lower arms 11 and 14 are turned off, The switching elements S2 and S3 of the upper and lower arms 12 and 13 are turned on. Thereby, the second operation mode as shown in FIG. 3B is set, and the positive electrode of the DC power supply 4 → the switching element S3 of the upper arm 13 → the commercial AC power supply 5 → the inductor 15 → the switching element S2 of the lower arm 12 → A current path called a negative electrode of the DC power supply 4 is formed.

  At the dead time DT from time t01 to t03 after the second operation mode period, the level vC of the carrier signal Ch is equal to or lower than the second arm command value A2 and equal to or higher than the first arm command value A1 (A2 ≧ vC). ≧ A1), the switching elements S1 to S4 of all the upper and lower arms 11 to 14 are turned off.

  Further, in the period T1 from time t03 to time t06, the level vC of the carrier signal Ch is smaller than the first arm command value A1 (A1> vC), so the switching elements S1 and S4 of the upper and lower arms 11 and 14 are turned on, The switching elements S2 and S3 of the upper and lower arms 12 and 13 are turned off. Thereby, the first operation mode as shown in FIG. 3A is set, and the positive electrode of the DC power supply 4 → the switching element S1 of the upper arm 11 → the inductor 15 → the commercial AC power supply 5 → the switching element S4 of the lower arm 14 → A current path called a negative electrode of the DC power supply 4 is formed.

  At the dead time DT from time t06 to t08 after the first operation mode period, the level vC of the carrier signal Ch is equal to or lower than the second arm command value A2 and equal to or higher than the first arm command value A1 (A2 ≧ vC ≧ A1). ) The switching elements S1 to S4 of all the upper and lower arms 11 to 14 are turned off.

  In the period T2 immediately after the time point t08, the level vC of the carrier signal Ch again becomes larger than the second arm command value A2 (vC> A2), so that the switching elements S1 and S4 of the upper and lower arms 11 and 14 are turned off. Then, the switching elements S2 and S3 of the upper and lower arms 12 and 13 are turned on to set the second operation mode as shown in FIG.

  Thereafter, similarly, in synchronization with the carrier signal Ch, all the switching elements S1 to S4 in the dead time are turned off (dead time DT), the first operation mode (period T1), and all the switching elements S1 to S4 in the dead time are turned off ( The operation sequence of the dead time DT), the second operation mode (period T2), and all the switching elements S1 to S4 in the dead time are turned off (dead time DT) is repeated.

  The output voltage command value PV indicates the output voltage vB of the inverter unit 2 and changes in synchronization with the AC voltage vs of the commercial AC power supply 2. When the output voltage command value PV rises to the positive side and the first and second arm command values A1 and A2 also rise, the first operation mode period T1 becomes longer and the second operation mode period T2 becomes shorter, The output current is rises to the positive polarity side. Further, when the output voltage command value PV decreases to the negative side and the first and second arm command values A1 and A2 also decrease, the first operation mode period T1 becomes shorter and the second operation mode period T2 becomes longer. Thus, the output current is drops to the negative polarity side. By repeating this, an output current is synchronized with the AC voltage vs of the commercial AC power supply 2 is formed and output.

  The graph of FIG. 4 schematically shows the output current command value PI and the current is (= output current) of the inductor 15. As apparent from the graph of FIG. 4, the output current io repeatedly rises and falls according to the output current command value PI, and has a waveform synchronized with the AC voltage vs of the commercial AC power supply 5. In addition, the output current io includes a harmonic component due to the on / off operation of each of the switching elements S1 to S4 with respect to the carrier signal Ch. This harmonic component is filtered by a low-pass filter (LPF) 107 shown in FIG. 11A and supplied to the commercial AC power supply 5.

  The dead time DT is the first because the switching element takes time until it becomes completely non-conductive even if the command to the switching element (semiconductor element such as IGBT and MOSFET) is switched from on to off. When the operation mode is immediately shifted to the second operation mode, or conversely, when the second operation mode is immediately shifted to the first operation mode, all the switching elements S1 to S4 or the switching elements S1 and S2 or the switching elements S3 and S4 are turned on. Since both terminals of the DC power supply 4 are short-circuited and are short-circuited, they are set to prevent this short circuit.

  Further, as shown in FIG. 3C, a third operation mode in which the switching elements S1 and S3 of the upper arms 11 and 13 are turned on and the switching elements S2 and S4 of the lower arms 12 and 14 are turned off, and As shown in FIG. 3D, the fourth operation mode in which the switching elements S1 and S3 of the upper arms 11 and 13 are turned off and the switching elements S2 and S4 of the lower arms 12 and 14 are turned on is the first operation mode. The output current is may be controlled by appropriately inserting between the operation mode, the second operation mode, and the dead time.

  By the way, if the output voltage command value PV is added or subtracted from the output voltage command value PV, the first and second arm command values A1 and A2 are set, and the time DT / 2 (dead time) corresponding to the output voltage command value PV is set. If the process of equally allocating (1/2 time of DT) to the period T1 and the period T2 is performed regularly, there is a disadvantage that an error occurs in the output voltage vB of the inverter.

  For example, when the output current is is sufficiently increased to the positive polarity side, the output current is remains in the R direction in FIG. 1 and the output current is is changed according to the first and second operation modes. Increase and decrease are repeated. In the dead time DT, the output current is in the R direction is maintained despite the fact that all the switching elements S1 to S4 are turned off. Therefore, as shown in FIG. A current path of negative electrode → parasitic diode d2 of switching element S2 of lower arm 12 → inductor 15 → commercial AC power supply 5 → parasitic diode d3 of switching element S3 of upper arm 13 → positive electrode of DC power supply 4 is formed. Accordingly, a current path similar to that in the second operation mode is formed while the dead time DT is being used.

  For this reason, not only in the period T2 in the second operation mode but also in the dead time DT, a current path similar to that in the second operation mode is formed, and apparently the period T2 in the second operation mode is extended. Is done. As a result, an error occurs in the output voltage vB of the inverter before or after the dead time DT, and thus an error occurs in the output current is.

  Similarly, when the output current is sufficiently lowered to the negative polarity side, the output current is is kept in the L direction in FIG. 1 according to the first and second operation modes. The increase / decrease is repeated. In the dead time DT, the output current is in the L direction is maintained even though all the switching elements S1 to S4 are turned off, so that the DC power supply 4 is connected as shown in FIG. A current path of negative electrode → parasitic diode d4 of switching element S4 of lower arm 14 → commercial AC power supply 5 → inductor 15 → parasitic diode d1 of switching element S1 of upper arm 11 → positive electrode of DC power supply 4 is formed. Therefore, a current path similar to that in the first operation mode is formed while the dead time DT is being used.

  For this reason, a current path similar to that in the first operation mode is formed not only in the first operation mode period T1 but also in the dead time DT, and apparently the first operation mode period T1 is extended. Is done. As a result, an error occurs in the output voltage vB of the inverter before or after the dead time DT, and thus an error occurs in the output current is.

  Thus, if an error occurs in the output voltage vB of the inverter before or after the dead time, this error appears as a waveform distortion of the output current is.

  The output current is with such distortion and the current iss supplied to the commercial AC power supply 5 are illustrated in the graphs of FIGS. 6 (a) and 6 (b). As is clear from these graphs, the output current is and the current iss supplied to the commercial AC power supply 5 are deviated from the output current command value PI and distorted.

  However, when the output current is is close to 0, the polarity of the output current is often changes every time the dead time DT, and it is difficult for the output current is to remain in the same polarity. There is almost no error in the output current is.

  Therefore, in order to compensate for such waveform distortion of the output current is, the control unit 3 of the present embodiment has an output current is from the midpoint of each arm of the inverter that is near 0, more positive than the vicinity of 0, And on the negative side of the vicinity of 0, and based on the determination result, the setting timing of the dead time DT is changed, and accordingly, the ON period of each switching element before and after the dead time DT T1 and the off period T2 are reciprocally expanded and contracted.

  Next, control of the output current is by the control unit 3 will be described according to the flowchart of FIG.

  First, the control unit 3 inputs the operation status data indicating the operation status of the inverter to the determination unit 31 (step S101), and the determination unit 31 performs the first operation as shown in FIG. 4 based on the operation status data. 1 and the second threshold value ± δ are set, and a range near 0 described later is appropriately set (step S102). The ± δ is set for each switching period.

  This operating state data indicates the inductance of the fixed inductor 15 and the frequency of the carrier signal Ch, the value of the variable output current is, and the like. For example, the determination unit 31 decreases the absolute values of the first and second threshold values ± δ as the inductance of the inductor 15 increases, or decreases the absolute values of the first and second threshold values ± δ as the inductance decreases. Increase the value. Alternatively, the absolute values of the first and second threshold values ± δ are decreased as the frequency of the carrier signal Ch is increased, and the absolute values of the first and second threshold values ± δ are increased as the frequency is decreased.

  Then, the determination unit 31 compares the output current command value PI as shown in FIG. 4 with the first and second threshold values ± δ, and on the basis of the comparison result, the output current is is near 0, more than the near 0. Whether it is on the positive polarity side or on the negative polarity side from the vicinity of 0 is determined (step S103). That is, if the output current command value PI is larger than the first and second threshold values ± δ and PI> + δ> −δ, it is determined that the output current is is on the positive polarity side from near 0 (step S103). ("Positive side"). If the output current command value PI is between the first and second threshold values ± δ and + δ ≧ PI ≧ −δ, it is determined that the output current is is near 0 (“near 0” in step S103). ). Further, if the output current command value PI is smaller than the first and second threshold values ± δ and + δ> −δ> PI, it is determined that the output current is is on the negative polarity side near 0 (in step S103). “Negative side”).

  Next, the control unit 3 inputs the determination result by the determination unit 31 to the timing setting unit 32. Based on the determination result, the timing setting unit 32 changes the first and second arm command values A1 and A2, changes the setting time of the dead time DT, and turns on each switching element before and after the dead time DT. The T1 and the off period T2 are reciprocally expanded and contracted.

  For example, if it is determined that the output current is is close to 0 (“near 0” in step S103), the timing setting unit 32 is constant with respect to the output voltage command value PV as shown in FIG. The first and second arm command values A1 and A2 are set by adding or subtracting the voltage width Δv.

  In this case, the dead time DT is not changed, and the first operation mode period T1 and the second operation mode period T2 are not expanded or contracted. Therefore, the error of the inverter output voltage vB before and after the dead time DT is not compensated (steps S104 and S105).

  This is because, as described above, when the output current is is near 0, there is almost no error in the output current is because there is no error in the output voltage vB of the inverter before or after the dead time DT. is there.

  If it is determined that the output current is is on the positive polarity side near 0 (“positive polarity side” in step S103), the timing setting unit 32 outputs the output voltage command as shown in FIG. The first arm command value A1 is made to coincide with the value PV, and a value obtained by adding a voltage width 2Δv corresponding to twice the constant voltage width Δv to the first arm command value A1 is set as the second arm command value A2. .

  In this case, the first and second arm command values A1 and A2 are increased by a constant voltage width Δv as compared with the case where the output current is shown in FIG. Each time t00 and t02 when vC is equal to or less than the second arm command value A2 and equal to or greater than the first arm command value A1 is shifted to the T2 side by the time DT / 2 (half time of the dead time DT). DT approaches T2 side for time DT / 2. Similarly, each time point when the level vC of the carrier signal Ch becomes equal to or lower than the second arm command value A2 and equal to or higher than the first arm command value A1 as compared to when the output current is shown in FIG. t07 and t09 approach the T2 side by time DT / 2, and the dead time DT approaches the T2 side by time DT / 2. Accordingly, the period T1 of the first operation mode is substantially extended, and the period T2 of the second operation mode is substantially shortened (steps S106 and S107).

  When the period T2 of the second operation mode is substantially shortened in this way, as described above, when the output current is from the center point of each arm of the inverter remains in the R direction in FIG. In addition, although the period T2 of the second operation mode is extended, this apparent extension of T2 is cancelled. As a result, no error occurs in the output voltage vB of the inverter before or after the dead time DT, so that the error of the output current is is compensated.

  Furthermore, if it is determined that the output current is is on the negative polarity side from near zero (“negative polarity side” in step S103), the timing setting unit 32 outputs the output voltage command as shown in FIG. A value obtained by matching the second arm command value A2 with the value PV and subtracting a voltage width 2Δv corresponding to twice the constant voltage width Δv from the second arm command value A2 is set as the first arm command value A1. .

  In this case, since the first and second arm command values A1 and A2 are reduced by a constant voltage width Δv as compared to when the output current is shown in FIG. 2B is near 0, the level of the carrier signal Ch Each time point t02 and t04 at which vC is equal to or smaller than the second arm command value A2 and equal to or greater than the first arm command value A1 approaches the T1 side by time DT / 2, and the dead time DT approaches the T1 side by time DT / 2. . Similarly, each time point when the level vC of the carrier signal Ch becomes equal to or lower than the second arm command value A2 and equal to or higher than the first arm command value A1 as compared to when the output current is shown in FIG. t05 and t07 are shifted to the T1 side by the time DT / 2, and the dead time DT is shifted to the T1 side by the time DT / 2. Accordingly, the period T1 of the first operation mode is substantially shortened, and the period T2 of the second operation mode is substantially extended (Steps S108 and S109).

  When the period T1 of the first operation mode is substantially shortened in this way, the period T1 of the first operation mode apparently appears in the state where the output current is remains in the L direction in FIG. 1 as described above. Is extended, but this apparent extension of T1 is cancelled. As a result, no error occurs in the output voltage vB of the inverter before or after the dead time DT, so that the error of the output current is is compensated.

  Thus, in the present embodiment, when the output current is from the midpoint of each arm of the inverter is near 0, the timing of the dead time DT is not changed, and the output current is is closer to the positive polarity side than near 0. Sometimes, the dead time DT is shifted to the T2 side by the time DT / 2 to extend the first operation mode period T1, to shorten the second operation mode period T2, and to further reduce the output current is from near zero. When it is on the sex side, the dead time DT is shifted to the T1 side by the time DT / 2 to shorten the period T1 of the first operation mode and extend the period T2 of the second operation mode. The apparent extension of the first operation mode period T1 and the second operation mode period T2 is canceled, and the inverter output voltage v before or after the dead time DT. Error in the output current is is compensated for errors does not occur.

  Further, since a complicated calculation process is not required for the determination relating to the output current is and the change of the dead time DT, the circuit configuration can be simplified.

  Furthermore, since the first and second threshold values ± δ are set based on the operating status data indicating the operating status of the inverter and the range near 0 is appropriately set, the waveform distortion of the output current is is more accurately determined. Can be compensated.

  Next, the control apparatus of the grid connection inverter which is 2nd Embodiment of this invention is demonstrated.

  The grid interconnection inverter of the present embodiment has the same configuration as that of the grid interconnection inverter 1 of FIG. 1, and a part of the dead time imparting method by the control unit 3 is different.

  As described above, when the output current is from the middle point of each arm of the inverter is near 0, an error occurs in the output current is because there is no error in the output voltage vB of the inverter before or after the dead time DT. There is almost no. Strictly speaking, however, the waveform of the output current is is generated because the voltage pulse of the inverter output voltage vB is not centrally arranged in each switching period even near zero.

  Therefore, when the output current is is near 0, the control unit 3 of the present embodiment determines whether the output current is when the upper and lower arms are on → off and off → on is positive or negative. By changing the setting timing of the dead time DT, the period T1 of the first operation mode and the period T2 of the second operation mode before and after the dead time DT are changed, and the current paths of the upper and lower arms before and after the dead time DT are changed. change. Thereby, even near 0, the voltage pulse of the inverter output voltage vB is centrally arranged in each switching period, so that the waveform distortion of the output current is is compensated and more accurate compensation is performed.

  Next, control of the output current is by the control unit 3 will be described with reference to the flowchart of FIG. In FIG. 8, the same step S as in FIG. Therefore, description of each step S101-S103, each step S106-S107, and each step S108-S109 is abbreviate | omitted, and only each step S111-S113 following step S103 is demonstrated.

  When the determination unit 31 determines that the output current is is near 0 (“near 0” in step S103), the output current is is positive when the upper and lower arms are turned on → off and turned off → on. And the negative polarity (step S111), and the determination result by the determination unit 31 is input to the timing setting unit 32.

  If it is determined that the output current is is near zero and the output current is positive when the upper and lower arms are turned on → off and turned off → on (“near 0” in step S103). As shown in FIG. 9 (when the slope of the carrier signal Ch is negative), the first arm command value A1 is matched with the output voltage command value PV as shown in FIG. A value obtained by adding a voltage width 2Δv corresponding to twice the constant voltage width Δv to the value A1 is set as the second arm command value A2 (step S112).

As a result, for example, as shown in FIG. 9, the second arm command value A1 is increased by a constant voltage width 2Δv, so that the level vC of the carrier signal Ch is not more than the second arm command value A2 and not less than the first arm command value A1. The respective time points t00 and t02 are shifted to the period T2 side by the time DT / 2, and the dead time DT is shifted to the T2 side by the time DT / 2. For this reason, before and after the dead time DT at this time, the period T1 of the first operation mode is substantially extended, and the period T2 of the second operation mode is substantially shortened (step S113).

  Further, the timing setting unit 32 determines that the output current is is in the vicinity of 0 and that the output current is is negative when the upper and lower arms are turned on → off and turned off → on (“ As shown in FIG. 9 (when the slope of the carrier signal Ch is positive), the second arm command value A2 is matched with the output voltage command value PV as shown in FIG. A value obtained by subtracting a voltage width 2Δv corresponding to twice the constant voltage width Δv from the arm command value A2 is set as the first arm command value A1 (step S114).

As a result, for example, as shown in FIG. 9, the first arm command value A1 is reduced by a constant voltage width 2Δv, so that the level vC of the carrier signal Ch is not more than the second arm command value A2 and not less than the first arm command value A1. The respective time points t05 and t07 are shifted to the period T1 side by the time DT / 2, and the dead time DT is shifted to the T1 side by the time DT / 2. Therefore, before and after the dead time DT at this time, the period T1 of the first operation mode is substantially shortened and the period T2 of the second operation mode is substantially extended (step S115).

  As described above, in this embodiment, when the output current is is close to 0, it is determined whether the output current is is positive or negative when each of the upper and lower arms is turned on → off and turned off → on. When the current is is positive, the dead time DT is shifted to the T2 side by the time DT / 2 to extend the first operation mode period T1, shorten the second operation mode period T2, and output current is. Is negative, the dead time DT is shifted to the T1 side by the time DT / 2 to shorten the period T1 of the first operation mode and extend the period T2 of the second operation mode. For this reason, even when the output current is is near 0, the voltage pulse of the inverter output voltage vB is centrally arranged in each switching period, so that the waveform distortion of the output current is is compensated.

  Also in this case, the circuit configuration is simple because no complicated arithmetic processing is required for the determination relating to the output current is and the change of the dead time DT.

  In addition, this invention is not limited to said each embodiment, It can deform | transform variously. For example, another method can be applied as a method for determining whether the output current is is in the vicinity of 0, on the positive side of the vicinity of 0, or on the negative side of the vicinity of 0. For example, for each cycle of the carrier signal, it is determined whether or not the output current is crosses 0. If the output current is crosses 0, it is determined that the output current is is close to 0 and the output current is is 0. If it does not cross, it may be determined whether the output current is is on the positive polarity side or the negative polarity side.

  Further, instead of the output current command value PI, an actual output current is is detected, and the output current is is detected when the output current is is near 0, more positive than near 0, and more negative than near 0. It may be used to determine which side is on the side.

  Further, in the second embodiment, the control near 0 is performed regardless of whether the output current is is near 0, on the positive side of the vicinity of 0, or on the negative side of the vicinity of 0. You may also go. Also by this, the same operation and effect as the first embodiment can be achieved. Further, the present invention is applicable not only to a single-phase voltage source inverter but also to a three-phase voltage source inverter having three sets of upper and lower arms 11 and 12, 13 and 14, and 17 and 18 as shown in FIG. Can do. Furthermore, the present invention can be applied not only to a grid-connected inverter that supplies an output current is to a commercial AC power supply but also to an inverter that supplies an output to a load that consumes power. Alternatively, only the first operation mode and the dead time in FIG. 3A are alternately repeated to form an output waveform on the positive polarity side, and only the second operation mode and the dead time in FIG. 3B are alternately repeated. Thus, the present invention can also be applied to an inverter that forms an output waveform on the negative polarity side.

It is a circuit diagram which shows roughly the control apparatus of the grid connection inverter which is 1st Embodiment of this invention. (A) thru | or (c) is the figure used in order to demonstrate the on-off control of the switching element of an upper and lower arm based on the comparison result of the carrier signal and the 1st and 2nd arm command value in the inverter of 1st Embodiment. . (A) thru | or (d) is a figure which shows the 1st thru | or 4th operation mode in the inverter of 1st Embodiment. It is a graph which shows typically the output current command value in the inverter of a 1st embodiment, and the output current just before an inductor. (A) And (b) is a figure which shows each current path at the time of the dead time in the inverter of 1st Embodiment. (A) And (b) is a graph which shows the output current with a distortion, and the output current just before an inductor. It is a flowchart which shows the control process of the output current in the inverter of 1st Embodiment. It is a flowchart which shows the control process of the output current in the control apparatus of the grid connection inverter which is 2nd Embodiment of this invention. It is the figure used in order to demonstrate on-off control of the switching element of an upper and lower arm based on the comparison result of the carrier signal and the 1st and 2nd arm command value in the inverter of a 2nd embodiment. It is a circuit diagram which shows roughly the three-phase voltage source inverter which can apply this invention. (A), (b) is a circuit diagram which shows roughly a common single phase voltage source inverter and a three phase voltage source inverter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 System interconnection inverter 2 Single phase voltage source inverter part 3 Control part 4 DC power supply 5 Commercial AC power supply 11, 13 Upper arm 12, 14 Lower arm S1, S2, S3, S4 Switching element 15 Inductor 31 Determination part 32 Timing setting part

Claims (3)

Connect the upper and lower arms with each switching element (semiconductor elements such as IGBT and MOSFET) connected in series, connect multiple sets of upper and lower arms in parallel, and connect the DC power supply to both ends of each set of upper and lower arms. The output is taken out from the midpoint of the upper and lower arms of each set, the first operation mode period during which the switching element of the upper arm that supplies the output current flowing to the positive polarity side is turned on, and the output current that flows to the negative polarity side The second operation mode period in which the switching elements of the lower arm to be turned on are alternately repeated, and a dead time for turning off all the upper and lower arm switching elements is set between the first operation mode period and the second operation mode period. In the inverter control device,
The first and second arm command values different from each other are compared with the carrier signal, the first operation mode period is set when the carrier signal becomes less than the first arm command value, and the carrier signal is the second arm command value. A timing setting means for setting a second operation mode period when exceeding, and setting a dead time when the carrier signal is between the first and second arm command values;
Determining means for determining whether the output current from the middle point of each upper and lower arm of the inverter is near 0, on the positive side from near 0, and on the negative side from near 0,
When the determination means determines that the output current is near 0, the timing setting means decreases the first arm command value by Δv and increases the second arm command value by Δv over one period of the carrier signal. When the output current is determined to be on the positive polarity side, the second arm command value is increased by 2Δv over one cycle of the carrier signal, and when the determination means determines that the output current is on the negative polarity side, The first arm command value is lowered by 2Δv over one carrier signal period, the dead time setting timing is changed, and the first and second operation mode periods before and after the dead time are reciprocally expanded and contracted. Inverter control device.   Based on the comparison result between the value corresponding to the output current level and two different threshold values, the determination means determines that the output current is near the zero cross, more positive than the near zero cross, and near the zero cross. The inverter control device according to claim 1, wherein the inverter control device determines which one is on the negative polarity side and changes each threshold according to the state of the inverter. Connect the upper and lower arms with each switching element (semiconductor elements such as IGBT and MOSFET) connected in series, connect multiple sets of upper and lower arms in parallel, and connect the DC power supply to both ends of each set of upper and lower arms. The output is taken out from the midpoint of the upper and lower arms of each set, the first operation mode period during which the switching element of the upper arm that supplies the output current flowing to the positive polarity side is turned on, and the output current that flows to the negative polarity side The second operation mode period in which the switching elements of the lower arm to be turned on are alternately repeated, and a dead time for turning off all the upper and lower arm switching elements is set between the first operation mode period and the second operation mode period. In the inverter control device,
The first and second arm command values different from each other are compared with the carrier signal, the first operation mode period is set when the carrier signal becomes less than the first arm command value, and the carrier signal is the second arm command value. A timing setting means for setting a second operation mode period when exceeding, and setting a dead time when the carrier signal is between the first and second arm command values;
Determining means for determining whether the output current from the middle point of each upper and lower arm at the time of turning on and off of each upper and lower arm of the inverter from the middle point of each upper and lower arm flows to the positive polarity side or the negative polarity side ,
The timing setting means, when the determination means determines that the output current flows to the positive polarity side, sets the second arm command value over a half cycle of the carrier signal including the switching timing of the on → off and off → on. When the determination means determines that the output current flows to the negative polarity side by 2Δv, the first arm command value is set to 2Δv over a half cycle of the carrier signal including the switching timing of ON → OFF or OFF → ON. A control apparatus for an inverter, wherein the inverter control device changes the dead time setting timing to change the first operation mode period and the second operation mode period before and after the dead time .

Images