JP4611663B2 - Overlay error measuring method, overlay error measuring apparatus, and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to an overlay error measurement method for measuring an overlay error of a pattern formed on a semiconductor wafer in a semiconductor device manufacturing process, an overlay error measuring apparatus, and a semiconductor device manufacturing method using them.

  In a manufacturing process of a semiconductor device such as an IC or LSI, a circuit pattern is formed by a so-called photolithography technique. In the photolithography technique, a pattern formed on a reticle or photomask is transferred onto a semiconductor wafer coated with a photosensitive material (resist) using a reduction projection exposure apparatus. Then, a resist pattern is formed by development processing, and a circuit pattern is formed by dry etching using this resist pattern as a mask. In order to configure a semiconductor device on a semiconductor wafer, it is necessary to repeat such circuit pattern formation about 20 to 30 times.

  The superimposition accuracy of the circuit pattern of the semiconductor device is required to be as shown in Table 1 “Product Critical Level Lithography Requirements” of SIA (Semiconductor Insulator Association) Roadmap 2000.

  In general, inspection of circuit pattern overlay accuracy involves forming a measurement pattern in addition to the circuit pattern in the semiconductor device manufacturing process, and measuring the overlay error of this measurement pattern using an overlay error measuring device. It is done by. The overlay error measuring device detects an image signal of an image of a measurement pattern, processes the detected image signal to detect a center position of the measurement pattern, and obtains a deviation amount of the center position of the measurement pattern. is there.

As a technique for detecting the center position of a pattern from an image signal of a pattern image, a symmetry matching method described in Patent Document 1 is known. The symmetry matching method uses a symmetry evaluation function that adds the squares of the differences between image signals at the same distance from the virtual center position of the waveform of the image signal, and changes the value of the symmetry evaluation function while changing the virtual center position. The virtual center position where the value of the symmetry evaluation function is minimized is detected as the center position of the pattern.
JP-A-6-151274

  In general, in the symmetry matching method, as the integration range of the symmetry evaluation function is increased, the amount of data increases and stable detection can be performed. However, if there is an asymmetry in the level difference of the pattern to be measured, the waveform of the image signal becomes asymmetric, which causes a problem in that the shape of the symmetry evaluation function is distorted and a measurement error occurs.

  On the other hand, Patent Document 1 discloses a technique in which an area in which the waveform of an image signal is asymmetric is obtained and an area with good symmetry excluding this area is used as a local section as an integration range. Yes. However, in order to obtain a region in which the waveform of the image signal is asymmetrical, a complicated process for detecting and comparing feature points such as maximum points, minimum points, and inflection points of the image signal is required.

  An object of the present invention is to measure the pattern overlay error with high accuracy by using the symmetry matching method and removing the influence of the pattern step asymmetry by a simple process. Another object of the present invention is to improve the pattern overlay accuracy and manufacture a high-quality semiconductor device.

  The first feature of the present invention is that in the symmetry matching method, the integration range of the symmetry evaluation function is set so that the minimum value of the symmetry evaluation function is minimized.

  The second feature of the present invention is that in the symmetry matching method, the focus position of the light receiving system is adjusted so that the minimum value of the symmetry evaluation function is minimized. At this time, the closer the focus position of the light receiving system is to the in-focus position, the stronger the intensity of light received by the light receiving system and the larger the image signal of the pattern image, so symmetry evaluation is performed according to the focus position of the light receiving system. Normalize the local minimum of the function.

  Conventionally, in the symmetry matching method, the position where the value of the symmetry evaluation function is minimized is important, and the magnitude of the minimum value itself is not regarded as important. In the present invention, attention is paid to the minimum value of the symmetry evaluation function. If the pattern steps are substantially symmetric, the waveform of the image signal is substantially symmetric, and the minimum value of the symmetry evaluation function is close to zero. On the other hand, if there is an asymmetry in the pattern steps, the waveform of the image signal becomes asymmetric, and the minimum value of the symmetry evaluation function increases. In the present invention, the integration range of the symmetry evaluation function is set or the focus position of the light receiving system is adjusted so that the minimum value of the symmetry evaluation function is minimized. Thereby, the influence of the asymmetry of the pattern step is most removed, and the detected center position approaches the true value. There is no need for complicated processing for obtaining a region where the waveform of the image signal is asymmetric.

  The semiconductor device manufacturing method of the present invention is to inspect the overlay accuracy of a pattern using the overlay error measuring method or overlay error measuring apparatus having any one of the above features.

  According to the present invention, by setting the integration range of the symmetry evaluation function so that the minimum value of the symmetry evaluation function becomes the smallest, the influence of the asymmetry of the pattern step is removed by simple processing, Pattern overlay errors can be accurately measured.

  Further, according to the present invention, the local minimum value of the symmetry evaluation function is normalized according to the focus position of the light receiving system, and the focus position of the light receiving system is adjusted so that the normalized minimum value is minimized. It is possible to accurately measure the overlay error of the pattern by removing the influence of the asymmetry of the pattern step by a simple process.

  According to the semiconductor device manufacturing method of the present invention, it is possible to improve the pattern overlay accuracy and manufacture a high-quality semiconductor device.

  FIG. 1 is a diagram showing a schematic configuration of an overlay error measuring apparatus according to an embodiment of the present invention. The overlay error measuring device includes a chuck 10, a stage 11, a light source 20, a light projecting system, a light receiving system, detectors 32 and 33, an image signal processing circuit 40, a control device 50, and a stage driving circuit 60. Yes.

  A semiconductor wafer 1 having a measurement pattern formed on the surface is fixed on a chuck 10. The stage 11 moves in the XY direction, rotates in the θ direction, and moves in the Z-axis direction while mounting the chuck 10. The stage drive circuit 60 drives the stage 11 under the control of the control device 50. The measurement mark on the semiconductor wafer 1 is positioned by the movement of the stage 11 in the XY direction and the rotation in the θ direction. Further, the focus position of the light receiving system is adjusted by the movement of the stage 11 in the Z-axis direction.

  Instead of moving the semiconductor wafer 1 by the stage 11, the positioning of the measurement mark and the adjustment of the focus position of the light receiving system may be performed by moving the light receiving system.

  The light source 20 includes, for example, a mercury lamp and generates illumination light. The light projecting system includes a light guide 21, an illumination aperture stop 22, an illumination relay lens 23, a half mirror 24, and an objective lens 25. Illumination light generated from the light source 20 passes through the light guide 21, the illumination aperture stop 22, and the illumination relay lens 23, is reflected by the half mirror 24, and is irradiated from the objective lens 25 onto the surface of the semiconductor wafer 1.

  The light receiving system includes an objective lens 25, a half mirror 24, an imaging lens 30, and a half mirror 31. Reflected light from the surface of the semiconductor wafer 1 is collected by the objective lens 25, passes through the half mirror 24, and then enters the half mirror 31 through the imaging lens 30.

  About half of the reflected light incident on the half mirror 31 passes through the half mirror 31 and forms an image on the light receiving surface of the detector 32. About half of the remaining reflected light incident on the half mirror 31 is reflected by the half mirror 31 and forms an image on the light receiving surface of the detector 33. The detectors 32 and 33 are CCD line sensors, and a plurality of pixels are arranged in the X direction on one side and in the Y direction on the other side. The detectors 32 and 33 output an image signal corresponding to the intensity of light received by the light receiving surface to the image signal processing circuit 40.

  Note that a two-dimensional area sensor may be used instead of the detectors 32 and 33, and in this case, the half mirror 31 is not necessary.

  The image signal processing circuit 40 includes an A / D converter, an image memory, a digital signal processing device (DPS), and the like. The image signal processing circuit 40 converts the image signal from the detectors 32 and 33 into a digital signal, and then calculates the value of the symmetry evaluation function, and the virtual center position where the value of the symmetry evaluation function is minimized. A process of detecting the center position of the measurement pattern and a process of obtaining a deviation amount of the center position of the measurement pattern are performed.

  First, these processes of the image signal processing circuit 40 will be described. 2A is a cross-sectional view of an example of a measurement pattern, and FIG. 2B is a diagram illustrating an example of an image signal of an image of the measurement pattern. In general, the measurement pattern includes an etching pattern and a resist pattern. FIG. 2A shows an example of a resist pattern, and two resist patterns 3a and 3b are formed on the film 2 formed on the surface of the semiconductor wafer. For the measurement pattern in FIG. 2A, the detector 32 outputs an image signal shown in FIG. 2B as an example.

  For the image signal shown in FIG. 2B, the image signal processing circuit 40 first performs processing for calculating the value of the symmetry evaluation function while changing the X coordinate of the virtual center position. The symmetry evaluation function integrates the squares of the differences between the image signals at equal distances from the virtual center position of the waveform of the image signal, and details thereof are described in Patent Document 1. FIG. 3 is a diagram illustrating an example of the calculated value of the symmetry evaluation function. In this example, the value of the symmetry evaluation function is calculated for the image signal shown in FIG. 2B by setting the integration range to W1.

  Subsequently, the image signal processing circuit 40 performs a process of detecting the virtual center position where the value of the symmetry evaluation function is minimized as the center position of the resist patterns 3a and 3b. In the example shown in FIG. 3, the X coordinate X1 of the virtual center position at which the value of the symmetry evaluation function is minimized is detected and used as the center position in the X direction of the two resist patterns 3a and 3b.

  The image signal processing circuit 40 similarly detects the center position in the X direction for the etching pattern. And the process which calculates | requires the deviation | shift amount of the center position of an etching pattern and the center position of a resist pattern is performed, and the overlay error of a X direction is measured. The image signal processing circuit 40 performs the same processing on the Y-direction image signal output from the detector 33 and measures the Y-direction overlay error.

  Next, the first feature of the present invention will be described. The first feature of the present invention is that the integration range of the symmetry evaluation function is set so that the image signal processing circuit 40 calculates the value of the symmetry evaluation function so that the minimum value of the symmetry evaluation function is minimized. Is to set.

  Here, the integration range in which the minimum value of the symmetry evaluation function becomes the smallest is determined based on the result of calculating the value of the symmetry evaluation function in a plurality of different integration ranges, for example. Hereinafter, with respect to the image signal shown in FIG. 2B, an example in which the value of the symmetry evaluation function is calculated with the integration ranges W1 and W2 will be described.

  FIG. 4 is an enlarged view of a portion where the value of the symmetry evaluation function is minimized. FIG. 4A shows an example in which the integration range is W1, and FIG. 4B shows the integration range W2. It is an example. As shown in FIG. 4A, in the example in which the integration range is W1, the X coordinate of the virtual center position where the value of the symmetry evaluation function is minimum is X1, and the minimum value is almost zero. On the other hand, as shown in FIG. 4B, in the example in which the integration range is W2, the X coordinate of the virtual center position where the value of the symmetry evaluation function is minimum is X2, and the minimum value is large.

  From these results, when the integration range of the symmetry evaluation function is set to W1, the minimum value of the symmetry evaluation function is smaller than in the case where the integration range is set to W2. Less. Therefore, the X coordinate X1 detected as the center position in the X direction of the two resist patterns 3a and 3b is closer to the true value than X2.

  In the example described above, there are two integration ranges W1 and W2. However, in the present invention, the value of the symmetry evaluation function is calculated in an appropriate range and a plurality of integration ranges, and based on the result. What is necessary is just to determine the integration range. By setting the integration range of the symmetry evaluation function so that the minimum value of the symmetry evaluation function becomes the smallest, the influence of the asymmetry of the pattern step is most eliminated, and the detected center position is a true value. Get closer to.

  Next, the second feature of the present invention will be described. The second feature of the present invention is that the focus position of the light receiving system is adjusted so that the minimum value of the symmetry evaluation function is minimized. At this time, the closer the focus position of the light receiving system is to the in-focus position, the stronger the intensity of light received by the light receiving system and the larger the image signal of the pattern image. Therefore, symmetry evaluation according to the focus position of the light receiving system Normalize the local minimum of the function.

  Here, the focus position at which the minimum value of the symmetry evaluation function becomes the smallest is, for example, detecting the image signal of the image of the measurement pattern at a plurality of different focus positions, and evaluating the symmetry of the image signal detected at each focus position. Calculate and determine the value of the function. In the embodiment shown in FIG. 1, the stage drive circuit 60 drives the stage 11 in the Z-axis direction under the control of the control circuit 50 to change the focus position of the light receiving system. The detectors 32 and 33 detect image signals of measurement pattern images at a plurality of different focus positions. The image signal processing circuit 40 performs processing for calculating the value of the symmetry evaluation function for the image signal detected at each focus position, and normalizes the minimum value of the symmetry evaluation function according to the focus position.

  FIG. 5 is a diagram showing a change in the normalized symmetry evaluation function depending on the focus position, and FIG. 5A shows an example in which the steps of the measurement pattern are almost symmetrical, and FIG. Is an example where the steps of the measurement pattern have asymmetry. As shown in FIG. 5A, when the level difference of the measurement pattern is substantially symmetric, the minimum value of the normalized symmetry evaluation function is substantially constant regardless of the focus position. On the other hand, as shown in FIG. 5B, when the step of the measurement pattern has asymmetry, the minimum value of the normalized symmetry evaluation function varies depending on the focus position.

  In the example shown in FIG. 5B, the minimum value of the normalized symmetry evaluation function is the smallest at the focus position F1, and the influence of the asymmetry of the pattern step is the smallest. Therefore, by controlling the stage driving circuit 60 by the control circuit 50 and driving the stage 11 in the Z-axis direction and adjusting the focus position of the light receiving system to this position, the influence of the asymmetry of the pattern step is most eliminated. Thus, the detected center position approaches the true value.

  Note that the focus position where the minimum value of the normalized symmetry evaluation function is the smallest does not always coincide with the in-focus position. In the present invention, the focus position of the light receiving system may be determined so that the minimum value of the normalized symmetry evaluation function is minimized regardless of the in-focus position.

  According to the embodiment described above, the image signal processing circuit 40 sets the integration range of the symmetry evaluation function so that the minimum value of the symmetry evaluation function becomes the smallest, so that the pattern can be easily processed. By removing the effect of the asymmetry of the step, it is possible to accurately measure the pattern overlay error.

  Further, according to the embodiment described above, the image signal processing circuit 40 normalizes the minimum value of the symmetry evaluation function according to the focus position of the light receiving system, and the control circuit 50, the stage drive circuit 60, and the stage 11 By adjusting the focus position of the light-receiving system so that the normalized minimum value becomes the smallest, the focus adjustment means becomes simple and eliminates the effects of pattern step asymmetry. The error can be measured with high accuracy.

  By using the overlay error measuring method or overlay error measuring apparatus of the present invention to inspect the pattern overlay accuracy, the pattern overlay accuracy can be improved and a high-quality semiconductor device can be manufactured. .

It is a figure which shows schematic structure of the overlay error measuring device by one embodiment of this invention. 2A is a cross-sectional view of an example of a measurement pattern, and FIG. 2B is a diagram illustrating an example of an image signal of an image of the measurement pattern. It is a figure which shows an example of the value of the calculated symmetry evaluation function. FIG. 4A is an enlarged view of a portion where the value of the symmetry evaluation function is minimized, FIG. 4A is an example in which the integration range is W1, and FIG. 4B is an example in which the integration range is W2. is there. FIGS. 5A and 5B are diagrams showing changes in the normalized symmetry evaluation function depending on the focus position, in which FIG. 5A shows an example in which the steps of the measurement pattern are substantially symmetrical, and FIG. 5B shows the measurement pattern. This is an example in which the steps are asymmetric.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Film | membrane 3a, 3b Resist pattern 10 Chuck 11 Stage 20 Light source 21 Light guide 22 Illumination aperture stop 23 Illumination relay lens 24, 31 Half mirror 25 Objective lens 30 Imaging lens 32, 33 Detector 40 Image signal processing Circuit 50 Controller 60 Stage drive circuit

Claims (6)

Detecting the image signal of the image of the pattern formed on the semiconductor wafer, calculating the value of the symmetry evaluation function that integrates the square of the difference between the image signals at the same distance from the virtual center position of the waveform of the image signal; An overlay error measurement method for detecting a virtual center position where a value of a symmetry evaluation function is a minimum as a pattern center position and obtaining a shift amount of the pattern center position,
An overlay error measurement characterized in that an integration range of squares of differences between image signals at equal distances from the virtual center position of the waveform of the image signal is set so that the minimum value of the symmetry evaluation function is minimized. Method. A light source that generates illumination light;
A light projecting system for irradiating the surface of the semiconductor wafer with illumination light generated by the light source;
A light receiving system for receiving reflected light from the surface of the semiconductor wafer;
Image signal detection means for detecting an image signal of an image of a pattern formed on the semiconductor wafer from the intensity of light received by the light receiving system;
A process of calculating a value of a symmetry evaluation function that integrates the square of the difference between image signals at equal distances from the virtual center position of the waveform of the image signal detected by the image signal detection means;
A process of detecting a virtual center position where the value of the symmetry evaluation function is a minimum as a center position of the pattern;
An overlay error measuring device comprising image signal processing means for performing processing for obtaining a shift amount of a center position of a pattern,
The image signal processing means sets an integration range of squares of differences of image signals at equal distances from the virtual center position of the waveform of the image signal so that the minimum value of the symmetry evaluation function is minimized. Characteristic overlay error measuring device. Symmetry that adjusts the focus position of the light receiving system to detect the image signal of the image of the pattern formed on the semiconductor wafer, and integrates the square of the difference between the image signals at the same distance from the virtual center position of the waveform of the image signal A method for calculating an overlay error, calculating a value of a property evaluation function, detecting a virtual center position at which the value of a symmetry evaluation function is minimal as a center position of a pattern, and obtaining a shift amount of the center position of the pattern,
An overlay error measuring method comprising: normalizing a minimum value of a symmetry evaluation function in accordance with a focus position of a light receiving system, and adjusting the light receiving system focus position so that the normalized minimum value is minimized. A light source that generates illumination light;
A light projecting system for irradiating the surface of the semiconductor wafer with illumination light generated by the light source;
A light receiving system for receiving reflected light from the surface of the semiconductor wafer;
Focus adjusting means for adjusting the focus position of the light receiving system;
Image signal detection means for detecting an image signal of an image of a pattern formed on the semiconductor wafer from the intensity of light received by the light receiving system;
A process of calculating a value of a symmetry evaluation function that integrates the square of the difference between image signals at equal distances from the virtual center position of the waveform of the image signal detected by the image signal detection means;
A process of detecting a virtual center position where the value of the symmetry evaluation function is a minimum as a center position of the pattern;
An overlay error measuring device comprising image signal processing means for performing processing for obtaining a shift amount of a center position of a pattern,
The image signal processing means normalizes the minimum value of the symmetry evaluation function according to the focus position of the light receiving system,
The focus adjustment means is such that the minimum value of the normalized symmetry evaluation function is minimized.
An overlay error measuring apparatus for adjusting a focus position of the light receiving system.   A method for manufacturing a semiconductor device, wherein the overlay accuracy of a pattern is inspected using the overlay error measurement method according to claim 1.   A method for manufacturing a semiconductor device, comprising: using the overlay error measuring device according to claim 2 or 4 to inspect pattern overlay accuracy.

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