JP4610246B2 - Clock frequency biasing apparatus and method, and radio communication apparatus incorporating the same - Google Patents

Description

  The present invention relates to avoiding an internal beat that interferes with a specific reception channel generated by internal oscillation means in a wireless communication device. More specifically, the present invention relates to avoiding internal beats by biasing the clock frequency of the control means of the wireless communication device. The present invention relates to a clock frequency biasing device, a method thereof, and a wireless communication apparatus incorporating the same.

  The harmonics generated by the clock generation circuit of the control circuit (microcomputer) of the wireless communication apparatus may interfere with other circuits and cause beat interference on the reception channel. This is called an internal beat, and there is a case where an internal beat occurs due to an unintended interference in design due to variations in elements and a small assembly error generated in an assembly process. For this reason, before the product is shipped, a final check regarding the internal beat is performed, and a measure called beat shift is adopted in which the clock frequency is shifted for a channel that is suppressed by the internal beat.

  Conventionally, in order to identify a channel that requires this beat shift, all the reception channels are written in the wireless communication device, and whether or not the channel is suppressed by abnormal noise or noise is identified by ear. For this reason, it was a very troublesome work to write all the frequencies to the radio and to check all the channels by ear. In addition, since it is confirmed with the ear, there is a problem that variation by humans is likely to occur, and quantitative identification becomes difficult.

When there is a possibility that the local oscillation frequency of the broadcast receiver may cause beat disturbance with respect to the reception frequency, the data for biasing the local oscillation frequency by the amount of occurrence of beat disturbance described in Patent Document 1 is stored, A method is known in which the local oscillation frequency is shifted according to stored data with respect to the corresponding reception frequency.
JP 2002-43963 A

  The present invention has been made to solve such a problem. The purpose of the present invention is to automatically check and set a reception channel to be beat-shifted instead of manually checking beat-shift, and Provided are a clock frequency biasing apparatus, a method thereof, and a radio communication apparatus incorporating the clock frequency biasing apparatus in which a beat shift of a clock frequency is performed according to set channel information when the reception channel is selected at the time of use.

The clock frequency deviation apparatus of the present invention includes a reception channel setting means for setting a reception channel, a beat detection means for receiving a received signal strength indication signal (RSSI: Received Signal Strength Indicator) and detecting an internal beat, and the beat detection Flag setting means for setting a beat shift on flag for the reception channel identified as having generated the internal beat and storing it in the reception channel setting means; and A clock frequency biasing device having beat shift means for receiving the beat shift on flag and biasing the clock frequency when a reception channel with the on flag set is set,
When the inspection button is pressed , the reception channel from the antenna is cut ,
The reception channel setting means is set to the lower limit reception channel and then repeatedly set one step at a time until the upper limit reception channel is set to the reception mode of each reception channel, and the beat detection means is from the lower limit reception channel to the upper limit reception channel. The reception signal strength indication signal for each reception channel is received and the presence or absence of an internal beat is detected, and the flag setting means is provided for each reception channel identified as having generated the internal beat by the beat detection means. When the beat shift on flag is set and stored in the reception channel setting means and used, the beat shift means uses the clock frequency when the selected reception channel is the reception channel with the beat on flag set. It is characterized by biasing.

The clock frequency deviation method of the present invention includes a reception channel setting means for setting a reception channel, a beat detection means for detecting an internal beat by receiving a received signal strength display signal, and the internal beat is generated by the beat detection means. Flag setting means for setting a beat shift on flag for the reception channel specified to be stored in the reception channel setting means, and the reception channel setting means for which the beat shift on flag is set A clock frequency biasing method for a clock frequency biasing device having beat shift means for biasing the clock frequency by receiving the beat shift on flag when setting a reception channel,
When the inspection button is pressed , the reception channel from the antenna is cut ,
The reception channel setting means sets the reception channel for each reception channel by repeatedly setting the reception channel for the reception channel one step at a time until the upper limit reception channel is set to the lower limit reception channel; Receiving the received signal strength indication signal for each receiving channel up to the receiving channel and detecting the presence or absence of an internal beat; and the flag setting means is identified by the beat detecting means that the internal beat has occurred A step of setting a beat shift on flag for each reception channel and storing it in the reception channel setting means; and when used, the beat shift means receives the selected reception channel with the beat on flag set. And biasing the clock frequency in the case of a channel. And butterflies.

  The wireless communication device of the present invention is characterized by incorporating the clock frequency deviation device.

  According to the clock frequency biasing apparatus and method of the present invention and the radio communication apparatus incorporating the same, the reception channel to be beat-shifted is automatically inspected and set in place of manual beat-shift inspection, and used by the user. When the receiving channel is sometimes selected, it is possible to provide a clock frequency biasing device and a method thereof, and a radio communication apparatus incorporating the same, in which a beat shift of the clock frequency is performed according to the set receiving channel information.

  FIG. 1 is a circuit block diagram illustrating an embodiment of a clock frequency biasing device according to the present invention. . The radio communication device 200 includes a control circuit 30 including a conventional antenna 10, a transmission / reception circuit 20, a clock generation circuit 40, and a clock frequency biasing device of the present invention. The clock frequency biasing apparatus includes a reception channel setting unit 60, a flag setting unit 70, a beat detection unit 80, and a beat shift unit 50.

  In FIG. 1, the reception channel setting means 60 of the wireless communication device 200 includes an inspection button for inspecting and setting a reception channel to be automatically beat-shifted before starting normal operation or personal use. And a reception channel selection button in normal use. It also has a memory for storing data for checking and setting all reception channels. When the check button is pressed, the reception channel setting means 60 sequentially reads the setting data from the memory, and the reception channel of the transmission / reception circuit 20 is set to the reception channel of the lower limit, that is, from the reception channel with the lowest frequency to the upper limit. Control to step up to high frequency reception channel.

  First, the check button of the reception channel setting means 60 is pressed, and a setting data signal is transmitted so as to set the lower limit reception channel. When the reception circuit of the transmission / reception circuit 20 receives this setting data signal, it cuts the reception channel signal from the antenna 10 and enters the reception mode of the lower limit channel. In this state, the internal beat signal in the reception channel is received, and the RSSI signal is output as the reception signal level. The beat detection means 80 receives this RSSI signal and determines whether or not it is below a predetermined value. If it is equal to or less than a predetermined value, it is determined that the internal beat is being suppressed, and a request signal for a beat shift on flag is sent to the flag setting means 70 to perform a beat shift.

  The flag setting means 70 receives this signal from the beat detection means 80, sets a beat shift on flag for the lower limit reception channel set by the reception channel setting means 60, and sets data for setting all reception channels. Is stored in the flag area of the memory for storing. If the RSSI signal at the beat detection means 80 is not less than or equal to a predetermined value, interference due to an internal beat in this reception channel has not occurred. Accordingly, since the beat shift on flag request signal is not transmitted from the beat detection means 80 to the flag setting means 70, no flag is set in the flag area of the lower limit reception channel. This series of processes is repeated one step at a time from the lower limit receiving channel to the upper limit receiving channel, and the internal beat inspection and response measures are automatically performed and completed.

  In normal use, when an arbitrary reception channel is set by pressing the reception channel selection button, the reception channel setting means 60 reads the setting data corresponding to the set information from the memory, and sets the reception frequency setting data in the transmission / reception circuit 20. Send as a signal. At this time, if a beat shift on flag is set in the flag area of the memory, a flag signal is transmitted to the beat shift means 50. The beat shift means 50 receives this signal and sends a beat shift signal to the clock generation circuit 40 included in the control circuit 30 to bias the clock frequency to a predetermined value. Therefore, due to this countermeasure, when reception starts on the reception channel in which the reception circuit of the transceiver circuit 20 of the wireless communication device 200 is set, the clock frequency is biased to a predetermined value, so that reception interference due to internal beat occurs. do not do.

  FIG. 2 is a circuit block diagram showing a clock generation circuit for biasing the clock frequency in the control circuit 30. The control circuit 30 includes a CPU 90 and a clock generation circuit 40. The CPU 90 of the control circuit 30 has an input terminal IN for a beat shift signal from the beat shift means 50 and an output terminal OUT for a control signal to the transmission / reception circuit 20. The base of the switch transistor TR of the clock generation circuit 40 is connected to the CPU 90. The emitter is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded. The collector is connected to one end of the capacitor C2 and one end of the crystal oscillator XTL, and is connected to the CPU 90. The other end of the capacitor C2 is grounded. The other end of the crystal resonator XTL is connected to one end of the capacitor C3 and is connected to the CPU 90. The other end of the capacitor C3 is grounded.

  When the CPU 90 receives the beat shift signal from the beat shift means 50 at the input terminal IN, the CPU 90 changes the setting of the base potential of the switch transistor TR to turn it on or off. As a result, the capacitor C1 is connected to or disconnected from the capacitor C2 in parallel, and the resonance frequency determined by the series resonance circuit of the capacitor C1, the crystal resonator XTL, and the capacitor C3 is varied. Since this connection switching control only needs to be performed for a reception channel that requires beat shift, it is only necessary to insert a series circuit of a pair of capacitors and a switch transistor. A control signal is output from the output terminal OUT of the CPU 90 to the transmission / reception circuit 20 at a processing speed corresponding to the biased or non-biased clock frequency to control communication.

  The circuit configuration shown in FIG. 1 may be any circuit or device as long as it realizes the function, and a part of the function can be realized by software. Furthermore, the function realizing means may be realized by a plurality of circuits, and a plurality of functions may be realized by a single circuit.

  FIG. 3 is a flowchart for explaining a frequency deviation sequence of the clock frequency deviation method according to the present invention. FIG. 3a is a flowchart showing an internal beat test sequence. FIG. 3b is a flowchart showing the operation sequence. In FIG. 3a, as a first reception channel setting step, first, the check button of the reception channel setting means 60 is pressed to start a channel scan and transmit a setting data signal to the transmission / reception circuit 20 so as to set the lower limit reception channel. (Step 100, Step 110). When the reception circuit of the transmission / reception circuit 20 receives this setting data signal, it cuts the reception channel signal from the antenna 10 and enters the reception mode of the lower limit channel. In this state, the internal beat signal in the reception channel is received, and the RSSI signal is output as the reception signal level (step 120). The beat detection means 80 receives this RSSI signal (step 130), determines whether or not it is below a predetermined value, and if it is below the predetermined value, determines that the internal beat has been suppressed, A request signal for a beat shift on flag is sent to the flag setting means 70 to shift (step 140).

  The flag setting means 70 receives this signal from the beat detection means 80, sets a beat shift on flag for the lower limit reception channel set by the reception channel setting means 60, and sets data for setting all reception channels. Is stored in the flag area of the memory for storing (step 150). If the RSSI signal in the beat detection means 80 is not less than or equal to a predetermined value, no interference due to the internal beat has occurred in this reception channel. Accordingly, since the beat shift on flag request signal is not transmitted from the beat detecting means 80 to the flag setting means 70, no flag is set in the flag area of the lower limit receiving channel (step 140). This series of processes is repeated one step at a time from the lower limit receiving channel to the upper limit receiving channel (step 160, step 170), and the internal beat check and response measures are automatically performed and completed (step 180).

  In FIG. 3b, as a second reception channel setting step in normal use, an arbitrary reception channel is set by pressing a reception channel selection button. The reception channel setting means 60 reads the setting data corresponding to the set information from the memory and transmits it to the transmission / reception circuit 20 as a reception channel setting data signal (step 200). At this time, if the beat shift on flag is set in the flag area of the memory (step 210), a flag signal is transmitted to the beat shift means 50 (step 220). The beat shift means 50 receives this signal and sends a beat shift signal to the clock generation circuit 40 of the control circuit 30 (step 230), biases the clock frequency to a predetermined value (step 240), and ends (step 250). ). Therefore, when the reception circuit of the transmission / reception circuit 20 of the wireless communication device 200 starts reception on the reception channel in which the flag is set, the clock frequency is biased to a predetermined value, so that reception interference due to the internal beat does not occur. .

  As described above, according to the clock frequency biasing apparatus and method and the radio communication apparatus incorporating the clock frequency biasing apparatus of the present invention, a reception channel to be beat shifted automatically is set instead of manual beat shift inspection. When the reception channel is selected at the time of use by the user, it is possible to provide a clock frequency biasing apparatus and method for performing a beat shift of the clock frequency according to the set channel information, and a radio communication apparatus incorporating the method. Accordingly, the inspection need not be performed before shipment, and the internal beat test sequence may be performed by pressing the inspection button when the set is started before the user starts using the wireless communication device.

  The present invention can be applied not only to business or personal wireless communication devices but also to broadcasting equipment or information communication equipment that may cause a slight change in the arrangement of parts due to a design change, which may cause an internal beat.

The circuit block diagram explaining embodiment of the clock frequency deviation apparatus by this invention. The circuit block diagram which shows a clock generation circuit. The flowchart which shows the sequence of the clock frequency deviation method by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Antenna 20 Transmission / reception circuit 30 Control circuit 40 Clock generation circuit 50 Beat shift means 60 Reception channel setting means 70 Flag setting means 80 Beat detection means 90 CPU
DESCRIPTION OF SYMBOLS 100 Clock frequency deviation apparatus 200 Radio | wireless communication apparatus TR Transistor C1-C3 Capacitor XTL Crystal oscillator IN Input terminal OUT Output terminal

Claims (3)

A receiving channel setting means for setting a receiving channel;
Beat detection means for receiving a received signal strength indication signal (RSSI: Received Signal Strength Indicator) and detecting an internal beat;
Flag setting means for setting a beat shift on flag for the reception channel identified as the occurrence of the internal beat by the beat detection means and storing it in the reception channel setting means;
And a beat shift means for receiving the beat shift on flag and biasing the clock frequency when the reception channel setting means sets the reception channel in which the beat shift on flag is set. There,
When the inspection button is pressed , the reception channel from the antenna is cut ,
The reception channel setting means is set to the lower limit reception channel and then repeatedly set one step at a time until the upper limit reception channel is set as the reception mode of each reception channel,
The beat detection means receives a received signal strength indication signal for each receiving channel from the lower limit receiving channel to the upper limit receiving channel to detect the presence or absence of an internal beat,
The flag setting means sets a beat shift on flag for each reception channel identified as having generated the internal beat by the beat detection means, and stores it in the reception channel setting means.
When using
The beat shift means biases the clock frequency when the selected reception channel is a reception channel for which the beat-on flag is set;
A clock frequency biasing device characterized by that. A receiving channel setting means for setting a receiving channel;
Beat detection means for receiving a received signal strength display signal and detecting an internal beat,
Flag setting means for setting a beat shift on flag for the reception channel identified as the occurrence of the internal beat by the beat detection means and storing it in the reception channel setting means;
The clock of the clock frequency biasing device includes beat shift means for receiving the beat shift on flag and biasing the clock frequency when the receiving channel setting means sets the receiving channel in which the beat shift on flag is set. A frequency biasing method,
When the inspection button is pressed , the reception channel from the antenna is cut ,
The reception channel setting means is configured to repeatedly set one step at a time until the upper limit reception channel is set to the lower limit reception channel and set the reception mode for each reception channel;
The beat detection means detects the presence or absence of an internal beat by receiving a reception signal strength display signal for each reception channel from the lower limit reception channel to the upper limit reception channel;
The flag setting means sets a beat shift on flag for each reception channel identified as having generated the internal beat by the beat detection means, and stores it in the reception channel setting means;
When using
The beat shift means biases the clock frequency when the selected reception channel is a reception channel with the beat-on flag set;
A clock frequency biasing method characterized by comprising:   A wireless communication device comprising the clock frequency biasing device according to claim 1.

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