JP4608607B2 - Method for forming fine pattern and method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a nanometer-level fine pattern on the surface of a compound semiconductor and a method for manufacturing a semiconductor device using the same.
[0002]
[Prior art]
Currently, integration of semiconductor integrated circuits is progressing, and a structure having an integration density of gigabit level is being realized in a semiconductor memory such as a DRAM. In order to manufacture a semiconductor integrated circuit having a gigabit level integration density, the dimensions of the semiconductor elements constituting the semiconductor integrated circuit are required to be sub-quarter micron and further reduced to a nanometer level. Become. As microfabrication technology advances, it is now possible to form mesoscopic to atom-scopic semiconductor elements, such as transistors using thermionic emission and semiconductor elements using single-electron behavior. Trial production of various semiconductor devices using quantum mechanical design such as the above has been started.
[0003]
Furthermore, recently, photonic crystals have been debated to construct a one-dimensional, two-dimensional, and three-dimensional structure having a periodic structure of the wavelength order of light and to obtain quantum optical phenomena different from classical optics. ing.
[0004]
Conventionally, in order to form a fine pattern on a semiconductor surface, a mask having a fine pattern is drawn by a photolithography method, and this mask is used to perform selective etching by a reactive ion etching (RIE) method or the like. It required complicated fine processing technology. However, when the dimension of the fine pattern is at the nanometer level, that is, below the wavelength of light, the target fine pattern cannot be exposed with light. For this reason, instead of the optical exposure method, an electron beam exposure method and an X-ray exposure method are being studied and used.
[0005]
[Problems to be solved by the invention]
However, in order to carry out the electron beam exposure method and the X-ray exposure method, an expensive apparatus of 1 billion yen or more such as an electron beam exposure apparatus or an X-ray exposure apparatus is required. Further, various problems to be solved still remain in the electron beam exposure method and the X-ray exposure method. In particular, the apparatus is not only large and expensive, but also has a high running cost and requires advanced technology. For this reason, a semiconductor device having a nanometer level fine size has a problem that the manufacturing cost is extremely high and the throughput is low.
[0006]
An object of the present invention is to provide a method for forming a nanometer level fine pattern on a semiconductor surface at a low cost by a very simple method.
[0007]
Another object of the present invention is to provide a method for manufacturing a semiconductor device having a nanometer level fine pattern at a low cost.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a fine pattern forming method according to the present invention includes (a) a step of cooling a single crystal substrate to a low temperature of −50 ° C. or lower and −273 ° C. or higher, and (b) charging the surface of the single crystal substrate. 1 × 10 particles¹⁴cm^-25 × 10 or more¹⁶cm^-2It is characterized by comprising at least a step of implanting with a predetermined acceleration voltage at the following dose, and (c) a step of returning the single crystal substrate to room temperature. Here, the “single crystal substrate” includes a compound semiconductor single crystal substrate and a single crystal substrate made of other inorganic materials. In addition, ions of various elements can be used as charged particles. In other words, a well-known ion implantation technique can be used for the injection of charged particles. In order to cool the compound semiconductor single crystal substrate to a low temperature, the compound semiconductor single crystal substrate is cooled by cooling a substrate holder for holding and fixing the compound semiconductor single crystal substrate using a predetermined refrigerant such as liquid helium or liquid nitrogen. A cooling method can be employed.
[0009]
According to the fine pattern forming method described above, various single crystal substrates such as gallium antimony (GaSb), indium antimony, for example, can be selected by selecting the temperature, acceleration voltage, and injection amount when the single crystal substrate is charged with charged particles. A nanometer-level honeycomb structure can be easily formed on the surface of a compound semiconductor single crystal substrate such as (InSb), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).
[0010]
Usually, the surface of an ion-implanted semiconductor at a certain temperature or higher, such as room temperature, is only amorphized to a depth at which the deposited energy is equal to or higher than a critical value, and no extreme deformation of the surface is observed. In fact, in the examination of ion implantation for gallium arsenide (GaAs) and indium phosphide (InP) performed by the inventors so far at a substrate temperature of room temperature, an amorphous layer having a certain depth from the surface and damage Only a region was formed, and such a unique structure could not be found. However, by cooling the single crystal substrate to a low temperature of −50 ° C. or lower and −273 ° C. or higher and injecting charged particles, the projected range R of the charged particles_pIs formed on the surface of the single crystal substrate. The diameter of the concave part (hole) constituting the honeycomb structure is the projected range R of the charged particles._pOf the order. For example, when the diameter of the recess (hole) constituting the honeycomb structure is approximately 50 nm, a recess having a depth of 250 nm is formed. The thickness of the wall separating the recess from the recess is about 5 nm.
[0011]
For example, in the case of a gallium antimony (GaSb) single crystal substrate, the honeycomb structure formed on the surface is observed with a transmission electron microscope, and the result of local analysis by Fourier transform and local composition analysis by EDX is the result of the honeycomb. The walls constituting the structure have a high concentration of gallium (Ga). In addition, the upper part of the wall constituting the honeycomb structure is amorphous, but crystallinity is observed in the lower part, and its orientation is consistent with the matrix of the substrate. From these results, it is considered that the behavior of point defects formed when charged particles are injected into a single crystal substrate at a low temperature dominates the formation of a honeycomb structure. That is, it is considered that the fine structure formed on the surface of the single crystal substrate of the present invention is formed by the following mechanism.
[0012]
(1) By injection of charged particles (ion implantation), atomic vacancies and interstitial atoms are formed on the surface of the single crystal substrate;
(2) Atomic vacancies formed on the surface of a single crystal substrate cannot move so much, but interstitial atoms move at a low temperature. Some of them form aggregates such as loops, and pulses (raised portions) occur on the surface of the single crystal substrate;
(3) When a certain period of time has passed and the injection of charged particles at a low temperature has further progressed, no defects are formed because the charged particles do not reach the part below the pulse;
(4) Interstitial atoms flow from the periphery into the area below this vein, forming an aggregate, and the vein grows at the root and forms a high wall. On the other hand, where it is not a pulse, atomic vacancies move and disappear on the surface of the single crystal substrate, and the surface of the single crystal substrate is rather receded, resulting in a deep nest (recess).
[0013]
Therefore, in the fine pattern forming method of the present invention, the temperature T of the single crystal substrate_SUB, Acceleration voltage V of charged particles_ACAnd charged particle type (ion species), charged particle injection dose φ, crystal plane orientation of the single crystal substrate, etc., so that the diameter 2r of the recess, the depth d, and the distance between the recesses It is possible to precisely control the wall thickness t and the angle θ formed with respect to the bottom surface of the wall recess. Specifically, the temperature T of the single crystal substrate_SUBTakes into account the balance of mobility of interstitial atoms and vacancies and the temperature T of the single crystal substrate_SUBYou can decide. In addition, by the injection of charged particles, interstitial atoms are projected from the surface of the single crystal substrate to a projected range R._pA part of this interstitial atom is projected in the lateral direction R_pMove to the extent. That is, the projected range R of the implanted ions R_pBy selecting, the size (radius) of the burrow (recess) can be determined. If the injection dose φ of charged particles is increased, the amount of interstitial atoms formed on the surface of the single crystal substrate increases, and the wall can be made higher. That is, the depth of the recess can be increased by increasing the injection dose φ of the charged particles. Moreover, since the amount of defect formation increases as the mass of charged particles to be injected increases, the depth of the concave portion can be controlled by selecting the mass of the charged particles. Therefore, as the kind of charged particles, tin ions (Sn⁺), Carbon ion (C⁺), Silicon ions (Si⁺), Germanium ion (Ge⁺) And the like may be selected according to the intended structure of the recess.
[0014]
The semiconductor device manufacturing method according to the present invention is an application of the above-described fine pattern forming method. That is, as an example of the single crystal substrate, a compound semiconductor single crystal substrate is selected, and (b) a step of forming a mask material having a predetermined opening on the surface of the compound semiconductor single crystal substrate; A step of cooling the semiconductor single crystal substrate to a low temperature of −50 ° C. or lower and −273 ° C. or higher, and (c) 1 × 10 charged particles on the surface of the single crystal substrate through the opening of the mask material.¹⁴cm^-25 × 10 or more¹⁶cm^-2A step of selectively injecting at a predetermined acceleration voltage with the following dose; (d) forming a recess on the surface of the single crystal substrate by returning the single crystal substrate to room temperature; and (e) a recess. And at least a step of epitaxial growth inside.
[0015]
According to the method for manufacturing a semiconductor device of the present invention, a structure in which the distance between the recesses is about 5 nm can be easily formed without using an expensive electron beam exposure apparatus or X-ray exposure apparatus. Therefore, mesoscopic scale and atomic scale semiconductor devices using the tunnel injection effect, ballistic transport effect, and other quantum mechanical effects can be easily manufactured.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.
[0017]
(Fine pattern formation method)
First, before entering a description of a specific method for manufacturing a semiconductor device, specific conditions for forming a nanometer level, mesoscopic scale, and atomic scale fine pattern on the surface of a single crystal substrate will be described. That is, as a method for forming a fine pattern according to an embodiment of the present invention, a case where a compound semiconductor single crystal substrate is used as a “single crystal substrate” will be described. In particular, a case where an InSb single crystal substrate having a (111) plane orientation and a GaSb single crystal substrate having a (100) plane orientation is used as the compound semiconductor single crystal substrate will be described.
[0018]
(A) First, the InSb single crystal substrate and the GaSb single crystal substrate are cooled to a low temperature of -130 ° C to -123 ° C. Specifically, the InSb single crystal substrate and the GaSb single crystal substrate are set in a substrate holder in the sample chamber of the ion implantation apparatus while maintaining adhesion, and the inside of the sample chamber is set to 10^-3Pa to 10^-8Evacuate to a predetermined pressure of Pa and cool in vacuum. That is, while measuring the temperature of the substrate holder with a temperature monitor such as a thermocouple, the liquid nitrogen (LN₂) Or other refrigerant.
[0019]
(B) Next, tin ions (Sn as charged particles) are formed on the surfaces of the InSb single crystal substrate and the GaSb single crystal substrate.⁺), Acceleration voltage V_AC= Ion implantation at a predetermined dose at 60 kV.
Specifically, four types of samples (sample A, sample B, sample C, and sample D) are prepared, and ion implantation is performed under the following conditions. Sample A is an InSb single crystal substrate, and samples B to D are GaSb single crystal substrates.
(Sample A) Dose amount φ = 6.7 × 10 at −130 ° C.¹⁴cm^-2,
(Sample B) Dose amount φ = 4 × 10 at −130 ° C.¹⁴cm^-2,
(Sample C) Dose amount φ = 8 × 10 at −130 ° C.¹⁴cm^-2,
(Sample D) Dose amount φ = 1.1 × 10 at −123 ° C.¹⁵cm^-2,
(C) When ion implantation under the above conditions is completed, the InSb single crystal substrate and the GaSb single crystal substrate are returned to room temperature by natural heating. When the InSb single crystal substrate and the GaSb single crystal substrate return to room temperature, the InSb single crystal substrate and the GaSb single crystal substrate are taken out from the sample chamber of the ion implantation apparatus.
[0020]
When the surface of these four types of samples (sample A, sample B, sample C, and sample D) is observed with a scanning electron microscope (SEM) and the cross section is observed with a transmission electron microscope (TEM), FIG. And a cross-sectional shape as shown in FIG. 1B are obtained. That is, according to the method for forming a fine pattern according to the embodiment of the present invention, as shown in FIG. 1B, a plurality of recesses 2 having a diameter 2r and a depth d are formed on the surface of the compound semiconductor single crystal substrate 1. Is formed in a honeycomb shape. A wall having a thickness t is formed between the recess 2 and the recess 2, and the wall forms an angle θ with respect to the bottom surface of the recess. The shape of the four types of samples will be described as follows.
[0021]
(Sample A) 2r = -50 nm, t = -10 nm, d = -200 nm, θ = -90 °;
(Sample B) 2r = ˜40 nm, hole density˜5 × 10¹³/ M²;
(Sample C) 2r = ˜50 nm, t = ˜5 nm-10 nm, d = ˜250 nm,
θ = 65 ° to 90 °, hole density to 3 × 10¹³/ M²;
(Sample D) 2r = -50 nm, t = -10 nm, d = -250 nm-300 nm
Hole density ~ 3 x 10¹³/ M²,
It is.
[0022]
From the above results, the following model can be estimated as the formation mechanism of the honeycomb-shaped recess 2.
[0023]
(1) First, among the point defects (lattice defects and atomic vacancies) generated by ion implantation, the substrate temperature T on which the single crystal substrates (sample A, sample B, sample C, and sample D) are held._SUBThen, the interstitial atoms move a certain distance, but the atomic vacancies do not move much.
[0024]
(2) Interstitial atoms move at the beginning of ion implantationShiSuppose that a part forms an aggregate such as a loop, and a bulge (pulse) is formed on the surface of the single crystal substrate. And let the part surrounded by the pulse be a basin.
[0025]
(3) A point defect is formed on the upper side of the pulse, but disappears because the surface of the single crystal substrate is close. When the injection of charged particles at a low temperature further proceeds after a certain period of time, the charged particles do not reach the lower part of the pulse, so that no point defect can be formed in the lower part of the pulse.
[0026]
(4) Directly under the basin (ion projection range R_pIs about 30 nm), point defects are formed. Some of the interstitial atoms move to the lower concentration (ie below the pulse).
[0027]
(5) They move to the root part of the pulse, the pulse becomes higher and becomes a wall.
[0028]
(6) Atomic vacancies formed just below the basin cannot move so much and go to the surface. That is, the basin does not rise (rather lower).
[0029]
(7) As a result, a honeycomb structure is formed.
[0030]
Thus, in the fine pattern forming method of the present invention, the temperature T of the single crystal substrate_SUB, Charged particle acceleration voltage V_ACAnd the charged particle type (ion type), implantation dose φ, and crystal plane orientation, the diameter 2r and depth d of the concave portion 2 constituting the honeycomb structure, and the distance between the concave portion 2 and the concave portion 2 It is possible to control the angle θ formed with respect to the wall having the thickness t of the wall and the bottom surface of the wall recess. That is, in the fine pattern forming method of the present invention, the size and shape of the recess can be controlled by selecting the conditions as follows.
[0031]
(B) Temperature T of the single crystal substrate_SUB: Considering the balance between interstitial atoms and vacancies mobility, temperature T of single crystal substrate_SUBYou can decide.
[0032]
(B) Acceleration voltage V_ACAnd ion species: If interstitial atoms are formed at a depth of h from the surface, a part of the interstitial atoms can move to about h in the lateral direction. The lateral movement distance of the interstitial atoms determines the size of the recess (burrow), and the radius of the recess becomes about h. Acceleration voltage V_ACIf the ion species is lowered or the ion species is increased, the projected range R of the implanted ions_pBecomes smaller (shallow). That is, the implanted ions reach only a shallow part of the substrate surface, and the radius of the concave portion becomes small. In the opposite case, the projected range R of the implanted ions_pBecomes deeper and the radius of the recess becomes larger. At the initial stage of burrow growth, the implantation dose φ is also related to the size.
[0033]
(C) Implanted dose amount φ: When the implanted dose amount φ is large, the amount of interstitial atoms formed increases and the wall becomes higher. That is, the burrow becomes deep. The greater the mass of the implanted ion species, the greater the amount of defect formation and the deeper the burrow.
[0034]
(Method for manufacturing semiconductor device)
The honeycomb structure described above can be used in a wide range of applications centering on optical devices and quantum effect semiconductor devices because of its size.
[0035]
For example, the thickness of the partition wall having a structure formed by the fine pattern forming method according to the embodiment of the present invention is about 5 nm, and a tunnel effect or a quantum mechanical effect appears in the behavior of electrons in the partition wall. In addition, since the size of the recess formed by the fine pattern formation method or between the recess and the recess is on the order of the wavelength of light, a two-dimensional or three-dimensional photonic crystal can be easily formed in a self-forming manner. Can be manufactured. That is, by the fine pattern forming method according to the embodiment of the present invention, it is possible to form a regular nanostructure structure and realize a photonic gap. For this reason, by using a photonic crystal to control the light confinement effect and the light emission characteristics, it is possible to manufacture a light emitting diode (LED) or the like having an operation speed and coherence similar to that of a semiconductor laser. Alternatively, if used as a semiconductor laser, a large gain and a sharp gain spectrum can be expected.
[0036]
Moreover, the regular surface structure of the nanometer level can relatively increase the surface area with respect to a certain chip area. For this reason, if the fine concave structure according to the embodiment of the present invention is applied to an element requiring a large surface area such as an olfactory sensor or a capacitor, a small and high-performance element can be realized.
[0037]
Furthermore, it is also possible to configure functional elements and semiconductor memories having the following mesoscopic scale and atomic scale structures.
[0038]
[Specific example 1: functional element]
4 and 5C are a schematic cross-sectional view and a plan view showing a structure of a tunnel injection type neuron element as an example of a functional element (a cross-section along the BB direction of FIG. 5C). The figure is FIG. 4). As shown in FIGS. 4 and 5C, the tunnel injection type neuron device according to the embodiment of the present invention includes a plurality of gate electrodes 141, 142, and a plurality of gate electrodes 141, 142, between the first electrode 161 and the second electrode 162. 143,... Are arranged. As is apparent from the cross-sectional view of FIG. 4, the n-type region 121 and the n-type region 122 made of GaSb, the n-type region 122 and the n-type region 123, the n-type region 123 and the n-type region 124, In the meantime, a tunnel injection layer composed of a p-type GaSb layer having a thickness of 5 nm is formed. The n-type regions 120, 121, 122,..., 129 are arranged one-dimensionally in the p-type GaSb substrate 11. The n-type region 120 located at one end of the one-dimensional array of n-type regions 120, 121, 122,.⁺The first contact region 171 made of a type GaSb region and the n type region 129 located at the other end include n⁺A second contact region 172 made of a type GaSb region is formed. The first electrode 161 made of a metal such as gold / germanium (Au—Ge) / nickel (Ni) / gold (Au) is provided so as to make ohmic contact with the first contact region 171 and the second contact region 172. The second electrodes 162 are connected to each other. The plurality of gate electrodes 141, 142, 143,... Are a single layer metal film such as aluminum (Al), a multilayer metal film such as titanium (Ti) / platinum (Pt) / gold (Au), tungsten silicide (WSi_x ) Etc. The gate electrodes 141, 142, 143,... Are respectively connected to the gate electrodes 141p, 142p, 143p,... Shown in the plan view of FIG. A plurality of input signals are applied. As shown in FIG. 4, a gate insulating film 13 is formed immediately below the gate electrodes 141, 142, 143,... And a plurality of inputs applied to the gate electrodes 141, 142, 143,. In accordance with the signal, the electric field of the tunnel injection layer immediately below the gate electrodes 141, 142, 143,... Is controlled, and the tunnel current flowing through each tunnel injection layer is controlled. As a result, a multi-value logic signal flows between the first electrode 161 and the second electrode 162 in accordance with a plurality of input signals, and a neuronal operation can be performed.
[0039]
The tunnel injection type neuron element shown in FIGS. 4 and 5C can be realized by the following manufacturing method.
[0040]
(A) First, a p-type GaSb substrate 11 having a (100) plane is prepared as a compound semiconductor single crystal substrate. An oxide film, a metal thin film, or a composite film thereof is deposited on the surface of the compound semiconductor single crystal substrate 11. Then, using a well-known photolithography technique, RIE method, or the like, a predetermined opening is formed in a part of the oxide film, the metal thin film, or a composite film thereof, and used as a mask material for ion implantation.
[0041]
(B) The compound semiconductor single crystal substrate 11 is set in a substrate holder in the sample chamber of the ion implantation apparatus. 10 inside the sample chamber^-3Pa to 10^-8Vacuum exhaust to a predetermined pressure of Pa. Then, while measuring the temperature of the substrate holder with a temperature monitor such as a thermocouple, it is cooled to a low temperature of −50 ° C. or lower and −273 ° C. or higher, for example, about −130 ° C. using a refrigerant such as liquid nitrogen. As a result, the compound semiconductor single crystal substrate 11 is cooled to a predetermined temperature.
[0042]
(C) When the compound semiconductor single crystal substrate 11 is cooled to a predetermined temperature, tin ions (Sn) are formed as charged particles on the surface of the single crystal substrate through the openings of the mask material.⁺) 1 x 10¹⁴cm^-25 × 10 or more¹⁶cm^-2The implantation is selectively performed at a predetermined acceleration voltage, for example, 60 kV at the following dose.
[0043]
(D) The compound semiconductor single crystal substrate 11 is returned to room temperature, and the compound semiconductor single crystal substrate 11 is taken out from the sample chamber of the ion implantation apparatus. Through the above steps, as shown in FIG. 5A, recesses 20, 21,..., 29 are formed on the surface of the compound semiconductor single crystal substrate 11. Since ions are selectively implanted using a mask material, the recesses 20, 21,..., 29 are arranged one-dimensionally, unlike FIG.
[0044]
(E) Chlorine (Cl₂If the surface of the recesses 20, 21,..., 29 is subjected to a light etching process by dry etching using a system etching gas, rectangular recesses 31, 32 surrounded by {110} planes on the four surfaces are formed. , ..., 39 can be formed. In the case of a certain purpose, it is also possible to omit this slight etching and adopt an irregular recess as shown in FIG. FIG. 2A is a cross-sectional view taken along the AA direction in FIG. Then, as shown in FIG. 2B, n is formed inside the recesses 31, 32, 33, 34,... Using an organic metal CVD (MOCVD) method, a molecular beam epitaxial (MBE) method, or the like. Epitaxial growth layer 12 made of type GaSb is epitaxially grown.
[0045]
(F) Subsequently, as shown in FIG. 2C, the surface is flattened by a method such as chemical mechanical polishing (CMP), and n in the recesses 31, 32,. Type GaSb regions 121, 122, 123, 124 are embedded. Thereafter, a gate insulating film 13 such as an oxide film or a nitride film having a thickness of 20 nm to 80 nm is deposited as shown in FIG. Instead of an insulating film such as an oxide film or a nitride film, a semiconductor layer such as aluminum antimony (AlSb), aluminum nitride (AlN) or zinc selenide (ZnSe) having a larger forbidden band than GaSb is epitaxially grown, and GaSb Even if a heterojunction is formed at the interface, a function equivalent to that of the gate insulating film 13 can be achieved.
[0046]
(G) Thereafter, as shown in FIG. 3E, on the gate insulating film 13, a single layer metal film such as aluminum (Al), titanium (Ti) / platinum (Pt) / gold (Au), etc. Multilayer metal film, tungsten silicide (WSi_xA conductive film 14 such as a silicide film is deposited using a known method such as a CVD method, a vacuum evaporation method, or a sputtering method. Then, if the conductor film 14 is patterned using the photolithography technique and the RIE method, the gate electrodes 141, 142, and 143 are completed.
[0047]
As shown in FIG. 4, n connected to the n-type GaSb region 120⁺N connected to the first contact region 171 composed of a GaSb region and an n-type GaSb region 129⁺Sn is formed when forming the second contact region 172 made of the type GaSb region.⁺Before selective ion implantation of silicon (Si⁺), Selenium (Se⁺) And other group IV elements may be selectively ion-implanted at room temperature and heat-treated for this activation. Then, a contact hole is opened in the gate insulating film 13 using photolithography technique and RIE method, and the first electrode 161 made of a metal such as gold / germanium (Au—Ge) / nickel (Ni) / gold (Au) is used. The second electrode 162 may be formed. For the patterning of the first electrode 161 and the second electrode 162, a known lift-off process may be used.
[0048]
As described above, according to the method of manufacturing a semiconductor device according to the embodiment of the present invention, a mesoscopic scale or atomic scale semiconductor device can be easily obtained without using an expensive electron beam exposure apparatus or X-ray exposure apparatus. Can be manufactured.
[0049]
4 and FIG. 5C, only two adjacent ones of the one-dimensional arrays of n-type regions 120, 121, 122,. That is, if one gate electrode is provided on the p-type GaSb layer between two adjacent n-type regions composed of GaSb, an insulated gate having the two adjacent n-type regions as source / drain regions. Type transistor.
[0050]
[Specific Example 2: Semiconductor memory]
FIG. 6A is an equivalent circuit diagram of a NAND type semiconductor memory (EEPROM), and FIG. 6B is a cross-sectional view of a part of the string (within a range indicated by a broken line). As shown in FIG. 6A, the NAND type EEPROM includes a plurality of bit lines BL._i , BL_{i + 1}, BL_{i + 2},... And a plurality of word lines WL orthogonal thereto_j, WL_{j + 1} , ..., WL_{j + n}Thus, a matrix is configured. Each bit line BL_i, BL_{i + 1}, BL_{i + 2},... Are each constituted by a string in which cells of a plurality of insulated gate transistors are connected in series. A string selection transistor and a ground selection transistor are connected to both ends of each string. A common string selection line SSL is used for each string selection transistor and ground selection transistor of each string._KAnd ground selection line GSL_KIs connected.
[0051]
6B, the n-type region 321 made of GaSb and the n-type region 322, the n-type region 322 and the n-type region 323, n-type. A p-type GaSb layer having a thickness of 5 nm is formed between the region 327 and the n-type region 328. The n-type regions 321, 322,..., 328 are arranged one-dimensionally in the p-type Ga Sb substrate 11. This one-dimensional arrangement is similar to FIG. 5 in that the tin ions (Sn⁺) 1x10¹⁴cm^-25 × 10¹⁶cm^-2What is necessary is just to selectively implant at an acceleration voltage of about 60 kV with the following dose. A floating gate electrode 242 and a control gate electrode 252 are arranged on the p-type GaSb layer between the n-type region 322 and the n-type region 323. Similarly, on the p-type GaSb layer between the n-type region 323 and the n-type region 324, the floating gate electrode 243 and the control gate electrode 253 are provided as the n-type region 326 and the n-type region. A floating gate electrode 245 and a control gate electrode 255 are disposed on the p-type GaSb layer between the first and second layers 327. On the upper part of the p-type GaSb layer between the n-type region 321 and the n-type region 322, the gate electrode 241 of the ground selection transistor, on the upper part of the p-type GaSb layer between the n-type region 327 and the n-type region 326. The gate electrode 246 of the string selection transistor is disposed.
[0052]
As described above, according to the method of manufacturing a semiconductor device according to the embodiment of the present invention, a semiconductor with a fine dimension as shown in FIG. 6 can be used without using an expensive electron beam exposure apparatus or X-ray exposure apparatus. Memory can be easily manufactured.
[0053]
(Other examples)
The discussion and drawings that form part of the above disclosure should not be construed as limiting the invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
[0054]
For example, in the above, GaSb and InSb are exemplified as the material for ion implantation at a low temperature. However, the honeycomb structure observed on the surface of the compound semiconductor single crystal substrate can be selected from other compound semiconductor single crystals if ion implantation conditions are selected. It can be formed on the surface of a substrate made of many inorganic substances as well as the substrate.
[0055]
FIG. 7 shows n inside the recess.⁺In this example, an element isolation region 21 is formed by embedding an epitaxial growth layer made of type GaSb and then forming a p-type region surrounding a 3 × 3 matrix in the center. N at the center of the 3 × 3 matrix⁺Type GaSb drain region, 8 n outside it⁺If the type GaSb is used as the source region and the gate electrode 145 is formed at the boundary, a unit insulated gate transistor is formed. Unit cells based on the unit insulated gate transistors can be arranged in a matrix to form a semiconductor memory such as a DRAM or a two-dimensional image sensor.
[0056]
Further, in FIG. 7, a rectangular recess is shown, but a recess such as a triangle or a hexagon can be formed according to the symmetry (anisotropy) of the crystal structure.
[0057]
As described above, the present invention provides a new functional semiconductor device other than the above semiconductor device, an electronic device having various functions using a porous inorganic material, a magnetic recording medium using a porous magnetic material, and the like. It is applicable to.
[0058]
As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.
[0059]
【The invention's effect】
According to the present invention, a nanometer level fine pattern can be formed on the surface of a single crystal substrate very easily.
[0060]
According to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having a nanometer level fine pattern can be provided at low cost.
[Brief description of the drawings]
FIG. 1 (a) is a scanning electron microscope (SEM) plan view of a semiconductor surface formed by a fine pattern forming method according to an embodiment of the present invention, and FIG. It is the cross-sectional shape observed with the scanning electron microscope (TEM).
FIG. 2 is a process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 1).
FIG. 3 is a process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 2).
FIG. 4 is a schematic cross-sectional view showing a structure of a tunnel injection type neuron element as a specific example 1 of the semiconductor device according to the embodiment of the invention.
5 is a process plan view for explaining the manufacturing method of the tunnel injection type neuron element of FIG. 4; FIG.
FIG. 6A is an equivalent circuit diagram of a NAND type EEPROM as a specific example 2 of the semiconductor device according to the embodiment of the present invention, and FIG. 6B is a cross-sectional view of a part of the string. It is.
FIG. 7 is a schematic plan view showing unit insulated gate transistors constituting a matrix structure as another example of the semiconductor device according to the embodiment of the invention.
[Explanation of symbols]
1,11 Semiconductor single crystal
2, 20-24, 27, 30-34, 39 Recess
12 Epitaxial growth layer
13 Gate insulation film
14 Conductor film
21 Device isolation region
120-124, 129, 321-328 n-type GaSb region
141, 142, 143, 145, 241, 246 Gate electrode
141p, 142p, 143p Gate electrode pad
161 First electrode
162 Second electrode
171 First contact region
172 Second contact region
242-245 Floating gate electrode
252 to 255 Control gate electrode

Claims (2)

The single crystal substrate is heated to −50 ° C. or lower and −273 so that the mobility of interstitial atoms generated by injecting charged particles into the single crystal substrate is larger than the mobility of atomic vacancies generated by the injection. Cooling to a low temperature of ℃ or higher,
Wherein at single crystal 1 × ¹⁰ 14 ^{cm -2} or more 5 × ¹⁰ 16 ^{cm -2} or less of a dose of the charged particles to the surface of the substrate, implanting a predetermined acceleration voltage,
Returning the single crystal substrate to room temperature ,
A method for forming a fine pattern, comprising: forming a honeycomb structure pattern comprising a plurality of recesses each having a diameter on the order of a projected range of the charged particles on the surface of the single crystal substrate . Forming a mask material having a predetermined opening on the surface of the single crystal substrate ;
The single crystal substrate is heated to −50 ° C. or lower so that the mobility of interstitial atoms generated by injecting charged particles into the single crystal substrate is larger than the mobility of atomic vacancies generated by the injection. Cooling to a low temperature of 273 ° C. or higher;
Through the opening of the mask material, the said charged particles on the surface of the single crystal substrate at 1 × ¹⁰ 14 ^{cm -2} or more 5 × ¹⁰ 16 ^{cm -2} or less of the dose, selective in predetermined acceleration voltage Injecting into
Returning the single crystal substrate to room temperature to form a honeycomb structure pattern having a plurality of recesses each having a diameter on the order of the projected range of the charged particles on the surface of the single crystal substrate;
The method of manufacturing a semiconductor device which comprises a step of each epitaxially grown inside the plurality of recesses.

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