JP4606998B2 - Network cache device and program - Google Patents

Description

  The present invention mediates communication between a computer and a storage device storing data necessary for the operation of the computer, and temporarily stores data obtained from the storage device by the computer or data stored in the storage device by the computer. In addition, the present invention relates to a network cache device that returns data to a computer without accessing the storage device if the data requested to be read from the computer is in temporarily stored data, and a program thereof.

  Patent Document 1 describes a network boot system that can shorten the time for starting a diskless personal computer (PC) that does not have a built-in hard disk device. In Patent Document 1, if the data requested to be transmitted from the diskless PC is a read request for a specified logical block, for example, logical block 0, the cache device transmits a read request for logical block 0 to the storage device. Then, a request for reading data for a preset OS image is transmitted to the storage apparatus. When receiving a response to read the OS image data from the storage device, the cache device stores the received OS image in a built-in storage medium, and this triggers a read request for logical block 1 and subsequent addresses from the diskless PC. On the other hand, without making a request to the storage apparatus, the corresponding data is transferred from the OS image stored in the own apparatus to the diskless PC. Further, in Patent Document 1, when an authentication request is sent from a diskless PC to an authentication server, if the authentication is normal, an instruction to read out an OS image is issued from the authentication server to the cache device. As an opportunity, it is described that an OS image “read request” is transmitted to the storage apparatus before receiving the first “read request” from the diskless PC.

JP-A-2005-149334

  In the network boot system described in Patent Literature 1, a computer (hereinafter described as an example of a PC) has read a predetermined logical block address of a storage device, or user authentication by a user who is about to start using the computer is successful. As a result, data prefetching starts. Then, the time from when the cache device starts reading data necessary for the operation of the PC to when the PC starts issuing a read request with the operation of the PC is only several seconds to several tens of seconds.

  Therefore, if the network transmission delay time between the cache device and the storage device cannot be ignored, or if the storage access latency cannot be ignored, the cache device issues a read request and The time required to complete the acquisition (hereinafter referred to as “network response time”) increases, the ratio of the network response time to the time required for data prefetching cannot be ignored, and the time required for data prefetching increases. There is a fear. FIG. 1 shows how network transmission delay time, bandwidth, and storage access waiting time affect network response time.

  As a result, when a read request is issued from the PC, prefetching of the target data is not executed, and a state in which the target data is not stored in the cache device (hereinafter referred to as “cache miss hit”) occurs. In that case, after issuing a read request of the PC, it is necessary to wait for data acquisition from the storage device using a network having a large transmission delay time or a small band (hereinafter referred to as “low performance”). As a result, the acquisition of data necessary for the operation of the PC is delayed, the effect of preventing the deterioration of the operation speed of the PC cannot be obtained sufficiently, and the PC user feels that the operation of the PC is slow, thus reducing convenience.

  In addition, when a best-effort commercial network provided by a telecommunications carrier is used as a network between the cache device and the storage device, the transmission delay time and bandwidth of the best-effort network fluctuate from moment to moment. The acquisition time of data necessary for the operation also varies, and the operation speed of the PC becomes unstable.

  The present invention is to solve the above-mentioned problem, and by increasing the speed of data prefetching by a cache device, a read request for data prefetching is performed prior to a read request from a computer. It is certain. That is, it becomes certain that the target data of the read request by the computer is already stored in the cache device (this is called “cache hit”).

  Then, after issuing the read request, the computer does not need to wait for acquisition of data from the storage device sequentially, and the same data can be acquired from a cache device with a short access time. This means that data is acquired via a network with higher performance, so that the operating performance of the computer is improved.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  According to a first aspect of the present invention, there is provided a storage device having a prefetch pattern data storage area for storing prefetch pattern data, and prefetch pattern data for prefetch pattern data for issuing a predecessor read request under the same condition as a read request issued by a computer. Data from the storage device by issuing a preceding read request according to the description of the pre-read pattern data before the computer starts issuing a read request to acquire data necessary for a specific operation and means for storing in the area And a means for temporarily storing the data in a cache data storage area.

  According to a second aspect of the present invention, there is provided a storage device having a prefetch pattern data storage area for storing prefetch pattern data, and a block to be read by a plurality of read requests issued continuously in time in a read request issued by a computer Means for storing, in the prefetch pattern data storage area, prefetch pattern data converted so as to issue one preceding read request for reading all of the consecutive block areas when the address areas are continuous; Before the computer starts issuing a read request to acquire data necessary for a specific operation, the data is acquired from the storage device by issuing a preceding read request according to the description of the prefetch pattern data. Means for temporarily storing data in the cache data storage area. The features.

  According to a third aspect of the present invention, when the same block address is read by a plurality of read requests in a storage device having a prefetch pattern data storage area for storing prefetch pattern data and a read request issued by a computer, the block address Is stored in the pre-read pattern data storage area in a plurality of blocks that are read by a single previous read request and converted so that a plurality of blocks having consecutive addresses are read by a single previous read request; Before the computer starts issuing a read request to acquire data necessary for a specific operation, the data is acquired from the storage device by issuing a preceding read request according to the description of the pre-read pattern data. To temporarily store the data in the cache data storage area Characterized in that it comprises a and.

  In a fourth aspect based on the third aspect, the storing means converts the read request so that the read request is issued in ascending or descending order of the block address of the read block targeted by the read request. Features.

  A fifth invention is characterized in that, in the third invention, the storing means converts and stores a read request including a block to be read earlier by a computer so that the read request is issued earlier. And

  According to a sixth aspect, in the first to fifth aspects, two or more sessions are established with the storage device, and any read request issued for data prefetching is one of the two or more sessions. It is characterized by comprising means for selecting and issuing.

  Hereinafter, the first to sixth inventions will be described using variables.

In performing a predetermined operation, the computer issues a read request for a certain block address in the storage device to acquire data necessary for the operation. The number of read requests is N in total, and the block number in the storage device that is read by the i-th read request is a plurality of consecutive block addresses with B _{i as the} start block address and L _{i as the} total number of blocks. Assume that the block address is known to the cache device. Hereinafter, the issue pattern of the read request accompanying the predetermined operation of the computer will be expressed as “read pattern sample (B _i , L _i )”. The notation [B _i , L _i ] means a section from the logical block address Bi to the logical block address B _i + L _i −1.

First to sixth invention, based on the known readout pattern sample _{(B i, L} i), it is to perform data prefetching. Among them, the second to fifth inventions reduce the issuance of read requests compared to the first invention by applying processing based on a certain algorithm to the read pattern samples (B _i , L _i ). And prefetching data. The algorithm is different in each of the second to fifth inventions. Further, the sixth invention does not reduce the issue of read requests, but tries to eliminate the influence of network response time as much as possible by issuing multiple read requests.

According to a first aspect of the present invention, data prefetching is performed by issuing N read requests, and the i-th read request is targeted for [B _i , L _i ]. . In short, the cache device performs data prefetching by completely imitating the read request issuance conditions based on the read pattern samples (B _i , L _i ).

  According to the present invention, even if the operation of the computer is started before the prefetching of data is completed, it becomes more certain that the data targeted by the read request from the computer is already stored in the cache device, and the cache hit The ratio of can be increased. As a result, the computer does not need to acquire data from the storage device, and the same data can be acquired from the cache device. This means that data is acquired via a network with higher performance, so that the operating performance of the computer is improved.

The second invention will be described. When attention is paid to the i-th to j-th total j-i + 1 read requests in the read pattern sample (B _i , L _i ), the i-th and i + 1-th, i + 1-th and i + 2-th,. The block addresses to be read in the read requests of the (−1st and jth) read requests are continuous (B _i + L _i = B _{i + 1} , B _{i + 1} + L _{i + 1} = B _{i + 2} ,... B _j−1 + L _j−1 = B _j ).

In such a case, the second invention reads [B _i , B _j + L _j −B _i ] from the i th to j th read requests (total j−i + 1) issued by the first invention. Data prefetching is performed by replacing the target read request once and issuing it to the storage device. For example, if the second read request is [2, 2], the third read request is [4, 3], and the fourth read request is [7, 4], these three read requests are Data prefetching is performed by replacing it with a single read request [2, 9] and issuing it to the storage device.

  According to this invention, in the first invention, the number of times of issuing read requests for data prefetching can be reduced to less than N times. As a result, it is possible to reduce the accumulated time of network response time that occurs every time a read request is issued, and to shorten the time required for data prefetching. Then, the cache hit rate (the number of cache hits per read request; the same applies hereinafter) can be increased, and the operation performance of the PC can be improved.

A third invention is readout pattern sample (B _{i, L i)} in terms of issuing a read request based on is similar to the invention of the first and 2, readout pattern sample (B _{i, L i)} following the It is processed by the method, and a read request is issued under conditions different from those of the first and second inventions.

First, in the read pattern sample (B _i , L _i ) (1 ≦ i ≦ N), as a result of changing the integer k in the range of 1 ≦ k ≦ N, B _k ≦ m ≦ B _k + L _k −1 is 1 Extract all integers m that have been satisfied more than once. This means that all block addresses that have been read one or more times are extracted from the read pattern sample.

Next, data read-ahead is performed by issuing a read request for reading the extracted block address m. However, block addresses m exist continuously (for example, if m = 0, 1, 2, 3, 5, 6, 7..., M = 0, 1, 2, 3 continuously) If the start block address of the continuous area is b _i , the number of blocks is l _i , [b _i , l _i ] ([0, 4] in the above example) is the read target Issue only one read request.

  According to the present invention, blocks having consecutive addresses are read by one read request, and the same block address is not read by two or more read requests. Then, the number of read requests can be further reduced as compared with the second invention that leaves room for the same block to be read twice or more. As a result, the accumulated network response time generated each time a read request is issued can be further reduced as compared with the second invention, and the data prefetching time can be shortened. Then, compared with the second invention, the cache hit rate can be further increased, and the operation performance of the PC can be improved.

  In the third invention, only the read target according to the read request is characterized, and the issue order of the read requests is not characteristic. On the other hand, the fourth and fifth inventions to be described later are characterized in that the order of issuing read requests is characterized in the third invention.

  In the fourth invention, the issuing order of the read requests that can be issued in the third invention is ascending order or descending order of the start block addresses.

  According to the present invention, read requests are issued in ascending order of logical block addresses, or data are acquired from the storage device. Then, when the storage device is a magnetic disk device and the block addresses are distributed in order from the center to the outer periphery on the magnetic disk or in the opposite direction, the magnetic head moves from the center to the outer periphery or its Since it moves smoothly in the reverse direction and does not perform useless reciprocation, it can be expected that data can be acquired from the storage device at high speed, and the data read-ahead time can be shortened. When the storage device is a RAID (Redundant Array of Independent Disks) device, generally, input / output with a built-in magnetic disk device is performed with a large data size. Waste is reduced and data read-ahead time can be shortened. Then, compared with the first and second inventions, the cache hit rate can be further increased, and the operation performance of the PC can be improved.

The fifth invention is characterized in that the issue order of read requests that can be issued in the third invention is determined by comparison with the read pattern samples (B _i , L _i ).

First, among the read requests that can be issued in the third invention, [b _i , l _i ] (b _i ≦ B ₁ ≦ B ₁ ) completely including the read target range of the read pattern sample (B ₁ , L ₁ ). + L ₁ ≦ b _i + l _i ) is selected and issued. Next, for the read pattern sample (B ₂ , L ₂ ), similarly, a read request that completely includes the read target range is issued. The same selection is performed for the read pattern samples (B ₃ , L ₃ ), (B ₄ , L ₄ ).

  According to the present invention, even if the operation of the computer is started before the data prefetching is completed, the data targeted for the read request from the computer is already stored in the cache device. Compared to this, it becomes more reliable, the cache hit rate can be further increased, and the operation performance of the PC can be improved.

  The sixth invention has a restriction that the PC issues a read request in order to acquire data from the storage device, and issues the next read request after confirming that the data has been returned. Is focused on. In the present invention, a plurality of sessions are established between the cache device and the storage device, and a read request associated with data prefetching is distributed and issued to a plurality of sessions, thereby avoiding the restriction.

  According to the present invention, after the i-th read request is issued, the next i + 1-th read request can be issued using another session before the data corresponding to the read command is returned. Thus, simple accumulation of network response time can be avoided, and data read-ahead speed can be increased. Then, compared with the first to fifth inventions, the cache hit rate can be further increased, and the operation performance of the PC can be improved.

  By reducing the number of read requests issued with data prefetching, or by issuing read requests via a plurality of sessions, the network utilization rate at the time of data prefetching can be increased and the data prefetching speed can be increased. As a result, when there is an arbitrary read request from the PC, the target data of the read request is already stored in the cache device, so the cache hit rate can be almost 100%. The operation (OS and application software startup) can be further accelerated.

  Further, when the cache hit rate is almost 100%, the PC acquires necessary data from the cache device instead of the storage device. Then, since the necessary data is acquired only through the LAN in which the state is relatively stable without going through the WAN whose state (bandwidth, delay time, etc.) is likely to change, the state change of the WAN The startup time of the OS and application software on the PC can be stabilized without being substantially affected by the above.

  FIG. 2 shows an example of the entire system configuration including the network cache apparatus according to the embodiment of the present invention. In FIG. 2, PC1 to PC3 are personal computers (hereinafter referred to as PCs) which are examples of computers. S1 is a storage device as an example of a storage device. C1 is a network cache device (hereinafter referred to as “cache device”). The PC1 to PC3, the cache device C1, and the storage device S1 are connected by an IP (Internet Protocol) network N1. Here, the network performance (small delay, large bandwidth, small packet loss, etc.) between the PC1 to PC3 and the cache device C1 is higher than the network performance between the cache device C1 and the storage device S1. Shall. For example, it is assumed that the PC1 to PC3 and the cache device C1 belong to the same LAN (Local Area Network) and are geographically close to each other. On the other hand, it is assumed that the LAN and the storage device S1 are connected by a WAN (Wide Area Network) and are geographically distant.

  Each node of the PC1 to PC3, the cache device C1, and the storage device S1 is assigned an IP (Internet Protocol) address and a TCP (Transmission Control Protocol) port number, and is mutually connected via the IP network N1 (LAN or WAN). TCP / IP communication is possible. Assume that the IP addresses assigned to PC1 to PC3 are p1 to p3, the IP address assigned to the cache device C1 is c1, and the IP address assigned to the storage device S1 is s1.

  There are initiators I1 to I3 inside PC1 to PC3. On the other hand, there is a target T1 inside the storage apparatus S1, and a target name tn1 is assigned. Logical units LU1 to LU3 are connected to the target T1, and logical unit numbers luna1 to luna3 are assigned to them. A storage area in one logical unit LU (Logical Unit) is composed of a large number of logical blocks, and a logical block address (LBA: Logical Block Address) is assigned to each logical block. The capacity of one logical block is usually 512 bytes, and when data larger than this is stored in the logical unit LU, it is stored in a plurality of logical blocks.

  The PC1 to PC3 acquire data stored in a specific logical unit LU in the storage device S1 using an iSCSI (Internet Small Computer System Interface) protocol in order to perform a specific operation. iSCSI is a protocol standardized by Internet Engineering Task Force (IETF), and its detailed specifications are described in RFC (Request for Comments) 3720.

  Specifically, first, the initiators I1 to I3 of the PC1 to PC3 send a Login Request operation to the target T1 in the storage apparatus S1, and return a Login Response from the target T1 in the storage apparatus S1, thereby causing the PC1 to return. -An iSCSI session is established between the initiators I1 to I3 in the PC3 and the target T1 in the storage device S1. Next, using the iSCSI session, the initiators I1 to I3 transmit a read request to the target T1, and obtain data by returning Data-In. Here, the “read request” specifically refers to a SCSI request operation in which a SCSI command “READ” is placed, and this is hereinafter referred to as “SCSI-READ”. According to SCSI-READ, by specifying the logical block address B in the LU and the total number L of logical blocks, a plurality of consecutive logical blocks having the top logical block address B and the total number of logical blocks L blocks are specified. Data can be read at once. Hereinafter, the continuous logical block area represented by B and L will be referred to as [B, L], and the SCSI-READ for reading the area will be referred to as “SCSI-READ [B, L]”. For example, the logical block [0, 12] indicates a total of twelve consecutive logical block areas with logical block addresses 0 to 11, and SCSI-READ [0, 12] reads data in the logical block area. SCSI-READ. Usually, one data is often scattered in a plurality of discontinuous logical blocks, and in this case, reading by a plurality of SCSI-READs is required.

  Hereafter, in the following, an embodiment in the case where PC1 among PC1 to PC3 operates will be described in detail. Therefore, it is assumed that all data (operating system (hereinafter referred to as OS), application program, etc.) necessary for the operation of the PC 1 is stored in the LU 1 in the storage apparatus S1.

  The cache device C1 has a role of relaying iSCSI operations and data transmitted and received between the PC 1 and the storage device S1 in accordance with the above procedure. That is, the Login Request, SCSI-READ, and other operations that the PC 1 transmits to the storage device S1 are once transmitted to the cache device C1, and are relayed to the storage device S1 by the cache device C1. Conversely, data returned from the storage apparatus S1 to the PC 1 is also relayed by the cache apparatus C1.

  There are various methods in which the cache device C1 relays iSCSI operations and data transmitted and received between the PC 1 and the storage device S1, and one method will be described in detail below.

  In this method, the cache device C1 is installed as one IP host (a node having the IP address c1) in the IP network N1 (LAN), and is transmitted from the PC1 to the storage device S1 or from the storage device S1 to the PC1. In this method, the incoming IP address of an IP packet for transferring an iSCSI operation or data is set to c1. FIG. 3 shows a relay sequence such as iSCSI operation by this method.

  First, the PC 1 establishes a TCP connection 1 with the cache device C1, and transmits a Login Request to the cache device C1 using the connection. The cache device C1 that has received the Login Request searches the Table 1 from the Login Request transmission source IP address (PC1 p1), thereby searching for the relay destination of the Login Request, and the storage device S1 ( A TCP connection 2 is established between the IP address s1 and the TCP port 3260), and the Login Request is relayed using the TCP connection 2. At this time, the cache device C1 manages that the TCP connection 1 and the TCP connection 2 are a pair.

  The storage device S1 that has received the Login Request returns a Login Response to the cache device C1 using the TCP connection 2, and the cache device C1 that has received the Login Response uses the TCP connection 1 corresponding to the TCP connection 2. , Relay Request is relayed to PC1. At this time, an iSCSI session is established between the PC 1 and the storage apparatus S1.

  Thereafter, all iSCSI operations, responses, and data transmitted / received between the PC 1 and the storage device S1 are transmitted / received using the connection 1, the TCP connection 2 and the iSCSI session.

  The cache device C1 further has a data cache function. The data cache function includes a passive type and an active type.

  The passive cache function is a function that stores (caches) data in the cache device when the initiator acquires the data from the target. That is, the data returned from the storage apparatus S1 to the PC1 is relayed by the cache apparatus C1 and is also stored in a storage device (memory, hard disk drive, etc.) in the cache apparatus C1. As a result, when the SCSI-READ is issued to read the same data from the PC 1 again to the storage device S1, the cache device C1 does not relay the SCSI-READ to the storage device S1, and thus the cache device C1. Returns the data to the PC 1 (cache hit).

  The active cache function is a function in which the cache device autonomously acquires data from the target and caches it before the initiator acquires data from the target, in addition to the passive cache function. That is, before the PC 1 issues SCSI-READ to the storage apparatus S1 in order to acquire data from the storage apparatus S1, the cache apparatus C1 autonomously issues SCSI-READ to the storage apparatus S1. The data expected to be acquired by the PC 1 is acquired in advance (hereinafter referred to as “data prefetching”) and stored in the cache device. When the PC 1 issues SCSI-READ to the storage apparatus S1 and tries to acquire data from the storage apparatus S1, it can be expected that the same data is already cached (cache hit). The device C1 does not relay the SCSI-READ to the storage device S1, and the cache device C1 returns the data to the PC1.

  The “data expected to be acquired by the PC 1” is specified by “prefetch pattern data”. The prefetch pattern data is data stored in a storage device in the cache device C1, and describes the SCSI-READ issuance conditions that the cache device C1 issues to the storage device S1 when data prefetching is performed. It is.

  An example format of the prefetch pattern data is shown in FIG. In FIG. 4, the first to third lines are information for specifying the data prefetch target LU. The first line is the IP address and TCP port number of the storage to which the data prefetch target LU belongs, the second line is the target name to which the LU belongs, and the third line is the logical unit number LUN of the LU. The fourth and subsequent lines are information for specifying the read target LBA in the logical unit numbers LUN specified up to the third line. Each line corresponds to the issuance of one SCSI-READ [B, L]. One column corresponds to the head logical block address (= B) to be read, and the second column corresponds to the total number of read blocks (= L).

  However, as long as necessary information can be specified, the format of the prefetch pattern data is not limited to that shown in FIG. The information in the first line (IP address, TCP port number), second line (target name), and third line (LU) in FIG. 4 does not need to be included in the prefetch pattern data. It may be held separately.

  According to the prefetch pattern data in FIG. 4, the cache device C1 has an IP address 192.168.1.1, a port number 3260, a target name iqn. com. Data prefetching is performed by establishing an iSCSI session with the target specified by hitachi-ntt-labs and issuing SCSI-READ to LU = 0. According to FIG. 4, SCSI-READ [0, 2] is issued first, and SCSI-READ [2, 2] is issued second.

  The pre-read pattern data can be freely created by a system administrator or the like according to the purpose of data pre-read (what is to be speeded up among PC operations). For example, in order to speed up the activation of specific application software, prefetch pattern data is created so that the LU and LBA storing the application software are data prefetch targets.

  From here onwards, in order to speed up the OS booting on a PC (without a hard disk drive), a method for creating prefetch pattern data will be described in detail, assuming that data necessary for OS booting is prefetched. To do.

The simplest method for creating the prefetch pattern data is to actually turn on the power of the PC 1 (if necessary, perform user authentication) to start the OS, and from the PC 1 to the cache until the start of the OS is completed. All (N) SCSI-READs [B _i , L _i ] (1 ≦ i ≦ N) transmitted to the device C1 are captured and the contents [B _i , L _i ] (1 ≦ i ≦ N) are captured. N) Pre-read pattern data (from the fourth line in FIG. 4) is described as described.

As a capture method, a packet capture device is installed in the network between the PC 1 and the cache device C1, and the contents of the SCSI-READ packet passing therethrough are analyzed, and [B _i , L _i ] (1 ≦ i ≦ N ) Value is extracted. As another method, there is a method in which the cache device itself is provided with a function of analyzing the contents of the SCSI-READ passing through and recording [B _i , L _i ] (1 ≦ i ≦ N) and using it. is there. It doesn't matter which one you choose.

When the prefetch pattern data created by the above method is stored in the cache device C1 as it is and prefetched, the n SCSI-READ [B _i , L _i ] (0 ≦ i) issued by the PC 1 when the OS starts up ≦ n) and the SCSI-READ that the cache device C1 issues to the storage device S1 by data prefetching are the same. In this way, in the data prefetching, the format of the prefetch pattern data that faithfully reproduces the SCSI-READ issued by the PC 1 is hereinafter referred to as “format 1”.

  If data prefetching is performed using format 1 prefetching pattern data and then the OS is activated on the PC 1, the read target data of the SCSI-READ command issued by the PC 1 is always present in the cache device. Then, since the PC 1 can acquire necessary data from the cache device C1 instead of the storage device S1, the OS activation in the PC 1 becomes faster.

  When starting up the OS, for example, in the case of Windows XP (trademark) which is an OS of Microsoft Corporation (trademark), it is known that the PC acquires about 200 to 300 MBytes of data. It has been found that it takes several tens of seconds to prefetch data of the same size with prefetch pattern data in format 1. Therefore, when the time from the start of data prefetching to the start of OS activation of the PC 1 is relatively short, the issuance of SCSI-READ by data prefetching may not be in time for the issuance of SCSI-READ from the PC. As a result, the PC 1 eventually has to wait for data acquisition from the storage device S1, and there is a problem that the effect of speeding up the OS startup in the PC 1 is reduced.

  Therefore, the redundancy of data prefetching in format 1 is eliminated by the following method to speed up data prefetching.

The SCSI-READ [B _i , L _i ] issued when the PC 1 starts up the OS is generally as shown in FIG. In FIG. 5, the horizontal axis represents LBA, and the vertical axis represents the number of times SCSI-READ issued. One line segment represents a range of a logical block to be read by one SCSI-READ. B represents the start position (leading LBA) of the line segment (reading range by one SCSI-READ command), and L represents the length of the line segment (total number of blocks read by one SCSI-READ command).

  In the example of FIG. 5, a total of 14 SCSI-READs are issued, but the first to third, fourth to fifth, sixth to eighth, ninth to eleventh, and twelfth to fourteenth SCSI-READ commands are , Each successive logical block area is read out.

  Here, the data acquisition procedure by SCSI is shown in FIG. FIG. 6 compares the case where 9 blocks of data are acquired with two SCSI-READs (left) and the case where data is acquired with one SCSI-READ (right). According to SCSI, in order to continuously issue SCSI-READ, the next SCSI-READ command is issued unless the data requested by the previously issued SCSI-READ is returned by Data-In. I can't. Then, the data of consecutive logical blocks (9 blocks in FIG. 6) is divided into a plurality of SCSI-READs as shown in FIG. 6 (left) (in FIG. 6 (left), the first 3 blocks, the second 6 blocks) Reading out all blocks with one SCSI-READ as shown in FIG. 6 (right) reduces the number of times SCSI-READ is issued, so reading is completed in a shorter time. be able to.

  In the case of FIG. 5, the SCSI-READs of the first to third, fourth to fifth, sixth to eighth, ninth to eleventh, and twelfth to fourteenths may be replaced with one SCSI-READ. Then, as shown in FIG. 7, the same data prefetching effect can be obtained even by using the prefetching pattern data obtained by converting the prefetching pattern data of format 1 into “format 2”.

  While the number of times SCSI-READ is issued in format 1 is 14, the number of prefetch pattern data in format 2 is 5. As a result, it is possible to reduce the accumulated time of the network response time generated with the issuance of SCSI-READ, so that the network utilization efficiency is increased and the time required for data prefetching can be reduced. If the time required for data prefetching can be reduced, the cache hit rate can be increased, and the operating performance of the PC 1 is improved.

  Looking at the conditions for issuing SCSI-READ in Format 2, the same logical block area is read out at the third and fifth times. However, in data read-ahead, if the same data is read once and cached, there is no need to read it again.

  In the format 2, separate SCSI-READs are issued even though the reading targets by the second and fourth SCSI-READs are continuous. This is because the conversion from format 1 to format 2 replaces them with a single SCSI-READ only when the time-sequential SCSI-READ read target is a continuous logical block. is there. However, the replacement target of SCSI-READ due to the continuity of the logical block to be read need not be limited to those that are issued continuously in time.

  Therefore, in order to eliminate the redundancy as described above, the prefetch pattern data of format 1 is converted to “format 3”. The conversion algorithm to format 3 is as shown in FIG.

The prefetch pattern data of format 3 is a block ([B ₆ , L ₆ ], [B ₇ , L ₇ ], [B ₈ , L ₈ ] in FIG. 7) that has been read twice or more in format 1. However, the number of times read by SCSI-READ is only one. In addition, the area where the logical block addresses are continuous is read by only one SCSI-READ. Furthermore, the SCSI-READ issuance order is set in ascending order of reading target logical block addresses or in descending order (in order of decreasing in FIG. 7).

  There are two effects of Type 3. First, while the number of times SCSI-READ is issued in format 1 is 14 and that in format 2 is 5, it is possible to reduce the number of times SCSI-READ is issued according to format 3 prefetch pattern data. . As a result, the time required for data prefetching can be reduced as compared with the format 1 and the format 2.

  Further, in the case where the storage device S1 is a magnetic disk device and logical block addresses are distributed in order from the center to the outer periphery on the magnetic disk or in the opposite direction, the magnetic head is accompanied by data prefetching based on the format 3. Can smoothly move from the center to the outer periphery or vice versa, and there is no wasteful reciprocation, so it can be expected that data can be acquired from the storage device S1 at high speed.

  From the above two points, the cache hit rate can be further increased as compared with the formats 1 and 2, so that the operation performance of the PC 1 is improved.

Looking at the issuance conditions of SCSI-READ in format 1 (data read as it is when the OS is started in PC1), logical blocks [B ₄ , L ₄ ] and [B ₅ , L ₅ ] are logical blocks [B ₆ , Despite being read before [L ₆ ], [B ₇ , L ₇ ], [B ₈ , L ₈ ], the order is reversed in format 3.

Then, the reading of data of the logical blocks [B ₆ , L ₆ ], [B ₇ , L ₇ ], [B ₈ , L ₈ ] is prioritized, and the logical blocks [B ₆ , L ₆ ], [B ₇ , L ₇ ] may occur when the data is not stored in the cache device C1. As a result, the SCSI-READ is relayed to the storage device S1 by the cache device C1, and data is acquired from the storage device S1 via a relatively low performance network (WAN). Will decline.

  In order to solve the above-mentioned problem, the pre-read pattern data of “Format 4” in which only the SCSI-READ issue order is changed in Format 3 is used. The conversion algorithm from format 1 to format 4 is shown in FIG.

  According to FIG. 9, the number of times SCSI-READ is issued in format 4 is 3, and the number is the same as that in format 3. Therefore, the time required for data prefetching is the same as that in format 3. However, the cache hit rate can be improved as compared with the format 3 in that the data actually required by the PC 1 is prefetched earlier. As a result, the OS startup in the PC 1 can be further accelerated.

  The pre-read pattern data of format 2 to format 4 can be obtained by reading the pre-read pattern data of format 1 by a program that operates based on the above-described algorithm, converting it to each format, and outputting it.

  In the embodiment described above, the speed of data prefetching is increased by converting the format of the prefetch pattern data. In the following, while the format of the prefetch pattern data is the same, the number of iSCSI sessions established between the initiator I1 in the PC1 and the target T1 in the storage device S1 for data prefetching is increased, and a plurality of iSCSI sessions are used. The principle and method for speeding up data read-ahead by issuing SCSI-READ will be described in detail.

  According to iSCSI and SCSI, when issuing SCSI-READ continuously, if the data requested by SCSI-READ is not returned, the next SCSI-READ is not issued. This is because it is based on a non-deterministic condition for determining the next operation based on the data read out in (1). Since the data prefetch processing of this embodiment is access to the storage apparatus based on the prefetch pattern data, a plurality of iSCSI sessions are established, and SCSI-READ is distributed and issued to each session. Then, the influence of the restriction can be minimized, and the utilization rate of the network increases. The principle is shown in FIG.

  FIG. 10 compares the case where five SCSI-READs are issued in a single iSCSI session (see FIG. 10 (left)) and the case where they are distributed and issued in three iSCSI sessions (see FIG. 10 (right)). is doing. The SCSI-READ distribution method may be a round robin method as shown in FIG. 10 or a random selection.

  In addition to using a plurality of sessions as an interface for issuing multiple read requests to the storage apparatus, Command Queueing defined after the SCSI2 specification may be used in a single session.

  Although the above embodiment has been described in detail assuming the case of speeding up the booting of the OS in the PC, the booting of application software required after the booting of the OS can also be speeded up using the present invention. . The method will be described in detail below.

As the simplest method for creating the prefetch pattern data, the PC 1 is cached during the period from when the power to the PC 1 is actually turned on (when necessary, user authentication is performed) to start the OS and the startup of the OS is completed. All (N) SCSI-READs [B _i , L _i ] (1 ≦ i ≦ N) transmitted to the device C1 are captured and the contents [B _i , L _i ] (1 ≦ i ≦ N) are captured. N) The method of describing the prefetch pattern data (in FIG. 4, the fourth and subsequent lines) as described above is already explained.

Here, without stopping the capture of SCSI-READ [B _i , L _i ] upon completion of the OS startup, after the OS startup is completed, the application software for which the startup is to be accelerated is started, and the capture is performed after the startup is completed. And prefetch pattern data is created in accordance with the captured content [B _i , L _i ]. Then, since the data required for starting up the application software is included in the target of the prefetch pattern data, not only the OS but also the data read out by starting up the application software is stored in the cache device in advance. It will be in the state. As a result, the start-up of the application software can be accelerated.

  Further, it is possible to set only the data necessary for starting the application software as the target of the prefetch pattern data. In that case, the startup of the OS cannot be accelerated, but only the startup of the application software can be accelerated.

  Next, an example of the internal structure (software structure) of the cache device C1 will be described with reference to FIG. As shown in FIG. 11, the cache device C1 includes an iSCSI target C101, a cache memory control function C102, a cache memory management function C103, a prefetch pattern data conversion function C104, and an iSCSI initiator C105 as software, and a storage device C106 as hardware. Prepare as. As the storage device C106, a memory, a hard disk, or other storage means can be used. The storage device C106 has a cache data storage area C107 and a prefetch pattern data storage area C108. The cache data storage area C107 and the prefetch pattern data storage area C108 are created in the storage device C106 by a program.

  Although not shown in the figure, the cache memory control function C102 stores in the prefetch pattern data storage area C108 prefetch pattern data for issuing a predecessor read request under the same conditions as the read request issued by the PC; Before the PC starts issuing a read request for acquiring data necessary for a specific operation, the storage apparatus S1 issues a preceding read request according to the description of the prefetch pattern data in the prefetch pattern data storage area C108. 2 or more sessions are established between the storage device S1 and the function of acquiring data from the storage device S1 and temporarily storing the data in the cache data storage area C107, and any data issued for data prefetching A function to issue a read request by selecting one of the two or more sessions Provided.

  Although the read-ahead pattern data conversion function C104 is not shown in the figure, in the read request issued by the PC, a plurality of read requests issued successively in time have consecutive block address areas to be read. In this case, the function of storing the prefetch pattern data converted so as to issue one preceding read request for reading all of the continuous block areas in the prefetch pattern data storage area C108, and the read issued by the PC In the request, when the same block address is read by a plurality of read requests, the block address is read by one preceding read request, and a plurality of blocks having consecutive addresses are one preceding read request. The prefetch pattern data converted so that it can be read by the And a function for storing the C108.

  As shown in FIG. 11, the iSCSI target C101, the cache memory control function C102, the cache memory management function C103, and the prefetch pattern data conversion function C104 are application programs, and the iSCSI initiator is a function of the operating system. The cache device C1 includes means for realizing each function when the CPU executes these programs. A part or all of the internal structure (software structure) of the cache device C1 may be configured by hardware.

  In FIG. 11, the iSCSI target C101 communicates with the iSCSI initiator function of the PCs 1 to 3, and has a function of transmitting and receiving iSCSI commands and data to and from the PCs 1 to 3. On the other hand, the iSCSI initiator C105 communicates with the iSCSI target function of the storage apparatus S1, and has a function of transmitting and receiving iSCSI commands and data to and from the storage apparatus S1.

  The cache memory control function C102 mediates input / output control between the iSCSI target C101 and the iSCSI initiator C105 (inside the operating system), and first provides functions related to the prior art.

  That is, when the SCSI-READ from the PC 1 is received via the iSCSI target C101, whether or not the data to be read by the SCSI-READ exists in the cache data storage area C107 via the cache memory management function C103. Search for. If it is determined that the cache data does not exist (miss hit) as a result of the search, the SCSI-READ is transmitted to the storage device S1 via the iSCSI initiator C105. On the contrary, if it is determined that the cache data exists (hit) as a result of the search, the target data is acquired from the cache data storage area C107 via the cache memory management function C103, and via the iSCSI target C101. Return to PC1. Further, as a result of the SCSI-READ transmitted by the PC 1 reaching the storage device S 1 due to a cache miss, when the data to be read is returned from the storage device S 1 by Data-In, the Data-In is sent to the PC 1. In addition to relaying, the data loaded in the Data-In is stored in the cache data storage area C107 via the cache memory management function C103.

  The cache memory control function C102 writes the prefetched pattern data according to the captured SCSI-READ into the prefetched pattern data storage area C108 via the cache memory management function C103, for example, as shown in FIG. This writing is performed when the PC 1 is started up last time or when the PC 1 is started for testing exclusively for the purpose of capture. Since the SCSI-READ is issued several thousand to several tens of thousands of times from the start of the OS to the completion of the OS startup, all of them are captured and stored in the prefetch pattern data storage area C108 as prefetch pattern data. .

  Further, the cache memory control function C102 also provides a data prefetching function and a multiple session establishment function according to the prior art. That is, the cache memory control function C102 reads the prefetch pattern data stored in the prefetch pattern storage area C108, and establishes a multiple iSCSI session between the iSCSI initiator C105 and the storage device S1. Then, by issuing SCSI-READ to the storage apparatus S1 according to the description of the prefetch pattern data via the iSCSI session, data is acquired from the storage apparatus S1, and the data is cached via the cache memory management function C103. Save in the storage area C107. When the multiple session establishment function is not used, one iSCSI session is established between the iSCSI initiator C105 and the storage device S1, and similar processing is performed.

  Next, the prefetch pattern data conversion function C104 will be described. The prefetch pattern conversion function C104 reads the prefetch pattern data stored in the prefetch pattern data storage area C108, converts it into each format, and writes the converted prefetch pattern data back to the prefetch pattern data storage area C108.

  Next, an example of the internal structure (hardware structure) of the cache device C1 will be described with reference to FIG.

  In FIG. 12, the hardware is composed of a CPU (Central Processing Unit) C111, a memory C112, a hard disk (HDD: Hard Disk Unit) C113, a NIC (Network Interface card) C114, and a system bus C115 that connects each unit.

  The CPU (C111) performs all the arithmetic processes necessary for realizing the processes according to the prior art and the processes detailed in the embodiments of the present invention.

  The operating system, iSCSI target, iSCSI initiator, program according to the prior art, and all programs according to the present invention in FIG. 11 can be stored in the memory C112 or the hard disk C113. These programs are appropriately loaded into the memory C112 and executed (the program stored in the memory C112 is loaded into another area in the memory C112 and executed). The NIC (C114) is connected to the IP network N1, and performs communication by IP between the PC1 to PC3 and the storage device S1.

  The storage device in FIG. 11 can be assigned C106, memory C112 or hard disk C113. When the memory C112 is allocated, the cache data can be written or read at a high speed, but the price per unit capacity is high. On the other hand, when assigned to the hard disk C113, the price per unit capacity is low, but there is a drawback that data cannot be written or read at high speed.

  The hardware structure described above can be provided by an ordinary personal computer, workstation, server, or the like that satisfies the requirements of the structure.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

It is the figure which showed a mode that the transmission delay time of a network, a zone | band, and the waiting time of storage access affect network response time. 1 is a diagram illustrating an example of an overall system configuration including a network cache device according to an embodiment of the present invention. It is the figure which showed the relay methods, such as iSCSI operation by the cache device. It is the figure which showed the example of a format of prefetch pattern data. FIG. 4 is a diagram illustrating addresses of logical blocks that are read when a PC starts up an OS. It is the figure which showed the data acquisition procedure by SCSI-READ. It is the figure which showed the algorithm which changes the format of prefetch pattern data from the format 1 to the format 2. It is the figure which showed the algorithm which changes the format of prefetch pattern data from the format 1 to the format 3. It is the figure which showed the algorithm which changes the format of prefetch pattern data from the format 1 to the format 4. It is the figure which showed the issuing procedure of SCSI-READ using a some iSCSI session. It is the figure which showed an example of the software structure of a cache apparatus. It is the figure which showed an example of the hardware structure of a cache apparatus.

Explanation of symbols

PC1 to PC3 ... personal computer, p1 to p3 ... IP address assigned to PC1 to PC3, I1 to I3 ... initiator, C1 ... network cache device, c1 ... IP address assigned to network cache device C1, N1 ... Network, S1... Storage device, s1... IP address assigned to storage device S1, LU1 to LU3... Logical unit, lun1 to lun... Logical unit number assigned to logical unit U1 to LU3, C101. C102: Cache memory control function, C103: Cache memory management function, C104: Prefetch pattern data conversion function, C105: iSCSI initiator, C106 storage device, C107: Cache data rating Region, C108 ... preread pattern data storage area, C111 ... CPU, C112 ... memory, C113 ... HDD, C114 ... NIC, C115 ... system bus

Claims (5)

Mediates communication between a computer and a storage device storing data necessary for the operation of the computer, and caches data acquired from the storage device by the computer or data stored in the storage device by the computer A network cache device that temporarily stores data in a data storage area and returns the data to the computer without accessing the storage device if the data requested to be read from the computer is in the cache data storage area Because
A storage device having a prefetch pattern data storage area for storing prefetch pattern data which is information relating to a read request issued to the storage device;
When the prefetch pattern data stored in the prefetch pattern data storage area is read and the same block address is read by a plurality of read requests in the read request corresponding to the prefetch pattern data, the block address is set once. prior read by the read request plurality of blocks addresses and which addresses are continuous, of a conversion means for storing the converted pre-read pattern data as read out by one of the preceding read request to the pre-read pattern data storage area,
Acquire data from the storage device by issuing a preceding read request according to the description of the converted prefetch pattern data before the computer starts issuing a read request to acquire data necessary for a specific operation. Means for temporarily storing the data in the cache data storage area;
Equipped with a,
The converting means converts a plurality of block addresses having consecutive addresses even when the reading order is not continuous when converting a plurality of block addresses having consecutive addresses so that they are read by a single preceding read request. network cache apparatus characterized that you conversion as read by one of the preceding read request. The network cache device according to claim 1 ,
The network cache device, wherein the conversion means converts and stores a read request so that the read request is issued in ascending or descending order of the block address of the read block. The network cache device according to claim 1 ,
And the converting means, the read request including blocks the computer requires a more early, and stores the converted to replace the previous read request issuance order of the corresponding to the read request to be issued earlier A network cache device. The network cache device according to any one of claims 1 to 3 ,
Establishing two or more communication session between the storage device, any read requests issued for data prefetching, further comprising means for issuing allocated to one of the two or more communication sessions A network cache device. 請 Motomeko 1 to network caching program for causing a network cache device according to the computer in one of claims any one of 4.

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