JP4599438B2 - Pipeline processing apparatus, pipeline processing method, and pipeline control program - Google Patents

Description

  The present invention relates to a pipeline processing apparatus and the like that performs pipeline processing using a multiprocessor, and in particular, reduces the total amount of data transfer between processor elements while retaining the characteristics of pipeline processing suitable for real-time requirements, and applications. The present invention relates to a pipeline processing apparatus that can reduce the development load.

  For example, when playing back a moving image, a certain amount of data processing may be requested in real time within a certain time.

  As a method for realizing the real-time request, there is an embedded system in which dedicated hardware such as a DSP (digital signal processor) is incorporated. In recent years, due to advances in processor technology, an increasing number of embedded systems perform program parallel processing using a multiprocessor.

  For example, each processor element (hereinafter also referred to as PE) has a relatively small local memory, and processing is performed after fetching execution code and data to be processed (hereinafter also referred to as target data) into the local memory. There is a system configured to do so. In the system having this configuration, it is not necessary to access an external resource such as a shared memory while processing data fetched into the local memory. Therefore, resource competition with other processors hardly occurs, and it is suitable for realizing a real-time request.

  However, when using a multiprocessor, how to schedule becomes a problem. That is, the problem is how to allocate a plurality of processors and programs in order to satisfy the real-time request. As a solution to this problem, there is a method of pipeline processing of software (hereinafter simply referred to as pipeline processing).

  In conventional pipeline processing, application software is divided in advance into stages such as a plurality of programs or functional modules. Then, each of the divided stages is assigned (loaded) to one PE. In many cases, the number of program divisions corresponds to the number of usable PEs.

  In the multiprocessor for pipeline processing, when target data is input, data for a processing unit determined from, for example, the size of the free area in the local memory is loaded into the first PE1. When the processing at PE1 is completed, the processing result data is transferred to PE2 at the next stage. At the same time as the second stage processing is started in PE2, new data is loaded into PE1 in the forefront stage. Then, the first data is transferred to PE3 which is the final stage of the pipeline, and the processing becomes a steady state. Thereafter, in all of PE1 to PE3, data is processed at the same time. As a result, desired required performance is satisfied.

Advantages of pipeline processing include the fact that PEs that access external resources such as memory and I / O are limited, so that resource contention is unlikely to occur, and processing time is easy to estimate, making real-time design easy. In addition, there is no need to synchronize the output stage because the processing order of the data is not reversed, and there is no problem even with data that cannot be divided in advance because the data is always sequentially processed.
Japanese Patent No. 3889726

  However, the pipeline processing described above has the following problems. The first problem is that data must be transferred between PEs corresponding to the number of pipeline stages. Data transfer is often performed by DMA (direct memory access). However, when there is a large amount of data to be transferred or when it is desired to increase the number of pipeline stages, DMA overhead may affect the entire system. In particular, in the case of hardware sharing a transfer bus, when the bus usage rate increases, it becomes difficult to estimate the waiting time until the bus can be used. As a result, real-time performance may not be realized.

  The second problem is that if there is even one stage with heavy processing, that stage becomes a bottleneck and the required performance of the entire system cannot be achieved. For example, as shown in FIG. 17, it is assumed that the processing performance of the entire software takes 14 ms per unit data on the assumption that the required performance of 5 ms per unit data is required. Therefore, it is assumed that the application designer divides the program into three stages and executes each stage with PE1 to PE3. Here, since PE1 to PE3 require processing times of 4 ms, 6 ms, and 4 ms, respectively, the PE2 does not satisfy the required performance. In short, even if PE1 and PE3 satisfy the required performance, if the PE2 does not satisfy the required performance, the system as a whole cannot achieve the required performance. The same applies when there is a margin in the number of PEs.

  Therefore, the application designer further divides the program so as to realize the desired required performance, and performs the work of assigning to the remaining PE. If the number of PEs is not sufficient, the application designer performs a review of program division.

  However, generally, the work of dividing a program is very labor intensive. When the work of dividing the program is performed, the application designer must accurately grasp the division point of the program. In addition, it is necessary to grasp the processing performance at each stage so that a bottleneck does not occur when divided.

  In addition, functional modules that cannot be divided in principle or practically become bottlenecks. This problem becomes more apparent as the number of stages increases to improve performance.

  Such a problem is recognized as a potential drawback of pipeline processing. On the other hand, for example, the scheduler recognizes the execution time of the program and the input / output relationship, and provides a framework for the application designer that can achieve the desired time by periodically scheduling the processing contents into a pipeline. There is also a method to provide (for example, see Patent Document 1).

  The present invention has been made in view of the above circumstances, and a pipeline processing apparatus and a pipeline processing method capable of reducing the total amount of data transfer between processor elements while retaining the characteristics of pipeline processing suitable for real-time requirements. And it aims at providing a pipeline control program.

The present invention takes the following means in order to solve the above problems.
According to a first aspect of the present invention, there is provided a local storage unit for storing an execution code and the target data when a program for pipeline processing of target data is divided into a plurality of stages, a path information storage unit for storing path information, A pipeline processing apparatus having a plurality of processor elements, wherein one processor element of the plurality of processor elements transmits each execution code of a divided stage when the application is initialized. Means for individually allocating to the local storage means, and path information writing means for determining the order of use of the processor elements and writing the path information according to the order of use in the path information storage means of the processor elements. provided, each of the plurality of processors elements, data processing for processing the target data by the execution code If the detection means detects that the execution code has finished processing the unit data amount of the target data, and the detection means detects that the execution code has finished processing the unit data amount, A pipeline processing apparatus comprising execution code transfer means for transferring the execution code to another processor element according to the path information.

  According to a first aspect of the present invention, at the time of initialization of an application, means for individually allocating each execution code of the divided stage to local storage means of each processor element, and determining the use order of each processor element, Path information writing means for writing the path information in accordance with the path information storage means of each processor element. When it is detected in each processor element that the processing of the unit data amount is completed by the execution code, the path information is Since the execution code is transferred to other processor elements, the bus usage rate can be reduced compared to transferring the target data, and the characteristics of pipeline processing suitable for real-time requirements can be maintained, and A pipeline processing apparatus capable of reducing the total amount of data transfer can be provided.

According to a second aspect of the present invention, there is provided local storage means for storing an execution code and the target data when a program for subjecting target data to pipeline processing is divided into a plurality of stages, and path information storage means for storing path information. A pipeline processing apparatus comprising a plurality of processor elements having status information storage means for storing status information corresponding to each stage, wherein one of the plurality of processor elements is an application Means for allocating the execution code of the first stage of the application program divided into a plurality of stages to the local storage means of one processor element at the time of initialization, and each of the plurality of processor elements stores the target data Data processing means for processing by the execution code and the local memory Means for setting the status information as empty, and means for sending a transfer request for the execution code to another processor element when the processing by the data processing means is completed. And when the status information is set to an empty state when the execution code transfer request is received from another processor element, a means for sending a permission response to the other processor element, and sending the transfer request Path information writing means for writing, in the path information storage means, path information having the permission response source processor element as the next transfer destination when a permission response is received from another processor element in response to a transfer request from the performing means And a means for transferring the execution code to another processor element according to the path information written by the path information writing means. It is a line processing equipment.

  In the second invention, when each processor element receives an execution code transfer request from another processor element, if the status information is set to an empty state, it sends a permission response and responds to the transfer request. If the authorization response is received from another processor element, the authorization response source processor element is set as the next transfer destination, and the execution code is transferred to the other processor element according to the path information. Thus, it is possible to provide a pipeline processing apparatus that can reduce the bus usage rate and reduce the total amount of data transfer between processor elements while retaining the characteristics of pipeline processing suitable for real-time requests.

  According to the present invention, it is possible to reduce the total amount of data transfer between processor elements and reduce the burden of application development while retaining the characteristics of pipeline processing suitable for real-time requirements.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present invention, the “application” includes not only a program but also middleware, a device driver, and the like.
<First Embodiment>
FIG. 1 is a schematic diagram showing the configuration of a pipeline processing apparatus 10 according to the first embodiment of the present invention. The pipeline processing apparatus 10 includes a plurality of processor elements PE1 to PE8, a shared memory 11, a bus 12, and input / output ports (I / O) 13 and 14. Note that the number of processor elements shown in FIG. 1 is merely an example, and the present invention is not limited to this.

The shared memory 11 is a storage device that stores a “scheduler” program. The scheduler has a function of dividing an application program into a plurality of stages at the time of initializing the application and individually assigning execution codes corresponding to the divided stages to the local memories 21 of the processor elements PE1 to PE8. Yes. Further, the scheduler has a function of determining the use order of the processor elements PE1 to PE8 and setting “path information” according to the use order in the pipeline control program of the processor elements PE1 to PE8.
Although the scheduler is stored in the shared memory 11 here, the present invention is not limited to this, and a configuration in which the scheduler is stored in the local memory 21 of the processor element may be used.

  As shown in FIG. 2, each of the processor elements PE <b> 1 to PE <b> 8 includes a local memory 21, an arithmetic unit 22, and a DMAC (direct memory access controller) 23.

  The local memory 21 is a storage device provided individually for each of the processor elements PE1 to PE8, and stores “execution code” for subjecting target data to pipeline processing and “target data”. The local memory 21 also stores a “pipeline control program”. The pipeline control program holds, as management information, path information and “status information” indicating the state of the stage buffer in which the execution code of the stage is stored. Based on these information, each of the processor elements PE1 to PE8 is stored. Control. Details of the pipeline control program will be described later.

  As shown in FIG. 3, the local memory 21 has a stage buffer (stage buffer) for storing the execution code of each stage being duplicated as a stage buffer A and a stage buffer B. As a result, the DMAC 23 can execute the next stage process (FIG. 3B) while the execution code is being transferred (FIG. 3A). As a result, the time lag required for the DMA processing time can be eliminated. This configuration is often used in the conventional data pipeline system.

  The arithmetic unit 22 processes target data with an execution code. Various functions are exhibited by incorporating a pipeline control program into the arithmetic unit 22. Specifically, the arithmetic unit 22 has a detection function for detecting that the execution code has finished processing the unit data amount of the target data. In addition, the arithmetic unit 22 has a function of activating DMA in the DMAC 23 when the detection function detects that the execution code has finished processing the unit data amount.

  When the DMAC 23 is activated by the arithmetic unit 22, the DMAC 23 transfers the execution code to other processor elements according to the path information stored in the local memory 21.

  FIG. 4 is a schematic diagram showing a functional configuration of the pipeline control program according to the present embodiment. The pipeline control program holds management information and a pipeline control program execution code.

  The management information is information necessary for the pipeline control program to control the processor element PE. As management information, for example, path information, information indicating a data buffer state, and information (including status information) indicating a stage buffer state are held. The management information is stored in a cache memory or the like.

  The path information is data indicating how the pipelines are connected, and corresponds to, for example, the “transfer destination PE number” shown in FIG. In the present embodiment, it is assumed that the route information is given a fixed value by the scheduler when the application is initialized. However, the present invention is not limited to this, and it may be changed dynamically during application execution.

  Other management information is dynamically changed when the application is executed, and holds the current execution state. For example, the information indicating the state of the data buffer includes the final stage number, the address of the buffer that holds the input data, the address of the buffer that holds the output data, and the effective data size. Information indicating the state of the stage buffer includes status information and a stage number.

  The stage buffer is a storage area for holding the execution code of each stage in the local memory 21 and is managed by a stage number for identifying each stage and status information indicating the state of the stage buffer. As shown in FIG. 5, the stage buffer transitions in the order of “empty state (IDLE)”, “preparation state (STANDBY)”, “execution state (ACTIVE)”, and “transfer state (TRANSFER)”. Here, by changing the setting of the status information, the state of the stage buffer is changed, and the pipeline sequential processing is realized.

  Since “ACTIVE” is in the state “currently executing this execution code”, there is at most one stage buffer that is ACTIVE in one PE. “STANDBY” is a state in which the execution code already exists but is not yet the time to execute it. When the processing of the stage currently in the ACTIVE state is completed, the stage in the STANDBY state is changed to the ACTIVE state.

  When the pipeline control program execution code is incorporated into the arithmetic unit 22, the arithmetic unit 22 functions as follows. First, the arithmetic unit 22 recognizes whether or not the processing of the execution code held by the PE is the first stage in the entire processing. When the data to be processed by the execution code of the first stage arrives at the arithmetic unit 22, the execution code is executed. The arithmetic unit 22 activates the DMA when the processing of the unit data amount is completed. The arithmetic unit 22 erases the executed execution code. When the execution code is DMA-transferred, the next stage execution code arrives (or has arrived), so the arithmetic unit 22 executes the next stage execution code. When the execution of the next stage is completed, the execution code is transferred according to the path information, and the execution code just executed is deleted. If this is repeated, the processing of the first stage has arrived when the processing of the final stage and the transfer of the execution code are completed.

  In addition, when there is a margin in the capacity of the local memory, there are cases where the execution code of all stages can be accommodated in the local memory of all PEs. In such a case, the transfer of the execution code entity can be omitted. The pipeline control program only needs to notify the preceding stage that the execution code for the next stage is ready (permission to execute the execution code for the next stage). For this reason, data transfer between PEs can be eliminated almost completely or not (only an interrupt or the like). Further, it is not necessary to delete the execution code for each processing unit. FIG. 6 is a diagram for explaining an initialization process in the pipeline processing apparatus 10. The initialization process in the pipeline processing apparatus 10 is executed by the scheduler, for example, at the start of an application. However, the subject that performs this initialization processing is not limited to the scheduler stored in the shared memory 11, but may be executed by a separate initialization program provided in each pipeline control program. In the following description, it is assumed that an application program for pipeline processing is divided into stages 1 to 3.

  First, an initialization command is sent to the scheduler at the start of an application. In response to this, the scheduler sets the route information of each PE and sends the corresponding route information to each PE (S1). Here, PE2, PE1, and PE3 are set as transfer destinations of PE3, PE2, and PE1, respectively.

  Subsequently, the scheduler sets the effective data buffer size of all PEs to 0 (S2). Then, the scheduler sets the status state of the duplicated second stage buffer B of all PEs to “IDLE” (S3).

  Next, the scheduler sets the final stage number of all PEs and the stage number of the first stage buffer A (S4). Here, the final stage number and the stage number of the stage buffer A are set to (3, 1), (1, 2), (2, 3) for PE3, PE2, and PE1, respectively.

  Subsequently, the scheduler loads the execution code of the stage corresponding to the first stage buffer A of each PE (S5). Here, stage 1, stage 2, and stage 3 are loaded to PE3, PE2, and PE1, respectively.

  Next, the scheduler sets the status state of the stage buffer A of all PEs to “STANDBY” (S6). Then, the scheduler sends “STANDBY notification” to all PEs (S7).

When the initialization process is performed in the above procedure, the pipeline processing apparatus 10 can execute the pipeline process.
After the initialization of the pipeline processing apparatus 10, STANDBY notification reception processing, stage end processing, and DMA completion notification reception processing are executed as needed in each PE.

  FIG. 7 is a diagram showing a procedure for receiving a STANDBY notification. When each PE receives the “STANDBY notification”, the status information of a certain stage buffer x is changed from “IDLE” to “STANDBY” (T1). If one of the stage buffers duplicated at the time of STANDBY notification is “ACTIVE”, the processing is continued (T2-Yes).

  On the other hand, if there is no stage buffer in the ACTIVE state, the next stage buffer is searched from the stage number and the final stage number (T2-No, T3).

  When the stage buffer is searched, the status information of the corresponding stage buffer is changed from “STANDBY” to “ACTIVE” (T4). When the status information is changed to ACTIVE, the pipeline control program performs processing for passing the first and last addresses of the buffer and the size of the buffer to the execution code of the corresponding stage (T5). Thereby, processing of the execution code of the corresponding stage is started.

  FIG. 8 is a diagram showing a procedure of stage end processing. In each PE, when an execution code completion notification is sent, the status information of the processed stage buffer x is changed from “ACTIVE” to “TRANSFER” (U1).

  The PE that has processed step U1 swaps the address of the input data buffer and the address of the output data buffer (U2). Then, the output size included in the execution code completion notification is set to an effective data size (U3). Also, the final stage number is updated (U4).

  Then, the PE searches the stage buffer (stage buff) of “idle state (IDLE)” from the transfer destination PE (U5). When an empty stage buffer is searched, the PE starts DMA transfer of the execution code to the transfer destination PE (U6-Yes, U7). Further, when the PE starts the DMA transfer, if the STANDBY notification described later is already received from another processor element, the PE searches the stage buffer of the next stage from the stage number and the final stage number (U8-Yes, U9).

  Then, when the stage buffer of the next stage is searched, the PE changes the status information of the corresponding stage buffer from “STANDBY” to “ACTIVE” (U10).

  Thereafter, the PE starts processing the execution code of the corresponding stage (U11). Specifically, the process is executed by passing the first and last addresses of the data buffer and the size of the buffer to the execution code.

  FIG. 9 is a diagram showing a procedure of DMA completion processing. In each PE, when the DMA transfer of the execution code is completed, a “STANDBY notification” is transmitted to the transfer destination PE (V1). The PE that has transmitted the STANDBY notification changes the status information of the stage buffer from “TRANSFER” to “IDLE”. As a result, the execution code is invalidated (V2).

  In the conventional pipeline processing method, as shown in FIG. 10A, the execution code is fixed to each processor element, and the target data is sequentially transferred from the left to the right of the page. On the other hand, in the method of this embodiment, as shown in FIG. 10B, the target data is fixed to each processor element, and the execution code is sequentially transferred in the reverse direction from right to left on the page.

  In other words, focusing on the stage, for example, when the execution code of stage 1 has a function of loading input data into the data buffer of the local memory 21, the execution code of stage 1 sends the next processor element PE3 after loading the target data. It moves and loads the next target data. Then, the execution code of the stage sequentially moves the processor elements P2, P1, P3... And repeats the above processing.

  Focusing on the data, first, the target data of the processing unit is loaded into the data buffer by the first stage 1, and the target data is passed to the output I / O or the like after the final stage 3 is completed. During this time, the target data continues to exist in the same processor element.

  When attention is paid to the processor element (PE), the following operation is performed. That is, the execution code arrives sequentially for one processing unit of the target data, and the data is processed. When the data processing is completed, the first stage 1 execution code and the target data are loaded into the data buffer. And the operation | movement which repeats this is performed.

  With the configuration described above, the following processing is performed in the pipeline processing apparatus 10 according to the present embodiment. That is, the scheduler individually allocates each execution code of the application program divided into a plurality of stages to the local memory 21 of each processor element PE1 to PE8 when initializing the application. Then, the scheduler determines the use order of the processor elements PE1 to PE8, and writes path information according to the use order to the local memory 21 of each processor element PE1 to PE8. During execution of the application, each of the processor elements PE1 to PE8 processes the target data with the execution code. When each processor element PE1 to PE8 detects that the execution code has finished processing the unit data amount of the target data, it transfers the execution code to other processor elements according to the path information.

  Therefore, in the pipeline processing apparatus 10 according to the present embodiment, the execution code is transferred instead of transferring the target data to other processor elements, so that the processor retains the characteristics of pipeline processing suitable for real-time processing. The total amount of data transfer between elements can be reduced.

  That is, when the total amount of execution code is smaller than the total amount of data, the total amount of transfer between PEs can be reduced by the difference, so that transfer overhead and bus contention can be reduced. As a result, the data processing time can be easily estimated, so that it is possible to save the application designer from having to divide a complicated and detailed program.

  When a small data piece generated by variable length code processing or the like remains, the data piece may be transferred to the preceding PE together with the execution code.

  Further, in the pipeline processing apparatus 10 according to the present embodiment, the input of the first stage data and the output of the last stage data may be implemented by an application, or may be implemented by a pipeline control program. It is not related to the essence of the present invention.

<Second Embodiment>
FIG. 11 is a schematic diagram showing the configuration of a pipeline processing apparatus 10S according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the part same as the already demonstrated part, and the overlapping description is abbreviate | omitted unless there is particular description. In the pipeline processing apparatus 10S according to the present embodiment, each processor element determines itself instead of the path information being determined by the scheduler.

  As shown in FIG. 12, the arithmetic unit 22S of each of the processor elements PE1 to PE8 incorporates a pipeline control program so that the data processing unit 31, the status information setting unit 32, the transfer request unit 33, the permission response unit 34, A path information writing unit 35 and an execution code transfer control unit 36 are provided.

  The data processing unit 31 processes target data with an execution code in each processor element. The status information setting unit 32 updates the status information of the stage buffer stored in the local memory 21S as needed. When the data processing unit 31 is not processing the target data, the status information setting unit 32 sets the status information to “free state (IDLE). ) ”.

  The transfer request unit 33 sends an execution code transfer request to another processor element when the processing by the data processing unit 31 is completed in each of the processor elements PE1 to PE8. The permission response unit 34 sends a permission response to the other processor element when the status information is set to “idle state (IDLE)” when the transfer request of the execution code is received from the other processor element. To do. When receiving a permission response from another processor element in response to the transfer request, the path information writing unit 35 writes path information with the processor element that is the permission response source as the next transfer destination in the local memory 21S. .

  The execution code transfer control unit 36 activates the DMAC 23 with DMA. Specifically, when execution of the execution code is completed in the data processing unit 31, the execution code transfer control unit 36 activates the DMA by sending an execution code completion notification to the DMAC 23. Here, the execution code transfer control unit 36 causes another processor element to DMA transfer the execution code according to the path information written by the path information writing unit 35.

  Next, the operation of the pipeline processing apparatus 10S according to the present embodiment will be described. First, when an application for processing target data is executed, initialization is performed, and an application program is divided into a plurality of stages by a scheduler or the like. Then, the execution code of the first stage is assigned to the local memory of one processor element PE1. Note that the status information is set to “IDLE” by the status information setting unit 42 when the processor elements PE1 to PE8 are not processing the target data.

  Subsequently, when the processing by the execution code is completed, the processor element PE1 sends a transfer request for the execution code to the other processor element PE2. The processor element PE2 that has received the transfer request sends a permission response to the processor element PE1 that is the transfer request source when the status information is set to the empty state.

  When the processor element PE1 receives a permission response from another processor element PE2 in response to the transfer request, the processor element PE1 sets path information with the processor element PE2 that is the permission response source as the next transfer destination. Then, the processor element PE1 transfers the execution code to the other processor element PE2 according to the set path information.

  As described above, in the pipeline processing apparatus 10S according to the present embodiment, when each processor element receives a permission response from another processor element in response to the transfer request, the processor element of the permission response source is Since the path information as the transfer destination is written in the local memory 21S and the execution code is transferred to other processor elements according to the path information, the bus usage rate can be suppressed as compared with the case of transferring the target data. The total amount of data transfer between processor elements can be reduced while retaining the pipeline processing characteristics suitable for the requirements.

<Third Embodiment>
The pipeline processing apparatus 10T according to the third embodiment of the present invention is a modification of the pipeline processing apparatus 10S according to the second embodiment, and dynamically determines the number of pipeline stages by duplicating the execution code. To do.

  The local memory 21T according to the present embodiment divides the state of each stage into sub-stages, and stores “sub-status information” indicating whether these sub-stages are in the head state or the continuation state together with the sub-stage number. That is, when the execution code is duplicated by the execution code duplication unit 40 described later, the ACTIVE state has two states: a head state indicating that it is the head of the copied execution code and a continuation state indicating that it is not the head. It will be distinguished by the state. Sub-status information is set corresponding to these two states.

  The arithmetic unit 22T according to the present embodiment further includes an execution code duplicating unit 40 as shown in FIG. The arithmetic unit 22T according to the present embodiment replaces the data processing unit 31, the transfer request unit 33, and the execution code transfer control unit 36 according to the second embodiment with a data processing unit 41, a transfer request unit 43, and an execution code transfer. A control unit 46 is provided.

  The execution code replication unit 40 generates a copy of the execution code when the processing by the execution code exceeds a preset request time. Detection of approaching the requested time is implemented by “timer interrupt”. Further, when the execution code is duplicated, the execution code duplication unit 40 sets the sub-status information of each stage corresponding to the duplication source execution code and the execution code obtained by duplication in association with the sub-stage number.

  In addition to the function of the data processing unit 31 according to the second embodiment, the data processing unit 41 resumes the processing of the target data from the stage state when the sub status information is set. In addition to the function of the transfer request unit 33 according to the second embodiment, the transfer request unit 43 sends a transfer request for an execution code copied to another processor element when the execution code replicating unit 40 copies the execution code. Send it out.

  Specifically, the transfer request unit 43 detects by a timer interrupt that processing by the execution code exceeds a preset request time. When a timer interrupt occurs, the transfer request unit 43 determines whether the sub status information is in the head state. When the sub status information is in the head state, the transfer request unit 43 determines whether the transfer destination PE is set as route information. If the transfer destination PE is not set, a free processor element (empty PE) is searched, and a transfer request is sent to the searched processor element.

  On the other hand, the transfer request unit 43 does not search for a free PE because the transfer destination PE should already be set as the path information when the sub status information is in the continuous state when the timer interrupt is notified. Further, since the copied execution code should already exist in the transfer destination PE, the execution code is not transferred. In this case, since it is not necessary to move the context of the processor element, an increase in the bus usage rate can be avoided.

  The execution code transfer control unit 46, in addition to the function of the execution code transfer control unit 36 according to the second embodiment, causes the copied execution code to be DMA-transferred to other processor elements based on the sub status information. The execution code transfer control unit 46 does not need to move the context in each processor element for the execution code in the continuation state. In such a case, the execution code transfer control unit 46 notifies only the substage number. As a result, an increase in processing time due to transferring the same execution code a plurality of times can be avoided. Further, the execution code transfer control unit 46 has a function of deleting the execution code when the processing of the target data is completed in the last substage. If the local memory 21T has a storage area that can accommodate the execution codes of all the stages, it is not necessary to transfer the execution codes, so only the sub status number is notified.

  Next, the operation of the pipeline processing apparatus 10T according to the present embodiment will be described with reference to FIG. As a premise, it is assumed that an application program for subjecting target data to pipeline processing is divided into three stages 1 to 3 and assigned to the processor elements PE1 to PE3, respectively (FIG. 14A).

  Under such a premise, when the processing of the processor element PE2 is not completed when the request time elapses and a timer interrupt occurs, the execution code is duplicated by the execution code duplication unit 40 in the processor element PE2. When the execution code is copied, the execution code transfer control unit 46 of the processor element PE2 activates the copied execution code by DMA. As a result, the same execution code is also stored in the processor element PE1 (FIG. 14B). In short, the execution code is duplicated and the number of PEs having the same execution code increases by one. When the execution code is copied, the execution code copying unit 40 sets the sub status information together with the sub stage number. Here, the head state is set to the execution code of the processor element PE1, and the continuation state is set to the execution code of the processor element PE2.

  Then, when such an operation is repeated until the time when all the processing of the first data unit is completed (the time when the pipeline processing is completed) (FIGS. 14C and 14D), the number of pipeline stages is determined, The route information is determined. In the example of FIG. 14, the state is determined in five stages.

  Thereafter, the target data is loaded into each processor element, and the execution code is sequentially executed. In this state, since all stages and sub-stages are completed within the required time in all the processor elements, the desired required performance can be achieved.

  FIG. 15 is a diagram showing a processing procedure when a timer interrupt occurs. In each PE, when the request time elapses and a timer interrupt occurs, if the sub-status information is in the leading state, the transfer destination PE does not have information on the current stage, so the execution code is transferred (W1). -Yes). When transferring the execution code, it is searched whether route information is set. If the route information is not set, a free PE is searched and set as a transfer destination PE (W2 to W4).

  When transferring execution codes to the transfer destination PE, each PE first searches the transfer destination PE for an empty stage buffer (W5). Each PE starts DMA transfer of an execution code to a transfer destination PE when a free stage buffer is searched (W6-Yes, W7). Then, when completing the DMA transfer, each PE changes the sub status information from the head state to the continuation state (W8).

  On the other hand, when the sub status information is in the continuation state in step W1, each PE does not transfer the execution code because there is an execution code copied to the transfer destination PE (W1-No).

  If the sub-status information is in the continuous state when the execution code completion notification is received, the execution of DMA is omitted for the same reason as the timer interrupt. The status information is only changed to “IDLE”.

  FIG. 16 is a diagram showing a procedure of DMA completion processing. In each PE, when the DMA transfer of the execution code is completed, a “STANDBY notification” is transmitted to the transfer destination PE (X1). Here, when the execution code copied to the PE that has transmitted the STANDBY notification does not exist, the processing has already been completed, and the status information is “TRANSFER”. Therefore, the status information is changed from “TRANSFER” to “IDLE” (X2-Yes, X3).

  On the other hand, when the PE that has transmitted the STANDBY notification has started DMA by a timer interrupt, the status information is not changed (X2-No). When the DMA is activated by a timer interrupt, the processing by the execution code is not completed, and the status information is maintained as “ACTIVE”.

  As described above, in the pipeline processing apparatus 10T according to the present embodiment, each processor element stores the sub-status information for classifying the state of the stage, and the request based on the execution code is set in advance. If the time is exceeded, the execution code processing is stopped and duplicated. If the execution code is duplicated, set the sub-status information indicating whether it is in the head or continuation state, transfer the duplicated execution code, and then Since the processing of the target data is resumed based on the sub status information, the processing in each processor element can be completed within the required time, and the desired required performance can be satisfied.

  For example, in the pipeline processing apparatus 10S according to the second embodiment, if 4 ms, 12 ms, and 4 ms are required for the processing of stages 1, 2, and 3, respectively, when a required performance of 5 ms per unit data amount is required, Stage 2 becomes a bottleneck and cannot satisfy the required performance. On the other hand, in the pipeline processing apparatus 10T according to the present embodiment, processing within 5 ms can be realized by processing the processing of stage 2 with three processor elements.

  Further, in the pipeline processing apparatus 10T according to the present embodiment, it is not necessary for the application designer to accurately grasp the processing time of each stage, so that the load on the application designer can be reduced. Specifically, the application designer only needs to divide into functional units such as data loading, decryption, compression / decompression, and data output. In addition, the application designer does not need to subdivide the execution code.

  The pipeline processing apparatus 10T according to the present embodiment is a pipeline process in which substages are sent in order as described above as an operation concept, but the execution code in the continuous state does not need to be moved and copied. Processing in the execution code becomes very simple.

  When focusing on one PE, even if the conceptual substage is changed due to the arrival of the required time, the content of the execution code itself is not changed. The data to be processed is not transferred while being stored in the local memory 21T. Accordingly, since the execution code and the data remain the same on the local memory 21T, the execution code can be paused or resumed at any timing. Furthermore, even when halfway data is being processed, it can be paused or resumed even when important information is held in a temporary variable or the like.

  In short, since an interrupt is just taken and the process returns, the execution code does not need to recognize it, and a pipeline operation can be performed with very high accuracy.

  Further, the pipeline processing apparatus 10T according to the present embodiment can perform transfer at any timing of application processing because the suspension and resumption for changing the substage are performed on the same PE. The application can be recognized as if, for example, a temporary timer interrupt has occurred and returned from there, so that the substage can be changed regardless of where the data to be processed and the execution code are being executed. Therefore, the time for actually processing one stage or sub-stage can be realized with very high accuracy (eg, timer interrupt accuracy) regardless of the contents of the application.

<Other variations>
Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine a component suitably in different embodiment.

  Note that the method described in the above embodiment is a program that can be executed by a computer, such as a magnetic disk (floppy (registered trademark) disk, hard disk, etc.), an optical disk (CD-ROM, DVD, etc.), a magneto-optical disk (MO). ), And can be distributed in a storage medium such as a semiconductor memory.

  In addition, as long as the storage medium can store a program and can be read by a computer, the storage format may be any form.

  In addition, an OS (operating system) operating on the computer based on an instruction of a program installed in the computer from the storage medium, MW (middleware) such as database management software, network software, and the like implement the above-described embodiment. A part of each process may be executed.

  Furthermore, the storage medium in the present invention is not limited to a medium independent of a computer, but also includes a storage medium in which a program transmitted via a LAN, the Internet, or the like is downloaded and stored or temporarily stored.

  Further, the number of storage media is not limited to one, and the case where the processing in the above embodiment is executed from a plurality of media is also included in the storage media in the present invention, and the media configuration may be any configuration.

  The computer according to the present invention executes each process in the above-described embodiment based on a program stored in a storage medium, and is a single device such as a personal computer or a system in which a plurality of devices are connected to a network. Any configuration may be used.

  In addition, the computer in the present invention is not limited to a personal computer, but includes an arithmetic processing device, a microcomputer, and the like included in an information processing device, and is a generic term for devices and devices that can realize the functions of the present invention by a program. .

It is a mimetic diagram showing the composition of pipeline processing device 10 concerning a 1st embodiment of the present invention. It is a schematic diagram which shows the structure of each processor element which concerns on the same embodiment. It is a schematic diagram which shows the concept of the local memory which concerns on the same embodiment. It is the schematic diagram which showed the function structure of the pipeline control program which concerns on the same embodiment. It is a schematic diagram which shows the state transition of the stage buffer which concerns on the same embodiment. It is a figure for demonstrating the initialization process in the pipeline processing apparatus 10 which concerns on the same embodiment. It is a figure which shows the procedure of the reception process of the STANDBY notification which concerns on the embodiment. It is a figure which shows the procedure of the completion | finish process of the stage which concerns on the same embodiment. It is a figure which shows the procedure of the DMA completion process which concerns on the embodiment. It is a figure for demonstrating the difference with the conventional pipeline process. It is a schematic diagram which shows the structure of the pipeline processing apparatus 10S which concerns on the 2nd Embodiment of this invention. It is a schematic diagram which shows the structure of each processor element which concerns on the same embodiment. It is a schematic diagram which shows the structure of each processor element which concerns on the 3rd Embodiment of this invention. It is a schematic diagram for demonstrating operation | movement of the pipeline processing apparatus 10T which concerns on the same embodiment. It is a figure which shows the procedure of a process when the timer interruption which concerns on the embodiment has arisen. It is a figure which shows the procedure of the DMA completion process which concerns on the embodiment. It is a schematic diagram for demonstrating general pipeline processing.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Pipeline processing apparatus, 11 ... Shared memory, 12 ... Bus, 13, 14 ... Input / output port, 21 ... Local memory, 22 ... Arithmetic unit, 23 ... DMAC, 31... Data processing unit, 32... Status information setting unit, 33... Transfer request unit, 34. Code transfer control unit, 40... Execution code duplication unit, 41... Data processing unit, 43... Transfer request unit, 46 ... execution code transfer control unit, PE1 to PE8.

Claims (6)

A plurality of processor elements having local storage means for storing an execution code and target data when a program for subjecting target data to pipeline processing is divided into a plurality of stages, and path information storage means for storing path information A pipeline processing apparatus comprising:
One processor element of the plurality of processor elements is:
Means for individually allocating each execution code of the divided stage to the local storage means of each processor element at the time of initialization of the application;
Path information writing means for determining the use order of the processor elements, and writing path information according to the use order in the path information storage means of the processor elements;
With
Each of the plurality of processor elements is
Data processing means for processing the target data with the execution code;
Detection means for detecting that the execution code has finished processing the unit data amount of the target data;
And an execution code transfer means for transferring the execution code to another processor element according to the path information when the detection means detects that the execution code has finished processing the unit data amount. Pipeline processing device. Corresponding to each stage, local storage means for storing the execution code and the target data when the program for pipeline processing of the target data is divided into a plurality of stages, path information storage means for storing path information, and A pipeline processing apparatus comprising a plurality of processor elements having status information storage means for storing status information
One processor element of the plurality of processor elements is:
Means for allocating the execution code of the first stage of the application program divided into a plurality of stages to the local storage means of one processor element at the time of initialization of the application;
Each of the plurality of processor elements is
Data processing means for processing the target data with the execution code;
When the execution code can be written in the local storage means, the means for setting the status information as an empty state;
Means for sending the execution code transfer request to another processor element when the processing by the data processing means is completed;
Means for sending an authorization response to the other processor element when the status information is set to an empty state when the execution code transfer request is received from the other processor element;
When a permission response is received from another processor element in response to a transfer request from the means for sending the transfer request, the path information with the processor element that is the permission response source as the next transfer destination is written in the path information storage means. Route information writing means;
A pipeline processing apparatus comprising: means for transferring the execution code to another processor element according to the path information written by the path information writing means. A plurality of processor elements having a local storage unit that stores an execution code and the target data when a program for pipeline processing of the target data is divided into a plurality of stages, and a path information storage unit that stores path information A pipeline processing method used in a pipeline processing apparatus comprising:
Individually assigning each execution code of the divided stage to the local storage means of each processor element when initializing the application;
A path information writing step of determining a use order of each processor element and writing path information according to the use order in a path information storage unit of each processor element;
In each processor element, a data processing step of processing the target data with the execution code;
A detection step of detecting that the execution code has finished processing the unit data amount of the target data;
An execution code transfer step of transferring the execution code to another processor element according to the path information when the detection step detects that the execution code has finished processing the unit data amount. Pipeline processing method. Corresponding to each stage, local storage means for storing the execution code and the target data when the program for pipeline processing of the target data is divided into a plurality of stages, path information storage means for storing path information, and A pipeline processing method used in a pipeline processing apparatus having a plurality of processor elements having status information storage means for storing status information
Dividing the program into a plurality of stages of execution code at the time of initialization of the application, and assigning the execution code of the first stage to the local storage means of one processor element;
In each processor element, a data processing step of processing target data with the execution code;
When the execution code can be written in the local storage means, the step of setting the status information as an empty state;
In each of the processor elements, when the processing by the data processing step is completed, a step of sending a transfer request for the execution code to another processor element;
In another processor element that has received the transfer request, if status information is set to an empty state, means for sending a permission response to the processor element that is the transfer request source,
A path information writing step of writing, in the path information storage means, path information having the permission response source processor element as the next transfer destination when receiving a permission response in response to the transfer request;
And a step of transferring the execution code to another processor element according to the path information written by the path information writing step. A pipeline processing program which is individually provided with storage means and is used in a pipeline processing apparatus having a plurality of processor elements for pipeline processing of target data, wherein one processor element of the plurality of processor elements The
Means for writing the execution code and the target data into the storage means when the program for pipeline processing is divided into a plurality of stages;
Means for writing path information in the storage means of each processor element according to a preset use order of each processor element at the time of initialization of the application;
Realized as
Each of the plurality of processor elements is
Data processing means for processing the target data with the execution code;
Detection means for detecting that the execution code has finished processing the unit data amount of the target data;
Pipeline processing for realizing execution code transfer means for transferring the execution code to another processor element according to the path information when the detection means detects that the execution code has finished processing the unit data amount program. A pipeline processing program used in a pipeline processing apparatus having a plurality of processor elements for individually processing storage data and subjecting target data to pipeline processing,
One processor element of the plurality of processor elements;
Means for writing the execution code and the target data into the storage means when the program for pipeline processing is divided into a plurality of stages;
Realized as
Each of the plurality of processor elements is
Data processing means for processing the target data with the execution code;
Means for setting the status information as empty when an execution code can be written in the storage means;
Means for sending the execution code transfer request to another processor element when the processing by the data processing means is completed;
Means for sending a permission response to the other processor element when the status information is set to an empty state when the execution code transfer request is received from the other processor element;
Means for writing, in the storage means, path information having the permission response source processor element as the next transfer destination when receiving a permission response from another processor element in response to the transfer request;
A pipeline processing program for realizing as means for transferring the execution code to another processor element according to the path information written in the storage means .

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