JP4584768B2 - Pixel defect correction device - Google Patents

Description

  The present invention relates to an apparatus for correcting pixel data corresponding to a defective pixel of an image sensor.

  A defective pixel is generally present in a solid-state imaging device. Such a tendency becomes remarkable especially in a small and high density image sensor. For defective pixels, pixel data is corrected by pixel defect correction processing, and pixel defect correction processing is performed using pixel data of normal pixels around the defective pixel.

  In the pixel defect correction process, it is first determined whether the image data being processed is of a defective pixel. When the image data corresponds to a defective pixel, correction (interpolation) processing is performed using surrounding pixel data. Whether or not the pixel corresponding to the image data is a defective pixel is determined with reference to a data table (defective pixel data table) in which position information of the defective pixel is registered in advance. In addition, since the pixel data used for correction needs to be normal pixel data, whether or not the pixel is a normal pixel by referring to the defective pixel data table even for a pixel that is a correction candidate. It is necessary to make a judgment.

  From the above, when the defective pixel data table is composed of one data table for all pixels, even when thinning is performed, for the pixel to be processed and the pixel to be corrected, Since it is necessary to search the defective pixel data table for all the pixels described above, much time is spent on the search process to determine the defective pixel and the correction candidate.

  For such a problem, a method of preparing a plurality of defective pixel data tables corresponding to the thinning mode has been proposed (Patent Document 1). In other words, since the data amount of the defective pixel data table is optimized for each thinning mode, it is not necessary to search for thinned pixels that do not need to be referred to, and the time required for the search process is greatly increased. Can be shortened.

In addition, a method has been proposed in which a circuit that performs correction processing for all pixels and a circuit that performs correction processing corresponding to each thinning mode are prepared separately, and these are appropriately selected according to the mode (patent). Reference 2).
Japanese Patent Laid-Open No. 9-247540 JP 2003-51990 A

  However, the methods of Patent Documents 1 and 2 have a problem that the memory capacity and the number of circuits increase as the number of thinning modes increases.

  An object of the present invention is to provide a pixel defect correction device that performs a defective pixel search process at a high speed without increasing a memory capacity.

  A pixel defect correction apparatus according to the present invention includes a defect correction calculation unit that corrects pixel data when input pixel data corresponds to a defective pixel, and m memories that cyclically sort and record all position information of defective pixels. A pixel position management unit that manages position information of m pixels including pixels corresponding to input pixel data, and m pieces of position information and m pieces of memory that are distributed and recorded in m pieces of position information and m memories, respectively. Compares the position information of defective pixels, and if the position information matches, outputs a match signal corresponding to the number, and only the match signal corresponding to the effective pixel of the match signals is defective. It is characterized by comprising a coincidence signal output control unit that outputs to the correction operation unit and an address management unit that manages the read addresses of the m memories corresponding to the number of coincidence signals.

  The pixel position management unit includes, for example, a counter that manages pixel position information for one pixel, and the position information of m pixels is managed by the value of this counter.

  The counter value is, for example, a two-dimensional coordinate value along the horizontal line and vertical line of the image sensor. The value of the counter is shifted by the shift amount of the corresponding pixel every time input pixel data is input. In addition, the pixel defect correction apparatus includes a thinning information management unit that holds and manages a shift amount necessary for management of position information in the pixel position management unit for each thinning mode.

  In addition, the pixel defect correction apparatus includes a thinning information management unit that holds and manages information on the coincidence signal corresponding to the effective pixel in the coincidence signal output control unit.

  Input pixel data is input in a predetermined order, and all position information of defective pixels is cyclically distributed to m memories according to the predetermined order, and the position information of m pixels corresponds to pixels that continue in the predetermined order. To do. At this time, the pixel defect correction apparatus includes m address counters that manage read addresses for each of the m memories, and cyclically corresponds to the number of matches corresponding to the order of the defective pixels according to the predetermined order. The number of the address counter is sequentially counted up.

  The position information of the m defective pixels read from the m memories corresponds to the first m pieces of position information in the predetermined order among the defective pixels whose matching is not confirmed in the matching information comparison unit.

  Further, m corresponds to the maximum unit of the thinning pattern, and when the total number of defective pixels is n, the m memories are set to a depth of n / m.

  The pixel defect correction apparatus according to the present invention is a pixel defect correction apparatus used in an image processing apparatus having a thinning pattern unit of m columns, and corrects defective pixels for input pixel data input according to a predetermined order. Defect correction calculation unit to be performed, m number of memories that circulate and record all position information of defective pixels according to a predetermined order, and m pixels continuous in a predetermined order including pixels corresponding to input pixel data Each time the input pixel data is newly input, the position information comparison unit that compares the position information of the m pixels and the position information of the m defective pixels according to a predetermined order in the m memories. Position information management unit for shifting the position information of m pixels including the corresponding pixels by a predetermined number of pixels in a predetermined order corresponding to the thinning pattern, and the position information of m defective pixels from the m memories The The address management unit that shifts the addresses to be read out by the number corresponding to the position information matched in the position information comparison unit along the predetermined order, and the position information match in the position information comparison unit occurs in the effective pixel. Only, it is characterized by having a coincidence signal output control unit for outputting a coincidence signal to the defect correction calculation unit.

  Still further, the pixel defect correction apparatus of the present invention circulates a defect correction calculation unit that corrects defective pixels for input pixel data input according to a predetermined order, and all position information of the defective pixels according to a predetermined order. M pieces of memory for sorting and recording, and comparing the position information of m consecutive pixels with m pieces of defective pixel position information recorded in the m memories, Defective pixels are detected from among the pixels, and the m defective pixel position information is the first m defective pixel position information according to a predetermined order corresponding to the undetected defective pixels, and the input pixel data The positional information of m pixels is shifted by the number of pixels shifted for each input, and the correction of the input pixel data is performed based on detection of defective pixels.

  As described above, it is possible to provide a pixel defect correction apparatus that performs a search process for defective pixels at high speed without increasing the memory capacity.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a block diagram schematically showing the overall configuration of an image processing system including a pixel defect correction apparatus according to an embodiment of the present invention.

  The image processing system may be anything as long as it is equipped with a pixel defect correction device. In the following, the digital camera 10 will be described as an example. In the digital camera 10, a subject image is formed on an image sensor (for example, CCD) 12 via a lens 11, and the image signal is input to an image processing device 13.

  The image processing device 13 is roughly divided into a pixel defect correction device 14 that performs pixel defect correction processing, a defect position information memory 15, and a circuit unit 16 that performs other conventionally known image processing. An image signal that has been subjected to pixel defect correction processing and other known image processing in the image processing device 13 is output to the user interface 17 and displayed as a still image or a moving image on a display device, for example. In FIG. 1, a configuration that is not directly related to the pixel defect correction process, such as a configuration related to driving of the image sensor 12, is omitted.

  In the defect position information memory 15, position information of defective pixels of the image sensor 12 is recorded as coordinate values, for example. The position information of the defective pixel is obtained in the inspection of the image sensor 12 performed in advance.

  FIG. 2 schematically shows the relationship between the arrangement of each pixel of the image sensor 12 and the coordinate value of each pixel. When the image sensor 12 is a color image sensor, for example, each pixel shown in FIG. 2 is an array in which only pixels corresponding to one color component (for example, only pixels corresponding to the R component) are extracted and arranged. .

  In the following description, only the pixel corresponding to one color component will be described, but the same applies to other color components (for example, G and B components). In the following description, the term “adjacent pixel” means “adjacent” in FIG. 2, and is not necessarily adjacent in the actual image sensor 12.

  As shown in FIG. 2, each pixel is arranged in a grid pattern, and the position of each pixel is a two-dimensional coordinate value (x, x, x) when the horizontal line direction corresponds to the X axis and the vertical line direction corresponds to the Y axis. y). For example, in FIG. 2, there are X pixels of the same color component in the horizontal line direction and Y pixels in the vertical line direction. In this embodiment, the reading operation from the image sensor 12 is (0, 0), (1, 0),..., (X, 0) by main scanning in the X-axis direction and sub-scanning in the Y-axis direction. 0), (0, 1),..., (X, 1), (0, 2),..., (X-1, Y), (X, Y). Are read in the order along the arrows in the figure.

  Next, the thinning pattern in the present embodiment will be described with reference to FIG. The thinning process is used for recording and reproducing moving images, monitoring an object using an electronic viewfinder (EVF), and recording a low-resolution still image. Therefore, a plurality of thinning patterns are generally prepared in accordance with the mode of use.

  The present invention can be applied to any thinning pattern, but in the present embodiment, a case where it is possible to deal with a thinning pattern in units of a maximum of four vertical lines will be described as an example. Note that, here, all pixel readout without thinning is also treated as one of the thinning patterns.

  As shown in FIG. 3, when four vertical lines are used as thinning pattern units (maximum units), a total of 15 thinning patterns A0 to A14 are possible. In FIG. 2, white pixels are read pixels (effective pixels), and gray pixels are thinned out pixels. That is, the pattern A0 is a case where thinning is not performed, and the patterns A1 to A4 are cases where one line is thinned every four vertical lines. The patterns A5 to A10 correspond to the case where two lines are thinned out for every four vertical lines, and the patterns A11 to A14 correspond to the case where three lines are thinned out for every four vertical lines.

  FIG. 4 is a diagram schematically showing a configuration of a defective pixel data table when four vertical lines are used as a thinning pattern unit. In the present embodiment in which four columns are used as units of thinning patterns, the defect position information memory 15 is composed of four memories (first memory to fourth memory) (see FIG. 5).

  When the total number of defective pixels is n, the first memory 151 to the fourth memory 154 are each set to a depth n / 4. Here, the depth n / 4 is a memory capacity for storing the number of two-dimensional coordinate values corresponding to the quotient when n is divisible by 4, and when n is not divisible by 4, the depth is quotient. This is a memory capacity for storing a two-dimensional coordinate value corresponding to the number obtained by adding 1 to. When there is a remainder, the first memory 151 to the fourth memory 154 are optimized with the memory capacity corresponding to the number obtained by adding 1 to the quotient and the remaining memory capacity corresponding to the quotient. It is also possible to do this.

  In the present embodiment, the position information of the defective pixels is obtained when the pixel data is read from the image sensor 12 in the order of reading, that is, when the main scan is performed in the X-axis direction and the sub-scan is performed in the Y-axis direction, as indicated by the arrows in FIG. The coordinate values (X1, Y1), (X2, Y2),... (Xn, Yn) are sequentially stored in the defect position information memory 15 in this order.

  Here, the coordinate value (Xi, Yi), which is the position information of the defective pixel, is cyclically transmitted to the first memory 151 to the fourth memory 154 in the order of the subscript i (i = 1, 2,..., N). Sorted. That is, (X1, Y1) is stored at the address M1_AD (1) of the first memory, and (X2, Y2) is stored at the address M2_AD (1) of the second memory. Further, (X3, Y3) is stored at the address M3_AD (1) of the third memory, and (X4, Y4) is stored at the address M4_AD (1) of the fourth memory. (X5, Y5) is stored again at the address M1_AD (2) of the first memory, and similarly, the coordinate values of the defective pixels are stored in each of the second memory 2 to the fourth memory. Similar processing is repeated until the last coordinate value (Xn, Yn) is stored.

  Therefore, when the number of memories is four as in the present embodiment, the coordinate value with the subscript i = 4k + 1 (k = 0, 1,...) Is in the first memory, and the coordinate value with i = 4k + 2 is In the second memory, the coordinate value i = 4k + 3 is stored in the third memory, and the coordinate value i = 4k + 4 is stored in the fourth memory.

  FIG. 5 is a block diagram schematically showing the configuration of the pixel defect correction apparatus 14 of the present embodiment. The configuration of the pixel defect correction apparatus 14 will be described with reference to FIG.

  The pixel defect correction device 14 mainly includes a pixel position monitoring unit 20, an address comparison unit 21, a coincidence signal output control unit 22, an address management unit 23, a thinning information management unit 24, and a defect correction calculation unit 25.

  The defect correction calculation unit 25 is a circuit that corrects pixel data of defective pixels using pixel data of adjacent normal pixels using a conventionally known method. That is, the image signal output from the image pickup device 12 is subjected to predetermined signal processing such as color separation processing, and then sequentially input to the defect correction calculation unit 25 as pixel data according to the sequence of FIG. When the input pixel data corresponds to that of the defective pixel, the defect correction calculation unit 25 corrects and outputs the pixel data using the pixel data of the adjacent normal pixels. Whether or not the input pixel data is a defective pixel is determined based on a signal from a coincidence signal output control unit 22 described later.

  The pixel position monitoring unit 20 is a circuit for monitoring and managing the position of the pixel corresponding to the input pixel data and compared in the address comparison unit 21, and includes an X-axis counter 201 and a Y-axis counter 202. The X-axis counter 201 and the Y-axis counter 202 correspond to the values of the X-axis component and the Y-axis component of the two-dimensional coordinates (x, y) shown in FIG.

  In the present embodiment, the coordinate values (x, y) held in the X-axis counter 201 and the Y-axis counter 202 are the first pixel of the pixel group (four pixels) currently being compared in the address comparison unit 21. Represents the X-axis coordinate value and the Y-axis coordinate value.

  Further, the pixel position monitoring unit 20 detects input of pixel data to the defect correction calculation unit 25 and updates each value of the X-axis counter 201 and the Y-axis counter 202. At this time, the shift amounts of the X-axis counter 201 and the Y-axis counter 202 are controlled based on the thinning information from the thinning information management unit 24 (described later).

  As shown in FIG. 5, the address comparison unit 21 includes a first comparison unit 211 to a fourth comparison unit 214 and a Y-axis comparison unit 215. The first comparison unit 211 to the fourth comparison unit 214 include the X-axis coordinate values of the four pixels to be compared and the X-coordinate values of the four defective pixels stored in the first memory 151 to the fourth memory 154. Is a circuit for comparing. Further, the Y-axis comparison unit 215 compares the Y-axis coordinate values of the four pixels to be compared with the Y-coordinate values of the four defective pixels stored in the first memory 151 to the fourth memory 154. Circuit.

  Here, the X-axis coordinate values of the four pixels to be compared are four consecutive coordinate values starting from the value of the X-axis counter 201. That is, if the value of the X-axis counter 201 is x, the X-axis coordinate values of the four pixels to be compared are “x”, “x + 1”, “x + 2”, and “x + 3”, respectively. Note that x + 1, x + 2, and x + 3 are obtained by adding the values 1, 2, and 3 to the value x in the adders 26 to 28. Note that the value of the X-axis counter 201 need not be the first coordinate value as long as the coordinate value of the pixel to be compared is specified and the coordinate value can be supplied to the address comparison unit 21. For example, a subtractor or a combination of a subtracter and an adder may be used.

  In the present embodiment, each of the first comparison unit 211 to the fourth comparison unit 214 and the Y-axis comparison unit 215 includes four comparators. For example, the value x of the X-axis counter 201 is input to the first comparison unit 211 and compared with four X-axis coordinate values stored in the first memory 151 to the fourth memory 154. Similarly, the values of x + 1, x + 2, and x + 3 obtained by adding 1, 2, and 3 to the value x of the X-axis counter 201 are input to the second comparison unit 212 to the fourth comparison unit 214, respectively. 151 to the four X-axis coordinate values stored in the fourth memory 154.

  In the present embodiment, the four pixels to be compared exist on the same horizontal line, and the Y-axis coordinate values of the four pixels are the same. Therefore, the Y-axis comparison unit 215 determines the value of the Y-axis counter 202. Only will be compared. That is, the value of the Y-axis counter 202 is input to the Y-axis comparison unit 215 and compared with the four Y-axis coordinate values stored in the first memory 151 to the fourth memory 154, respectively.

  From the first memory 151 to the fourth memory 154, four X-axis coordinate values respectively corresponding to four defective pixels are input to each of the first comparison unit 211 to the fourth comparison unit 214 via the data bus DB. Four Y-axis coordinate values are input to the Y-axis comparison unit 215. At this time, the X-axis coordinate value and the Y-axis coordinate value are read from the first memory 151 to the fourth memory 154 based on the read address values of the first address counter 155 to the fourth address counter 158, respectively. The values of the first address counter 155 to the fourth address counter 158 are managed by the address management unit 23.

  In each of the first comparison unit 211 to the fourth comparison unit 214 of the address comparison unit 21, the input X-axis coordinate value from the X-axis counter 201 is the X axis of the defective pixel from the first memory 151 to the fourth memory 154. A coincidence signal is output when it coincides with one of the coordinate values. The match signals output from each of the first comparison unit 211 to the fourth comparison unit 214 are input to the match signal output control unit 22 and the address management unit 23, respectively.

  Note that the output of the coincidence signal from the first comparison unit 211 to the fourth comparison unit 214 is controlled based on the comparison result in the Y-axis comparison unit 215. That is, in each of the first comparison unit 211 to the fourth comparison unit 214, the Y-axis coordinate value read from the first memory 151 to the fourth memory 154 is output from the memory that matches the value of the Y-axis counter 202. Only the comparator to which the X-axis coordinate value is input can output a coincidence signal.

That is, assuming that the values of the X-axis counter 201 and the Y-axis counter 202 of the pixel position monitoring unit 20 are x and y, respectively, (x, y) = (X _i , Y _i ), (x + 1, y) = (X _{i +1} , Y _{i + 1} ), (x + 2, y) = (X _{i + 2} , Y _{i + 2} ), or (x + 3, y) = (X _{i + 3} , Y _{i + 3} ) A signal is output from each of the comparison units 211 to 214.

  The coincidence signals output from the comparison units 211 to 214 are input to the coincidence signal output control unit 22 and the address management unit 23. The address management unit 23 includes a coincidence number counting unit 231 and a head memory monitoring unit 232, and the coincidence signal input to the address management unit 23 is counted by the coincidence number counting unit 231. The result counted in the coincidence number counting unit 231 is sent to the head memory monitoring unit 232.

  The head memory monitoring unit 232 manages the head memory, which will be described later, according to the number of coincidence signals, and the values of the first address counter 155 to the fourth address counter 158 of the defect position information memory 15 are based on the number of coincidence signals. Update. On the other hand, the coincidence signal output control unit 22 controls whether to output each coincidence signal output to the defect correction calculation unit 25 based on the thinning information from the thinning information management unit 24, as will be described later.

  The defect correction calculation unit 25 determines whether or not the pixel data input based on the coincidence signal output from the coincidence signal output control unit 22 corresponds to the defective pixel, and the input pixel data corresponds to the defective pixel. The pixel data is corrected (interpolated) based on the pixel data of normal pixels by using a conventionally known method (such as replacement with pixel data of normal pixels or pixel defect correction calculation using pixel data of normal pixels) ), Output corrected pixel data. If the input pixel data does not correspond to a defective pixel, the input pixel data is output as it is.

  Next, with reference to FIGS. 5 to 7, an outline of the operation of the defective pixel search process in the pixel defect correction device 14 and the defect position information memory 15 of the present embodiment will be described. FIG. 6 is a flowchart showing an outline of the defective pixel search process of the present embodiment, and FIG. 7 is a block diagram schematically showing the configuration of the coincidence signal output control unit 22.

  When one of the thinning modes (including the case without thinning) A0 to A14 shown in FIG. 3 is selected and a release button (not shown) of the camera is pressed, for example, the processing of FIG. 6 starts. Is done.

  In step S101, an initialization process is executed. For example, each control parameter of the thinning information management unit 24 is initialized according to the thinning mode, and the values of the X-axis counter 201 and the Y-axis counter 202 of the pixel position monitoring unit 20 are initialized to (0, 0). Further, on / off of the switch of the coincidence signal output control unit 22 is set according to the control parameter set in the thinning information management unit 24, and the first memory in the address management unit 23 and the first to first in the defect position information memory 15 are set. The values of the fourth address counters 155 to 158 are set to initial values.

  In step S <b> 102, pixel data of effective pixels is input from the image sensor 12 to the defect correction calculation unit 25 in accordance with the selected thinning mode. Here, an effective pixel is a pixel from which data is read out from the image sensor 12 (a pixel other than a pixel to be thinned out). In step S103, it is determined whether or not the effective pixel data input to the defect correction calculation unit 25 is the first input.

  If it is determined in step S103 that the input is the first pixel data, the process proceeds to step S105. If not, in step S104, the X-axis counter 201, Y of the pixel position monitoring unit 20 is processed. The value of the axis counter 202 is updated according to the value of each parameter set corresponding to the thinning mode of the thinning information management unit 24.

  In step S105, the switch of the coincidence signal output control unit 22 is updated based on the values of the X-axis and Y-axis counters 201 and 202. As shown in FIG. 7, the coincidence signal output control unit 22 is provided with four switches S <b> 1 to S <b> 4, and one terminal of each switch is connected to each of the first comparison unit 211 to the fourth comparison unit 214. Connected to each output terminal. The other terminal of each switch is connected to the defect correction calculation unit 25. Switching of the on / off states of the switches S1 to S4 is controlled by a control signal from the thinning information management unit 24, respectively.

  In step S <b> 106, in the address comparison unit 21, the values of the X-axis and Y-axis counters 201 and 202 of the pixel position monitoring unit 20 (and values obtained by adding +1 to +3 to the X-axis counter value) are stored in the first position of the defect position information memory 15. It is compared with the defective pixel position information stored at the addresses indicated by the first address counter 155 to the fourth address counter 158.

  If there is a match in any of the first to fourth comparison units 211 to 214 of the address comparison unit 21, a match signal is output from the comparator. That is, in step S107, if a coincidence signal is output, the process proceeds to step S108 assuming that defective pixels are included. If no coincidence signal is output from any comparator, the process proceeds to step S112.

  In step S108, the number of coincidence signals output from the address comparison unit 21 is counted in the coincidence number counting unit 231 of the address management unit 23. In step S109, the head memory monitoring unit 232 updates the head memory based on the count result of the coincidence number counting unit 231. In step S110, the values of the first to fourth address counters 155 to 158 of the defect position information memory 15 are updated based on the updated head memory.

  In step S111, when a coincidence signal is input to the defect correction computation unit 25 via the coincidence signal output control unit 22, a conventionally well-known defect correction computation process is performed on the pixel data, thereby correcting the pixel. Data is output from the defect correction calculation unit 25. On the other hand, when the coincidence signal is not input to the defect correction calculation unit 25, the input pixel data is output as it is. That is, when the coincidence signal is input from the coincidence signal output control unit 22 to the defect correction calculation unit 25, the input pixel data corresponds to the defective pixel, and when the coincidence signal is not input, it corresponds to the normal pixel. is doing. The output of the coincidence signal from the coincidence signal output control unit 22 is controlled based on the on / off states of the switches S1 to S4 in the coincidence signal output control unit 22.

  In step S112, it is determined whether or not the input corresponds to the last pixel data. If the input is not the last input, the processes in and after step S102 are repeated. On the other hand, when the pixel data input to the defect correction calculation unit 25 is the last input, this process ends.

  Note that steps S104 and S105, steps S108 to S110, and step S111 are actually performed in parallel, and the processing procedure of FIG. 6 is for convenience of explanation. Not too much.

  Next, with reference to FIG. 3 to FIG. 5 and FIG. 7, the operation of each unit in the defective pixel search process according to the present embodiment will be described in more detail with specific examples.

  For example, when the thinning mode A5 is set and the release switch is pressed, the pixel data of the pixel coordinates (0, 2) is first read from the image sensor 12 and input to the defect correction calculation unit 25. The

  At this time, the values of the X-axis counter 201 and the Y-axis counter 202 are initially set to (0, 0), and the values of the first address counter 155 to the fourth address counter 158 of the defect position information memory 15 are M1 respectively. -AD (1), M2-AD (1), M3-AD (1), M4-AD (1), and the top memory is initially set to M1-AD (1). In the coincidence signal output control unit 22, the switches S1 and S2 are turned off and the switches S3 and S4 are set to the on state corresponding to the thinning pattern.

  At this time, the address comparison unit 21 compares the first four pixels with pixel coordinates (0, 0), (1, 0), (2, 0), (3, 0), Four defective pixel position coordinates (X1, Y1) stored in each address M1-AD (1), M2-AD (1), M3-AD (1), M4-AD (1) of the fourth memory ( X2, Y2), (X3, Y3), (X4, Y4).

  That is, the first comparison unit 211 compares the value “0” of the X-axis counter 201 with each value of X1 to X4, and the second comparison unit 212 compares the value “1” corresponding to “X-axis counter value + 1”. And the values of X1 to X4 are compared. Similarly, in the third and fourth comparison units 213 and 214, the values “2” and “3” corresponding to “X-axis counter value +2” and “X-axis counter value +3” are compared with the values of X1 to X4, respectively. Is done. Further, the Y-axis comparison unit 215 compares the value “0” of the Y-axis counter 202 with each value of Y1 to Y4.

  Also, when the pixels (0, 0), (1, 0), (2, 0), (3, 0) are to be compared, the effective pixels are (2, 0), (3, 0). As for the switches S1 to S4 of the coincidence signal output control unit 22, only the switches S3 and S4 corresponding to the effective pixels (2, 0) and (3, 0) are turned on, and the switches S1 and S2 corresponding to the thinned pixels are , Is turned off.

  For example, when two pixels (1, 0) and (2, 0) among the eight pixels (0, 0) to (0, 7) are defective pixels, the address M1-AD (1) of the first memory 151 ), Coordinate values (1, 0) and (2, 0) are stored as (X1, Y1) and (X2, Y2) at the address M2-AD (1) of the second memory 152, respectively. Therefore, pixel coordinates (0,0), (1,0), (2,0), (3,0) and defective pixel position coordinates (X1, Y1), (X2, Y2), (X3, Y3), When (X4, Y4) are compared, the coincidence signal is output from the second comparison unit 212 and the third comparison unit 213.

  In the coincidence signal output control unit 22, since the switches S3 and S4 connected to the third and fourth comparison units 213 and 214 are in an on state, the coincidence signal output from the third comparison unit 213 is corrected for defects. Input to the calculation unit 25. Thereby, the defect correction calculation unit 25 performs correction processing on the pixel data of the input pixel (2, 0), and the pixel data corrected by any conventionally known method is the defect correction calculation unit 25. Is output from. If the pixel (3, 0) is not a defective pixel but a pixel (2, 0), the coincidence signal from the fourth comparison unit 214 is input to the defect correction calculation unit 25. Therefore, the defect correction calculation unit 25 is controlled to perform defect correction when the pixel data corresponding to the next pixel (3, 0) is next input.

  On the other hand, in the address management unit 23, the number of coincidence signals from the address comparison unit 21 is counted in the coincidence number counting unit 231. Now, since the coincidence signals are output from the second comparison unit 212 and the third comparison unit 213, the number of coincidence signals is “2”, and the head memory monitoring unit 232 sets the head memory as the head of “current”. Shifting from the memory M1-AD (1) by two memories, the head memory is changed to M3-AD (1).

  The head memory is updated according to the order of the defective pixel position coordinates sequentially stored in the first to fourth memories in accordance with the pixel arrangement in the image sensor 12. That is, the top memory is M1-AD (1), M2-AD storing (X1, Y1), (X2, Y2),..., (X5, Y5),. (1),..., M1-AD (2),..., M4-AD (n / 4).

  At this time, the address value M1-AD (1) of the first address counter 155 and the address value M2-AD (1) of the second address counter 156 are counted up, and M1-AD (2), M2-AD ( Updated to 2). That is, the defective pixel position coordinates stored in the first to fourth memories to be compared in the address comparing unit 21 are the four pixels after the first memory in the above order, and the movement of the first memory is the defect that has been searched. It plays a role of removing pixel position coordinates from search candidates.

  This completes the process when the first effective pixel (2, 0) in the thinning mode A5 is input to the defect correction calculation unit 25. Next, as shown in FIG. 3, the second effective pixel (3, 0) in the thinning mode A <b> 5 is input to the defect correction calculation unit 25. At this time, the value of the X-axis counter 201 of the pixel position monitoring unit 20 includes the pixel data pixel (first effective pixel) input immediately before and the pixel data pixel input this time (second effective pixel). Is incremented by the number of pixels shifted between (the number of pixels shifted between the previous input pixel data and the current input pixel data).

  That is, in this case, since the input pixel data is shifted by one pixel from the pixel (2, 0) to the pixel data corresponding to the pixel (3, 0), the value of the X-axis counter 201 is “0 + 1”, “1” is set, and the value (X, Y) of the pixel position monitoring unit 20 is (1, 0). Therefore, in the address comparison unit 21, the coordinate values (1, 0), (2, 0), (3, 0), (4, 0) of the four pixels and the current head memory M3-AD (1) and subsequent 4 The defective pixel position coordinates (X3, Y3), (X4, Y4), (X5, Y5), (X6, Y6) corresponding to the pixels are respectively compared.

  At this time, among the pixels (1, 0), (2, 0), (3, 0), and (4, 0) to be compared by the address comparison unit 21, the pixel corresponding to the effective pixel is ( 2, 0), (3, 0), the switches S1 to S4 of the coincidence signal output control unit 22 are turned on in the X coordinates of the effective pixels (2, 0), (3, 0). The switches S2 and S3 are connected to the second and third comparison units 212 and 213 that compare the values, and the switches S1 and S4 are turned off.

  Now, the position coordinates for four pixels selected as the comparison object from the defect position information memory 15 are (X3, Y3), (X4, Y4), (X5, Y5), (X6, Y6). , 0) to (0, 7), only the pixels (1, 0) and (2, 0) correspond to the defective pixels, and their coordinate values are (X1, Y1), (X2, Y2), the coincidence signal is not output in this comparison process. Therefore, the values of the top memory and the first to fourth address counters 155 to 158 are not updated, and the input pixel data corresponding to the pixel (3, 0) is also corrected in the defect correction calculation unit 25. It is output without any change.

  Next, pixel data of the third effective pixel (6, 0) is input to the defect correction calculation unit 25. At this time, the value of the X-axis counter 201 is incremented by the shift from the second effective pixel (3, 0) to the currently input effective pixel (6, 0), that is, by 3 pixels.

  That is, the value of the X-axis counter 201 is “1 + 3”, that is, “4”, and the value of (X, Y) of the pixel position monitoring unit 20 is (4, 0). Therefore, in the address comparison unit 21, the coordinate values (4, 0), (5, 0), (6, 0), (7, 0) of the four pixels and the current head memory M3-AD (1) and subsequent 4 The defective pixel position coordinates (X3, Y3), (X4, Y4), (X5, Y5), (X6, Y6) corresponding to the pixels are respectively compared, and the same processing is repeated thereafter.

  Note that the shift amount of the X-axis counter and the ON / OFF setting of the switches S1 to S4 of the coincidence signal output control unit 22 are different for each thinning mode, but these values are different for each thinning mode. It is stored as control parameters, and the processing described above is executed based on the values of these control parameters. In the example of the pattern A5, the control parameter is a repetition of 1, 3 as the shift amount in the horizontal direction, 1 for each horizontal line as the shift amount in the vertical direction, and the on / off of the switches (S1, S2, S3, S4). As the off setting, (off, off, on, on) and (off, on, on, off) are repeated.

  As is apparent from FIG. 2, when scanning in the X-axis direction is completed and the value of the X-axis counter 201 exceeds the maximum value X, the value of the Y-axis counter 202 is incremented by 1, and the X-axis counter 201 The value is reset to 0.

  As described above, according to the present embodiment, it is not necessary to prepare a data table in which position information of defective pixels is recorded for each thinning pattern, and non-overlapping defective pixel information corresponding to all pixels is stored as one data. Since it only has to be held as a table, the memory capacity can be saved greatly.

  In this embodiment, four columns are used as thinning pattern units. However, according to the present invention, m memories are provided correspondingly to thinning patterns using arbitrary m columns as units, and defective pixels are provided in the memory. By positioning and recording the position information in a cyclic manner, the position information of m defective pixels can be simultaneously compared. Further, since the counter of the pixel position monitoring unit is counted up (shifted) according to the thinning pattern, the number of searches can be reduced according to the thinning amount in the thinning mode in which thinning is performed, so that high-speed search processing is possible. Can be realized.

  Furthermore, any thinning pattern with a thinning pattern of m columns or less as a unit can be dealt with by simply controlling the shift amount of the counter of the pixel position monitoring unit corresponding to the thinning pattern. There is no need to provide a circuit or to prepare a complicated program. With a simple configuration, the memory capacity can be reduced, the search processing speed can be increased, and the cost can be reduced.

  In the present embodiment, each of the first to fourth comparison units includes four comparators, and each comparison unit compares the value output from each of the first to fourth memories. One comparator is provided in the first comparator, two comparators in the second comparator, three comparators in the third comparator, and four comparators in the fourth comparator. The coordinate values of the “first memory” to “first memory + 1” in the second comparison unit, the coordinate values of “first memory” to “first memory + 2” in the third comparison unit, and “ The coordinate values of “first memory” to “first memory + 3” may be compared.

  In this embodiment, two-dimensional coordinates corresponding to the pixel array of the image sensor are used as a method of representing the position of the pixel corresponding to the pixel data to be processed and the position of the defective pixel recorded in the memory. However, the position information representing the pixel position may be any information that can uniquely represent the pixel position, and may be, for example, one-dimensional coordinates.

It is a block diagram which shows the structure of the digital camera which is one Embodiment of this invention. It is a schematic diagram which shows the relationship between the pixel arrangement | sequence of an image pick-up element, the position coordinate of a pixel, and the reading order (scanning method) of pixel data. It is a schematic diagram which shows 15 thinning patterns in this embodiment. It is a schematic diagram of the defective pixel data table which shows the storage method of the defective pixel position information to the 1st-4th memory of a defective position information memory with the address of each memory. It is a block diagram which shows the structure of a pixel defect correction apparatus. It is a flowchart which shows the outline of the defective pixel search process of this embodiment. It is a block diagram which shows typically the structure of a coincidence signal output control part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 12 Image sensor 14 Pixel defect correction apparatus 15 Defect position information memory 20 Pixel position monitoring part 21 Address comparison part (position information comparison part)
22 coincidence signal output control unit 23 address management unit 24 thinning information management unit 25 defect correction calculation unit 151 to 154 first to fourth memories 155 to 158 first to fourth address counters 211 to 214 first to fourth comparison unit 231 Number of coincidence counting unit 232 First memory monitoring unit

Claims (13)

A defect correction calculation unit that corrects the pixel data when the input pixel data corresponds to a defective pixel;
M memories for cyclically sorting and recording all position information of the defective pixels;
A pixel position management unit that manages position information of m pixels including pixels corresponding to the input pixel data;
A comparison is made between the position information of the m pixels and the position information of the m defective pixels that are distributed and recorded in the m memories, and if the position information matches, the number is matched. A position information comparison unit that outputs a matching signal,
A coincidence signal output control unit that outputs only the coincidence signal corresponding to an effective pixel among the coincidence signals to the defect correction calculation unit;
A pixel defect correction apparatus comprising: an address management unit that manages read addresses of the m memories in correspondence with the number of the coincidence signals.   The said pixel position management part is provided with the counter which manages the pixel position information for 1 pixel, The position information of the said m pixels is managed by the value of the said counter. Pixel defect correction device.   The pixel defect correction device according to claim 2, wherein the value of the counter is a two-dimensional coordinate value along a horizontal line and a vertical line of the image sensor.   3. The pixel defect correction apparatus according to claim 2, wherein the value of the counter is shifted by the shift amount of the corresponding pixel every time the input pixel data is input.   The pixel defect correction apparatus according to claim 4, further comprising: a thinning information management unit that holds and manages the shift amount necessary for management of position information in the pixel position management unit for each thinning mode.   The pixel defect correction apparatus according to claim 1, further comprising: a thinning information management unit that holds and manages information on a coincidence signal corresponding to an effective pixel in the coincidence signal output control unit.   The input pixel data is input in a predetermined order, all the position information of the defective pixels is cyclically distributed to the m memories according to the predetermined order, and the position information of the m pixels is the predetermined order. The pixel defect correction apparatus according to claim 1, wherein the pixel defect correction apparatus corresponds to continuous pixels.   M address counters for managing the read addresses for each of the m memories, and a number of address counters corresponding to the number of coincidence corresponding to the order of the defective pixels according to the predetermined order. The pixel defect correction apparatus according to claim 7, wherein the values of are sequentially counted up.   The position information of the m defective pixels read from the m memories is the first m position information in the predetermined order among the defective pixels whose matching is not confirmed in the matching information comparison unit. The pixel defect correction device according to claim 7.   The pixel defect correction apparatus according to claim 1, wherein the m corresponds to a maximum unit of a thinning pattern.   2. The pixel defect correction device according to claim 1, wherein when the total number of defective pixels is n, the m memories are set to a depth of n / m. A pixel defect correction apparatus used in an image processing apparatus having thinning pattern units of m columns,
A defect correction calculation unit that corrects defective pixels for input pixel data input according to a predetermined order;
M number of memories that cyclically sort and record all position information of defective pixels according to the predetermined order;
Comparing position information of m pixels that are consecutive in the predetermined order including pixels corresponding to the input pixel data with position information of m defective pixels in the predetermined order of the m memories A position information comparison unit
Each time input pixel data is newly input, the position information of the m pixels including the pixel corresponding to the input pixel data is shifted by a predetermined number of pixels in the predetermined order corresponding to the thinning pattern. A location information management unit;
An address management unit that shifts the address for reading the position information of the m defective pixels from the m memories in the predetermined order by the number corresponding to the position information matched in the position information comparison unit;
A pixel defect correction apparatus comprising: a match signal output control unit that outputs a match signal to the defect correction calculation unit only when the position information match in the position information comparison unit occurs in an effective pixel. A defect correction calculation unit that corrects defective pixels for input pixel data input according to a predetermined order; and
M number of memories that cyclically sort and record all position information of defective pixels according to the predetermined order;
Comparing the positional information of m consecutive pixels with the consecutive m defective pixel position information recorded in the m memories, detecting defective pixels from the m pixels, The m defective pixel position information is the first m defective pixel position information according to the predetermined order corresponding to the undetected defective pixels, and the number of pixels shifted for each input of the input pixel data. The pixel defect correction apparatus, wherein positional information of the m pixels is shifted, and the correction of the input pixel data is performed based on detection of the defective pixel.

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