JP4584124B2 - Information processing apparatus, error processing method thereof, and control program - Google Patents

Description

  The present invention relates to an information processing apparatus, an error processing method thereof, and a control program, and more particularly, to a transaction from when a transaction issued from a processor or the like is accepted until a reply is returned by out-of-order processing. The present invention relates to an information processing apparatus to be managed, an error processing method thereof, and a control program.

  An information processing apparatus that manages a transaction from when a transaction issued by a processor or the like is received until a reply is returned is known.

  There are two methods for managing this transaction. One of them is a method of returning replies according to the transaction issue order, which is based on FIFO (first-in, first-out), and the transaction issue order and reply response order match (for example, Patent Document 1 and 2).

  The other is a method in which the transaction issue order and reply response order do not match, and this is the above-mentioned out-of-order processing.

  In the conventional transaction management, when a failure occurs in the data, the failure is recovered by using an error correction function such as ECC (error correcting code).

  However, when a failure occurs in the address control system, it is necessary to ensure coherency and prevent data corruption, so the operation cannot be continued and the system is down.

  On the other hand, even if it is possible to continue the operation by retrying, if there is a failure in a specific part of the buffer (hereinafter referred to as “fixed failure”), the failure of the retry causes the system to go down. You may be invited.

  Also, when processing out-of-order transactions, in general, a plurality of transactions are overlapped for higher performance. For this reason, a large number of buffers composed of hard macros and registers are used in the part that performs out-of-order processing.

  Therefore, if a failure occurs in one of these buffers, it will lead to a system failure. Therefore, when higher reliability is required, a measure for continuing the operation is required.

  By the way, the inventions described in Patent Documents 1 and 2 described above relate to an apparatus that issues a subsequent write transaction without waiting for the completion of the preceding write transaction for speeding up. When the preceding write transaction is retried, In order to protect the order guarantee of subsequent write transactions issued from the same source, all subsequent write transactions are retried.

  As another invention, all received transaction information is held in the buffer in the system control function until the processing is completed, and the stored transaction is reissued in the system control at the time of failure. A memory access control device that prevents system down is disclosed (for example, see Patent Document 3).

  As another invention, when an interrupt is received, if the transaction being processed can be retried, an apparatus that processes the interrupt first and then retry the transaction is disclosed (for example, a patent) Reference 4).

JP 2001-216259 A (paragraph 0008, FIG. 1) JP 2002-108836 A (paragraph 0008, FIG. 1) Japanese Laid-Open Patent Publication No. 01-140357 (page 3, upper left column, lines 8-14, FIG. 1) JP 2002-091939 A (paragraph 0014, FIG. 1)

  The inventions described in Patent Documents 1 and 2 described above relate to management of transactions in which the transaction issue order and the reply response order match, and are premised on the FIFO. For this reason, all subsequent write transactions are retried in order to protect the order guarantee of subsequent write transactions issued from the same source.

  On the other hand, the present invention relates to out-of-order transaction management. Unlike out-of-order transaction management, all of the subsequent transactions issued from the same source are not necessarily executed in order to guarantee the order. There is no need to retry. An object of the present invention is to reduce system down by retrying a transaction that has been processed at a location where a failure has occurred.

  Therefore, the inventions described in Patent Documents 1 and 2 are completely different from the present invention in all of the objects, configurations, and effects.

  In addition, the invention described in Patent Document 3 does not touch on coherency guarantees and countermeasures for buffer fixing failures, avoiding system down while ensuring coherency, and avoiding frequent retries due to buffer fixing failures. It is difficult to do.

  The invention described in Patent Document 4 described above is intended to speed up interrupt processing, and the object is completely different from the present invention.

  Accordingly, an object of the present invention is to enable continuous operation from transaction acceptance to reply return in a state where coherency guarantee is maintained when a failure occurs in transaction management, and is caused by a fixed buffer failure. An object of the present invention is to provide an information processing apparatus capable of reducing system down, an error processing method thereof, and a control program.

In order to solve the above-described problem, an information processing apparatus according to the present invention manages an transaction from when a transaction is received from an issuer until a reply is returned by an out-of-order process. The device detects failures related to transaction management in the buffer that stores received transactions by distinguishing between failures that can be retried and failures that cannot be retried, and when a retryable failure is detected, the transaction is retried and It includes a transaction control means for retrying other transactions having a coherency relationship.

The error processing method according to the present invention is an error processing method in an information processing apparatus that manages a transaction from when a transaction from an issuer is accepted until a reply is returned in an out-of-order process. Therefore, failure related to transaction management in the buffer that stores accepted transactions is detected by distinguishing between failures that can be retried and failures that cannot be retried. When a failure that can be retried is detected, the transaction is retried and the transaction and coherency It includes a transaction control step for retrying other related transactions.

Further, the control program according to the present invention controls an error processing method in an information processing apparatus that manages a transaction from when a transaction is received from an issuer to when a reply is returned in an out-of-order process. This is a program that detects failures related to transaction management in the buffer that stores accepted transactions in the computer by distinguishing between failures that can be retried and failures that cannot be retried, and when a retryable failure is detected , along with retrying the transaction, The present invention is characterized in that a transaction control process for retrying other transactions having a coherency relationship with the transaction is executed.

  According to the present invention, a failure in a buffer for storing an accepted transaction is detected, and other transactions that have a coherency relationship with the transaction are retried along with the retry of the transaction.

  According to the present invention, since the above configuration is included, when a failure occurs in transaction management, processing from acceptance of a transaction to return of a reply can be continuously performed in a state where coherency guarantee is maintained, and a buffer is stored. It is possible to reduce the system down due to the fixed failure.

  Specifically, it is composed of hard macros and registers in the system control unit that manages transactions from when a transaction issued by a processor or the like is received by the information processing apparatus to when a reply is returned by out-of-order processing. Even when a failure occurs in a specific part of the buffer, a continuous operation can be performed while coherency is maintained, and a degeneration operation is also performed, so that it is possible to reduce failures that immediately lead to system down. Therefore, it is useful as a countermeasure for intermittent hardware failures and fixed failures for specific entries in the buffer. In addition, since it is highly possible that a failure occurs in a place other than information such as a transaction identifier used when retrying to a processor or the like, it is highly possible that a continuous operation can be performed, so that it is possible to widen the scope of repair of a hardware failure.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a configuration diagram of an example of an information processing apparatus according to the present invention. Referring to the figure, an example of an information processing apparatus according to the present invention includes a system control unit 1, a plurality of processors 2 (2-1 to 2-n (n is a positive integer)), and a plurality of devices 3 ( 3-1 to 3 -m (m is a positive integer)), the first memory 4, and the second memory 5.

  The plurality of processors 2, the plurality of devices 3, the first memory 4 and the second memory 5 are connected to the system control unit 1.

  The system control unit 1 receives a transaction from the processor 2, the first memory 4, or the device 3 and performs control.

  In this embodiment, an example of processing from receiving a transaction issued by the processor 2 to returning a reply by out-of-order processing will be described. However, the processing is not limited to the transaction issued by the processor 2. The present invention can be applied to transactions issued by other devices such as the first memory 4 and the device 3.

  On the other hand, the system control unit 1 includes an out-of-order transaction control unit 11 (hereinafter referred to as a transaction control unit 11) and a subsequent retry unit 12, and the transaction control unit 11 includes a buffer 21, a fault A detection unit 22, a reply control unit 23, and a failure counter monitoring unit 24 are included.

  The failure detection unit 22 includes a retryable failure unit 31 and a nonretryable failure unit 32, and the reply control unit 23 includes a retry unit 41.

The retryable failure unit 31 of the failure detection unit 22 transmits and receives signals to and from the buffer 21, and transmits a signal based on the received signal to the subsequent retry unit 12 and the retry unit 41 in the reply control unit 23. The retry impossible unit 32 only receives a signal from the buffer 21 .

  Further, the signal from the buffer 21 is transmitted to the retry unit 41 of the reply control unit 23, and the signal from the reply control unit 23 is transmitted to the subsequent retry unit 12.

  Further, the buffer 21 and the fault counter monitoring unit 24 transmit and receive signals to and from each other.

  The failure detection unit 22 detects a failure in the system control unit 1 by distinguishing between a retryable failure unit 31 and a retry impossible failure unit 32. When a failure occurs, the retry unit 41 of the reply control unit 23 issues a retry of a transaction in which a failure has occurred or another transaction being processed to the processors 2-1 to 2-n.

  The subsequent retry unit 12 retries a transaction issued by the subsequent processor until the retry processing of the transaction in which the failure is detected is completed. The failure counter monitoring unit 24 monitors a failure counter 52 described later provided in the buffer 21.

  Next, an example of the configuration of the buffer 21 will be described. FIG. 2 is a diagram illustrating an example of the configuration of the buffer 21. Referring to the figure, the buffer 21 includes a plurality of entries (entries 0 to p (p is a positive integer)), and each entry includes a busy flag 50, information 51, and a failure counter 52. One entry corresponds to one transaction.

  The failure counter 52 stores the number of failure occurrences. The failure counter monitoring unit 24 monitors the number of failure occurrences indicated by the failure counter 52 in order to prevent system down due to frequent retries at the time of a fixed failure, and if the failure occurring within a certain period is within the allowable number of times, the failure counter If the fault exceeds the allowable range, the buffer 21 is degenerated by recognizing that the fault is a fixed fault.

  The transaction control unit 11 manages each transaction using a unique identifier from the time when the transaction issued by the processor 2 is received until the reply is returned by out-of-order processing.

  When a failure occurs in the buffer 21 composed of a plurality of entries in the transaction control unit 11, a function for relieving the failure while issuing a retry to the processor 2 and maintaining coherency is configured as follows.

  The function for issuing a retry to the processor when a failure occurs is composed of a retryable failure unit 31, a retry impossible failure unit 32, a retry unit 41, and a subsequent retry unit 12 of the failure detection unit 22. The fault counter 52 in the buffer 21 and the fault counter monitoring unit 24 are configured.

  The failure detection unit 22 of the buffer 21 is configured to divide a failure that can be retried to the processor 2 and continue the operation as a retryable failure unit 31, and as a failure unit 32 that cannot be retried when the continuous operation is impossible. To do.

  Examples of the failure detected by the retry impossible failure unit 32 include a transaction identifier issued by the processor 2. This is because in out-of-order processing, a reply is returned to the processor 2 using the identifier assigned when the processor 2 issues a transaction. If a failure has occurred in this identifier, the retry can be performed correctly. This is because there is not.

  The retry unit 41 is included in the reply control unit 23 that responds to the transaction received from the processor 2, and from the retryable failure unit 31 when the retryable failure unit 31 of the failure detection unit 22 detects a buffer 21 failure. This function receives a notification and issues a retry as a kind of reply to the processor 2 in the transaction of the entry in the buffer 21 in which a failure is detected.

  In addition, when the transaction in which the failure is detected is a transaction that needs to ensure coherency, the other transaction stored in the buffer 21 also has a function of issuing a retry to the processor 2 to maintain coherency.

  The subsequent retry unit 12 is a function for retrying a transaction newly issued from the processor 2 between the occurrence of a failure and the completion of retry processing of the transaction in which the failure is detected. Becomes effective when coherency guarantee is required, and is released when retry processing of a faulty transaction is completed.

  The subsequent retry unit 12 accepts a new transaction issued by the processor 2 if it is not subject to coherency guarantee and performs normal processing while the subsequent retry unit 12 is valid, and makes a retry if it is subject to coherency guarantee. Guarantees coherency.

  A failure counter 52 in the buffer 21 is provided for each entry, and is incremented by one every time a failure occurs. The failure counter monitoring unit 24 is a function for monitoring the failure counter 52 in the buffer 21 and sets the number of failure occurrences to be degenerated in advance, and degenerates the entry when the value of the failure counter 52 exceeds the set number of times.

  Also, the number of failures that can be allowed within a certain period is determined, and the failure counter 52 is reset when the value of the failure counter 52 is less than the set number. For the degeneration method, the buffer in-use flag 50 is set to “in use”, and invalid information that does not affect other controls such as all “0” is stored in the information 51 and invalidated. Since the entry is not newly selected by setting the in-use flag 50 to “in use”, a function equivalent to degeneration can be obtained without providing a special circuit.

  Next, the error processing method of the system control unit 1 will be described in detail. FIG. 3 is a flowchart illustrating an example of processing for a transaction in which a failure is detected.

  Referring to FIG. 3, the failure detection unit 22 detects a failure in the buffer 21 (S101). When a failure is detected by the retryable failure unit 31 (in the case of “YES” in S102), the failure counter 52 of the entry of the buffer 21 in which the failure has occurred without counting down the system is counted up (S103), and the retry unit In 41, information necessary for issuing a retry to the processor 2 or the like is read and a retry process is performed (S104).

  When the retry issuance to the processor 2 is completed, if the subsequent retry unit 12 is valid (“YES” in S105), the subsequent retry unit 12 is released (S106), and the process is terminated.

  Reuse of transaction entries for which retry processing has been completed is possible, such as when it can be used immediately, when it is used after being reset for a certain period, or when other buffers are reset and used. Varies depending on the application and location of failure.

  When the failure detection is not the retryable failure unit 31 (in the case of “NO” in S102), that is, when the failure detection unit 32 detects that the failure is not possible to retry, the system is brought down (S109).

  When a failure is detected by the retryable failure unit 31 (in the case of “YES” in S102), it is also checked whether or not the transaction of the entry of the buffer 21 in which the failure is detected is a coherency guarantee target transaction (S107).

  Unless it can be clearly determined that the transaction is not a coherency guarantee target transaction (in the case of “YES” in S107), it is regarded as a coherency guarantee target transaction and the subsequent retry unit 12 is enabled (S108).

  An example in which it cannot be clearly determined that the transaction is not subject to coherency guarantee is a case where a failure occurs in information for judging whether or not the transaction is subject to coherency guarantee.

If the subsequent retry unit 12 is not valid (in the case of “NO” in S105 ) , and if it can be clearly determined that the transaction is not a coherency guarantee target transaction (in the case of “NO” in S107), the process is terminated.

  FIG. 4 is a flowchart showing an example of processing for a transaction in the out-of-order processing other than the transaction in which a failure is detected when a failure is detected in the retryable failure unit 31 of the buffer 21.

  Referring to FIG. 4, when a failure is detected in the retryable failure unit 31 (S201), the retry unit 41 checks whether the transaction in which the failure is detected is a coherency guarantee target (S202).

  If the transaction in which the failure is detected is not subject to coherency guarantee (“NO” in S202), the out-of-order transaction being processed continues normal processing (S205).

  If the transaction in which the failure is detected is subject to coherency guarantee (in the case of “YES” in S202), it is checked whether the transaction is subject to coherency guarantee for all out-of-order transactions being processed ( If it is not a coherency guarantee target (in the case of “NO” in S203), normal processing is continued (S205), and if it is a coherency guarantee target (in the case of “YES” in S203), a retry process is performed. (S204).

  In the retry process (S204), a retry flag (not shown) is provided in the information 51 of each entry in the buffer 21, and when it is determined that the transaction requires the retry process when a failure occurs, the entry of the entry of that transaction is stored. The retry flag is made valid, and after the conditions necessary for performing the reply in the normal operation are met, the retry is replaced, and a retry is issued to the processor to end the processing. If data accompanies, the data is discarded and the process is terminated.

  FIG. 5 is a flowchart showing an example of processing when a new transaction is issued from the processor 2 during processing of a failure detected by the retryable failure unit 31. When a transaction is received from the processor 2 (S301), it is checked whether the subsequent retry unit 12 is valid (S302).

  If the subsequent retry unit 12 is invalid (in the case of “NO” in S302), the transaction is accepted and normal processing such as out-of-order processing is performed (S305).

  If the subsequent retry unit 12 is valid (“YES” in S302), it is checked whether or not the transaction received from the processor 2 is a coherency guarantee target (S303). If “YES”, retry processing is performed (S304), and if it is not a coherency guarantee target (“NO” in S303), the transaction is accepted and normal processing such as out-of-order processing is continued (S305). ).

  FIG. 6 is a flowchart showing an example of the monitoring operation of the failure counter 52 of the buffer 21. The failure counter monitoring unit 24 monitors the failure counter 52 in each entry of the buffer 21 at regular intervals (S401), and when the value of the failure counter 52 exceeds the number of degeneration thresholds (“YES” in S402). ), The corresponding entry in the buffer 21 is degenerated (S405).

  This is to prevent frequent retries due to fixed failures. Here, the degeneration threshold number is the number of failure occurrences at which degeneration starts, and can be set to any value according to the requirements to be used.

  As a degeneration / reduction method, the entry flag 51 of the entry in the buffer 21 is made valid so that the entry is not used anew, and at the same time, the information 51 of the entry is set so as not to affect other controls. Is degenerated by writing invalid data such as all “0”.

  When the failure counter 52 is equal to or smaller than the degeneration threshold number (in the case of “NO” in S402), the value of the resettable number set as the allowable number of failures within a certain period is compared with the value of the failure counter 52 (S403). ) If the number is less than the resettable number (“NO” in S403), the failure counter 52 is reset (S404). This is to prevent a decrease in buffer capacity due to buffer degeneration caused by intermittent failure.

  On the other hand, when the resettable number is exceeded (“YES” in S403), the failure counter 52 is not reset.

Next, the control program for the error processing method will be described in detail. Referring to FIG. 1, a first memory 4 and a second memory 5 are displayed. The first memory stores a control program or data for performing processing other than error processing according to the present invention. On the other hand, the second memory 5 stores a control program for performing error processing according to the present invention.
The control program for performing error processing according to the present invention is a program for causing a computer (system control unit 1 in FIG. 1 in this embodiment) to execute the processing shown in the flowcharts in FIGS.

  The system control unit 1 reads a control program for performing error processing from the second memory 5 and controls the transaction control unit 11 and the subsequent retry unit 12 according to the program. Since the details of the control have already been described, the description thereof will be omitted.

  In the present embodiment, the error processing method is realized by a control program. However, this can also be realized by a hardware sequence.

  In a system in which a processor has a retry function and processes an out-of-order transaction, it is effective when a large amount of buffers are used, and it can be used in an information processing apparatus that requires high reliability. Further, the present invention can be applied not only to a processor but also from an I / O card or a memory when a retry function is provided and out-of-order processing is performed.

It is a block diagram of an example of the information processing apparatus which concerns on this invention. 3 is a diagram illustrating an example of a configuration of a buffer 21. FIG. It is a flowchart which shows an example of the process about the transaction by which the failure was detected. 10 is a flowchart illustrating an example of processing for a transaction in the process of out-of-order processing other than the transaction in which a failure is detected when a failure is detected in the retryable failure unit 31 of the buffer 21. 10 is a flowchart illustrating an example of processing when a new transaction is issued from a processor 2 during processing of a failure detected by a retryable failure unit 31. 4 is a flowchart illustrating an example of a monitoring operation of a failure counter 52 of a buffer 21.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 System control part 2 Processor 3 Device 4 1st memory 5 2nd memory 11 Out-of-order transaction control part 12 Subsequent retry part 23 Reply control part 24 Fault counter monitoring part 31 Retryable fault part 32 Retry impossible fault part 41 Retry unit 50 In-use flag 51 Information 52 Fault counter

Claims (12)

An information processing apparatus that manages a transaction from when a transaction is received from an issuer until a reply is returned in an out-of-order process.
Detects failures related to transaction management in the buffer that stores accepted transactions by distinguishing between failures that can be retried and failures that cannot be retried. When a failure that can be retried is detected, there is a relationship between the transaction and coherency along with the retry of the transaction. An information processing apparatus comprising transaction control means for retrying another transaction. The information processing apparatus according to claim 1, wherein another transaction having a coherency relationship with the transaction related to the failure detection is a transaction being processed when the failure occurs. The information processing apparatus according to claim 1, wherein the other transaction having a coherency relationship with the transaction related to the failure detection is a newly issued transaction. The buffer is provided with a failure counter that records the number of failure occurrences of an entry corresponding to a transaction from the issuer, and the transaction control means degenerates the entry when the failure counter value exceeds a certain threshold. The information processing apparatus according to claim 1, wherein: An error processing method in an information processing apparatus that manages a transaction after receiving a transaction from an issuer until returning a reply in an out-of-order process,
Detects failures related to transaction management in the buffer that stores accepted transactions by distinguishing between failures that can be retried and failures that cannot be retried. When a failure that can be retried is detected, there is a relationship between the transaction and coherency along with the retry of the transaction. An error processing method comprising a transaction control step for retrying another transaction. 6. The error processing method according to claim 5, wherein another transaction having a coherency relationship with the transaction related to the failure detection is a transaction being processed when the failure occurs. 6. The error processing method according to claim 5, wherein the other transaction having a coherency relationship with the transaction related to the failure detection is a newly issued transaction. The buffer is provided with a failure counter that records the number of failure occurrences of an entry corresponding to a transaction from the issuer, and the transaction control means degenerates the entry when the failure counter value exceeds a certain threshold. The error processing method according to claim 5, wherein: A control program for an error processing method in an information processing apparatus that manages a transaction from when a transaction is received from an issuer until a reply is returned in an out-of-order process.
The computer detects failures related to transaction management in the buffer that stores accepted transactions by distinguishing between failures that can be retried and failures that cannot be retried. When a retryable failure is detected, the transaction is retried and the transaction and coherency A control program for executing transaction control processing that retries other related transactions. The control program according to claim 9, wherein the other transaction having a coherency relationship with the transaction related to the failure detection is a transaction being processed when the failure occurs. The control program according to claim 9, wherein another transaction having a coherency relationship with the transaction related to the failure detection is a newly issued transaction. The buffer is provided with a failure counter that records the number of failure occurrences of an entry corresponding to a transaction from the issuer, and the transaction control means degenerates the entry when the failure counter value exceeds a certain threshold. The control program according to claim 9, wherein the control program is performed.

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