JP4573401B2 - FG signal chattering prevention circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an FG signal chattering prevention circuit used for detecting and controlling the number of revolutions in a DC motor such as a fan motor.
[0002]
[Prior art]
In DC motors used for fan motors, etc., the rotational position of the motor is detected by a hall element, the hall output signal taken out from the hall element is compared by a comparator and converted into a rectangular waveform comparator output signal, and the comparator output The control signal for controlling the output transistor of the motor circuit is taken from the signal, a multi-phase control signal is formed, the output transistor of the motor circuit is sequentially turned ON / OFF, the drive current is supplied to the drive coil, and the motor is rotated. .
[0003]
The control signal is taken out from the comparator output signal obtained by comparing the hall output signal taken out from the hall element, and the FG signal is taken out, and the rotational speed of the motor is fed back by the FG signal to detect and control the rotational speed of the motor. To do.
[0004]
However, since the Hall output signal extracted from the Hall element includes noise, chattering occurs when the FG signal is switched from low level to high level or from high level to low level, and the motor speed cannot be controlled accurately. .
[0005]
The following measures are taken to prevent the chattering.
(1) Hysteresis was applied to the comparator.
{Circle around (2)} In terms of wiring, the wiring from the output of the Hall element to the comparator (motor driver IC) is arranged and wired so that other signal waveforms (especially noise of the reverse phase signal waveform) are difficult to travel.
(3) The adjacent pins of the comparator input are arranged in the same phase.
(4) Insert a capacitor between Hall element inputs to synchronize with the noise.
[0006]
[Problem to be Solved by the Invention]
However, the point at which the Hall element crosses zero is also a switching point of the motor coil drive phase, so even if the above measures are added, no sufficient measures can be taken. In particular, as the set and control board are downsized, they are easily affected by other wiring, and the zero cross point of the Hall element, that is, when the FG output signal switches from low level to high level or from high level to low level. Chattering is likely to occur.
[0007]
[Means for Solving the Problems]
In the present invention, a Hall output signal taken out from a Hall element that detects the rotational position of the motor is compared by a comparator to generate a rectangular-wave-shaped comparator output signal. A symmetric rectangular wave signal is converted, the symmetric rectangular wave signal is delayed by a first delay circuit and a second delay circuit, respectively, and the first delayed rectangular wave signal delayed by the first delay circuit is passed through a first compensation transistor. In addition to the input of the second delay circuit, the second delayed rectangular wave signal delayed by the second delay circuit is added to the input of the first delay circuit via the second compensation transistor to prevent chattering of the FG signal.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
In FIG. 1, reference numeral 1 denotes a hall element that detects the rotational position of the motor, and 2 denotes a comparator that compares the hall output signals H1 and H2 detected from the hall element 1, and takes out a rectangular wave comparator output signal K. Reference numeral 3 denotes a two-distribution circuit, which divides the comparator output signal compared by the comparator 2 into two to form symmetric rectangular wave signals S1 and S2 having high and low symmetry.
[0009]
4a and 4b are first and second delay circuits for delaying the two distributed symmetric rectangular wave signals S1 and S2, and 5a and 5b are the delayed first and second delayed rectangular wave signals T1 and T2, respectively. The first and second compensation transistors 6 for adding are output transistors for extracting the FG signal.
[0010]
Referring to FIG. 3, when the motor rotates, Hall output signals H1 and H2 are generated from the Hall element 1. The hall output signals H1 and H2 carry noise, and chattering occurs at the zero cross point.
[0011]
The hall output signals H1 and H2 are applied to the comparator 2 and compared with a reference voltage to generate a comparator output signal K. Since the hall output signals H1 and H2 include chattering, the hall output signals H1 and H2 are changed from low level to high level or high level. Chattering occurs when switching from low to low.
[0012]
The comparator output signal K is applied to the 2-distribution circuit 3 to be converted into high / low symmetrical symmetrical rectangular wave signals S1 and S2, and is applied to the first and second delay circuits 4a and 4b to be delayed. The first delayed rectangular waveform signal T1 delayed by the first delay circuit 4a is applied to the base of the first compensation transistor 5a, and the output signal from the collector of the first compensation transistor 5a is the counterpart second delay circuit 4b. Added to the input side.
[0013]
Similarly, the second delayed rectangular waveform signal T2 delayed by the second extension circuit 4b is applied to the base of the second compensation transistor 5b. The output signal taken out from the collector of the second compensation transistor 5b is applied to the input side of the counterpart first delay circuit 4a.
[0014]
By passing the delayed first and second delayed rectangular wave signals T1 and T2 to the input side of the other party, the high level state is maintained for a while when switching from the high level to the low level. When switching from the level to the high level, the low level state is maintained for a while, so that erroneous signals due to short-time noise are not accepted.
[0015]
The signal which does not accept the error signal, that is, the first and second delay circuits 4a and 4b from which chattering has been removed is taken out from the first delay circuit 4a of the first and second delayed rectangular wave signals. The delayed rectangular wave signal 4b is applied to the base of the output transistor 6, and the FG signal is extracted from the base of the output transistor 6 and used for detecting or controlling the rotational speed of the motor.
[0016]
FIG. 2 is a specific circuit diagram of the FG signal chattering prevention circuit of the present invention. The comparator 1 includes transistors Q1, Q2, Q3, Q4, and Q5 constituting a current mirror circuit, transistors Q6 and Q9 connected to the current mirror circuit, a base connected to the Hall element 1, and an emitter of each of the transistors Q6 and Q9. It comprises transistors Q10 and Q11 connected to the base, transistors Q14 and Q15 connected to the transistors Q6 and Q9, and transistors Q16, Q17 and Q18, and a constant current source 8 is connected to the transistor Q1.
[0017]
The two-distribution circuit 3 includes transistors Q19, Q21, Q22, and Q24 constituting each current mirror circuit, a transistor Q25 having a base connected to the collector of the transistor Q18, a dividing resistor R3 and R4 connected to the base, and an emitter having the transistor Q25 Transistor Q26 connected to the emitter, transistors Q27 and Q28 connected to the emitters of the connected transistors Q25 and Q26, and transistors Q30, Q31 and Q32 connected to the transistors Q21 and Q24, respectively.
[0018]
The first delay circuit 4a includes a transistor Q37 having a base connected to a resistor R6 and an output signal of the transistor Q21 of the two-distribution circuit 3 being applied via a transistor Q38.
[0019]
The second delay circuit 4b includes a transistor Q34 having a base connected to a resistor R7 and an output signal of the transistor Q24 of the two distribution circuit 3 being applied via a transistor Q55.
[0020]
The collector of the transistor Q34 of the second delay circuit 4b is connected to the base of the first compensation transistor 5a, and the collector of the first compensation transistor 5a is connected to the transistor Q38 of the first delay circuit 4a. The output signal of the circuit 4b is applied to the input side of the first delay circuit 4a, and the collector of the transistor Q37 of the first delay circuit 4a is connected to the base of the second compensation transistor 5b, and the second compensation transistor 5b. Is connected to the transistor Q55 of the second delay circuit 4b, and the output signal of the first delay circuit 4a is applied to the input side of the second delay circuit 4b.
[0021]
In the above circuit, the Hall output signals H1 and H2 generated by the Hall element 1 are applied to the transistors Q10 and Q11 of the comparator 2, and the signals of H1 and H2 are compared by the differential circuit. The comparison result is added to the transistor Q16, and a rectangular wave comparator output signal K is extracted from the transistor Q18.
[0022]
The extracted comparator output signal K is applied to the transistor Q25 of the 2-distributor circuit 3 and compared with the divided voltage B divided by the resistors R3 and R4 connected to the base of the transistor Q26.
[0023]
When the comparator output signal K applied to the base of the transistor Q25 is greater than the divided voltage B applied to the base of the transistor Q26, the transistor Q25 is turned on, current flows through the transistors Q19 and Q21, and a symmetric rectangular wave signal to the transistor Q38. The high level portion of S1 is extracted. When the comparator output signal K applied to the base of the transistor Q25 is smaller than the divided voltage B applied to the base of the transistor Q26, the transistor Q26 is turned on, current flows through the transistors Q22 and Q24, and the symmetrical rectangular wave signal S2 to the transistor Q55. The high level part of is taken out. Accordingly, the symmetric rectangular wave signal S1 and the symmetric rectangular wave signal S2 shown in FIG.
[0024]
The symmetrical rectangular wave signal S1 taken out from the collector of the transistor Q21 of the two distribution circuit 3 is applied to the base of the transistor Q38 of the first delay circuit 4a, and its output signal is applied to the transistor Q37. When the symmetric rectangular wave signal S1 is at a high level, the transistor Q38 is turned on, and accordingly the transistor Q37 is turned on. However, even if the symmetric rectangular wave signal S1 changes from a high level to a low level, the transistor Q37 continues to be turned on for several μ seconds. Therefore, the first delayed rectangular wave signal T1 delayed from the collector of the transistor Q37 is taken out.
[0025]
The symmetric rectangular wave signal S2 taken out from the collector of the transistor Q24 of the two distribution circuit 3 is applied to the base of the transistor Q55 of the delay circuit 4b, and the output signal is applied to the transistor Q34. When the symmetric rectangular wave signal S2 is at a high level, the transistor Q55 is turned on, and accordingly the transistor Q34 is turned on. However, the transistor Q34 continues to be turned on for several microseconds even when the symmetric rectangular wave signal S2 changes from a high level to a low level. Therefore, the second delayed rectangular wave signal T2 delayed from the collector of the transistor Q37 is taken out.
[0026]
The first delayed rectangular wave signal T1 extracted from the collector of the transistor Q37 is applied to the base of the second compensation transistor 5b, and the output signal extracted from the collector of the second compensation transistor 5b is the second delay circuit. 4b is added to the base of transistor Q55.
[0027]
Now, assume that the first delayed rectangular wave signal T1 changes from high level to low level, and the symmetric rectangular wave signal S2 applied to the transistor Q55 changes from low level to high level. Since the first delayed rectangular wave signal T1 is delayed when changing from the high level to the low level, the first delayed rectangular wave signal S2 applied to the transistor Q55 is applied to the base of the second compensating transistor 5b even when the symmetric rectangular wave signal S2 becomes the high level. Since the 1-delayed rectangular wave signal T1 remains at the high level, the symmetric rectangular wave signal S2 is suppressed. Therefore, even if chattering occurs during switching of the symmetric rectangular wave signal S2, it is suppressed.
[0028]
Similarly, the second delayed rectangular wave signal T2 extracted from the collector of the transistor Q34 is applied to the base of the first compensation transistor 5a, and the output signal extracted from the collector of the first compensation transistor 5a is the first compensation transistor 5a. Applied to the base of the transistor Q38 of the delay circuit 5a.
[0029]
The second delayed rectangular wave signal T2 changes from high level to low level, and the symmetric rectangular wave signal S1 applied to the transistor Q38 changes from low level to high level. Since the second delayed rectangular wave signal T2 is delayed when changing from the high level to the low level, the second delayed rectangular wave signal T1 applied to the base of the first compensating transistor 5a even when the symmetric rectangular wave signal S1 applied to the transistor Q38 becomes high level. Since the two-delayed rectangular wave signal T2 remains at the high level, the symmetric rectangular wave signal S1 is suppressed, and chattering that occurs when switching the symmetric rectangular wave signal S2 is suppressed.
[0030]
The first delayed rectangular wave signal T1 from the first delay circuit 4a in which the chattering is suppressed is applied to the output transistor 6, and the FG signal is extracted from the output transistor 6.
[0031]
Thus, the first delayed rectangular wave signal T1 extracted from the collector of the transistor Q37 is applied to the transistor Q34 of the second delay circuit 4b via the second compensation transistor 5b, and is extracted from the collector of the transistor Q34. The second delayed rectangular wave signal T2 is applied to the base of the transistor Q37 of the first delay circuit 4a via the first compensating transistor 5a, and when the delayed rectangular wave signal is switched from the high level to the low level, the high level is obtained. This state is held for a while, and the low level state is held for a while when switching from the low level to the high level.
[0032]
【The invention's effect】
The FG signal chattering prevention circuit according to the present invention forms a symmetric rectangular wave signal having a high / low symmetry with an output signal by a two-distribution circuit, and a delayed rectangular wave signal obtained by delaying the symmetric rectangular wave signal. When the signal switches from high level to low level, the high level state is held for a while, and when the signal switches from low level to high level, the low level state is held for a period of time. Chattering can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an FG signal chattering prevention circuit of the present invention;
FIG. 2 is a circuit diagram showing an FG signal chattering prevention circuit of the present invention;
FIG. 3 is a waveform diagram of each part in the FG signal chattering prevention circuit of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Hall element 2 Comparator 3 2 distribution circuit 4a 1st delay circuit 4b 2nd delay circuit 5a 1st compensation transistor 5b 2nd compensation transistor 6 Output transistor

Claims (4)

A hall element that detects the rotational position of the motor;
A comparator that compares the Hall output signal extracted from the Hall element and generates a rectangular-wave-shaped comparator output signal;
A two-distribution circuit for converting the comparator output signal into a symmetric rectangular wave signal of high / low symmetry;
A first delay circuit and a second delay circuit that respectively delay the symmetric rectangular wave signal;
A first compensation transistor for adding a first delayed rectangular wave signal delayed by the first delay circuit to an input of a second delay circuit;
Wherein Ri second name more second compensation Totaranjisuta adding a second delayed rectangular wave signal delayed by the delay circuit to the input of the first delay circuit,
The first and second compensation transistors may temporarily add first and second delayed rectangular wave signals having the same level as the symmetric rectangular wave signal when the symmetric rectangular wave signal is switched to high / low or low / high. An FG signal chattering prevention circuit.   The two-distribution circuit comprises transistors Q19, Q21, Q22, and Q24 that are connected to emitter-collector paths to form a current mirror circuit, respectively. Transistors Q25 and Q26 are connected to each other. In addition, a divided voltage divided by a resistor is applied to the base of the transistor Q26, the comparator output signal is compared with the divided voltage, and a first symmetric rectangular wave signal is extracted from the transistor Q21 of one current mirror circuit, 2. The FG signal chattering prevention circuit according to claim 1, wherein the second symmetric rectangular wave signal is extracted from a transistor Q <b> 24 of the other current mirror circuit. 3.   The first delay circuit includes a transistor Q38 to which a signal from the transistor Q21 of the two-distribution circuit is applied to the base, and a transistor Q37 to which a resistor is connected to the base and to which the output signal of the transistor Q38 is added to delay the signal. 2. The circuit according to claim 1, wherein the circuit comprises a transistor Q55 to which a signal from a transistor Q24 of a two-distribution circuit is applied to a base, and a transistor Q34 to which a resistor is connected to the base and an output signal of the transistor Q55 is added and delayed. The chattering prevention circuit of FG signal of description.   The first delayed rectangular wave signal delayed by the transistor Q37 of the first delay circuit is added to the base of the second compensation transistor 5b, and the output signal of the second compensation transistor 5b is added to the base of the transistor Q55 of the second delay circuit. In addition, the second delayed rectangular wave signal delayed by the transistor Q34 of the second delay circuit is added to the base of the first compensation transistor 5a, and the output signal of the first compensation transistor 5a is applied to the transistor of the first delay circuit. 4. The FG signal chattering prevention circuit according to claim 3, which is added to the base of Q38.

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