JP4568041B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a new MOS transistor having a tensile strain in a channel region and a manufacturing method thereof.

  In recent years, a distortion technique has attracted attention as a post-scaling technique. This technology utilizes the effect of increasing carrier mobility by reducing the effective mass of carriers and inter-band scattering by applying tensile strain to the Si in the channel part of MOS transistors and changing the band structure. It is.

Currently, the strained Si transistor that is most studied has a structure in which a strain relaxation SiGe layer is formed on a bulk Si substrate and a strained Si layer is formed thereon. [For example, Non-Patent Document 1]
In the above structure, it is necessary to form a SiGe layer, but there are some problems caused by this. First, defects such as dislocations are likely to occur in the SiGe layer, and these defects also affect the strained Si layer on the surface, leading to the generation of defect levels and surface roughness in the channel portion, resulting in carrier movement. Bring about a decrease in the degree. Usually, the SiGe layer is formed by epitaxial growth on a bulk Si substrate. In order to prevent defects such as dislocation caused by the difference in lattice constant between Si and Ge (about 4%), a Ge concentration gradient is first applied. A layer (buffer layer) is formed, and a strain relaxation SiGe layer is formed thereon. Defects can be reduced by adopting such a structure, but the defects cannot be completely removed, and development of a technique for further reducing defects by using CMP (Chemical Mechanical Polish) technology or the like is underway. Is in the situation.

  In addition, when forming the SiGe layer, there is a problem that it is difficult to increase the Ge concentration in the SiGe layer. If the Ge concentration in the SiGe layer can be increased, a large stress can be applied to the strained Si formed thereon, and an improvement in carrier mobility can be expected. However, when the Ge concentration increases, it becomes difficult to epitaxially grow a film having a good surface morphology, and eventually, a film having the expected carrier mobility cannot be obtained.

  Furthermore, there is a problem that Ge in the SiGe layer diffuses into the strained Si layer in the heat treatment step in device fabrication. When Ge reaches the interface between the channel and the gate insulating film in a heat treatment process such as initial oxidation or gate oxidation, it acts as a defect level and causes a decrease in mobility.

  In recent years, in a fine MOS transistor, attempts have been made to reduce parasitic capacitance and suppress a short channel effect by adopting a structure (SOI structure) in which an insulating layer is provided below a channel layer. However, even if the strained Si structure described so far is formed on an SOI substrate, the SiGe layer is too thick (for example,> 1 μm), so that the advantage of the SOI structure cannot be utilized. .

Furthermore, in order to overcome the above problems, there is a report that high performance is achieved by forming a strained Si layer on an SOI (Silicon On Insulator) substrate using a SiGe layer formation and bonding technique. is there. [For example, Non-Patent Document 2]
In this case, there are many problems such as poor in-plane uniformity and high cost.
K.Rim et al., Sympo.on VLSI Tech., "Characteristics and Device Design of Sub-100nm Strained Si N- and PMOSFETs" pp98-99,2002 K. Rim et al., IEEE IEDM, "Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs" pp49-52,2003

  An object of the present invention is to solve the above-mentioned various problems in the formation of a strained Si transistor according to the prior art using a SiGe layer, and to propose a strained Si transistor having a new structure.

A semiconductor device of the present invention is formed on a support substrate, an insulating layer formed on the support substrate, an SOI substrate including a semiconductor layer formed on the insulating layer, and the semiconductor layer of the SOI substrate. A gate insulating film; and a gate electrode formed on the gate insulating film. In addition, the semiconductor layer has a distorted region that protrudes in a direction away from the support substrate in both the gate length direction and the gate width direction of the gate electrode below the gate electrode.

  With such a configuration, by forming a MOS transistor by providing a gate on a semiconductor layer in a distorted shape region that is convex due to tensile stress applied with the formation of a cavity as necessary, this is achieved. A channel is formed in the semiconductor layer, that is, a semiconductor layer having strained Si, so that a transistor with high carrier mobility can be obtained.

  In the semiconductor device of the present invention, the distorted region is surrounded by an insulating layer by an appropriate method. With this configuration, the semiconductor device of the present invention can be formed with high integration.

  The semiconductor device of the present invention uses a new structure that does not use a SiGe layer, so that tensile stress is applied to the channel portion and the carrier mobility is increased without being affected by the adverse effects of using germanium. A MOS transistor can be formed.

By introducing a new structure different from the prior art, a strained Si transistor can be realized. Specific examples of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
[First embodiment]
1-5 is explanatory drawing of the manufacturing process of a 1st Example. In these, (a) to (o) and (c-2), (d-2) are cross-sectional views of each step, and (c-TOP), (e-TOP), (h-TOP), (J-TOP), (l-TOP), (n-TOP), and (o-TOP) are plan views viewed from directly above in the process steps of the corresponding cross-sectional views. AA ′ in the figure indicates the cross-sectional position of each cross-sectional view.

In FIG. 1A, a buried SiO ₂ layer (BOX layer, Buried Oxide layer) 11 and a single crystal silicon layer (SOI layer, Silicon On Insulator layer) 12 are formed on a single crystal silicon support substrate 10. 1 shows an SOI substrate. The thickness of the SOI layer 12 can be adjusted by thermal oxidation and a thermal oxide film removal process using a hydrofluoric acid solution. Here, for example, the BOX layer 11 is 200 nm and the SOI layer 12 is 60 nm. Note that here, the SOI layer 12 is made of p-type single crystal silicon in order to explain an example of a method for manufacturing an n-channel transistor. In the case of a p-channel transistor, the SOI layer 12 is n-type single crystal silicon.

  As shown in FIG. 1B, a resist process is used at a position that does not overlap with the element region (at least the distance between the element region and the portion closest to the element region does not exceed the limit of exposure alignment accuracy). The SOI layer 12 is etched by a process such as (Reactive Ion Etching), and a hole 20 whose depth reaches the surface of the BOX layer 11 is formed. Here, the opening diameter of the hole 20 is, for example, a square having a side of 500 nm.

  Next, as shown in FIG. 1C, the BOX layer 11 is isotropically etched from the hole 20 by, for example, etching for 30 minutes in a 5% hydrofluoric acid solution to form the cavity 30. FIG. 1 (c-TOP) shows a view as seen from directly above. As shown in the figure, the hole 20 is composed of four positions that do not overlap the element region, and a cavity 30 is formed in the range indicated by the broken line. Moreover, it shows that the support substrate 10 of single crystal silicon is observed inside the hole 20 as viewed from above.

  When the SOI layer 12 is relatively thin (for example, 20 nm or less), as shown in FIG. 1C-2, the SOI layer 12 immediately above the cavity 30 may warp slightly upward. In this case, a tensile stress is applied to the SOI layer 12, and if the stress (strain) has a desired magnitude, the processes after FIG. For example, when the thickness of the SOI layer 12 is 15 nm, a tensile stress (distortion rate of 0.8% or more) of 1 GPa or more is applied to the SOI layer 12 according to the result of Raman scattering measurement.

  Here, the cause of the SOI layer 12 warping upward is not clear. As a possibility, since the stress (compressive stress in the SOI layer 12) generated at the interface between the SOI substrate 12 and the BOX layer 11 used here is released by etching of the BOX layer 11, the SOI layer 12 is deformed ( It can be considered that the projection is convex.

Subsequently to FIG. 1C, a thermally oxidized SiO ₂ film 40 is formed by thermal oxidation as shown in FIG. Here, the thickness of the thermally oxidized SiO ₂ film 40 is set to 5 nm by dry oxidation at 800 ° C., for example.

At this time, as shown in FIG. 1D-2, the SOI layer 12 immediately above the cavity 30 may slightly warp upward. In this case, a tensile stress is applied to the SOI layer 12, and if the stress (strain) has a desired magnitude, the processes after FIG. Also, here, instead of dry oxidation, by performing heat treatment at 800 ° C. or higher in an inert gas such as N ₂ or Ar, the SOI layer 12 directly above the cavity 30 is deformed upward and tensile stress is applied. May be. Even in the case of using this process, the processes after FIG.

Here, when the heat treatment is performed in this way, it is unclear as to why the SOI layer 12 directly above the cavity 30 is warped slightly upward. Possibility is that deformation of the SOI layer 12 due to the difference in thermal expansion coefficient between Si and SiO ₂ (the expansion coefficient of Si is larger than that of SiO ₂ ), or rearrangement of Si atoms in the SOI layer 12 during heating. Deformation by etc. can be considered.

  Now, as shown in FIG. 2 (e) and FIG. 2 (e-TOP) following FIG. 1 (d), the cavity 30 is not completely filled by CVD (Chemical Vapor Deposition) (that is, FIG. A polysilicon film 50 is deposited (so that there is a gap 51 inside). FIG. 2E is a cross-sectional view taken along the line A-A ′ in FIG. 2E of the plan view (e-TOP). Here, for example, a film thickness of 90 to 120 nm is deposited. The reason why the deposited film thickness is wide is that there is a case in which the SOI layer 12 immediately above the cavity 30 is warped slightly upward as described above. Note that the material to be embedded here is not limited to polysilicon, but an oxidizable semiconductor such as Ge or an oxidizable metal such as Ti may be used.

Next, as shown in FIG. 2F, a thermally oxidized SiO ₂ film 60 is formed by thermal oxidation. At this time, the volume of the portion in which the polysilicon film 50 is embedded expands, and is deformed into a shape as shown in this figure, whereby a cavity 61 is formed. In this case, tensile stress is applied to the deformed SOI layer 12. Here, for example, by dry oxidation at 1000 ° C., the thickness of the thermally oxidized SiO ₂ film 60 is set to 100 nm. In this case, tensile stress (distortion rate 0.6% or more) of 750 MPa or more is applied to the SOI layer 12 from the result of the Raman scattering measurement. In addition, after this figure, illustration of the hole 20 part in sectional drawing is abbreviate | omitted. Similar results can be obtained when an oxidizable semiconductor or an oxidizable metal is used instead of the polysilicon film 50 in FIG.

Then, as shown in FIG. 2G, the thermally oxidized SiO ₂ film 60 and the polysilicon film 50 are removed by dry etching by RIE or the like. Thereafter, the upper thermally oxidized SiO ₂ film 40 is wet etched using a hydrofluoric acid solution.

Next, as shown in FIG. 2 (h) and FIG. 2 (h-TOP), a thermally oxidized SiO ₂ film 70 by thermal oxidation (initial oxidation) (here, 7 nm in thickness by dry oxidation at 800 ° C., for example) Is formed on the SOI layer 12, and a Si ₃ N ₄ film 71 (for example, 120 nm thick) is deposited on the entire surface including the SOI layer 12 and the inside of the cavity 61 by CVD. Next, as shown in FIG. 2 (h-TOP), the resist is patterned into an element isolation shape, and the Si ₃ N ₄ film 71 and the thermally oxidized SiO ₂ film 70 are subjected to RIE processing using the resist as a mask. Then, the resist is removed. The cavity 72 formed here is an inner region indicated by a broken line, and the polysilicon film 50 and the single crystal silicon support substrate 10 are observed from the hole 20.

Next, as shown in FIG. 3I, an element isolation SiO ₂ (LOCOS / LOCal Oxidation Of Silicon) film 80 is formed by thermal oxidation (field oxidation). Here, for example, the element isolation SiO ₂ film 80 having a thickness of 120 nm is formed by wet oxidation at 1000 ° C.

Next, as shown in FIGS. 3J and 3J-TOP, the Si ₃ N ₄ film 71 is wet-etched using a phosphoric acid solution. At this time, the cavity 90 appears again. Subsequently, the thermally oxidized SiO ₂ film 70 is wet-etched using a hydrofluoric acid solution.

Then, as shown in FIG. 3K, a gate oxide SiO ₂ film 100 is formed by thermal oxidation (gate oxidation). Here, for example, by dry oxidation at 800 ° C., the thickness of the gate oxide SiO ₂ film 100 is set to 3 nm. As the gate insulating film, a high-k film such as HfO ₂ may be used instead of the oxide SiO ₂ film.

  Next, as shown in FIGS. 4 (l) and 4 (l-TOP), after depositing a polysilicon film 110 on the entire surface by CVD, a resist is patterned into a gate electrode shape, and the polysilicon film is used as a mask. 111 is processed by RIE to form a gate electrode 110, and then the resist is removed. Here, for example, the thickness of the polysilicon film 111 is 100 nm and the gate length is 50 nm. Instead of polysilicon for the gate electrode. Polysilicon, germanium, or the like may be used.

Next, as shown in FIG. 4M, ion implantation is performed to form the extension implantation layer 120. Here, for example, the implanted ions are As ⁺ . In the case of a p-channel transistor, the implanted ion is B ⁺ .

Next, as shown in FIG. 4 (n) and FIG. 4 (n-TOP), after depositing the SiO ₂ film 130 on the entire surface by CVD, the SiO ₂ sidewall 130 is formed on the sidewall of the gate electrode 110 by RIE or the like. To do. Here, for example, the thickness of the SiO ₂ film 130 is 130 nm.

Then, as shown in FIG. 5 (o) and FIG. 5 (o-TOP), ion implantation is performed to form a source / drain implanted layer 140. Here, for example, the implanted ions are As ⁺ . In the case of a p-channel transistor, the implanted ion is B ⁺ .

  The source / drain electrodes may be metal silicided or have an elevated structure. Further, the gate electrode may be silicided.

  FIG. 6 shows a schematic bird's-eye view of the transistor formed according to the first embodiment. Compared with the conventional type shown in FIG. 7, it can be seen that the channel portion is deformed so as to protrude upward, and tensile strain is applied to the channel portion. In this embodiment, the carrier mobility is 1.6 times higher than that of the conventional type.

In this embodiment, there is a thin SiO ₂ layer (thermally oxidized SiO ₂ film 40) below the channel layer (SOI layer 12), but a polysilicon film 50 remains under the SiO ₂ layer (completely SOI). It's hard to say structure. If you want to realize the SOI structure, a thermal oxidation process FIG. 2 (f), the a method such thermally oxidizing the polysilicon until the thermally oxidized SiO ₂ film 40, SiO by CVD in FIG 2 (e) ₂ After embedding the film, polysilicon may be embedded, and then the polysilicon may be thermally oxidized until reaching the CVD-SiO ₂ film.
[Second Embodiment]
In the case of the first embodiment, since the occupied area is somewhat larger than that of the conventional type of FIG. 7, it is difficult to apply to a place where a high degree of integration is required. Therefore, the second embodiment applies a method of applying distortion due to physical distortion to the channel portion while maintaining the conventional degree of integration.

    8-12 is explanatory drawing of the manufacturing process of a 1st Example. In these, (a) to (o) are cross-sectional views of each step, and (c-TOP), (d-TOP), (e-TOP), (h-TOP), (i-TOP), (J-TOP), (l-TOP), (n-TOP), and (o-TOP) are plan views viewed from directly above in the process steps of the corresponding cross-sectional views. A-A 'in the drawing indicates the cross-sectional position of each cross-sectional view.

Also in the second embodiment, the substrate used is the same as that of the first embodiment. In FIG. 8A, a buried SiO ₂ layer (BOX layer, Buried Oxide layer) 11 and a single crystal silicon layer (SOI layer, Silicon On Insulator layer) 12 are formed on a support substrate 10 made of single crystal silicon. 1 shows an SOI substrate. Here, for example, the BOX layer 11 is 200 nm and the SOI layer 12 is 60 nm. Here again, the SOI layer 12 is assumed to be p-type single crystal silicon in order to explain an example of a method for manufacturing an n-channel transistor. In the case of a p-channel transistor, the SOI layer 12 is n-type single crystal silicon.

Next, as shown in FIG. 8B, a thermally oxidized SiO ₂ film 200 is formed by heat treatment. Here, for example, by dry oxidation at 800 ° C., the thickness of the thermally oxidized SiO ₂ film 200 is set to 5 nm.

Next, as shown in FIG. 8C and FIG. 8C-TOP, a resist is patterned into an element isolation shape, and a thermal oxide SiO ₂ film 200, an SOI layer 12, and a BOX layer 11 are formed using the resist as a mask. RIE processing is performed to form a groove 210 (in other words, a mesa laminated structure having an element isolation shape). Thereafter, the resist is removed.

Next, as shown in FIG. 8 (d) and FIG. 8 (d-TOP), it was deposited on the entire surface of the Si ₃ N ₄ film 220 with thickness larger than the depth of the groove 210 by CVD, Si ₃ by CMP The N ₄ film 220 is polished. At this time, an STI structure (Shallow Trench Isolation structure) having a shape in which the Si ₃ N ₄ film 220 is embedded in the groove 210 is obtained by using the thermally oxidized SiO ₂ film 200 on the uppermost surface of the mesa laminated structure as an etching stopper. . Here, for example, the thickness of the Si ₃ N ₄ film 220 during CVD is set to 300 nm. The material of the STI structure is not limited to Si ₃ N _4, and other materials that do not dissolve when wet etching SiO ₂ may be used.

Next, as shown in FIGS. 9E and 9E-TOP, the thermally oxidized SiO ₂ film 200 is wet-etched using a hydrofluoric acid solution. Thereafter, a resist is patterned in the SOI layer 12 that has been subjected to element isolation processing so that at least the distance between the edge of the element isolation pattern and the portion closest to the element isolation pattern does not exceed the limit of exposure alignment accuracy. And using this as a mask, the SOI layer 12 is etched by a process such as RIE to form a hole 230 whose depth reaches the surface of the BOX layer 11. Thereafter, the resist is removed. Here, for example, one side of the opening of the hole 230 is a square of 500 nm.

  Then, as shown in FIG. 9F, the cavity 240 is formed by isotropically selective wet etching of the BOX layer 11 from the hole 230 using a hydrofluoric acid solution. Here, for example, etching is performed in a 5% hydrofluoric acid solution for 30 minutes.

Next, as shown in FIG. 9G, a thermally oxidized SiO ₂ film 250 is formed by thermal oxidation. Here, for example, by dry oxidation at 800 ° C., the thickness of the thermally oxidized SiO ₂ film 250 is set to 5 nm.

  Next, as shown in FIGS. 9H and 9H-TOP, a polysilicon film 260 is deposited to such an extent that the cavity 240 is not completely filled (a gap 261 is formed) by CVD. Here, for example, the thickness of the polysilicon film 260 is 90 nm. The material to be embedded here is not limited to polysilicon, but an oxidizable semiconductor such as Ge or an oxidizable metal such as Ti may be used.

Next, as shown in FIGS. 10I and 10I-TOP, a thermally oxidized SiO ₂ film 270 is formed by thermal oxidation. At this time, the volume of the portion where the polysilicon film 260 is embedded expands, and is deformed into a shape as shown in the cross-sectional view, so that a cavity 271 is formed. In this case, tensile stress is applied to the deformed SOI layer 12. Here, for example, the thickness of the thermally oxidized SiO ₂ film 270 is set to 100 nm by dry oxidation at 1000 ° C. In addition, illustration of the hole 230 part in sectional drawing is abbreviate | omitted after this figure. Similar results can be obtained even when an oxidizable semiconductor or metal is used in place of the polysilicon film 260 in FIGS. 9H and 9H-TOP.

Next, as shown in FIG. 10J and FIG. 10J-TOP, the thermally oxidized SiO ₂ film 270 and the polysilicon film 260 on the surface are etched away by RIE or the like. Thereafter, the upper thermally oxidized SiO ₂ film 250 is wet etched using a hydrofluoric acid solution.

Then, a gate oxide SiO ₂ film 280 is formed as shown in FIG. Here, for example, by dry oxidation at 800 ° C., the thickness of the gate oxide SiO ₂ film 280 is set to 3 nm. As the gate insulating film, a high-k film such as HfO ₂ may be used instead of the oxide SiO ₂ film.

  Next, as shown in FIGS. 11 (l) and 11 (l-TOP), a polysilicon film 290 is deposited on the entire surface by CVD, and then a resist is patterned into a gate electrode shape, and polysilicon is used as a mask. The film 290 is processed by RIE to form a gate electrode 290. Here, for example, the thickness of the polysilicon film 290 is 100 nm and the gate length is 50 nm. Note that polysilicon, germanium, or the like may be used for the gate electrode instead of polysilicon.

Next, as shown in FIG. 11M, ion implantation is performed to form the extension implantation layer 300. Here, for example, the ion to be implanted is As ⁺ . In the case of a p-channel transistor, the implanted ion is B ⁺ .

Next, as shown in FIG. 11 (n) and FIG. 11 (n-TOP), after depositing the SiO ₂ film 310 on the entire surface by CVD, the SiO ₂ sidewall 310 is formed on the side wall of the gate electrode 290 by RIE or the like. To do. Here, for example, the thickness of the SiO ₂ film 310 is 130 nm.

Then, as shown in FIG. 12 (o) and FIG. 12 (o-TOP), ion implantation is performed to form the source / drain implantation layer 320. Here, for example, the ion to be implanted is As ⁺ . In the case of a p-channel transistor, the implanted ion is B ⁺ . The source / drain electrodes may be metal silicided or have an elevated structure. Further, the gate electrode may be formed into a metal silicide.

  In the steps of FIGS. 9F and 9G, the SOI layer 12 may warp slightly upward as in the first embodiment. In that case, the same process change as in the first embodiment is performed.

  FIG. 13 shows a schematic bird's-eye view of the transistor formed according to the second embodiment. Compared with the conventional type shown in FIG. 14, it can be seen that the channel portion is deformed so as to protrude upward, and tensile strain is applied to the channel portion. Further, in the case of this structure, since the occupation area is the same as that of the conventional type in FIG. 14, distortion due to physical distortion can be applied to the channel portion without sacrificing the degree of integration.

In this embodiment, there is a thin SiO ₂ layer (thermally oxidized SiO ₂ film 250) below the channel layer (SOI layer 12), but a polysilicon film 50 remains below the SiO ₂ layer (completely SOI 2). It's hard to say structure. If you want to realize the SOI structure, a thermal oxidation step of FIG. 10 (i), a method such as thermal oxidation of the polysilicon until the thermally oxidized SiO ₂ film 250, SiO by CVD in FIG 9 (h) ₂ After embedding the film, polysilicon may be embedded, and then the polysilicon may be thermally oxidized until reaching the CVD-SiO ₂ film.

The following additional notes are further disclosed with respect to the embodiments including the first and second examples.
(Appendix 1) A distorted shape having at least a semiconductor substrate, an insulating layer formed thereon, and a semiconductor layer formed thereon, the semiconductor layer projecting in a direction opposite to the insulating layer side A semiconductor device having a region, wherein a channel is formed in the distorted region. (Claim 1)
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the semiconductor substrate is a silicon substrate, the insulating layer is a silicon oxide layer, and the semiconductor layer is a silicon layer. (Claim 2) (Appendix 3) The semiconductor device according to appendix 1, wherein the semiconductor substrate is a silicon substrate, the insulating layer is a silicon nitride layer, and the semiconductor layer is a silicon layer.
(Appendix 4) The semiconductor device according to appendix 1 or 2, wherein at least a cavity is formed between the distorted region and the semiconductor substrate. (Claim 3) (Appendix 5) The semiconductor device according to any one of appendices 1 to 3, wherein the distorted region is formed so as to be surrounded by a region defining insulating layer. (Claim 4)
(Supplementary note 6) The semiconductor device according to supplementary note 5, wherein the region defining insulating layer is a thermal oxide film having a LOCOS (LOCal Oxidation of Silicon) structure.
(Supplementary note 7) The semiconductor device according to supplementary note 5, wherein the region defining insulating layer is an insulating layer having an STI (Shallow Trench Isolation) structure.
(Supplementary Note 8) In a laminated substrate having a first layer on a semiconductor substrate and a second layer made of a semiconductor layer thereon, an opening reaching the first layer is formed in a part of the second layer. In the first step of forming, a second step of forming a cavity larger than the opening in a part of the first layer through the opening, and in the second step, oxygen or an inert gas is further added. A third step of forming an insulating film by performing a heat treatment therein, and a step of forming a channel on the second layer formed on the second step or the third step. A method for manufacturing a semiconductor device. (Claim 5)
(Supplementary Note 9) In the third step, a step of forming a channel on the second layer formed by the fourth step of performing thermal oxidation after filling the cavity with a semiconductor or a conductor. The method for manufacturing a semiconductor device according to appendix 8, wherein:
(Supplementary note 10) The method for manufacturing a semiconductor device according to supplementary note 9, wherein in the fourth step, the cavity is filled with a semiconductor or a conductor so that a gap is formed.
(Supplementary note 11) The method of manufacturing a semiconductor device according to any one of supplementary notes 8 to 10, wherein the first layer is an insulating layer, and the laminated substrate is an SOI (Silicon On Insulator) substrate.

Manufacturing process diagram of the first embodiment of the present invention (1) Manufacturing process diagram of the first embodiment of the present invention (2) Manufacturing process diagram of the first embodiment of the present invention (3) Manufacturing process diagram of the first embodiment of the present invention (4) Manufacturing process diagram of the first embodiment of the present invention (5) Overhead schematic diagram of the first embodiment of the present invention Overhead schematic diagram of a conventional example corresponding to the first embodiment of the present invention Manufacturing process diagram of the second embodiment of the present invention (1) Manufacturing process diagram of the second embodiment of the present invention (2) Manufacturing process diagram of the second embodiment of the present invention (3) Manufacturing process diagram of the second embodiment of the present invention (4) Manufacturing process diagram of the second embodiment of the present invention (5) Overhead schematic diagram of the second embodiment of the present invention Overhead schematic diagram of a conventional example corresponding to the second embodiment of the present invention

Explanation of symbols

10 Support substrate (single crystal silicon) 11 BOX layer (SiO ₂ )
12 SOI layer (single crystal silicon)
20, 230 hole 30, 61, 72, 90, 112, 132, 240, 271 cavity 40, 60, 70, 131, 200, 250, 270 thermally oxidized SiO ₂
50, 111, 260 Polysilicon 51, 261 Clearance 71 Si ₃ N ₄
80 LOCOS (SiO ₂ )
100,280 Gate oxide film (thermally oxidized SiO ₂ )
110,290 Gate electrode (polysilicon)
120, 300 Extension injection region (As ⁺ )
130, 310 Side wall (SiO ₂ )
140, 320 Source / drain implantation region (As ⁺ )
210 Groove 220 STI (Si ₃ N ₄ )

Claims (5)

An SOI substrate including a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer;
A gate insulating film formed on the semiconductor layer of the SOI substrate;
A gate electrode formed on the gate insulating film;
Have
The semiconductor device, wherein the semiconductor layer has a distortion-shaped region that protrudes in a direction away from the support substrate in any of a gate length direction and a gate width direction of the gate electrode below the gate electrode. . The semiconductor device according to claim 1 , wherein the semiconductor substrate is a silicon substrate, the insulating layer is a silicon oxide layer, and the semiconductor layer is a silicon layer. Forming a gate insulating film on the semiconductor layer of the SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer;
Forming a gate electrode on the gate insulating film;
Have
Before the step of forming the gate insulating film, a cavity is formed below the region of the insulating layer where the gate electrode is to be formed, and below the region of the semiconductor layer where the gate electrode is to be formed, A method of manufacturing a semiconductor device, comprising: forming a distorted region that protrudes in a direction away from the support substrate in both the gate length direction and the gate width direction of the gate electrode. Forming a gate insulating film on the semiconductor layer of the SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer;
Forming a gate electrode on the gate insulating film;
Have
Before the step of forming the gate insulating film,
Forming a cavity below a region of the insulating layer where the gate electrode is to be formed;
A distortion-shaped region that protrudes in a direction away from the support substrate in both the gate length direction and the gate width direction of the gate electrode below the region of the semiconductor layer where the gate electrode is to be formed by performing a heat treatment Forming a step;
A method for manufacturing a semiconductor device, comprising: Forming a gate insulating film on the semiconductor layer of the SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer;
Forming a gate electrode on the gate insulating film;
Have
Before the step of forming the gate insulating film,
Forming a cavity below a region of the insulating layer where the gate electrode is to be formed;
Forming a oxidizable film having a gap in the cavity;
The support substrate is expanded in both the gate length direction and the gate width direction of the gate electrode below the region of the semiconductor layer where the gate electrode is to be formed by expanding the film by thermal oxidation of the oxidizable film. Forming a distortion-shaped region that is convex in a direction away from
A method for manufacturing a semiconductor device, comprising:

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