JP4565122B2 - Image moment sensor, image moment measurement device, image moment sensor calculation method, and image moment measurement method - Google Patents

Description

  The present invention relates to an image moment sensor, an image moment measurement device, an image moment sensor calculation method, and an image moment measurement method.

  Although automatic control of devices using sensor information is generally performed, few devices use image information. In order to analyze image information in real time and acquire necessary information, a powerful processor for processing a large amount of image information is required in addition to the image sensor. This leads to an increase in equipment size and cost.

  On the other hand, there is a position sensor that uses a semiconductor position detection element (PSD) and outputs only image feature amounts, not image information itself. However, this position sensor can be used only in a limited environment because the obtained feature amount is only the position of a single target and the background image is not separated.

Therefore, as a sensor for solving such a problem, there is a vision chip having a processing circuit for each pixel of the image sensor (see, for example, Patent Document 1). This vision chip can output various feature amounts of an image by performing imaging on an image plane and each processing circuit performing image processing and arithmetic processing.
JP 2001-195564 A (page 3-5, FIG. 1)

  However, since the conventional vision chip has a processing circuit for each pixel of the image sensor, each pixel circuit becomes large, and it is difficult to achieve high resolution and high sensitivity. In addition, although this vision chip can perform a calculation necessary for obtaining a moment amount as a feature amount at high speed, there is room for improvement in further speeding up.

  The present invention has been made in view of such conventional problems, and is to simplify the configuration of a pixel circuit. Further, the present invention provides a configuration capable of speeding up the calculation of the moment amount.

In order to achieve this object, an image sensor according to the first aspect of the present invention provides:
The number of rows M (M is a positive integer), the number of columns as the N (N is a positive integer), M × N number of processing elements arranged in a matrix, each processing element, the light the light received from images A column for converting the light detection signal to a signal level corresponding to the intensity, binarizing the light detection signal to generate binary data, and selecting a column necessary for obtaining the moment amount m _pq shown in Equation 1 The selection signal x ^p _i is supplied, and the processing element of the column selected based on the supplied column selection signal x ^p _i adds the binary data in the row direction, and the calculation result of the processing element of each row Respectively, an image processing unit configured to output the data dx shown in Equation 2,
The row selection for selecting the rows needed to obtain moment amount m _pq signal y ^q _j is supplied, among the output data dx from each row of the image processing unit, the supplied row selection signal y ^q _a column adder that adds the data dx output from the row selected based on _j in the column direction and outputs the data dy shown in Equation 3,
The column selection signal x ^p _i and the row selection signal y ^q _j are generated by setting a row and a column necessary for obtaining the moment amount m _pq shown in Equation 1, and the generated column selection signal x ^p a signal processing unit that supplies _i to the image processing unit and supplies the row selection signal y ^q _j to the column addition unit.

The signal processing unit is supplied with area information indicating a rectangular area, generates a column selection signal for the rectangular area based on the supplied area information, and generates the column selection signal generated for the rectangular area and the column selection. Performs a logical product operation with the signal x ^p _i and supplies a calculated value of the logical product operation to the image processing unit, and generates a row selection signal for the rectangular region based on the region information, _{Alternatively} , a logical product operation may be performed on the row selection signal generated in step ⁽ _b) and the row selection signal y ^q _j, and the operation value of the logical product operation may be supplied to the column adder.

Each processing element of the image processing unit includes:
A light detection unit that receives light from the image, photoelectrically converts the received light into a light detection signal having a signal level corresponding to light intensity, and
A binarization unit that binarizes the light detection signal output by the light detection unit and outputs binary data;
And said column selection signal x ^p _i is supplied, on the basis of the supplied the column selection signal x ^p _i, the binary data output control unit for binarizing unit controls the output of the binary data output,
The binary data output from the binary data output control unit is added to the addition data supplied from the processing element of ((x−1), y) coordinates to generate new addition data, and the generated new data A line addition unit that supplies the addition data to a processing element of ((x + 1), y) coordinates.

The row adder of each processing element is
A carry data holding unit for holding the generated carry data at the fall of the clock signal supplied to the processing element of the ((x-1), y) coordinate and outputting the held carry data at the next addition; ,
The binary data output from the binary data output control unit, the binary data supplied from the processing element of ((x-1), y) coordinates, and the carry data output from the carry data holding unit are added. New addition data and carry data are generated, the generated new addition data is output to the processing element of the ((x + 1), y) coordinate, and the generated carry data is supplied to the carry data holding unit. And an adding unit.

The signal processing unit supplies a clock signal to the image processing unit,
The row addition unit of each processing element is configured by a dynamic circuit that repeatedly charges and evaluates according to a supplied clock signal and holds data added during the evaluation period by using a parasitic capacitance of the transistor,
The clock signal supplied from the signal processing unit is sequentially delayed to generate an n-th (n is an integer of 1 or more) clock signal, and the generated n-th clock signal is transmitted to each processing element in the n-th column. A clock signal delay unit for supplying to the row addition unit;
The image processing unit may be configured by connecting the dynamic circuits in multiple stages.

In synchronization with the clock signal supplied from the signal processing unit or the clock signal delay unit, the column selection signal x ^p _i supplied from the signal processing unit is supplied to each processing element in the order of supply. A column selection signal supply unit;
The image processing unit may be configured by a variable length pipeline configuration.

  The image processing unit, the column addition unit, and the signal processing unit may be configured by an integrated circuit.

Each processing element of the image processing unit includes:
A light detection unit that receives light from the image, photoelectrically converts the received light into a light detection signal having a signal level corresponding to light intensity, and
A binarization unit that binarizes the light detection signal output by the light detection unit and outputs binary data;
An operation value of a logical product operation of the column selection signal generated based on the region information and the column selection signal x ^p _i is supplied, and the binarization unit outputs 2 based on the supplied operation value A binary data output control unit for controlling output of value data;
The binary data output from the binary data output control unit is added to the addition data supplied from the processing element of ((x−1), y) coordinates to generate new addition data, and the generated new data A line addition unit that supplies the addition data to a processing element of ((x + 1), y) coordinates.

The row adder of each processing element is
A carry data holding unit for holding the generated carry data at the fall of the clock signal supplied to the processing element of the ((x-1), y) coordinate and outputting the held carry data at the next addition; ,
The binary data output from the binary data output control unit, the binary data supplied from the processing element of ((x-1), y) coordinates, and the carry data output from the carry data holding unit are added. New addition data and carry data are generated, the generated new addition data is output to the processing element of the ((x + 1), y) coordinate, and the generated carry data is supplied to the carry data holding unit. And an adding unit.

The signal processing unit supplies a clock signal to the image processing unit,
The row addition unit of each processing element is configured by a dynamic circuit that repeatedly charges and evaluates according to a supplied clock signal and holds data added during the evaluation period by using a parasitic capacitance of the transistor,
The clock signal supplied from the signal processing unit is sequentially delayed to generate an n-th (n is an integer of 1 or more) clock signal, and the generated n-th clock signal is transmitted to each processing element in the n-th column. A clock signal delay unit for supplying to the row addition unit;
The dynamic circuit may be connected in multiple stages to configure the image processing unit.

In synchronization with the clock signal supplied from the signal processing unit or the clock signal delay unit, the column selection signal generated for the rectangular area as the operation value supplied from the signal processing unit and the column selection signal x ^p a column selection signal supply unit that supplies the operation values of the logical product operation with _i to each of the processing elements in the order of supply;
The image processing unit may be configured by a variable length pipeline configuration.

  The image processing unit, the column addition unit, and the signal processing unit may be configured by an integrated circuit.

An image moment measuring apparatus according to a second aspect of the present invention is:
The above-described image moment sensor that outputs the data dy shown in Equation 3,
A control unit that obtains the moment amount m _pq by substituting the data dy output from the image moment sensor into Equation 1 and performing an operation.

  The control unit sets a plurality of rectangular regions for the supplied image, sequentially supplies region information indicating the regions of the rectangular regions to the signal processing unit, and outputs the information from the column addition unit. The obtained data dy is obtained, and based on each data dy obtained for each area information, the moment amount is calculated according to Equation 1, and obtained by calculation for each area corresponding to the supplied image. The moment amounts of the supplied images may be acquired by adding the moment amounts thus obtained.

  When the rectangular area is unknown, the control unit divides the entire area into blocks of a predetermined size, obtains a total value of each block, and performs a labeling process using the total value of each block. The area information of each rectangular area may be acquired.

  The control unit supplies a plurality of luminance threshold values to the binarization unit of each processing element, acquires a moment amount for each luminance threshold value, and obtains a moment amount of a target image as a plurality of acquired moment amounts. You may make it acquire by calculating | requiring the difference of these.

  The control unit causes the binarization unit to sequentially binarize the photodetection signals output at different timings during exposure of the photodetection unit, and obtains data dy from the column addition unit. It is also possible to obtain and calculate the moment amount of the image.

A light source that emits light;
A light projecting unit for projecting the light emitted from the light source unit to the moment amount measurement object and the background,
The image moment sensor outputs the data dy shown in Equation 3 for the image formed based on the reflected light of the light from the moment amount measurement object and the background,
The control unit supplies a blinking signal for blinking light to the light source unit to cause the light to blink, and from the image moment sensor when the light is turned on and when the light is turned off. By obtaining the output data dy shown in Equation 3 and obtaining the difference between the two moment amounts obtained based on the obtained data dy, the image of the measurement object and the background image are separated, You may make it acquire the moment amount of the said measurement target object.

The calculation method of the image moment sensor according to the third aspect of the present invention is:
The number of rows M (M is a positive integer), the number of columns as the N (N is a positive integer), M × N number of processing elements arranged in a matrix, each processing element, the light the light received from images An image processing unit configured to convert to a light detection signal having a signal level corresponding to the intensity, each processing element adds binary data in the row direction , and outputs data dx for each row;
A column addition unit that adds data dx output from each row of the image processing unit and outputs data dy, and obtains a moment amount of the image, the image moment sensor calculating method comprising:
Setting a row and a column necessary for obtaining the moment amount m _pq shown in Equation 4 to generate a column selection signal x ^p _i and a row selection signal y ^q _j ;
The generated column selection signal x ^p _i is supplied to each processing element of the image processing unit, the column of the processing element is selected, and the calculation result of the processing element of each row is sent to the image processing unit, respectively. Outputting the data dx shown in Formula 5 ;
The generated row selection signal y ^q _j is supplied to the column addition unit, and the column addition unit is based on the supplied row selection signal y ^q _j among the data dx output from each row of the image processing unit. Adding the data dx output from the selected row and outputting the data dy shown in Equation 6 ;
Obtaining the data dy output from the column adder, and calculating the moment amount m _pq according to Equation ( 4 ).

An image moment measuring method according to a fourth aspect of the present invention is:
Projecting light on the object of moment measurement and the background;
According to the calculation method of the image moment sensor described above, calculating the moment amount of the image formed based on the reflected light of the projected light;
Turning off the light and stopping the light projection to the moment measurement object and the background;
According to the calculation method of the image moment sensor described above, calculating the moment amount of the image formed based on the reflected light of the projected light;
The measurement object image and the background image are separated by obtaining a difference between the moment amount calculated when the light is projected and the moment amount calculated when the light projection is stopped, and the measurement is performed. Obtaining a moment amount of the object.

  According to the present invention, the configuration of the pixel circuit can be simplified. In addition, the moment amount calculation can be speeded up.

Hereinafter, an image moment sensor and an image moment measuring device according to an embodiment of the present invention will be described with reference to the drawings.
(Embodiment 1)
The configuration of the image moment sensor according to the first embodiment is shown in FIG.
The image moment sensor according to the first embodiment receives light from a subject and acquires a moment amount as a feature amount of the subject image.

In general, the moment amount m _pq is expressed by the following _{equation (} 7 ).

Here, when the integer is represented as a binary number by d, the integer d is represented by the following number 8 .
The moment amount m _pq shown in Equation 1 is obtained by Equation 9 using _Equation 8 .

According to Equation 9 , an algorithm as shown in FIG. 2 is established. In this algorithm, the column of each image data I (x, y) necessary for the moment amount calculation is designated, addition operation is performed in the row direction, and the obtained calculation result is added to the row necessary for the moment amount calculation. This indicates that the moment amount of the image data I (x, y) can be obtained by designating and adding in the column direction.

  This eliminates the need for a configuration that directly designates a row in the image data I (x, y). If such a configuration can be omitted for each pixel of the image data I (x, y), the circuit configuration can be greatly simplified.

The image moment sensor includes the image processing unit 1, the column addition unit 2, and the signal processing unit 3 in order to obtain the moment amount m _pq based on the formula 3, and is configured by a vision chip. In this image moment sensor, the image processing unit 1, the column addition unit 2, and the signal processing unit 3 are integrated into a single chip.

The signal processing unit 3 is supplied with a command from an external circuit (not shown) of the image moment sensor, and receives a clock signal φ [0] and column selection signals x ^p _i [0] to x ^p _i [N] to the image processing unit 1. -1] and the row selection signal y ^q _j is supplied to the column adder 2.

Column select signal _{^{x p i [0] ~x p}} i [N-1] is a signal for selecting a column required to capture the moment amount. The row selection signal y ^q _j is a signal for selecting a row necessary for obtaining the moment amount. Further, the signal SOUT output from the column adder 2 indicates a coefficient of each digit of 2 when the moment amount is expressed by a binary number as shown in Equation 9 . Incidentally, hereinafter, the column selection signal _{^{x p i [0] ~x p}} i [N-1], respectively, marked xi [0] ~xi [N- 1], referred to as yj row selection signal y ^q _j Shall.

  The image processing unit 1 includes a delay circuit (denoted as “delay” in the drawing) 11_0 to 11_ (N-2), first-in first-out (FIFO) 12_0 to 12_ (N-1), and image processing. Element (hereinafter, simply referred to as “processing element”) 13_xy (x = 0 to N−1, y = 0 to N−1; N is a positive integer).

  The delay circuits 11_0 to 11_ (N-2) sequentially delay the clock signal φ [0] supplied from the signal processing unit 3 to generate the k-th (k is an integer of 1 or more) clock signal φ [k]. Is to be generated.

  As shown in FIG. 3, the delay circuit 11_0 delays the clock signal φ [0] supplied from the signal processing unit 3 by a time td to generate the clock signal φ [1]. The delay circuit 11_0 supplies the generated clock signal φ [1] to the delay circuit 11_1, the FIFO 12_1, and the processing elements 13_10 to 13_1 (N−1).

  The delay circuit 11_k1 (k1 = 1 to (N-2)) delays the supplied clock signal φ [k1] by a time td, and generates the generated clock signal φ [k1 + 1] as a delay circuit 11_ (k +1), FIFO 12_ (k + 1), and processing elements 13_ (k + 1) 1 to 13_ (k + 1) N.

  FIFOs 12_0 to 12_ (N-1) are provided for configuring a variable-length pipeline. The FIFOs 12_0 to 12_ (N-1) respectively receive the column selection signals xi [0] to xi [N-1] supplied from the signal processing unit 3 at time t0 shown in FIG. , Once stored.

  FIFOs 12_0 to 12_ (N-1) supply the stored column selection signals xi [0] to xi [N-1] in accordance with the clock timing of the clock signals φ [0] to [N-2], respectively. It supplies to each processing element 13_xy in the order which was done. As shown in FIG. 5, the FIFOs 12_0 to 12_ (N-1) store the remaining column selection signals xi [0] to xi [N-1] at time t4.

  The processing element 13_xy receives reflected light from the acquired image, converts it into a light detection signal, and performs arithmetic processing for each converted light detection signal.

  As shown in FIG. 6, processing element 13_xy in the y-th row is set as processing element 13_ky (0 ≦ k ≦ N−1), and each processing element 13_ky includes PD (light detector) 101, binarization circuit 102, AND circuit (logical product circuit) 103, FA (full adder) 104, and DFF 105.

  The PD 101 is a photodetector that photoelectrically converts received light into a light detection signal having a signal level corresponding to the light intensity.

  The binarization circuit 102 binarizes the light detection signal by comparing the signal level of the light detection signal converted by the PD 101 with the supplied luminance threshold value, and outputs binary data.

  The binarization circuit 102 outputs a signal of “1” (Hi) level when the signal level of the light detection signal S2 is equal to or higher than the luminance threshold value, and outputs a signal S3 of “0” (Low) level when it is lower than the luminance threshold value. Is output.

  The AND circuit 103 of the processing element 13_ky controls the output of the binary data output from the binarization circuit 102 based on the column selection signal xi [k] supplied from the FIFO 12_k. The AND circuit 103 outputs or blocks the binary data generated by the binarization circuit 102 by calculating a logical product of the column selection signal xi [k] and the binary data.

  The AND circuit 103 outputs the binary signal output from the binarization circuit 102 to the FA 104 when the column selection signal xi [k] supplied from the FIFO 12_k is “1”.

  In addition, when the column selection signal xi [k] supplied from the FIFO 12_k is “0”, the AND circuit 103 cuts off the output of the binary data output from the binarization circuit 102 to the FA 104 and outputs the FA 104 "0" is output to.

  Since each processing element 13_xy includes such an AND circuit 103, the image moment sensor can select one of the processing elements 13_xy and acquire a feature amount (moment amount) of the image.

  The FA 104 is a full adder, and the data Dk-1 supplied from the processing element 13_ (k-1) y on the left in the row direction, the data Dk supplied from the AND circuit 103, and the carry supplied from the DFF 105 Ci is added to generate data Dk + 1 as new addition data.

  As shown in FIG. 7, the FA 104 includes NMOS circuits 111 and 112 and transistors Q11 to Q14.

  The transistors Q11 and Q12 are a PMOS transistor and an NMOS transistor, respectively. The source of the transistor Q11 is connected to the power supply, the source of the transistor Q12 is grounded, and the clock signal φ [k] is supplied to the gates of the transistors Q11 and Q12.

  The transistors Q13 and Q14 are a PMOS transistor and an NMOS transistor, respectively. The source of the transistor Q13 is connected to the power supply, the source of the transistor Q14 is grounded, and the clock signal φ [k + 1] is supplied to the gates of the transistors Q13 and Q14.

  The NMOS circuit 111 includes transistors Q15 to Q19. Transistors Q15 to Q19 are NMOS transistors. The drain of the transistor Q15 is connected to the drain of the transistor Q11, and the carry Ci is supplied to the gate.

  The drains of the transistors Q16 and Q17 are connected to the source of the transistor Q15, and the respective sources are connected to the drain of the transistor Q12. Data Dk-1 and Dk are supplied to the gates of the transistors Q16 and Q17, respectively. Data Dk-1 is supplied from the adjacent processing element 13_ (k-1) y in the same row. The data Dk is supplied from the AND circuit 103 of the processing element 13_ky.

  The drains of the transistors Q18 and Q19 are connected to the drain of the transistor Q11 and the source of the transistor Q18, respectively, and data Dk-1 and Dk are supplied to the gates, respectively. The source of transistor Q19 is connected to the drain of transistor Q12.

  The NMOS circuit 111 and the transistors Q11 and Q13 constitute a dynamic NMOS circuit. That is, as shown in FIG. 8, when the clock signal φ [k] before time t12 is “0”, the transistor Q11 is turned on and the transistor Q12 is turned off. The NMOS circuit 111 is charged according to the state of the carry Ci and the data Dk-1 and Dk. The NMOS circuit 111 holds the addition data.

  When the clock signal φ [k] becomes “1” at time t12, the transistor Q11 is turned off and the transistor Q12 is turned on. The value of carry Co is determined by the state of carry Ci and data Dk-1, Dk.

  The NMOS circuit 112 includes transistors Q20 to Q26. The transistors 20 to Q26 are NMOS transistors. The drain of the transistor Q20 is connected to the drain of the transistor Q13, and the carry Co is supplied to the gate.

  The drains of transistors Q21, Q22, and Q23 are connected to the source of transistor Q20, and the respective sources are connected to the drain of transistor Q14. Data Dk-1, Dk and carry Co are supplied to the gates of the transistors Q21, Q22 and Q23, respectively.

  The drain of transistor Q24 is connected to the drain of transistor Q13. The drain of transistor Q25 is connected to the source of transistor Q24. The drain of transistor Q26 is connected to the source of transistor Q25. The source of transistor Q26 is connected to the drain of transistor Q14.

  The NMOS circuit 112 and the transistors Q12 and Q14 constitute a dynamic NMOS circuit. That is, as shown in FIG. 8, when the clock signal φ [k + 1] before time t13 is “0”, the transistor Q13 is turned on and the transistor Q14 is turned off. The NMOS circuit 111 is charged according to the states of carry Co and Ci and data Dk-1 and Dk. The NMOS circuit 111 holds the addition data.

  When the clock signal φ [k + 1] becomes “1” at time t13, the transistor Q13 is turned off and the transistor Q14 is turned on. The value of the data Dinv at the input end of the inverter 113 is determined by the states of carry Co and Ci and data Dk-1 and Dk. The inverter 113 inverts the value of the data Dinv and supplies the inverted data Dk + 1 to the processing element 13_ (k + 1) y.

  The FA 104 of this embodiment is configured to include such a dynamic NMOS circuit.

  The DFF 105 takes in the carry Co from the FA 104 at the time of rising before the clock signal φ [k], and supplies the carry Ci to the FA 104. The DFF 105 includes inverters 121 to 123 and transistors Q31 to Q36.

  Each of the inverters 121, 122, and 123 has two control terminals, and inverts and outputs the signal supplied to the input terminal when “1” is supplied to the two control terminals. The input terminal of the inverter 121 is connected to the drain of the transistor Q11 of the FA 104 and is supplied with a carry Co. The output terminal of the inverter 121 is connected to the input terminal of the inverter 122. The output terminal of the inverter 122 is connected to the input terminal of the inverter 123. The output terminal of the inverter 123 is connected to the gate of the transistor Q15 of the NMOS circuit 111 and supplies the carry Ci.

  Transistors Q31, Q33, and Q35 are PMOS transistors. The sources of the transistors Q31, Q33, and Q35 are connected to a positive voltage power source. The drains of the transistors Q31, Q33, and Q35 are connected to one control terminal of the inverters 121, 122, and 123, respectively. An inverted signal of the clock signal φ [k−1], an inverted signal of the clock signal φ [k], and a clock signal φ [k] are supplied to the gates of the transistors Q31, Q33, and Q35.

  Transistors Q32, Q34, and Q36 are NMOS transistors. The sources of the transistors Q32, Q34, and Q36 are connected to a negative voltage power supply, the drains are connected to the other control terminals of the inverters 121, 122, and 123, and the clock signal φ [k− 1], φ [k], and an inverted signal of φ [k] are supplied.

  As shown in FIG. 8, when the clock signal φ [k−1] falls at time t14, the transistors Q31 and Q32 are turned off, and the inverter 121 inverts and outputs the value of the carry Co.

  Next, when the clock signal φ [k] rises, the transistors Q33 and Q34 are turned on, and the inverter 122 inverts and outputs the output value of the inverter 121.

  When the clock signal φ [k] falls, the transistors Q35 and Q36 are turned on, and the inverter 123 inverts the output value of the inverter 122.

  As described above, the DFF 105 is prevented from capturing the carry data Co from time t14 to time t15. After time t14, the data Dk-1 is converted to the previous processing element 13_ (k-1) y as addition data. This is because it has been updated. For this reason, as described above, the DFF 105 takes in the carry Co from the FA 104 at time t14 before the clock signal φ [k−1] falls.

  Further, the image moment sensor of this embodiment is configured by a domino logic circuit in which dynamic NMOS circuits are connected in multiple stages. Further, this image moment sensor is constituted by a self-timed domino logic circuit.

  The self-timed domino logic circuit is configured so that the clock signal φ [k] generated by delaying the clock signal φ [k−1] supplied to the previous processing element 13_xy is supplied to the next processing element 13_xy. It is a configured circuit.

  In the self-timed domino logic circuit, the output signal of the dynamic NMOS circuit only changes from “1” to “0”, and the signal does not invert many times until the output stabilizes. Low power consumption is achieved.

  However, a dynamic NMOS circuit cannot output a correct logical value when directly connected. An example in which this dynamic NMOS circuit is directly connected is shown in FIG.

  In FIG. 9A, the transistors Q201 and Q202 and the NMOS logic circuit 201 constitute a first-stage dynamic NMOS circuit. The transistors Q203 and Q204 and the NMOS logic circuit 202 constitute a second-stage dynamic NMOS circuit. The NMOS logic circuit 201 is supplied with a signal S201, the NMOS logic circuit 202 is supplied with a signal S202, and the second-stage dynamic NMOS circuit outputs a signal S203.

  As shown in FIG. 9B, when the signal S202 changes from “1” → “1” or “1” → “0”, the signal S203 also changes from “1” → “1” or “1”. → Changes to “0”. However, once the signal S203 changes to “0”, it cannot return to “1”. Thus, in a self-timed domino logic circuit in which dynamic NMOS circuits are directly connected in multiple stages, the signal of each output stage changes only from “1” to “0”.

  In contrast, the circuit shown in FIG. 10A includes a delay circuit 203. The delay circuit (delay) 203 supplies a clock signal Φ ′ generated by delaying the clock signal Φ to the gate of the transistor Q202.

  As shown in FIG. 10B, the signal S203 can return to “1” even if it once changes to “0”. For this reason, the self-timed domino logic circuit can output a correct logic value. The delay circuits 12_1 to 12_N are provided for connecting dynamic NMOS circuits in multiple stages by self-timed domino logic.

  The column addition unit 2 selects a row based on the row selection signal yj among the row data output from the processing elements 11_ (N-1) 0 to 11_ (N-1) (N-1) of the image processing unit 1. The data of the selected row is further calculated in the column direction. The column adder 2 outputs the calculation result to the outside of the image moment sensor as a signal SOUT indicating the moment amount.

Next, the operation of the image moment sensor according to the first embodiment will be described.
Here, the case where the image processing unit 1 is 8 × 8 pixels and the first moment amount is acquired will be described.

The first moment amount is expressed by the following equation 10 according to equation 9 .

In order to obtain the first moment amount according to Equation 10 , the image processing unit 1 may generate patterns as shown in FIGS. The pattern shown in FIG. 11A is a pattern for obtaining a coefficient of 2 to the 0th power in the case of i = 0 shown in Equation 10 , that is. The column selection signals x0 [0] to x0 [7] for generating such a pattern are “01010101”.

The pattern shown in FIG. 11B is a pattern for obtaining a coefficient of the power of 2 in the case of i = 1 shown in Equation 10 , that is. The column selection signals x1 [0] to x1 [7] for generating such a pattern are “00110011”.

The pattern shown in FIG. 11C is a pattern for obtaining the coefficient of the square of 2 when i = 2 shown in Formula 10 . The column selection signals x2 [0] to x2 [7] for generating such a pattern are “00001111”.

The pattern shown in FIG. 11D is a pattern for obtaining a coefficient of 2 3 when i = 3 shown in Expression 10 . The column selection signals x3 [0] to x3 [7] for generating such a pattern are “00000000”.

  The signal processing unit 3 performs image processing on column selection signals x0 [0] to x0 [7] to x3 [0] to x3 [7] for generating patterns as shown in FIGS. Supply to part 1. By calculating the logical product of these patterns and the image data I (x, y), and adding the partial sums for the obtained patterns, the first moment amount can be obtained.

  As shown in FIG. 12, the FIFOs 12_0 to 12_7 receive the column selection signals x0 [0] to x3 [7] to x0 [7] to x3 [7] supplied from the signal processing unit 3 at time t20 shown in FIG. In the order of supply.

  As shown in FIG. 13, when the clock signal φ [0] supplied from the signal processing unit 3 rises at time t21, the FIFO 12_0 sends the column selection signal to the processing elements 13_00 to 13_07 in synchronization with the rise. x0 [0] is supplied.

The input image data I (x, y) is converted into image data as shown in FIG. 14A, and the addition operation in the processing elements 13_04 to 13_74 is shown in FIGS. In the figure, D _{04 to} D ₇₄ indicate the values of the processing elements 13_04 to 13_74, and C _{14 to} C ₇₄ indicate the carry of each of the processing elements 13_04 to 13_74.

  In the processing element 13_04, the PD 101 converts it into a light detection signal having a signal level corresponding to the light intensity of the image data I (1,1). The binarization circuit 102 converts the light detection signal into binary data “0” by comparing the signal level of the light detection signal converted by the PD 101 with the supplied luminance threshold.

  The AND circuit 103 of the processing element 13_04 blocks the output of the binary data “0” converted by the binarization circuit 102 to the FA 104 because the column selection signal x0 [0] = 0, and the FA 104 of the processing element 13_04. The data “0” is output to.

The FA 104 of the processing element 13_04 adds the data “0” output from the AND circuit 103 and carry Ci = 0, and obtains data D ₀₄ = 0 and carry C ₀₄ = 0. Then, as shown in FIG. 15A, the FA 104 of the processing element 13_04 supplies the acquired data D ₀₄ = 0 to the processing element 13_14, and supplies the acquired carry C ₁₄ = 0 as the carry Co to the DFF 105. .

The same applies to the processing elements 13_00 to 13_03 and 13_05 to 13_07. Accordingly, the FA 104 of the processing elements 13_00 to 13_07 supplies D _{00 to} D ₀₇ = “00000000” to the processing elements 13_10 to 13_17, respectively.

  As shown in FIG. 13, when the clock φ [1] generated by the delay circuit 11_0 rises at the time t22 after the delay time td, the FIFO 12_1 selects the column in synchronization with the rise of the clock φ [1]. The signal x0 [1] = 1 is supplied to the processing elements 13_10 to 13_17.

  In the processing element 13_14, the light intensity of the image data I (1,4) is substantially “0”, so that the signal level of the light detection signal converted by the PD 101 is also substantially “0”. The binarization circuit 102 converts this photodetection signal into binary data “0”.

  The AND circuit 103 outputs the binary data “0” converted by the binarization circuit 102 to the FA 104 because the column selection signal x0 [1] = 1.

The FA 104 of the processing element 13_14 has already been supplied with data D ₀₄ = 0 from the processing element 13_04. Therefore, the FA 104 of the processing element 13_14 adds the data D ₀₄ = 0, the data D ₁₄ = 0 output from the AND circuit 103, and the carry Ci = 0 supplied from the DFF 105, and adds the data D _{Get 14} = 0 and carry C ₁₄ = 0. Then, as shown in FIG. 15B, the FA 104 of the processing element 13_14 supplies the acquired data D ₁₄ = 0 to the processing element 13_24, and supplies the acquired carry C ₁₄ = 0 as the carry Co to the DFF 105. .

The same applies to the processing elements 13_10 to 13_13 and 13_15 to 13_17. Accordingly, the FA 104 of the processing elements 13_10 to 13_17 supplies D _{10 to} D ₁₇ = “00000000” to the processing elements 13_20 to 13_27, respectively.

  As shown in FIG. 13, when the clock signal φ [2] generated by the delay circuit 11_1 rises at time t23, the FIFO 12_2 synchronizes with the rise of the clock signal φ [2] and the column selection signal x0 [2]. = 0 is supplied to the processing elements 13_20 to 13_27.

The FA 104 of the processing element 13_24 adds the data D ₁₄ = 0 supplied from the processing element 13_14, the data D ₂₄ = 0 output from the AND circuit 103, and the carry Ci = 0 supplied from the DFF 105. Data D ₂₄ = 0 and carry C ₂₄ = 0 are acquired. Then, as shown in FIG. 15C, the FA 104 of the processing element 13_24 supplies the acquired data D ₂₄ = 0 to the processing element 13_34, and supplies the acquired carry C ₂₄ = 0 as the carry Co to the DFF 105. .

The same applies to the processing elements 13_20 to 13_23 and 13_25 to 13_27. Accordingly, the FA 104 of the processing elements 13_20 to 13_27 supplies D _{20 to} D ₂₇ = “00000000” to the processing elements 13_30 to 13_37, respectively.

  As shown in FIG. 13, when the clock signal φ [3] generated by the delay circuit 11_2 rises at time t24, the FIFO 12_3 synchronizes with the rise of the clock signal φ [3], and the column selection signal x0 [3] = 1 is supplied to the processing elements 13_30 to 13_37.

The FA 104 of the processing element 13_34 adds the data D ₂₄ = 0 supplied from the processing element 13_24, the data D ₃₄ = 1 output from the AND circuit 103, and the carry Ci = 0 supplied from the DFF 105. Data D ₃₄ = 1 and carry C ₃₄ = 0 are acquired. Then, as shown in FIG. 15D, the FA 104 of the processing element 13_34 supplies the acquired data D ₃₄ = 1 to the processing element 13_44, and supplies the acquired carry C ₃₄ = 0 as the carry Co to the DFF 105. .

The same applies to the processing elements 13_30 to 13_33 and 13_35 to 13_37. Therefore, the FA 104 of the processing elements 13_30 to 13_37 supplies D _{30 to} D37 = “00001100” to the processing elements 13_40 to 13_47, respectively.

  As shown in FIG. 13, when the clock signal φ [4] generated by the delay circuit 11_3 rises at time t25, the FIFO 12_4 synchronizes with the rising edge of the clock signal φ [4] and the column selection signal x0 [4]. = 0 is supplied to the processing elements 13_40 to 13_47.

The FA 104 of the processing element 13_44 adds the data D ₃₄ = 1 supplied from the processing element 13_34, the data D ₄₄ = 0 output from the AND circuit 103, and the carry Ci = 0 supplied from the DFF 105. , Data D ₄₄ = 1 and carry C ₄₄ are acquired. Then, as shown in FIG. 15E, the FA 104 of the processing element 13_44 supplies the acquired data D ₄₄ = 1 to the processing element 13_54, and supplies the acquired carry C ₄₄ = 0 as the carry Co to the DFF 105. .

The same applies to the processing elements 13_40 to 13_43 and 13_45 to 13_47. Accordingly, the FA 104 of the processing elements 13_40 to 13_47 supplies D _{40 to} D ₄₇ = “00001100” to the processing elements 13_50 to 13_57, respectively.

  As shown in FIG. 13, when the clock signal φ [5] generated by the delay circuit 11_4 rises at time t26, the FIFO 12_5 synchronizes with the rise of the clock signal φ [5] and the column selection signal x0 [5]. = 1 is supplied to the processing elements 13_50 to 13_57.

The FA 104 of the processing element 13_54 adds the data D ₄₄ = 1 supplied from the processing element 13_44, the data D ₅₄ = 1 output from the AND circuit 103, and the carry Ci = 0 supplied from the DFF 105. , Data D ₅₄ = 0 and carry C ₅₄ = 1 are acquired. Then, as shown in FIG. 15F, the FA 104 of the processing element 13_54 supplies the acquired data D ₅₄ = 0 to the processing element 13_64, and supplies the acquired carry C ₅₄ = 1 as the carry Co to the DFF 105. .

The same applies to the processing elements 13_50 to 13_53 and 13_55 to 13_57. Accordingly, the FA 104 of the processing elements 13_50 to 13_57 supplies D _{50 to} D ₅₇ = “00110000” to the processing elements 13_60 to 13_67, respectively.

  As shown in FIG. 13, when the clock signal φ [6] generated by the delay circuit 11_5 rises at time t27, the FIFO 12_6 synchronizes with the rise of the clock signal φ [6] and the column selection signal x0 [6]. = 0 is supplied to the processing elements 13_60 to 13_67.

The FA 104 of the processing element 13_64 adds the data D ₅₄ = 0 supplied from the processing element 13_45, the data D ₆₄ = 0 output from the AND circuit 103, and the carry Ci = 0 supplied from the DFF 105. Data D ₆₄ = 0 and carry C ₆₄ = 0 are acquired. Then, as shown in FIG. 15G, the FA 104 of the processing element 13_64 supplies the acquired data D ₆₄ = 0 to the processing element 13_74, and supplies the acquired carry C ₆₄ = 0 as the carry Co to the DFF 105. .

The same applies to the processing elements 13_60 to 13_63 and 13_65 to 13_67. Accordingly, the FA 104 of the processing elements 13_60 to 13_67 supplies D _{60 to} D ₆₇ = “00110000” to the processing elements 13_70 to 13_77, respectively.

  As shown in FIG. 13, when the clock signal φ [7] generated by the delay circuit 11_6 rises at time t28, the FIFO 12_7 synchronizes with the rise of the clock signal φ [7] and the column selection signal x0 [7]. = 1 is supplied to the processing elements 13_70 to 13_77.

The FA 104 of the processing element 13_74 adds the data D ₆₄ = 0 supplied from the processing element 13_64, the data D ₇₄ = 0 output from the AND circuit 103, and the carry Ci = 0 supplied from the DFF 105. , Data D ₇₄ = 0 and carry C ₇₄ = 0 are acquired. Then, as shown in FIG. 15 (h), the FA 104 of the processing element 13_74 supplies the acquired data D ₇₄ = 0 to the column adder 2, and supplies the acquired carry C ₇₄ = 0 as the carry Co to the DFF 105. To do.

The same applies to the processing elements 13_70 to 13_73 and 13_75 to 13_77. Therefore, the FA 104 of the processing elements 13_70 to 13_77 supplies D _{70 to} D ₇₇ = “00110000” to the column adder 2 as shown in FIG.

  In this way, when the column selection signals x0 [0] to x0 [7] are supplied, the image processing unit 1 calculates the partial sum of the image data as shown in FIG.

  Then, the image processing unit 1 supplies a calculation result as shown in FIG. 14B-3 to the column addition unit 2 for each row. The column addition unit 2 selects a row based on the row selection signal yj supplied from the signal processing unit 3, and sequentially adds the partial sums output from the selected row. Then, the column addition unit 2 outputs data indicating a coefficient of 2 to the 0th power as the addition result.

  Further, as shown in FIG. 13, at time t25, the clock signal φ [0] supplied from the signal processing unit 3 rises, and the FIFO 12_0 selects column selections for the processing elements 13_00 to 13_07, respectively, in synchronization with the rise. The signal x1 [0] = 0 is supplied.

  As shown in FIG. 13, at time t26, the clock signal φ [1] supplied from the delay circuit 11_1 rises, and the FIFO 12_1 synchronizes with the rise to the processing elements 13_10 to 13_17, respectively, to the column selection signal x1. [1] = 0 is supplied.

  Similarly, the FIFO 12_2 supplies the column selection signal x1 [2] = 1 to the processing elements 13_20 to 13_27, respectively, at time t27. The FIFO 12_3 also supplies the column selection signal x1 [3] = 1 to the processing elements 13_30 to 13_37, respectively, at time t28.

  FIFOs 12_3 to 12_7 also have x0 [3] = 1 as processing elements 13_30 to 13_37, x0 [4] = 0 as processing elements 13_40 to 13_47, and x0 [5] = 0 as processing elements 13_50 to 13_57, x0, respectively. [6] = 1 is sequentially supplied to the processing elements 13_60 to 13_67, and x0 [7] = 1 is sequentially supplied to the processing elements 13_70 to 13_77 as time passes.

  Accordingly, as shown in FIG. 16C-1, based on the column selection signal x1 supplied from the signal processing unit 3, the processing elements 13_20 to 13_27 in the third column and the processing elements 13_30 in the fourth column To 13_37, the sixth column processing elements 13_50 to 13_57, and the eighth column processing elements 13_70 to 13_77 are selected.

  When these processing elements are selected, each selected processing element obtains a partial sum of the image data I (x, y) as shown in FIG. 16 (c-2), and FIG. 16 (c-3). As shown, the obtained partial sum is supplied to the column adder 2.

  The column addition unit 2 selects a row based on the row selection signal y1 supplied from the signal processing unit 3, and sequentially adds the partial sums output from the selected row. Then, the column addition unit 2 outputs data indicating a coefficient of the power of 2 as the addition result.

  Next, as shown in FIG. 16 (d-1), based on the column selection signal x2 supplied from the signal processing unit 3, the processing elements 13_40 to 13_47 in the fifth column and the processing elements in the sixth column 13_50 to 13_57, the seventh column processing elements 13_60 to 13_67, and the eighth column processing elements 13_70 to 13_77 are selected.

  When these processing elements are selected, the selected processing elements 13_40 to 13_47, 13_50 to 13_57, 13_60 to 13_67, and 13_70 to 13_77 are converted into image data I (x, The partial sum of y) is obtained, and the obtained partial sum is supplied to the column adder 2 as shown in FIG.

  The column adder 2 selects a row based on the row selection signal y2 supplied from the signal processor 3, and sequentially adds the partial sums output from the selected row. Then, the column addition unit 2 outputs data indicating the coefficient of the square of 2 as the addition result.

  Next, as shown in FIG. 16 (e-1), the FIFOs 12_0 to 12_7 convert the column selection signals x3 [0] to x3 [7] = “00000000” supplied from the signal processing unit 3 into the respective processing elements 13_xy ( x = 0 to 7, y = 0 to 7). The AND circuit 103 of each processing element 13_xy cuts off the supply of the binary data output from the binarization circuit 102 to the FA 104 and supplies “0” to the FA 104.

  As shown in FIG. 16E-2, each processing element 13_xy adds the value supplied from the processing element on the left and the carry Co, and supplies the added value to the processing element on the right. Then, each of the processing elements 13_70 to 13_77 supplies the addition result to the column addition unit 2 as illustrated in FIG.

  The column addition unit 2 selects a row based on the row selection signal y3 supplied from the signal processing unit 3, and sequentially adds the partial sums output from the selected row. Then, the column addition unit 2 outputs data indicating a coefficient of 2 to the cube as the addition result.

  In this way, the data of each processing element 13_xy is cleared as shown in FIGS. 16 (f-1) to (f-3).

  As shown in FIG. 13, at time t25, the FIFO 12_4 supplies the column selection signal x0 [0] = 0 to the processing element 40_13_47 and executes the addition operation. However, in the processing elements 13_00 to 13_07, the addition operation is Even when the column selection signal x1 [0] = 0 is supplied, the processing elements 13_00 to 13_07 can execute the addition operation. Thus, since the image processing unit 1 is configured by a variable pipeline, the image processing unit 1 can perform a plurality of addition operations in parallel, and can calculate a moment amount at a higher speed.

  Here, the operation speed when the image moment sensor is configured by the variable-length pipeline is compared with the operation speed when the image moment sensor is not configured. If the delay time per stage of each processing element 13_xy is 0.5 ns and the number of stages (number of columns) is 240, the operating frequency is 8.3 MHz without a variable-length pipeline. On the other hand, when the external control signal is 100 MHz, the operation speed becomes 12 times as compared with the case without the provision of the 12-stage variable-length pipeline domino circuit.

  In addition, since the image moment sensor is equipped with a variable-length pipeline domino circuit, even if the frequency of the external control signal changes or the period is not stabilized due to an interrupt, etc., it is always possible to change the hardware without changing the hardware. Optimal operating speed can be obtained.

As described above, according to the first embodiment, the image moment sensor is obtained by multiplying each image data I (x, y) by the column selection signal x _i and adding the calculation result in the row direction. The calculation result is multiplied by the row selection signal yj and added in the column direction to obtain the moment amount of the image data I (x, y).

  Therefore, a configuration for supplying the row selection signal yj directly to the image data I (x, y) is not necessary, and the configuration of the pixel circuit can be simplified. In addition, since it is not necessary to calculate partial sums for all combinations of i and j, the calculation processing is reduced and the calculation time can be shortened. That is, the moment amount calculation can be speeded up.

  The FA 104 of each processing element 13_xy is configured by a dynamic NMOS circuit, and each dynamic NMOS circuit is connected in multiple stages by a domino logic (self-timed domino) circuit. Accordingly, a reduction in area and power saving can be realized.

  In particular, by reducing the area of each processing element having a calculation function for each pixel, each processing element 13_xy can be reduced, and if each processing element 13_xy is reduced, the resolution can be increased and the sensitivity can be increased. It can also be improved.

  Further, the column selection signal xi is supplied to each processing element 13_xy in accordance with the clock timing of the domino logic circuit, and the image processing unit 1 is configured by a variable-length pipeline, so that the moment amount can be calculated at high speed. It becomes like this. Each processing element 13_xy of the image processing unit 1 can always perform an operation at an optimum operation speed with respect to the timing of the external control signal supplied from the external circuit.

(Embodiment 2)
The second to fifth embodiments relate to an image moment measuring apparatus that measures the moment amount of a target image using the image moment sensor according to the first embodiment.

  First, the image moment measuring apparatus according to the second embodiment is configured to acquire the moment amount for each target image when there are a plurality of target images for which the moment amount is obtained.

  When there are a plurality of target images g11 and g12 as target images for obtaining the moment amount, as shown in FIG. 17B, a plurality of rectangular regions Sp_11, Sp_12, and Sp_13 are displayed as shown in FIG. Divide the data to show the moment amount. Then, if the obtained data is added and calculated outside the image moment sensor according to the first embodiment, the respective moment amounts of the target images g11 and g12 can be obtained.

  The image moment measuring apparatus according to the second embodiment is configured to acquire the moment amount in this way.

  As shown in FIG. 18, the image moment measuring apparatus 20 according to the second embodiment includes an image moment sensor 21 and a control unit 22.

  The control unit 22 supplies information necessary for processing to the image moment sensor 21 to control the image moment sensor 21, and acquires data related to the moment amount from the image moment sensor 21. When the respective rectangular areas Sp_11, Sp_12, and Sp_13 of the target images g11 and g12 are known, the control unit 22 sequentially supplies the area information to the image moment sensor 21.

  The image moment sensor 21 is the same as that of the first embodiment. As shown in FIG. 17A, the signal processing unit 3 of the image moment sensor 21 selects a column for a rectangular area based on the supplied area information when the area information of the rectangular areas Sp_11, Sp_12, and Sp_13 is known. A signal is generated, a logical product of the generated column selection signal and the column selection signals xi [0] to [N-1] is calculated, and the calculated value is supplied to the image processing unit 1.

  Further, the signal processing unit 3 generates a row selection signal for the rectangular region based on the supplied region information, calculates a logical product of the generated row selection signal and the row selection signal yj, and calculates the calculated value. This is supplied to the column adder 2.

Control unit 22, for each supplies area information, acquires the matrix data dy output from the column adder unit 2 performs calculation of the moment amount m _pq according to Equation 1, adds the computed moment amount m _pq .

  When the regions of the respective rectangular regions Sp_11, Sp_12, Sp_13 of the target images g11, g12 are unknown, the control unit 22 divides the entire region into blocks of a predetermined size as shown in FIG. The total value of each block is obtained.

  As illustrated in FIG. 19B, the control unit 22 acquires region information of the rectangular regions Sp_11, Sp_12, and Sp_13 from the total value of each block by labeling processing.

  The control unit 22 performs the labeling process as follows. The control unit 22 first raster scans each block from the upper left, and if the sum of the labels not added is determined to be a certain value or more, the left and upper blocks are examined. Add a label with the same value as that label. When the label is not attached, the control unit 22 attaches a new label.

  The control unit 22 pays attention to a certain block. When the left block, the upper block, and the target block are connected, the control unit 22 checks the label value of each block. When all the three blocks have the same label, the control unit 22 performs raster scanning until the next sum is determined to be a block having a certain value or more.

  When a different label is attached to either the target block and the left block or the upper block, the control unit 22 compares the label values of the left block and the upper block and attaches a label with a smaller value to the target block. To do.

  The control unit 22 performs the same operation with a block having a label that has not been assigned as a new block of interest, and checks the connectivity of each block for each target block. If the total does not exceed a certain value, the control unit 22 does not set the block as a target area.

  For example, if the total sum of blocks is a small value less than a preset value, the block may be due to noise. In such a case, the control unit 22 excludes the block from the target area for acquiring the moment amount.

  As described above, according to the second embodiment, when there are a plurality of target images, the control unit 22 obtains data indicating the moment amount by dividing into a plurality of rectangular regions Sp_11, Sp_12, and Sp_13. This data is added and calculated.

  Therefore, the respective moment amounts of the respective target images can be acquired. In addition, when the region information of the target region is unknown, the control unit 22 obtains the block sum and performs the labeling process, so that the region information can be acquired and erroneous processing due to noise can be prevented. it can.

  Further, even when the number of times of acquiring the moment amount is increased by acquiring the moment amount in a plurality of regions, the moment amount of the target image can be obtained in a short time by using the image moment sensor according to the first embodiment. Can be acquired.

(Embodiment 3)
The image moment measuring apparatus according to the third embodiment is configured to acquire a moment amount of a specific image as a target image from a plurality of images having different brightnesses.

  For example, as shown in FIG. 20, it is assumed that images g21, g22, and g23 exist in the entire image g20, and the luminance values thereof are v1, v2, and v3 (v1 <v2 <v3), respectively. In this case, if a luminance threshold value is set and binarized with respect to the luminance of the target images g21, g22, and g23, a binary image can be acquired by selecting an image for each luminance. It is also possible to acquire the amount of moment using the image of No. 1 as the target image.

  For this reason, the image moment measuring apparatus 20 according to the third embodiment has the configuration of the first embodiment, and the control unit 22 includes a memory (not shown), and luminance thresholds Vth1, Vth2 (v1 <Vth1 <v2 <Vth2). <V3) and the acquired moment amount are stored. The brightness threshold values Vth1 and Vth2 may be set in advance if the brightness values v1, v2, and v3 are known, and may be variable if they are unknown.

  Further, the image moment measuring apparatus 20 according to the third embodiment is configured such that the control unit 22 supplies the luminance threshold values Vth1 and Vth2 to the binarization circuit 102 of each processing element 13_xy.

  When the target image is g22 and the moment amount of the target image g22 is acquired, the control unit 22 reads the luminance threshold value Vth1 from the memory and supplies it to the binarization circuit 102 of each processing element 13_xy. Since v1 <Vth1 <v2 <v3, the image processing unit 1 acquires a binary image (G22 + G23) as shown in FIG.

  As in the first embodiment, the signal processing unit 3 supplies the image processing unit 1 with a column selection signal for acquiring the moment amount. Each processing element 13_xy of the image processing unit 1 performs arithmetic processing on the image in the row direction. The signal processing unit 3 supplies the row selection signal yj to the column addition unit 2. The control unit 22 acquires a signal SOUT indicating the moment amount from the column addition unit 2. The control unit 22 calculates the moment amount m (g22 + g23) of the image (g22 + g23) based on the acquired signal SOUT.

  Next, the control unit 22 reads the luminance threshold value Vth2 from the memory and supplies it to the binarization circuit 102 of each processing element 13_xy. Since v1 <v2 <Vth2 <v3, the image processing unit 1 acquires a binary image G23 as shown in FIG.

  As in the first embodiment, the signal processing unit 3 supplies the image processing unit 1 with a column selection signal for obtaining the moment amount, and supplies the column addition unit 2 with a row selection signal yj. The control unit 22 acquires the signal SOUT indicating the moment amount from the column addition unit 2, and calculates the moment amount m (g23) of the image g23 based on the acquired signal SOUT.

  The control unit 22 obtains the difference between the acquired moment amounts m (g22 + g23) and m (g23). The difference between the moment amount m (g22 + g23) and m (g23) is the moment amount m (g22) of the image g22. Therefore, the control unit 22 acquires a virtual binary image G22 of the target image g22 as shown in FIG. 21C, and based on the binary image G22, the moment amount m (g22) of the target image g22. You will get the same results as you get.

  When the target image is g21 and the moment amount m (g21) of the target image g21 is acquired, the control unit 22 acquires and acquires the moment amount m (g21 + g22 + g23) of the image g20 shown in FIG. The difference between the calculated moment amount m (g21 + g22 + g23) and m (g22 + g23) is obtained. In this way, the moment amount m (g21) of the target image g21 can be acquired. That is, the control unit 22 can individually acquire the moment amounts of all the images g21, g22, and g23 from the image g20 shown in FIG.

  As described above, according to the third embodiment, the control unit 22 is obtained by supplying the luminance threshold to the image moment sensor 21 and setting the luminance threshold for a plurality of images having different brightness. The moment amount of a specific image is calculated based on a plurality of binary images.

  Therefore, the moment amount of the target image can be acquired from a plurality of images with different brightness. Further, by performing such a process, even when the number of times of acquiring the moment amount is increased, the moment amount of the target image can be acquired in a short time by using the image moment sensor according to the first embodiment. .

(Embodiment 4)
The image moment measuring apparatus according to the fourth embodiment performs binarization at different timings during exposure of a PD (photodetector) while keeping the luminance threshold constant, and calculates a moment amount.

  Even if the luminance threshold is not changed as in the third embodiment, images with different brightness can be acquired by performing binarization at different timings during exposure of the PD 101.

  The moment amounts of these images can be acquired for each output timing of the light detection signal of the PD 101.

  Moreover, there is an advantage that the dynamic range can be widened by performing such processing. However, since the moment amount is calculated during exposure, it is necessary to calculate the moment amount at a high speed in order to increase the gray scale gradation.

  Each processing element 13_xy of the image moment sensor according to the fourth embodiment includes the binarization circuit 102 having the configuration shown in FIG. 22 as well as the configuration of the first embodiment. The binarization circuit 102 includes transistors Q41 and Q42, a capacitor C11, and a comparator 131.

  The PD 101 is composed of a photodiode. When light is received, a photocurrent Ipd having a current amount corresponding to the light intensity of the received light flows. The cathode of the photodiode is connected to a power source, and the anode is grounded.

  The comparator 131 converts the photodetection signal Vpd of the PD 101 into a binarized signal, and a reference voltage Vref is applied to the − terminal (inverting input terminal). The comparator 131 outputs a signal of “1” level when the signal level of the photodetection signal Vpd of the PD 101 is higher than the reference voltage Vref.

  The transistor Q41 is a transistor for connecting the + terminal of the comparator 131 and the cathode of the photodiode (PD101), and is an NMOS transistor.

  The drain of the transistor Q41 is connected to the + terminal (non-inverting input terminal) of the comparator 131, and the source is connected to the cathode of the photodiode (PD101).

  A signal sam is supplied to the gate of the transistor Q41. When the level of the signal sam becomes “1”, the transistor Q41 is turned on to connect the + terminal of the comparator 131 and the cathode of the photodiode (PD101).

  The transistor Q42 is a transistor for applying a power supply voltage to the + terminal of the comparator 131, and is composed of an NMOS transistor. The drain of the transistor Q42 is connected to the power supply, and the source is connected to the + terminal of the comparator 131.

  A signal res is supplied to the gate of the transistor Q42. When the level of the signal res becomes “1”, the transistor Q42 is turned on and a voltage is applied to the + terminal of the comparator 131.

  The capacitor C11 is for holding the voltage at the + terminal of the comparator 131 (sample hold).

Next, the operation of the image moment measuring apparatus 20 according to the fourth embodiment will be described.
As shown in FIG. 23, before the time t40, the transistor Q41 is turned off when the gate is supplied with the signal sam of “0”, and disconnects between the positive terminal of the comparator 131 and the cathode of the photodiode.

  Further, the transistor Q42 is turned on when the gate is supplied with the signal res of “1” level, and applies a voltage to the + terminal of the comparator 131.

  When the signal level of the signal sam becomes “1” at time t40, the transistor Q41 is turned on to connect the + terminal of the comparator 131 and the cathode of the photodiode (PD101).

  At time t41, when the signal level of the signal res supplied to the gate of the transistor Q42 becomes “1”, the transistor Q42 is turned off and the application of the voltage to the + terminal of the comparator 131 is stopped.

  When the PD 101 receives light, a photocurrent Ipd flows through the PD 101. When the photocurrent Ipd flows, the signal level of the photodetection signal Vpd of the PD 101 is lowered. The amount of photocurrent Ipd flowing through the PD 101 is determined by the light intensity of light received by the PD 101, and the rate at which the signal level of the photodetection signal Vpd of the PD 101 decreases is based on the amount of photocurrent Ipd flowing through the PD 101. It is determined.

  If the input image g (t40) is a grayscale image with different gradations depending on the position as shown in FIG. 23, the light intensity of the light received by the PD 101 varies depending on the position of the processing element 13_xy.

  In the case of the central processing element 13_44, as indicated by the characteristic line L13_44 in FIG. 23, the light intensity of the light received by the PD 101 is large, and the current amount of the photocurrent Ipd is also large. Therefore, the photodetection signal Vpd decreases most quickly.

  As indicated by the characteristic line L13_33 in FIG. 23, in the case of the processing element 13_33, the light intensity of the light received by the PD 101 is smaller than that of the PD 101 of the processing element 13_44, and the amount of photocurrent Ipd is also small. Therefore, the light detection signal Vpd falls later than the processing element 13_44.

  As indicated by the characteristic line L13_22 in FIG. 23, in the case of the processing element 13_22, the light intensity of the light received by the PD 101 is the smallest and the current amount of the photocurrent Ipd is also the smallest. Therefore, the photodetection signal Vpd decreases most slowly.

  Assume that the binary image obtained at time t42 is a binary image G (t42) as shown in FIG. At this time, the control unit 22 sends a command to the image moment sensor 21, the signal processing unit 3 supplies a column selection signal to the image processing unit 1, and a row selection signal yj for acquiring the moment amount is sent to the column addition unit 2. When supplied, the control unit 22 acquires a signal SOUT indicating the moment amount of the binary image G (t42) from the column addition unit 2. The control unit 22 reconstructs the binary image G (t42) based on the acquired signal SOUT.

  Similarly, it is assumed that the binary image obtained at time t43 is a binary image G (t43) as shown in FIG. At this time, the control unit 22 sends a command to the image moment sensor 21, the signal processing unit 3 supplies a column selection signal to the image processing unit 1, and a row selection signal yj for acquiring the moment amount is sent to the column addition unit 2. Supply. The control unit 22 acquires a signal SOUT indicating the moment amount of the binary image G (t43) from the column addition unit 2. The control unit 22 reconstructs the binary image G (t43) based on the acquired signal SOUT.

  Similarly, the binary image obtained at time t44 is assumed to be a binary image G (t44) as shown in FIG. At this time, the control unit 22 sends a command to the image moment sensor 21, the signal processing unit 3 supplies a column selection signal to the image processing unit 1, and a row selection signal yj for acquiring the moment amount is sent to the column addition unit 2. Supply. The control unit 22 acquires a signal SOUT indicating the moment amount of the binary image G (t44) from the column addition unit 2. The control unit 22 reconstructs the binary image G (t44) based on the acquired signal SOUT.

  Then, the control unit 22 combines the binary images G (t42), G (t43), and G (t44) to form a reconstructed image G (t40).

  As described above, according to the fourth embodiment, the control unit 22 sends a command to the image moment sensor 21 at different timings during exposure of the PD (photodetector) while keeping the luminance threshold value constant. The moment sensor 21 binarizes the light detection signal in accordance with the command, and calculates the moment amount.

  Therefore, even in the case of a gray scale image, the moment amount of the image can be acquired and the dynamic range can be widened. A reconstructed image can also be formed based on each binary image.

  In addition, since the moment amount of the target image can be acquired in a short time by using the image moment sensor according to the first embodiment, even if the binary image changes over time, such processing is performed. Can be performed.

(Embodiment 5)
Embodiment 5 relates to an image moment measuring device, and this image moment measuring device projects a background image and an object by projecting flashing light when the object of measurement of the moment amount overlaps the background. The image is separated.

  As shown in FIG. 24A, when the measurement object m overlaps the backgrounds b1 and b2, and the luminance of the measurement object m and the luminances of the backgrounds b1 and b2 are almost the same, the image moment sensor 21 is Then, a binary image G31 as shown in FIG. 24B is formed. As shown in FIG. 24B, in the formed binary image G31, the image of the measurement object m and the background image overlap, and it is difficult to separate these images. If the image of the measurement object m and the images of the backgrounds b1 and b2 cannot be separated, it is difficult to obtain the moment amount of the measurement object m.

  In this case, as shown in FIG. 24 (c), if the image G32 as shown in FIG. 24 (d) is obtained by projecting the blinking light from the light source device 23, both of the images G31 and G32 are obtained. Due to the difference, the image of the measurement object m and the images of the backgrounds b1 and b2 can be separated. The image moment measuring apparatus according to the fifth embodiment is configured based on such a concept.

FIG. 25 shows the configuration of the image moment measuring apparatus according to the fifth embodiment.
The image moment measuring device 20 according to the fifth embodiment includes an image moment sensor 21, a control unit 22, a light source device 23, a beam splitter 24, and a lens 25.

  The image moment sensor 21 has the configuration of the first embodiment. The light source device 23 emits blinking light based on the control signal S21 supplied from the control unit 22. The control signal S21 is a pulse signal whose signal level is switched between “1” and “0” at a constant cycle. The light source device 23 is turned on when the signal level of the supplied control signal S21 is “1”, and is turned off when the signal level of the control signal S21 is “0”.

  The beam splitter 24 is for separating outgoing light and incident light. The beam splitter 24 guides the flashing light emitted from the light source device 23 to be emitted, and guides the incident light to the image moment sensor 21. The lens 25 is for diffusing the light to be projected.

  The control unit 22 supplies a control signal S21 to the light source device 23, and controls the image moment sensor 21 to acquire the moment amount of the image by the received light. The control unit 22 controls the image moment sensor 21 to acquire the moment amount when the signal level of the supplied control signal S21 is “1” and “0”.

Next, the operation of the image moment measuring apparatus 20 according to the fifth embodiment will be described.
The controller 22 supplies the control signal S21 as shown in FIG. The light source device 23 is lit when the signal level of the supplied control signal S21 is “1”.

  The light emitted from the light source device 23 is emitted through the beam splitter 24 and the lens 25, and is projected onto the measurement object m and the backgrounds b1 and b2.

  The light projected on the measurement object m and the backgrounds b1 and b2 is reflected, and the reflected light enters the image moment sensor 21 via the lens 25 and the beam splitter 24.

  As shown in FIG. 26B, when the light source device 23 is turned on, the image moment sensor 21 forms a binary image G31 with the received light. As shown in FIG. 26B, this binary image G31 includes a binary image of the measurement object image m and a binary image of the backgrounds b1 and b2. The image moment sensor 21 calculates the moment amount of the binary image G31 and supplies the calculated moment amount to the control unit 22.

  The light source device 23 is turned off when the signal level of the supplied control signal S21 becomes “0”.

  The image moment sensor 21 forms a binary image G32 as shown in FIG. This binary image G32 includes only the images of the backgrounds b1 and b2, and does not include the image of the measurement object m.

  The image moment sensor 21 acquires the moment amount of the binary image G32 and supplies it to the control unit 22. The control unit 22 calculates the difference between the moment amount of the supplied binary image G31 and the moment amount of the binary image G32, and acquires the moment amount of the binary image G33, which is a difference image between the binary images G31 and G32. . This moment amount is the moment amount of the measuring object m.

  As described above, according to the fifth embodiment, the image moment measuring device 20 projects the flashing light, and the image moment sensor 21 determines that the signal level of the supplied control signal is “1” and “ When 0 ", the moment amounts of the binary images G31 and G32 are acquired. The control unit 22 obtains the moment amount of the measurement object m by obtaining the difference between the moment amounts of the two binary images G31 and G32.

  Accordingly, even when the image of the measurement object m and the images of the backgrounds b1 and b2 overlap and the moment amount of the measurement object m cannot be directly acquired, the moment amount of the measurement object m can be acquired. .

In carrying out the present invention, various forms are conceivable and the present invention is not limited to the above embodiment.
For example, in the second to fifth embodiments, the image moment measuring device has been described. Among these, Embodiments 2 to 4 may include a control unit in the image moment sensor so that the image moment sensor executes the above-described processing.

It is a block diagram which shows the structure of the image moment sensor which concerns on Embodiment 1 of this invention. It is a figure which shows the algorithm of the image moment sensor shown in FIG. 2 is a timing chart showing clock signals generated by each delay circuit shown in FIG. 1. It is a figure which shows the column selection signal which each FIFO stored, when the signal processing part shown in FIG. 1 supplied the column selection signal. It is a figure which shows a column selection signal in the remainder which each FIFO shown in FIG. 1 stored when time passed. It is a block diagram which shows the structure of each processing element shown in FIG. It is a circuit diagram which shows the structure of FA and DFF shown in FIG. It is a timing chart which shows operation | movement of FA and DFF shown in FIG. It is the figure which shows the example which connected the dynamic NMOS circuit directly, and the timing chart which shows the operation | movement. 2 is a diagram showing an example in which a dynamic NMOS circuit is provided with a delay circuit, and a timing chart showing the operation thereof. FIG. It is a figure which shows the pattern for acquiring the amount of primary moments. It is a figure which shows the column selection signal which each FIFO stored, when a column selection signal is supplied from a signal processing part as 8x8 pixel. 13 is a timing chart showing the operation of the variable pipeline when each FIFO stores the column selection signal shown in FIG. It is a figure which shows concretely operation (1) in the case of acquiring the amount of primary moments of an input picture. It is a figure which shows an addition operation concretely. It is a figure which shows concretely operation (2) in the case of acquiring the amount of primary moments of an input picture. It is a figure which shows the outline | summary of a process of the image moment measuring device which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the image moment measuring device which concerns on Embodiment 2 of this invention. It is a figure which shows the process of the image moment measuring device in case area | region information is unknown. It is a figure which shows the outline | summary of a process of the image moment measuring device which concerns on Embodiment 3 of this invention. It is a figure which shows operation | movement of the image moment measuring device which concerns on Embodiment 3. FIG. It is a circuit diagram which shows the structure of the binarization circuit with which the image moment measuring device which concerns on Embodiment 4 of this invention is provided. It is a figure which shows operation | movement of the image moment measuring device which concerns on Embodiment 4. FIG. It is a figure which shows the outline | summary of a process of the image moment measuring device which concerns on Embodiment 5 of this invention. It is a block diagram which shows the structure of the image moment measuring device which concerns on Embodiment 5 of this invention. It is a figure which shows operation | movement of the image moment measuring device shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image processing part 2 Column addition part 3 Signal processing part
11_0 to 11_ (N-2) delay circuit
12_0 ~ 12_ (N-1) FIFO
13_xy (x = 0 to N−1, y = 0 to N−1) processing element

Claims (21)

The number of rows M (M is a positive integer), the number of columns as the N (N is a positive integer), M × N number of processing elements arranged in a matrix, each processing element, the light the light received from images A column for converting the light detection signal to a signal level corresponding to the intensity, binarizing the light detection signal to generate binary data, and selecting a column necessary for obtaining the moment amount m _pq shown in Equation 1 The selection signal x ^p _i is supplied, and the processing element of the column selected based on the supplied column selection signal x ^p _i adds the binary data in the row direction, and the calculation result of the processing element of each row Respectively, an image processing unit configured to output the data dx shown in Equation 2,
The row selection for selecting the rows needed to obtain moment amount m _pq signal y ^q _j is supplied, among the output data dx from each row of the image processing unit, the supplied row selection signal y ^q _a column adder that adds the data dx output from the row selected based on _j in the column direction and outputs the data dy shown in Equation 3,
The column selection signal x ^p _i and the row selection signal y ^q _j are generated by setting a row and a column necessary for obtaining the moment amount m _pq shown in Equation 1, and the generated column selection signal x ^p a signal processing unit that supplies _i to the image processing unit and supplies the row selection signal y ^q _j to the column addition unit,
An image moment sensor.
The signal processing unit is supplied with area information indicating a rectangular area, generates a column selection signal for the rectangular area based on the supplied area information, and generates the column selection signal generated for the rectangular area and the column selection. Performs a logical product operation with the signal x ^p _i and supplies a calculated value of the logical product operation to the image processing unit, and generates a row selection signal for the rectangular region based on the region information, Performing a logical product operation on the generated row selection signal and the row selection signal y ^q _j, and supplying an operation value of the logical product operation to the column adder.
The image moment sensor according to claim 1. Each processing element of the image processing unit includes:
A light detection unit that receives light from the image, photoelectrically converts the received light into a light detection signal having a signal level corresponding to light intensity, and
A binarization unit that binarizes the light detection signal output by the light detection unit and outputs binary data;
And said column selection signal x ^p _i is supplied, on the basis of the supplied the column selection signal x ^p _i, the binary data output control unit for binarizing unit controls the output of the binary data output,
The binary data output from the binary data output control unit is added to the addition data supplied from the processing element of ((x−1), y) coordinates to generate new addition data, and the generated new data A line addition unit that supplies the addition data to a processing element of ((x + 1), y) coordinates,
The image moment sensor according to claim 1. The row adder of each processing element is
A carry data holding unit for holding the generated carry data at the fall of the clock signal supplied to the processing element of the ((x-1), y) coordinate and outputting the held carry data at the next addition; ,
The binary data output from the binary data output control unit, the binary data supplied from the processing element of ((x-1), y) coordinates, and the carry data output from the carry data holding unit are added. New addition data and carry data are generated, the generated new addition data is output to the processing element of the ((x + 1), y) coordinate, and the generated carry data is supplied to the carry data holding unit. An adder, and
The image moment sensor according to claim 3. The signal processing unit supplies a clock signal to the image processing unit,
The row addition unit of each processing element is configured by a dynamic circuit that repeatedly charges and evaluates according to a supplied clock signal and holds data added during the evaluation period by using a parasitic capacitance of the transistor,
The clock signal supplied from the signal processing unit is sequentially delayed to generate an n-th (n is an integer of 1 or more) clock signal, and the generated n-th clock signal is transmitted to each processing element in the n-th column. A clock signal delay unit for supplying to the row addition unit;
The dynamic circuit is connected in multiple stages to form the image processing unit.
The image moment sensor according to claim 4. In synchronization with the clock signal supplied from the signal processing unit or the clock signal delay unit, the column selection signal x ^p _i supplied from the signal processing unit is supplied to each processing element in the order of supply. A column selection signal supply unit;
The image processing unit is configured by a variable length pipeline configuration,
The image moment sensor according to claim 5.   The image moment according to claim 1, wherein the image processing unit, the column addition unit, and the signal processing unit are configured by integrated integrated circuits. Sensor. Each processing element of the image processing unit includes:
A light detection unit that receives light from the image, photoelectrically converts the received light into a light detection signal having a signal level corresponding to light intensity, and
A binarization unit that binarizes the light detection signal output by the light detection unit and outputs binary data;
An operation value of a logical product operation of the column selection signal generated based on the region information and the column selection signal x ^p _i is supplied, and the binarization unit outputs 2 based on the supplied operation value A binary data output control unit for controlling output of value data;
The binary data output from the binary data output control unit is added to the addition data supplied from the processing element of ((x−1), y) coordinates to generate new addition data, and the generated new data A line addition unit that supplies the addition data to a processing element of ((x + 1), y) coordinates,
The image moment sensor according to claim 2. The row adder of each processing element is
A carry data holding unit for holding the generated carry data at the fall of the clock signal supplied to the processing element of the ((x-1), y) coordinate and outputting the held carry data at the next addition; ,
The binary data output from the binary data output control unit, the binary data supplied from the processing element of ((x-1), y) coordinates, and the carry data output from the carry data holding unit are added. New addition data and carry data are generated, the generated new addition data is output to the processing element of the ((x + 1), y) coordinate, and the generated carry data is supplied to the carry data holding unit. An adder, and
The image moment sensor according to claim 8. The signal processing unit supplies a clock signal to the image processing unit,
The row addition unit of each processing element is configured by a dynamic circuit that repeatedly charges and evaluates according to a supplied clock signal and holds data added during the evaluation period by using a parasitic capacitance of the transistor,
The clock signal supplied from the signal processing unit is sequentially delayed to generate an n-th (n is an integer of 1 or more) clock signal, and the generated n-th clock signal is transmitted to each processing element in the n-th column. A clock signal delay unit for supplying to the row addition unit;
The dynamic circuit is connected in multiple stages to form the image processing unit.
The image moment sensor according to claim 9. In synchronization with the clock signal supplied from the signal processing unit or the clock signal delay unit, the column selection signal generated for the rectangular area as the operation value supplied from the signal processing unit and the column selection signal x ^p a column selection signal supply unit that supplies the operation values of the logical product operation with _i to each of the processing elements in the order of supply;
The image processing unit is configured by a variable length pipeline configuration,
The image moment sensor according to claim 10.   The image moment according to any one of claims 2, 8 to 11, wherein the image processing unit, the column addition unit, and the signal processing unit are configured by an integrated circuit. Sensor. The image moment sensor according to any one of claims 1, 3 to 7, which outputs the data dy represented by Equation (3),
A controller that obtains the moment amount m _pq by substituting the data dy output by the image moment sensor into Equation 1 and performing an operation.
An image moment measuring apparatus characterized by that. The image moment sensor according to any one of claims 2, 8 to 12, which outputs the data dy represented by Equation (3),
A controller that obtains the moment amount m _pq by substituting the data dy output by the image moment sensor into Equation 1 and performing an operation.
An image moment measuring apparatus characterized by that. The control unit sets a plurality of rectangular regions for the supplied image, sequentially supplies region information indicating the rectangular regions to the signal processing unit, and is output from the column addition unit. The data dy is acquired, and based on each data dy acquired for each area information, the moment amount is calculated according to Equation 1, and the moment acquired by calculation is calculated for each area corresponding to the supplied image. Obtaining the moment amount of the supplied image by adding the amount,
The image moment measuring apparatus according to claim 14, wherein: When the rectangular area is unknown, the control unit divides the entire area into blocks of a predetermined size, obtains a total value of each block, and performs a labeling process using the total value of each block. , Get the area information of each rectangular area,
The image moment measuring apparatus according to claim 15, wherein: The control unit supplies a plurality of luminance threshold values to the binarization unit of each processing element, acquires a moment amount for each luminance threshold value, and obtains a moment amount of a target image as a plurality of acquired moment amounts. Get by calculating the difference between
The image moment measuring device according to any one of claims 13 to 16, wherein The control unit causes the binarization unit to sequentially binarize the photodetection signals output at different timings during exposure of the photodetection unit, and obtains data dy from the column addition unit. To obtain and calculate the moment amount of the image,
The image moment measuring device according to any one of claims 13 to 17, wherein A light source that emits light;
A light projecting unit for projecting the light emitted from the light source unit to the moment amount measurement object and the background,
The image moment sensor outputs the data dy shown in Equation 3 for the image formed based on the reflected light of the light from the moment amount measurement object and the background,
The control unit supplies a blinking signal for blinking light to the light source unit to cause the light to blink, and from the image moment sensor when the light is turned on and when the light is turned off. By obtaining the output data dy shown in Equation 3 and obtaining the difference between the two moment amounts obtained based on the obtained data dy, the image of the measurement object and the background image are separated, Obtaining the amount of moment of the measurement object;
19. The image moment measuring apparatus according to any one of 13 to 18, wherein the apparatus is an image moment measuring apparatus. The number of rows M (M is a positive integer), the number of columns as the N (N is a positive integer), M × N number of processing elements arranged in a matrix, each processing element, the light the light received from images An image processing unit configured to convert to a light detection signal having a signal level corresponding to the intensity, add each binary data in the row direction , and output data dx for each row;
A column addition unit that adds data dx output from each row of the image processing unit and outputs data dy, and obtains the amount of moment of the image, the image moment sensor calculating method comprising:
Setting a row and a column necessary for obtaining the moment amount m _pq shown in Equation 4 to generate a column selection signal x ^p _i and a row selection signal y ^q _j ;
The generated column selection signal x ^p _i is supplied to each processing element of the image processing unit, the column of the processing element is selected, and the calculation result of the processing element of each row is sent to the image processing unit, respectively. Outputting the data dx shown in Formula 5 ;
The generated row selection signal y ^q _j is supplied to the column adder, and the column adder is supplied to the column adder based on the supplied row selection signal y ^q _j out of the data dx output from each row of the image processing unit. Adding data dx output from the selected row to output data dy shown in Equation 6 ;
Obtaining the data dy output from the column adder, and calculating the moment amount m _pq according to _Equation 4 ;
An image moment sensor calculation method characterized by the above.
Projecting light on the object of moment measurement and the background;
A step of calculating a moment amount of an image formed based on reflected light of the projected light according to the calculation method of the image moment sensor according to claim 20;
Turning off the light and stopping the light projection to the moment measurement object and the background;
A step of calculating a moment amount of an image formed based on reflected light of the projected light according to the calculation method of the image moment sensor according to claim 20;
The measurement object image and the background image are separated by obtaining a difference between the moment amount calculated when the light is projected and the moment amount calculated when the light projection is stopped, and the measurement is performed. Obtaining a moment amount of the object,
An image moment measuring method characterized by that.