JP4554466B2 - Power switch circuit - Google Patents

Description

  The present invention relates to a DC power supply device, and more particularly to a power switch circuit that turns on and off the supply of power to a primary battery.

Various electric devices using a primary battery as a DC power supply device are known. Such an electric device includes a primary battery, a load (power consuming device), and a power switch circuit. The power switch circuit is set to an on state in which power of the primary battery is supplied to the load or an off state in which supply of the power of the primary battery to the load is stopped by operating the operation switch. As such an electric device, for example, a buried object detection device that detects a buried object such as a reinforcing bar or a beam covered by a wall is known.
In order to suppress wasteful power consumption, a power switch circuit of an electric device using a primary battery as a DC power supply device is required to completely cut off current from the primary battery when it is set to an off state. Further, from the viewpoint of operability and cost, it is desired to use a single pole single throw switch (SPST switch) as an operation switch. The power switch circuit is required to be configured with as few parts as possible.
As a single-pole single-throw switch, it has a fixed contact and a movable contact. When a pressing force is applied to the operation unit, the movable contact contacts the fixed contact (or the movable contact moves away from the fixed contact), and the operation unit It is desirable to use a switch in which the movable contact moves away from the fixed contact (or the movable contact contacts the fixed contact) when the application of the pressing force to is stopped. Hereinafter, a state where the movable contact is in contact with the fixed contact is referred to as “on”, and a state where the movable contact is separated from the fixed contact is referred to as “off”.

Conventionally, a power switch circuit 110 shown in FIG. 9 is known. (See Non-Patent Document 1)
In the conventional power switch circuit 110, a series circuit of a PNP transistor Q111 and resistors R111 and R112 and a series circuit of resistors R113 and R114 and an NPN transistor Q112 are connected in parallel between the positive terminal and the negative terminal of the primary battery B. ing. The connection point between the resistors R113 and R114 is connected to the base terminal of the PNP transistor Q111, and the connection point between the resistors R111 and R112 is connected to the base terminal of the NPN transistor Q112. Thus, a holding circuit is configured to hold an on state in which both transistors Q111 and Q112 are in a conductive state or an off state in which both transistors are in a nonconductive state.
Further, a series circuit of resistors R115 and R116 and a capacitor C111 is connected between the positive terminal and the negative terminal of the temporary battery B. The connection point between the resistors R115 and R116 is connected to the negative terminal via the NPN transistor Q113, and the base terminal of the NPN transistor Q113 is connected to the connection point between the resistors R111 and R112 via the resistor R117. Yes. Furthermore, the connection point between the resistor R116 and the capacitor C111 is connected to the connection point between the resistors R111 and R112 via the resistor R118 and the single pole single throw switch S111. Thus, the control circuit 111 is configured to control the holding circuit from the off state to the on state or from the on state to the off state.

The conventional power switch circuit 110 operates as follows.
When the holding circuit is in the off state, the capacitor C111 is charged via the resistors R115 and R116.
When the single-pole single-throw switch S111 is turned on in this state, the capacitor C111 is discharged through the resistor R118 and the single-pole single-throw switch S111. As a result, the NPN transistor Q112 becomes conductive. When the NPN transistor Q112 is turned on, the PNP transistor Q111 and the NPN transistor Q113 are also turned on. That is, the holding circuit is turned on.
Thereafter, when the single-pole single-throw switch S111 is turned off, the capacitor C111 is discharged through the NPN transistor Q113 in a conductive state.
In this state, when the single-pole single-throw switch S111 is turned on, the capacitor C111 is charged via the PNP transistor Q111, the resistor R111, the single-pole single-throw switch S111, and the resistor R118 that are in a conductive state. As a result, NPN transistor Q112 is turned off. When NPN transistor Q112 is turned off, PNP transistor Q111 and NPN transistor Q113 are also turned off. That is, the holding circuit is turned off.
Thereafter, when the single-pole single-throw switch S111 is turned off, the capacitor C111 is charged via the resistors R115 and R116.
Thereafter, similarly, the holding circuit is set to the on state or the off state each time the single-pole single-throw switch S111 is turned on.
“EDN Japan” (Lead Business Information, March 2005, p86-p87)

The conventional power switch circuit 110 completely cuts off the current from the DC power supply device B when the holding circuit is set in the OFF state while using a single pole single throw switch as the operation switch S111.
However, the conventional power switch circuit 110 requires resistors R115 to R117, an NPN transistor Q113, and the like for charging or discharging the capacitor C111. For this reason, there is a demand for further reduction in the number of components constituting the power switch circuit 110.
The present invention has been made in view of such a point, and an object of the present invention is to provide a power switch circuit that can be configured at low cost by reducing the number of components.

A first invention of the present invention for solving the above problem is a power switch circuit as set forth in claim 1.
The present invention controls a holding circuit that holds an ON state in which power of a DC power supply device is supplied to a load or an OFF state in which supply of power of the DC power supply device to a load is stopped, and a holding circuit is controlled to be in an ON state or an OFF state. A control circuit is provided.
The holding circuit includes a first circuit in which a first type transistor and a first resistor are connected in series, a second type transistor and a second resistor connected in parallel to the DC power supply device. A second circuit connected in series; The base terminal of the first type transistor of the first circuit, the second circuit, and the base terminal of the second type transistor of the second circuit and the first circuit are the first and second types. When both of the transistors are non-conductive, if one type of transistor is conductive, the other transistor is also conductive. When both the first and second types of transistors are conductive, one transistor is non-conductive When in a state, the other transistor is also connected to be in a non-conductive state.
The holding circuit of the present invention is typically configured as a latch circuit. The first type and second type transistors typically correspond to PNP transistors and NPN transistors.
For this reason, in order to switch the holding circuit from the off state to the on state, the control circuit of the present invention only needs to control at least one type of transistor to the conductive state, while switching the holding circuit from the on state to the off state. For this, at least one kind of transistor may be controlled to be non-conductive.
The control circuit of the present invention includes a single-pole single-throw switch and a capacitor, and includes an intermediate point of the first circuit, an intermediate point of the second circuit, a first power supply terminal, and a second power supply terminal. Is connected to one of the power terminals. The “intermediate point of the first circuit” and the “intermediate point of the second circuit” include the connection point of the transistor and the resistor and the intermediate point of the resistor of the first circuit and the second circuit.
A single-pole single-throw switch has a fixed contact and a movable contact, and the movable contact contacts the fixed contact (ON) only while the operation unit is operated (for example, pressed), or the movable contact is a fixed contact. (Off) switch to leave. Such a single-pole single-throw switch is small, inexpensive, and easy to operate.
In the present embodiment, since the single-pole single-throw switch is used as the operation switch, the holding circuit is configured to be switched on or off each time the single-pole single-throw switch is turned on.
The connection mode of components in the control circuit, the midpoint between the control circuit and the first circuit, the midpoint of the second circuit, the connection mode with one power supply terminal of the first power supply terminal and the second power supply terminal When the single-pole single-throw switch is turned on while the holding circuit is off, at least one of the first and second type transistors is turned on, and the single-pole single-throw switch is turned on when the holding circuit is off. Then, it is sufficient that at least one of the first and second types of transistors is configured to be in a non-conductive state. Preferably, a connection mode is used in which charging and discharging operations of the capacitor of the control circuit are performed using components constituting the holding circuit.
In the present invention, since the control circuit is connected to the intermediate point of the first circuit, the intermediate point of the second circuit, one of the first power supply terminal and the second power supply terminal, the capacitor is charged. Alternatively, a holding circuit component can be used as a component for discharging. Thereby, the number of parts can be reduced significantly.
In addition, since the control circuit can be configured without using a transistor, the configuration of the control circuit can be greatly simplified.

A second aspect of the present invention is a power switch circuit as set forth in the second aspect.
In the present invention, as the connection mode between the control circuit and the first circuit, the intermediate point of the second circuit, the intermediate point of the second circuit, one power supply terminal of the first power supply terminal and the second power supply terminal, the following operation modes are provided. A satisfactory connection mode is used.
When the single-pole single-throw switch is turned off while the holding circuit is off, the capacitor is discharged. At this time, discharging of the capacitor may be performed through a resistor provided in the holding circuit, or may be performed through a resistor provided in the control circuit.
When the single-pole single-throw switch is turned on while the holding circuit is in the off state, the capacitor is charged via the single-pole single-throw switch, thereby at least one of the first and second types of transistors. The transistor becomes conductive.
When the holding circuit is turned on and the single-pole single-throw switch is turned off, the capacitor is charged through one of the first and second types of transistors that are in a conducting state. As one type of transistor at this time, a transistor different from the transistor which is turned on by discharging the capacitor is used.
When the single-pole single-throw switch is turned on while the holding circuit is on, the capacitor is discharged through the single-pole single-throw switch, so that at least one type of transistor of the first and second types of transistors is It becomes a non-conductive state. As the transistor which is turned off by discharging the capacitor at this time, a transistor which is turned on by charging the capacitor is preferably used.
As in the first invention, the present invention can greatly reduce the number of components and can simplify the configuration of the control circuit.

A third aspect of the present invention is a power switch circuit as set forth in the third aspect.
In the present invention, when the holding circuit is turned on and the single-pole single-throw switch is turned on, the control circuit prevents the discharge current from the capacitor from flowing in a direction in which other types of transistors are conducted. have.
A diode is typically used as the current blocking means.
In the aspect of “blocking the discharge current of the capacitor from flowing in the direction in which the other type of transistor conducts”, the mode of blocking the discharge current of the capacitor from being supplied to the base terminal of the other type of transistor, A mode is included in which the base potential of the other type of transistor is prevented from reaching the potential at which the other transistor becomes conductive due to the discharge current of the capacitor.
By providing such current blocking means, when the single-pole single-throw switch is turned on while the holding circuit is turned on, one type of transistor can be surely turned off.

A fourth aspect of the present invention is a power switch circuit as set forth in the fourth aspect.
In the present invention, as the connection mode between the control circuit and the first circuit, the intermediate point of the second circuit, the intermediate point of the second circuit, one power supply terminal of the first power supply terminal and the second power supply terminal, the following operation modes are provided. A satisfactory connection mode is used.
When the single-pole single-throw switch is turned off while the holding circuit is off, the capacitor is charged. At this time, the capacitor is preferably charged using a resistor provided in the holding circuit.
When the single-pole single-throw switch is turned on while the holding circuit is off, the capacitor is discharged through the single-pole single-throw switch, thereby at least one of the first and second types of transistors. Becomes conductive.
When the single-pole single-throw switch is turned off while the holding circuit is on, the capacitor is discharged through one of the first and second types of transistors that are in a conducting state. At this time, it is preferable to use a transistor that has become conductive due to the discharge of the capacitor as the one type of transistor.
When the holding circuit is on and the single-pole single-throw switch is turned on, the capacitor is charged via one of the first and second types of transistors that are in conduction and the single-pole single-throw switch. As a result, the other type of transistor is turned off. At this time, it is preferable to use a transistor of a different type from the transistor which has been rendered conductive by discharging the capacitor, as one type of transistor.
As in the first invention, the present invention can greatly reduce the number of components and can simplify the configuration of the control circuit.

  If the power switch circuit according to any one of claims 1 to 4 is used, the number of parts can be reduced and the configuration can be simplified.

Embodiments of the present invention will be described below with reference to the drawings.
A first embodiment of the present invention is shown in FIG.
In the present embodiment, the power switch circuit of the present invention is applied to an electric device including a DC power supply device B, a load (power consumption circuit) L, and a power switch circuit 10.
As the DC power supply device B, a primary battery is used. Further, as the load L, an appropriate electric circuit corresponding to the use of the electric device or the like is used. For example, a detection circuit for detecting reinforcing bars or beams covered with walls, a detection circuit for detecting pipes buried in the ground, a motor for driving a work tool, or the like is used.
The power switch circuit 10 turns on a holding circuit that can hold an ON state in which the power of the DC power supply B is supplied to the load L and an OFF state in which the supply of the power of the DC power supply B to the load L is stopped. The control circuit 11 is configured to control from the state to the off state or from the off state to the on state.

In the holding circuit, a series circuit of a PNP transistor Q11 and resistors R11 and R12 and a series circuit of resistors R13 and R14 and an NPN transistor Q12 are connected in parallel to the positive terminal and the negative terminal of the DC power supply device B. In the present embodiment, each series circuit is connected to the negative terminal of the DC power supply device B via a ground electrode (earth electrode).
In the present embodiment, one of the positive electrode terminal and the negative electrode terminal of the DC power supply device B corresponds to the “first power supply terminal” of the present invention, and the other corresponds to the “second power supply terminal” of the present invention.
The connection point between the resistors R13 and R14 is connected to the base terminal of the PNP transistor Q11, and the connection point between the resistors R11 and R12 is connected to the base terminal of the NPN transistor Q12.
As a result, in the holding circuit, both the transistors Q11 and Q12 are turned on, the power of the DC power supply B is supplied to the load L, and the transistors Q11 and Q12 are both turned off, An off state in which the supply of power from the power supply device B to the load L is stopped is maintained. Such a holding circuit is usually called a “latch circuit”.
In the present embodiment, the collector terminal of the PNP transistor Q11 is connected to the load L.
In the present embodiment, one of the series circuit of the PNP transistor Q11 and the resistors R11 and R12 and the series circuit of the resistors R13 and R14 and the NPN transistor Q12 corresponds to the “first circuit” of the present invention, and the other corresponds to the “first circuit” of the present invention. This corresponds to “second circuit”. Further, one of the PNP transistor Q11 and the NPN transistor Q12 corresponds to the “first type transistor” of the present invention, and the other corresponds to the “second type transistor” of the present invention, and a set of resistors R11 and R12. And one of the pair of R13 and R14 corresponds to the “first resistor” of the present invention, the other corresponds to the “second resistor” of the present invention, and the connection point between the collector terminal of the NPN transistor Q11 and the resistor R11 One of the connection points of the resistors R13 and R14 corresponds to the “middle point of the first circuit” of the present invention, and the other corresponds to the “middle point of the second circuit” of the present invention.

In the present embodiment, the control circuit 11 is provided between the connection point of the collector terminal of the PNP transistor Q11 and the resistor R11, the connection point of the resistors R13 and R14, and the negative electrode terminal.
The control circuit 11 includes a single pole single throw switch S11, resistors R15 and R16, and a capacitor C11.
The resistors R15 and R16 and the single pole single throw switch S11 are connected in series. In this series circuit, the PNP is connected so that the resistor R15 is connected to the connection point between the collector terminal of the PNP transistor Q11 and the resistor R11, and the single-pole single throw switch S11 is connected to the connection point between the resistors R13 and R14. The transistor Q11 is arranged between a connection point between the collector terminal of the transistor Q11 and the resistor R11 and a connection point between the resistors R13 and R14.
The connection point between the resistors R15 and R16 is connected to the negative terminal of the DC power supply device via the capacitor C11.
In this embodiment, as the single-pole single-throw switch (SPST switch) S11, the movable contact contacts (turns on) the fixed contact only while the pressing force is applied to the operation portion, and the pressing force to the operation portion is reduced. When the application is stopped, a switch is used in which the movable contact leaves (turns off) the fixed contact.

Next, the operation of the present embodiment will be described with reference to FIG. FIG. 2 is a diagram illustrating waveforms of each part of the power switch circuit 10.
[Period I] (Period during which the holding circuit is in the OFF state)
It is assumed that the DC power supply device (primary battery) B is connected to the power switch circuit 10 at the time t11 when the single pole single throw switch S11 is turned off and the holding circuit is in the off state.
At this time, the PNP transistor Q11 and the NPN transistor Q12 are nonconductive. For this reason, the capacitor C11 is in a discharged state, and among the terminals of the capacitor C11, the potential of the terminal connected to the connection point of the resistors R16 and R15 (hereinafter referred to as “the potential of the capacitor C11”) is “0”. . The potential of the base terminal of the PNP transistor Q11 with respect to the emitter terminal (hereinafter referred to as “base potential”) and the potential of the collector terminal of the PNP transistor Q11 (hereinafter referred to as “collector potential”) are also “0”.
The period I is continued until the single-pole single-throw switch S11 is turned on.

[Period II] (period in which the single-pole single-throw switch S11 is on)
When the single-pole single-throw switch S11 is turned on at time t12 when the holding circuit is in the off state, the capacitor C11 is connected via the resistor R13 and the emitter terminal-base terminal of the PNP transistor Q11, the single-pole single-throw switch S11, and the resistor R16. Charging current. Here, since the resistance value of the circuit through which the charging current to the capacitor C11 flows is set small, the potential of the capacitor C11 is a value X2 (for example, 4 V) close to the power supply voltage V1 (for example, 5 V) of the DC power supply device B. .4V). Further, when a charging current flows to the capacitor C11, the resistance value of each resistor is set so that the base potential of the PNP transistor Q11 becomes equal to or higher than a value (for example, 0.6V) at which the PNP transistor Q11 becomes conductive. ing. Thereby, the PNP transistor Q11 becomes conductive.
The resistance value of the resistor R16 is set to a value that limits the current flowing from the emitter terminal to the base terminal of the PNP transistor Q11 to a safe value when the capacitor C11 is charged.
When the PNP transistor Q11 becomes conductive, the collector current of the PNP transistor Q11 flows to the base terminal-emitter terminal of the NPN transistor Q12 and the resistor R12 via the resistor R11. Here, when the collector current of the PNP transistor Q11 flows, the resistance value of each resistor is set so that the base potential of the NPN transistor Q12 becomes equal to or higher than a value (for example, 0.6 V) at which the NPN transistor Q12 becomes conductive. Has been. As a result, the NPN transistor Q12 becomes conductive.
When the NPN transistor Q12 becomes conductive, the emitter current of the NPN transistor Q12 flows through the resistor R13, the emitter terminal-base terminal of the PNP transistor Q11, and the resistor R14. Here, when the collector current of the NPN transistor Q12 flows, the resistance value of each resistor is set so that the base potential of the PNP transistor Q11 becomes equal to or higher than the value at which the PNP transistor Q11 becomes conductive. Thereby, the conduction state of the PNP transistor Q11 is maintained.
Therefore, the holding circuit is controlled to an on state in which both the PNP transistor Q11 and the NPN transistor Q12 are in a conductive state. In other words, the holding circuit is switched from the off state to the on state. At this time, the collector potential of the PNP transistor Q11 rises to a potential substantially close to the power supply voltage V1 of the DC power supply device B, and DC power is supplied to the load L.
Period II continues until the single pole switch S11 is turned off.

[Period III] (Period during which the single-pole single-throw switch S11 is off)
When the single-pole single-throw switch S11 is turned off at time t13 after the holding circuit is turned on, the capacitor C11 is charged via the PNP transistor Q11 and the resistor R15 that are in a conductive state. Here, since the voltage drop between the emitter terminal and the collector terminal of the PNP transistor Q11 is extremely small, the potential of the capacitor C11 gradually increases to a value X1 (for example, 5V) substantially equal to the power supply voltage V1 of the DC power supply device B.
Period III continues until single-pole single-throw switch S11 is turned on.

[Period IV] (period in which the single-pole single-throw switch S11 is on)
When the holding circuit is turned on and the single-pole single-throw switch S11 is turned off at time t14, when the single-pole single-throw switch S11 is turned on, the charged capacitor C11 is connected to the resistor R16, the single-pole single-throw switch S11. It is connected to the base terminal of the PNP transistor Q11 via the throw switch S11.
At this time, since the potential of the capacitor C11 is substantially equal to the power supply voltage V1, the base potential of the PNP transistor Q11 becomes less than the value at which the PNP transistor Q11 becomes conductive. As a result, the PNP transistor Q11 is turned off.
When the PNP transistor Q11 is turned off, the base potential of the NPN transistor Q12 becomes less than the value at which the NPN transistor Q12 is turned on. As a result, the NPN transistor Q12 is also turned off.
Therefore, the holding circuit is controlled to an off state in which both the PNP transistor Q11 and the NPN transistor Q12 are in a non-conductive state. In other words, the holding circuit is switched from the on state to the off state. At this time, the potential of the capacitor C11 is discharged through the resistors R15, R11, and R12.
The collector potential of the PNP transistor Q11 and the base potential of the NPN transistor Q12 are values obtained by dividing the potential of the capacitor C11 by the resistors R15, R11, and R12. It should be noted that the operation of the load L stops when the collector potential of the PNP transistor Q11 falls below the operating voltage value of the load L as the capacitor C11 is discharged.
The period IV is continued until the single-pole single-throw switch S11 is turned off.

When the single-pole single-throw switch S11 is turned off at time t15 after the holding circuit is turned off, the capacitor C11 is discharged through the resistors R15, R11, and R12. When a predetermined period elapses after the single-pole switch S11 is turned off, the potential of the capacitor C11 becomes “0”, which is the same as the period I. Thereby, the current of the DC power supply device B is completely cut off.
Thereafter, each time the single-pole single-throw switch S11 is turned on, the holding circuit is turned on so that both the PNP transistor Q11 and the NPN transistor Q12 are turned on, and both the PNP transistor Q11 and the NPN transistor Q12 are turned off. Switches to the off state alternately (alternate operation).
Note that the resistance values of the resistors R11 and R12 are set to values at which the holding circuit can be appropriately switched from the off state to the on state. The resistance value of the resistor R15 is set to a value that prevents the operation of the holding circuit from becoming unstable due to chattering of the single-pole single-throw switch S11.

As described above, according to the present embodiment, the current from the DC power supply device is completely obtained when the holding circuit (latch circuit) is set to the OFF state while using an inexpensive and easy-to-operate single-pole single-throw switch. Will be blocked. Thereby, useless power consumption can be suppressed and the usable time of the DC power supply device can be lengthened.
In the present embodiment, the series circuit of the PNP transistor Q11 and the resistors R11 and R12, the series circuit of the resistors R13 and R14 and the NPN transistor Q12, and the negative terminal of the DC power supply device B, which constitute the holding circuit (latch circuit). A control circuit composed of a single pole single throw switch, a resistor and a capacitor is connected between them. When the single-pole single-throw switch S11 is turned on while the holding circuit is on , the capacitor C11 is discharged through the conductive NPN transistor Q12, and the single-pole single-throw switch S11 is turned on while the holding circuit is on. When is turned off, the capacitor C11 is charged through the transistor Q11 which is in a conductive state. Thereby, the components constituting the holding circuit can be used as components for charging or discharging the capacitor of the control circuit. Therefore, the number of components can be greatly reduced as compared with the conventional power switch circuit. Furthermore, since the transistor used in the conventional control circuit of the power switch circuit can be omitted, the circuit configuration can be greatly simplified.

Various modifications can be made to the first embodiment.
A first modification of the first embodiment is shown in FIG.
In the power switch circuit 20 shown in FIG. 3, the holding circuit (latch circuit) includes a series circuit of a PNP transistor Q21 and resistors R21 and R22, and a series circuit of resistors R23, R26 and R24 and an NPN transistor Q22. Are connected in parallel to the positive terminal and the negative terminal. The connection point between the resistors R23 and R26 is connected to the base terminal of the PNP transistor Q21, and the connection point between the resistors R21 and R22 is connected to the base terminal of the NPN transistor Q22.
In the present embodiment, a resistor R26 corresponding to the resistor R16 of the embodiment shown in FIG. 1 is arranged at the position shown in FIG. Even when the resistor R26 is arranged at the position shown in FIG. 3, when the capacitor C21 is charged, the current flowing through the emitter terminal-base terminal of the PNP transistor Q21 can be limited to a safe value.
A capacitor C22 is connected in parallel with the resistor R23. The capacitor C22 is for preventing the PNP transistor Q21 from being turned on when the DC power supply device B is connected to the power switch circuit 20. As the capacitor C22, a capacitor having a sufficiently smaller capacity than the capacity of the capacitor C11 is used.

In the present embodiment, the control circuit 21 is connected between the collector terminal of the PNP transistor Q21 and the resistor R21, the junction point of the resistors R26 and R24, and the negative terminal of the DC power supply device.
The control circuit 21 includes a diode D21, resistors R25 and R27, a single pole single throw switch S21, and a capacitor C21.
The diode D21, the resistor R25, and the single pole single throw switch S21 are connected in series. In this series circuit, the PNP is such that the diode D21 is connected to the connection point between the collector terminal of the PNP transistor Q21 and the resistor R21, and the single pole single throw switch S21 is connected to the connection point between the resistors R26 and R24. The transistor Q21 is arranged between the connection point of the collector terminal of the transistor Q21 and the resistor R21 and the connection point of the resistors R26 and R24. At this time, the diode D21 is disposed such that the positive terminal is connected to the connection point between the collector terminal of the PNP transistor Q21 and the resistor R21, and the negative terminal is connected to the resistor R25.
A connection point between the single-pole single-throw switch S21 and the resistor R25 is connected to the negative terminal of the DC power supply device B through the capacitor C21. The connection point between the resistor R25 and the negative electrode terminal of the diode D21 is connected to the negative electrode terminal of the DC power supply device B through the resistor R27.
In the present embodiment, one of the connection point between the collector terminal of the PNP transistor Q21 and the resistor R21 and the connection point between the resistors R26 and R24 corresponds to the “middle point of the first circuit” of the present invention, and the other is the main point. This corresponds to the “midpoint of the circuit 2” of the invention. The diode D21 corresponds to the “current blocking means” of the present invention.

In the embodiment shown in FIG. 1, the base potential of the PNP transistor Q11 is lowered by the potential of the capacitor C11 during [period IV] (period in which the single-pole single-throw switch S11 is turned on), and the PNP transistor Q11. Is turned off.
At this time, when a discharge current flows from the capacitor C11 to the base terminal and the emitter terminal of the NPN transistor Q12 via the resistors R15 and R11, the conduction state of the NPN transistor Q12 is maintained. In this case, it becomes difficult to turn off the PNP transistor Q11. That is, it becomes difficult to control the holding circuit from the on state to the off state.
Therefore, in the embodiment shown in FIG. 3, a diode D21 is connected between the resistor R25 and a connection point between the collector terminal of the PNP transistor Q21 and the resistor R21. The diode D21 is connected to prevent the discharge current of the capacitor C21 from flowing through the base terminal and the emitter terminal of the NPN transistor Q22 via the resistors R25 and R21.
Along with the provision of the diode D21, a resistor R27 for discharging the capacitor C21 is provided. In this case, the resistance values of the resistors R25 and R27 are set to values that prevent the operation of the holding circuit from becoming unstable due to chattering of the single-pole single-throw switch S21.
In this way, by providing the diode D21 that prevents the discharge current of the capacitor C21 from flowing through the base terminal-emitter terminal of the NPN transistor Q22, the value of each component (for example, the resistance value of each resistor, etc.) can be reduced. The allowable range when setting is expanded. Then, by expanding the allowable range when setting the values of the respective components, the normal operation range of the power switch circuit 20 with respect to fluctuations in the power supply voltage V1 of the DC power supply device B can be widened. Thereby, the usable time of DC power supply B can be lengthened.

In the present embodiment, the holding circuit of the power switch circuit 20 holds the on state. For this reason, when the holding circuit of the power switch circuit 20 is set to the on state, an operation for setting the holding circuit of the power switch circuit 20 to the off state is necessary. However, the operation of setting the power switch circuit 20 to the off state may be forgotten. In this case, the power of the DC power supply device B is wasted.
Therefore, in the present embodiment, the holding circuit of the power switch circuit 20 can be set to an off state by a CPU provided in the electric device.
In FIG. 3, the collector terminal of the PNP transistor Q23 for CPU output is connected to the connection point between the resistors R21 and R22, and the emitter terminal is connected to the negative terminal of the DC power supply device B. The CPU starts calculating the elapsed time when the holding circuit of the power switch circuit 20 is set to the ON state by the operation of the single-pole single-throw switch S21. When the holding circuit is held in the on state for a set time or longer, a signal for turning on the PNP transistor Q23 is supplied to the base terminal of the PNP transistor Q23. As a result, the PNP transistor Q23 becomes conductive, and the base potential of the NPN transistor Q22 decreases. Therefore, NPN transistor Q22 is turned off, and the holding circuit is forcibly switched from the on state to the off state.
As shown in FIG. 3, when the PNP transistor Q34 is connected to the connection point between the resistors R21 and R22, the NPN transistor Q23 is in a high impedance state except when the PNP transistor Q23 becomes conductive. Become. Therefore, the operation of the holding circuit is not affected by the PNP transistor Q23.
As a signal output form from the CPU, the base potential of the NPN transistor Q22 can be lowered only when a set time has elapsed after the holding circuit is set to the on state, and otherwise the operation of the holding circuit is performed. The configuration is not limited to the signal output form by the open collector connection as long as it is configured so as not to affect.
Other operations of the power switch circuit of the present embodiment are the same as those of the embodiment shown in FIG.
In the present embodiment, the CPU including the transistor Q23 corresponds to the “forced stop circuit” of the present invention.

As described above, in the present embodiment, since the diode D21 that prevents the discharge current of the capacitor C21 from flowing to the base terminal of the NPN transistor Q22 is provided, the allowable range when setting the set values of the respective components is set. Can be wide.
Thereby, the normal operation range of the power switch circuit 20 with respect to the fluctuation of the power supply voltage V1 of the DC power supply B can be widened. For example, in the circuit simulation, the power supply switch circuit 10 shown in FIG. 1 performs an alternate operation when the power supply voltage V1 is in the range of 4.0V to 5.8V. On the other hand, in the power supply switch circuit 20 shown in FIG. 3, the alternate operation is performed when the power supply voltage V1 is in the range of 3.9V to 8.2V.
In addition, since the forced stop circuit constituted by the CPU including the transistor Q23 is provided, forgetting to turn off the power switch circuit 20 can be prevented.
Therefore, the allowable use time of the DC power supply device B can be extended.

Next, a second modification of the first embodiment is shown in FIG.
The power switch circuit 30 shown in FIG. 4 is the same as the power switch circuit 20 shown in FIG. 3 except that the PNP transistor Q33 is connected to the PNP transistor Q31 by Darlington and the load L is connected to the PNP transistor Q33. It is the same composition as.
The PNP transistor Q33 has an emitter terminal connected to the positive terminal of the DC power supply B, a base terminal connected to the emitter terminal of the PNP transistor Q31, and a collector terminal connected to the load L.
In the present embodiment, small signal transistors are used as the PNP transistor Q31 and the NPN transistor Q32 constituting the holding circuit, and a power transistor is used as the PNP transistor Q33 that supplies current to the load L.
Thereby, a large current can be supplied to the load L with an inexpensive configuration.

FIG. 5 shows a third modification of the first embodiment.
A power switch circuit 40 shown in FIG. 5 has the same configuration as that of the power switch circuit 20 shown in FIG. 3 except that a PNP transistor Q43 is provided and a load L is connected to the PNP transistor Q43. is there.
The PNP transistor Q43 has an emitter terminal connected to the positive terminal of the DC power supply B, a base terminal connected to a connection point between the resistor R44 and the collector terminal of the NPN transistor Q42 via a resistor R48, and a collector terminal connected to the load. Connected to L.
In the present embodiment, small signal transistors are used as the PNP transistor Q41 and the NPN transistor Q42 constituting the holding circuit, and a power transistor is used as the PNP transistor Q43.
Thereby, a large current can be supplied to the load L with an inexpensive configuration.

In the first embodiment, the conduction state and the non-conduction state of the PNP transistor are controlled by the control circuit. However, the conduction state and the non-conduction state of the NPN transistor can also be controlled by the control circuit.
A second embodiment of the present invention is shown in FIG.
In the present embodiment, as in the first embodiment, the power switch circuit of the present invention is applied to an electric device including a DC power supply device B, a load (power consumption circuit) L, and a power switch circuit 50. Is.
The power switch circuit 50 includes a holding circuit (latch circuit) and a control circuit 51.
As in the first embodiment, the holding circuit (latch circuit) includes a series circuit of a PNP transistor Q51 and resistors R51 and R52, and a series circuit of resistors R53 and R54 and an NPN transistor Q52. The terminal and the negative terminal are connected in parallel. The connection point between the resistors R53 and R54 is connected to the base terminal of the PNP transistor Q51, and the connection point between the resistors R51 and R52 is connected to the base terminal of the NPN transistor Q52.
In the present embodiment, one of the series circuit of the PNP transistor Q51 and the resistors R51 and R52, and the series circuit of the resistors R53 and R54 and the NPN transistor Q52 corresponds to the “first circuit” of the present invention, and the other corresponds to the “first circuit” of the present invention. This corresponds to “second circuit”. Further, one of the PNP transistor Q51 and the NPN transistor Q52 corresponds to the “first type transistor” of the present invention, and the other corresponds to the “second type transistor” of the present invention. One of the connection point, the resistor R54, the collector terminal of the NPN transistor Q52 and the connection point corresponds to the “middle point of the first circuit” of the present invention, and the other corresponds to the “middle point of the second circuit” of the present invention. To do.

In the present embodiment, the control circuit 51 is provided between the connection point between the resistor R51 and the resistor R52, the connection point between the resistor R54 and the collector terminal of the NPN transistor Q52, and the negative electrode terminal of the DC power supply device B. Yes.
The control circuit 51 includes a single-pole single-throw switch S51, resistors R55 and R56, and a capacitor C51.
The single pole single throw switch S51 and the resistors R56 and R55 are connected in series. In this series circuit, the resistor R51 and the resistor R51 are connected such that the single-pole single-throw switch S51 is connected to the connection point between the resistors R51 and R52, and the resistor R55 is connected to the connection point between the resistor R54 and the collector terminal of the PNP transistor Q52. It is disposed between a connection point between the resistor R52 and a connection point between the resistor R54 and the collector terminal of the NPN transistor Q52.
The connection point between the resistors R55 and R56 is connected to the negative terminal of the DC power supply device B through the capacitor C51.

Next, the operation of the present embodiment will be described with reference to FIG. FIG. 7 is a diagram showing waveforms at various parts of the power switch circuit 50.
[Period I] (Period during which the holding circuit is in the OFF state)
It is assumed that the single-pole single-throw switch S51 is off and the DC power supply device (primary battery) B is connected to the power switch circuit 50 at time t51 when the holding circuit is in the off state.
At this time, the PNP transistor Q51 and the NPN transistor Q52 are nonconductive. For this reason, the capacitor C51 is charged via the resistors R53, R54, and R55. The potential of the capacitor C51 gradually increases to Y1, which is substantially equal to the power supply voltage V1 of the DC power supply device B. The base potential of the NPN transistor Q52 and the collector potential of the PNP transistor Q11 are “0”.
The period I is continued until the single-pole single-throw switch S51 is turned on.

[Period II] (Period during which the single-pole single-throw switch S51 is on)
When the single-pole single-throw switch S51 is turned on at the time t52 when the holding circuit is in the off state, the discharge current of the capacitor C51 is changed to the base terminal of the resistor R56, the single-pole single-throw switch S51, the resistor R52, and the NPN transistor Q52. It flows through the emitter terminal. The current from the DC power supply B flows through the resistors R53, R54, R55, R56, the single-pole single-throw switch S51, the resistor R52, and the base terminal-emitter terminal of the NPN transistor Q52. Here, when such a current flows, the resistance value of each resistor is set so that the base potential of the NPN transistor Q52 becomes equal to or higher than a value (for example, 0.6 V) at which the NPN transistor Q52 becomes conductive. ing. As a result, the NPN transistor Q52 becomes conductive.
The resistance value of the resistor R56 is set to a value that limits the current flowing through the base terminal of the NPN transistor Q52 to a safe value by discharging the capacitor C51.
When the NPN transistor Q52 becomes conductive, the collector current of the NPN transistor Q52 flows through the resistor R53, the emitter terminal-base terminal of the PNP transistor Q51, and the resistor R54. Here, when the collector current of the NPN transistor Q52 flows, the resistance value of each resistor is set so that the base potential of the PNP transistor Q51 becomes equal to or higher than the value at which the PNP transistor Q51 becomes conductive (for example, 0.6 V). ing. Thereby, the PNP transistor Q51 becomes conductive.
When the PNP transistor Q51 becomes conductive, the collector current of the PNP transistor Q51 flows through the resistors R51 and R52 and the base terminal-emitter terminal of the NPN transistor Q52. Here, when the collector current of the PNP transistor Q51 flows, the resistance value of each resistor is set so that the base potential of the NPN transistor Q52 becomes equal to or higher than the value at which the NPN transistor Q52 becomes conductive. The conduction state is maintained.
Therefore, the holding circuit is controlled to an on state in which both the PNP transistor Q51 and the NPN transistor Q52 are in a conductive state. In other words, the holding circuit is switched from the off state to the on state.
At this time, the collector potential of the PNP transistor Q51 rises to a value substantially close to the power supply voltage V1 of the DC power supply device B, and DC power is supplied to the load L.
Further, when the NPN transistor Q52 becomes conductive, the collector potential of the NPN transistor Q52 becomes almost “0”. For this reason, the potential of the capacitor C51 is a value Y2 determined by the resistance values of the resistors R55 and R56.
The period II is continued until the single pole switch S51 is turned off.

[Period III] (Period during which the single-pole single-throw switch S51 is off)
When the single-pole single-throw switch S51 is turned off at time t53 after the holding circuit is turned on, the capacitor C51 connects the resistor R55 and the collector terminal-emitter terminal of the NPN transistor Q52 in the conductive state. To discharge through. As a result, the potential of the capacitor C51 gradually decreases to “0”.
Period III continues until single-pole single-throw switch S51 is turned on.

[Period IV] (Period in which single-pole single-throw switch S51 is on)
When the single-pole single-throw switch S51 is turned on at time t54 when the holding circuit is turned on and the single-pole single-throw switch S51 is turned off, the capacitor C51 is in the conductive state. Are charged via the emitter terminal-collector terminal, resistor R51, single-pole single-throw switch S51, and resistor R56.
Here, when the capacitor C41 is charged via the PNP transistor Q51, the resistance value of each resistor is set so that the base potential of the NPN transistor Q52 is less than the value at which the NPN transistor Q52 is in a conductive state. . As a result, NPN transistor Q52 is turned off.
Note that when the NPN transistor Q52 is turned off, the capacitor C51 is also charged via the resistors R53, R54, and R55. In addition, a current flows through the resistors R53, R54, R55, R56, the single-pole single-throw switch S51, and the resistor R52, and this current causes the base potential of the NPN transistor Q52 to exceed the value at which the NPN transistor Q52 becomes conductive. The resistance value of each resistor is set so that it does not occur.
When the NPN transistor Q52 is turned off, the base potential of the PNP transistor Q51 falls below a value at which the PNP transistor Q51 is turned on. As a result, the PNP transistor Q51 is also turned off.
Therefore, the holding circuit is controlled to an off state in which both the PNP transistor Q51 and the NPN transistor Q52 are in a non-conductive state. In other words, the holding circuit is switched from the on state to the off state.
The collector potential of the PNP transistor Q51 and the base potential of the NPN transistor Q52 are values obtained by dividing the potential of the capacitor C51 by the resistors R56 and R52. Note that when the collector potential of the PNP transistor Q51 falls below the operating voltage value of the load L, the operation of the load L stops.
The period IV is continued until the single-pole single-throw switch S51 is turned off.

When the single-pole single-throw switch S51 is turned off at time t55 after the holding circuit is turned off, the capacitor C51 is charged via the resistors R53, R54, and R55. When a predetermined period elapses after the single-pole single-throw switch S51 is turned off, the potential of the capacitor C51 becomes Y1, which is substantially equal to the power supply voltage V1, and is in the same state as the period I. Thereby, the current of the DC power supply device B is completely cut off.
Thereafter, each time the single-pole single-throw switch S51 is turned on, the holding circuit is alternately switched between an on state and an off state (alternate operation is performed).
Note that the resistance values of the resistors R53 and R54 are set to values at which the holding circuit can be appropriately switched from the off state to the on state. The resistance value of the resistor R55 is set to a value that prevents the operation of the holding circuit from becoming unstable due to chattering of the single-pole single-throw switch S51.

  As described above, also in the present embodiment, as in the first embodiment, the series circuit of the PNP transistor Q51 and the resistors R51 and R52, the resistors R53 and R54, which form the holding circuit (latch circuit), Between the series circuit of the NPN transistor Q52 and the negative terminal of the DC power supply device B, a control circuit composed of a single pole single throw switch, a resistor and a capacitor is connected. When the holding circuit is off and the single-pole single-throw switch S51 is turned off, the capacitor C51 is charged via the resistors R53 and R54, and when the holding circuit is on and the single-pole single-throw switch S51 is turned off. When the capacitor C51 is discharged through the conductive NPN transistor Q52, and the holding circuit is turned on and the single-pole single-throw switch S51 is turned on, the conductive PNP transistor Q51 and the resistor R51 are connected. The capacitor C51 is configured to be charged via the via. As a result, the components constituting the holding circuit (latch circuit) can also be used as components for charging or discharging the capacitor of the control circuit, and the number of components can be greatly reduced. Furthermore, since the control circuit can be configured without using a transistor, the circuit configuration can be greatly simplified.

In the first embodiment shown in FIG. 1, the PNP transistor is turned on using the charging current of the capacitor and the PNP transistor is turned off using the discharging current of the capacitor. Can be used to make the PNP transistor conductive, and the charging current of the capacitor can be used to make the PNP transistor non-conductive.
A third embodiment of the present invention is shown in FIG. In the present embodiment, the capacitor C11 of the first embodiment shown in FIG. 1 is connected to the positive terminal of the DC power supply device B.
The holding circuit (latch circuit) of the power switch circuit 60 of the present embodiment has the same configuration as the holding circuit of the first embodiment shown in FIG.
The control circuit 61 is provided between the connection point between the resistors R62 and R61, the connection point between the collector terminal of the PNP transistor Q62 and the resistor R64, and the positive electrode terminal of the DC power supply device B.
The control circuit 61 includes a single pole single throw switch S61, resistors R65 and R66, and a capacitor C61.
Single pole single throw switch S61 and resistors R66 and R65 are connected in series. In this series circuit, the connection between the resistors R62 and R61 is such that the single-pole single-throw switch S61 is connected to the connection point between the resistors R62 and R61, and the resistor R65 is connected to the connection point between the PNP transistor Q62 and the resistor R64. Between the collector terminal of the PNP transistor Q62 and the resistor R64.
The connection point between the resistors R66 and R65 is connected to the positive terminal of the DC power supply device B through the capacitor C61.
In the present embodiment, one of the connection point between the resistors R62 and R61 and the connection point between the collector terminal of the PNP transistor Q62 and the resistor R64 corresponds to the “middle point of the first circuit” of the present invention, and the other is the main point. This corresponds to the “midpoint of the second circuit” of the invention.

Next, the operation of the present embodiment will be described.
[Period I] (Period during which the holding circuit is in the OFF state)
It is assumed that the single-pole single-throw switch S61 is off and the DC power supply (primary battery) B is connected to the power switch circuit 10 when the holding circuit is in the off state.
At this time, the PNP transistor Q62 and the NPN transistor Q61 are nonconductive. For this reason, the capacitor C61 is charged via the resistors R65, R64, and R63. The potential of the capacitor C61 is substantially equal to the power supply voltage V1.
[Period II] (period in which the single-pole single-throw switch S11 is on)
When the single-pole single-throw switch S61 is turned on when the holding circuit is in the off state, the capacitor C61 passes through the resistor R62 and the emitter terminal-base terminal of the PNP transistor Q62, the single-pole single-throw switch S61, and the resistor R66. To discharge. As a result, the PNP transistor Q62 becomes conductive. When the PNP transistor Q62 becomes conductive, the NPN transistor Q61 also becomes conductive.
Therefore, the holding circuit is controlled to an on state in which both the PNP transistor Q62 and the NPN transistor Q61 are in a conductive state.
[Period III] (Period during which the single-pole single-throw switch S11 is off)
When the single-pole single-throw switch S61 is turned off at the time after the holding circuit is turned on, the capacitor C61 is discharged through the PNP transistor Q62 and the resistor R65 that are in the conductive state.
[Period IV] (period in which the single-pole single-throw switch S11 is on)
When the holding circuit is turned on and the single-pole single-throw switch S61 is turned off, when the single-pole single-throw switch S61 is turned on, the capacitor C61 includes a resistor R66, a single-pole single throw switch S61, Charging is performed through the resistor R61 and the collector terminal-emitter terminal of the NPN transistor Q61 in the conductive state. As a result, the PNP transistor Q62 is turned off. When PNP transistor Q62 is turned off, NPN transistor Q61 is also turned off.
Therefore, the holding circuit is controlled to an off state in which both the PNP transistor Q62 and the NPN transistor Q61 are in a non-conductive state.
When the single-pole single-throw switch S61 is turned off at a time after the holding circuit is turned off, the capacitor C61 is charged through the resistors R65, R64, and R63, and is in the same state as the period I.

  Also in the present embodiment, as in the first and second embodiments, a series circuit of a PNP transistor Q62 and resistors R64 and R63, and a resistor R62 and a resistor constituting a holding circuit (latch circuit). A control circuit composed of a single-pole single-throw switch, a resistor and a capacitor is connected between the series circuit of R61 and NPN transistor Q61 and the positive terminal of the DC power supply device B. When the single-pole single-throw switch S61 is turned off while the holding circuit is off, the capacitor C61 is charged via the resistors R64 and R63, and when the single-pole single-throw switch S61 is turned off while the holding circuit is on. When the capacitor C61 is discharged through the conductive PNP transistor Q62 and the single-pole single-throw switch S61 is turned on while the holding circuit is turned on, the conductive NPN transistor Q61 and the resistor R61 are connected. The capacitor C61 is configured to be charged via the via. As a result, the components constituting the holding circuit (latch circuit) can also be used as components for charging or discharging the capacitor of the control circuit, and the number of components can be greatly reduced. Furthermore, since the control circuit can be configured without using a transistor, the circuit configuration can be greatly simplified.

The present invention is not limited to the configuration described in the embodiment, and various changes, additions, and deletions are possible.
The present invention can be used by appropriately combining the configurations described in the embodiments. For example, as a control mode of the control circuit, a control mode in which at least one type of transistor is made conductive by a capacitor charging operation and at least one type of transistor is made non-conductive by a capacitor discharging operation, or Any of the control modes in which at least one type of transistor is turned on by the discharging operation and at least one type of transistor is turned off by the charging operation of the capacitor can be used. In addition, as an arrangement mode of the control circuit, an intermediate point of the first circuit, an aspect of being arranged between the intermediate point of the second circuit and the first power supply terminal, or an intermediate point of the first circuit, Any of the modes arranged between the midpoint of the second circuit and the second power supply terminal can be used. In addition, in order to reduce the wasteful power consumption of the DC power supply device due to the mode of providing a current blocking means for limiting the direction in which the capacitor discharge current flows in order to widen the allowable range for setting the value of each component, A control mode in which the holding circuit is forcibly switched off by the stop circuit can also be appropriately selected and used.
Further, the structure of the holding circuit (latch circuit) is not limited to the structure described in the embodiment.
Further, the configuration of the control circuit is not limited to the configuration described in the embodiment.
The power switch circuit of the present invention can also be used when supplying power to a load from a DC power supply device other than the primary battery.

According to the present invention, “(Aspect 1) is a power switch circuit according to any one of claims 1 to 4, wherein at least one of the first and second types of transistors of the holding circuit is in a non-conductive state. The power switch circuit is provided with a forced stop circuit.
The forced stop circuit normally does not affect the state of the holding circuit, but operates when a predetermined condition is satisfied (for example, when the holding circuit remains on for more than a set time) Then, at least one of the first and second types of transistors in the holding circuit is turned off. The forcible stop circuit is preferably configured to operate in response to an output signal from a CPU (processing device) that outputs a control signal when it is determined that the holding circuit has been kept on for a set time or longer. The forced stop circuit typically has a high impedance in a normal state, and has a low impedance when operated by an output signal from the CPU so as to bypass a current flowing through the base terminal and the emitter terminal of at least one transistor. Preferably it is comprised.
By using this embodiment, it is possible to prevent wasteful power consumption of the DC power supply device due to forgetting to cut off the power switch circuit.
Further, the present invention provides a “DC power supply circuit, a load, and a power switch circuit set to an on state in which power of the DC power supply device is supplied to the load or an off state in which supply of power from the DC power supply device to the load is stopped. An electric apparatus using the power switch circuit according to any one of claims 1 to 4 and aspect 1 as a power switch circuit.
For an electric device including a DC power supply device, a power switch circuit, and a load (power consuming device), for example, a detection circuit for detecting reinforcing bars and beams covered with walls, pipes buried in the ground, and the like. An embedded object detection device, an electric tool including a motor that drives a work tool, and the like are included.

It is a figure which shows the 1st Embodiment of this invention. It is a figure which shows the waveform of each part of 1st Embodiment. It is a figure which shows the 1st example of a change of 1st Embodiment. It is a figure which shows the 2nd modification of 1st Embodiment. It is a figure which shows the 3rd modification of 1st Embodiment. It is a figure which shows the 2nd Embodiment of this invention. It is a figure which shows the waveform of each part of 2nd Embodiment. It is a figure which shows 3rd Embodiment. It is a figure which shows a prior art example.

Explanation of symbols

B DC power supply 10, 20, 30, 40, 50, 60, 110 Power switch circuit 11, 21, 31, 41, 51, 61, 111 Control circuit Q11, Q21, Q31, Q33, Q41, Q43, Q51, Q62 Q111 PNP transistors Q12, Q22, Q23, Q32, Q34, Q42, Q44, Q52, Q61, Q112, Q113 NPN transistors R11-R16, R21-R27, R31-R37, R41-R48, R51-R56, R61-RR68 R111 to R118 Resistors C11, C21, C22, C31, C32, C41, C42, C51, C61, C111 Capacitors S11, S21, S31, S41, S51, S61, S111 Single pole single throw switch (SPST switch)

Claims (4)

An ON state provided between the first power supply terminal and the second power supply terminal of the DC power supply device and supplying the power of the DC power supply device to the load or an OFF state of stopping the supply of the power of the DC power supply device to the load. A power switch circuit comprising: a holding circuit for holding; and a control circuit for controlling the holding circuit from an off state to an on state or from an on state to an off state,
The holding circuit is connected in parallel to the first power supply terminal and the second power supply terminal of the DC power supply device, and the first circuit in which the first type transistor and the first resistor are connected in series; The second circuit includes a second circuit in which a second type transistor and a second resistor are connected in series, and the base terminal, the second circuit, and the second circuit of the first type transistor of the first circuit The base terminal of the second type transistor of the circuit and the first circuit are at least when the first type transistor of the first circuit and the second type transistor of the second circuit are both non-conductive. When one type of transistor is turned on, both types of transistors are turned on, and both the first type transistor of the first circuit and the second type of transistor of the second circuit are both turned on. Less when conductive When one type of transistor is in a non-conductive state, both types of transistors are connected to be in an off state in which both types of transistors are in a non-conductive state.
The control circuit includes a single-pole single-throw switch and a capacitor, and includes an intermediate point of the first circuit, an intermediate point of the second circuit, a first power supply terminal and a second power supply of the DC power supply device . Connected to one power terminal of the terminal,
When the single-pole single-throw switch is turned on while the holding circuit is in an off state, the control circuit has at least one type of the first type transistor of the first circuit and the second type transistor of the second circuit. transistor becomes conductive, the holding circuit is a single pole, single throw switch in the on state is turned on, at least one of the second type transistors of the first type of transistor and the second circuit of the first circuit power supply switch circuit of the kind of the transistor is configured to be non-conductive. The power switch circuit according to claim 1,
The control circuit
When the single-pole single-throw switch is turned off while the holding circuit is off, the capacitor is discharged,
When the holding circuit is a single pole, single throw switch in the off state is turned on, by the capacitor is charged via a single pole single throw switch, at least one type of transistor is rendered conductive,
When the holding circuit is turned on and the single-pole single-throw switch is turned off, the capacitor is charged via one kind of transistor that is in a conductive state,
When the holding circuit is a single pole, single throw switch in the on state is turned on, by the capacitor discharges through the single-pole single-throw switch is configured as at least one type of transistor is turned off Power switch circuit. The power switch circuit according to claim 2,
The control circuit has current blocking means for blocking the discharge current from the capacitor from flowing in the direction in which the other type of transistor is conductive when the single-pole single-throw switch is turned on while the holding circuit is on. Power switch circuit. The power switch circuit according to claim 1,
The control circuit
When the holding circuit is off and the single-pole single-throw switch is turned off, the capacitor is charged,
When the holding circuit is a single pole, single throw switch in the off state is turned on, by the capacitor discharges through the single-pole single-throw switch, at least one type of transistor is rendered conductive,
When the holding circuit is turned on and the single-pole single-throw switch is turned off, the capacitor is discharged through one type of transistor that is in a conductive state,
When the holding circuit is turned on and the single-pole single-throw switch is turned on, one type of transistor that is in a conducting state and the capacitor are charged via the single-pole single-throw switch, thereby the other type of transistor Is a power switch circuit configured to be non-conductive.

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