JP4542623B2 - Scrambler, scramble processing method and program - Google Patents

Description

  The present invention relates to a scrambler, a scramble processing method, and a program.

  For example, when communication is performed using a multilevel digital modulation method such as 4-level FSK (Frequency Shift Keying) modulation, binary (or less than normal) modulation is used to temporarily change the bit rate in an important bit element. The Euclidean distance may be set as large as possible compared to other bit elements that are relatively unimportant. By performing such processing, it is possible to have a function substantially equivalent to that in which error correction is performed on data to be transmitted.

  In addition, data on a transmission path is often scrambled for the purpose of avoiding energy concentration due to modulation bias and making information confidential. By scrambling the data in this manner, for example, even when the original information data is all the same value (as a specific example, data indicating all “0”), the modulated signal is converted into pseudo noise (PN; Pseudo Noise). Conventionally, when data is scrambled, an exclusive OR (ExOR) of the target information data and a scramble pattern that is a bit string prepared in advance has been obtained by a logic operation circuit or the like (for example, non-patent) Reference 1). Here, the scramble pattern is often generated as a PN code sequence or the like. In general, the scramble code is variably set as an initial value given to the PN code generator so that various scramble patterns can be generated.

  As an example, a description will be given of a procedure for scrambling a predetermined data string in one frame in a data transmission method having a frame structure composed of a synchronization word and an information data set serving as a functional channel. Here, the synchronization word becomes a timing signal at the time of decoding, and the information data set is a set of data classified for each function such as voice data and data for communication control.

  In this case, after error correction coding is performed independently for each functional channel included in one frame, each functional channel is combined into one to assemble a frame, and a non-scrambled frame is completed. From this, an exclusive OR of a predetermined data string and a scramble pattern is obtained to create a data string for transmission. The transmission data string created in this way is converted into symbol data, and then used as modulation data for modulation of a carrier wave and sent out on a transmission line. On the transmission data receiving side, after demodulating the transmission data, descrambling that is the reverse of the scrambled procedure can be performed to restore the original information data set and the like.

  As described above, the scramble for the data string constituting one frame is performed on each bit value immediately before the conversion to the symbol data.

“Narrowband Digital Communication System (SCPC / FDMA) Standard ARIB STD-T61 Version 1.0 Volume 2”, May 27, 1999, p. 142-143

  As described above, in order to increase the Euclidean distance in important bit elements as compared with other bit elements, the arrangement of each data in the symbol data is important. Therefore, if each bit value before conversion to symbol data is scrambled as in the prior art, it becomes difficult to take a sufficiently large Euclidean distance in important bit elements.

  Therefore, it is conceivable to improve the error tolerance of the portion by performing predetermined processing on the portion corresponding to the important bit element after scrambling the data string. In this case, however, it is necessary to perform processing for each functional channel after assembling the frame once. Therefore, there is a problem that the processing becomes complicated when the contents of the function channel change and the positions of important bit elements are changed, for example, when the audio data is changed to data for communication control.

  The present invention has been made in view of the above situation, and when improving error resilience using a multi-level modulation scheme, the data sequence is scrambled with a simple operation, and the contents of the functional channel An object of the present invention is to provide a scrambler or the like that can be scrambled by a simple process even when the change occurs.

In order to achieve the above object, a scrambler according to the first aspect of the present invention provides:
Pattern generation means for generating a scramble pattern;
Multiplication value determining means for determining a positive or negative multiplication value corresponding to the bit value of each bit included in the binary bit string constituting the scramble pattern generated by the pattern generating means;
High priority data is supplied with predetermined data, each bit of bit data with high importance is divided and redundant bit data is added, while bit data with low importance has a predetermined number of bits. Symbol data generating means for generating a symbol data string representing a string of multi-level symbols including at least one set of predetermined positive and negative values having equal absolute values in the range by dividing,
Multiplication processing means for performing multiplication between the symbol data and the multiplication value determined corresponding to the bit value of each bit in the scramble pattern by the multiplication value determination means,
It is characterized by that.

  The multiplication value determining means determines −1 as a multiplication value when the bit value included in the scramble pattern is a predetermined bit value as an inversion operation value, and the bit value included in the scramble pattern has a non-inversion operation. When the value is a predetermined bit value, +1 may be determined as the multiplication value.

The scramble processing method according to the second aspect of the present invention provides:
A scramble processing method by a data processing device,
A pattern generation step for generating a scramble pattern;
A multiplication value determining step for determining a positive or negative multiplication value corresponding to the bit value of each bit included in the binary bit string constituting the scramble pattern generated in the pattern generation step;
High priority data is supplied with predetermined data, each bit of bit data with high importance is divided and redundant bit data is added, while bit data with low importance has a predetermined number of bits. A symbol data generation step for generating a symbol data string representing a string of multi-valued symbols including at least one set of predetermined positive and negative values having equal absolute values in the range by dividing;
A multiplication processing step of executing multiplication of the symbol data and a multiplication value determined corresponding to the bit value of each bit in the scramble pattern in the multiplication value determination step;
It is characterized by that.

The program according to the third aspect of the present invention is:
On the computer,
A pattern generation step for generating a scramble pattern;
A multiplication value determining step for determining a positive or negative multiplication value corresponding to the bit value of each bit included in the binary bit string constituting the scramble pattern generated in the pattern generation step;
High priority data is supplied with predetermined data, each bit of bit data with high importance is divided and redundant bit data is added, while bit data with low importance has a predetermined number of bits. A symbol data generation step for generating a symbol data string representing a string of multi-valued symbols including at least one set of predetermined positive and negative values having equal absolute values in the range by dividing;
A multiplication processing step of performing multiplication of the symbol data and the multiplication value determined corresponding to the bit value of each bit in the scramble pattern in the multiplication value determination step;
The process including is executed.

  According to the present invention, the data string can be scrambled by a simple operation, and can be scrambled by simple processing even when the contents of the functional channel change.

It is a figure which shows the example of 1 structure of the scrambler which concerns on embodiment of this invention. It is a flowchart which shows an example of the process performed with a scrambler. It is a figure which shows an example of the program for implement | achieving the process of step S102 and step S103 shown in FIG. It is a figure which shows the structural example of the transmission / reception system containing the transmitter / receiver to which a scrambler is applied. It is a figure which shows typically the process which performs the interleaving to information data. It is a figure which shows an example of the eye pattern which a baseband signal forms. It is a figure which shows a specific example of the output value in each site | part of a scrambler. It is a figure which shows a specific example of the operation | movement which produces | generates a baseband signal.

  Hereinafter, a scrambler according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration example of a scrambler 100 according to an embodiment of the present invention. Each configuration shown in FIG. 1 includes a CPU in a microcomputer system such as LSI (Large Scale Integration) mounted on a communication device that performs communication using a multi-level modulation method such as 4-level FSK (Frequency Shift Keying) modulation. (Central Processing Unit) or a data processing device configured by DSP (Digital Signal Processor) or the like is executed by software by executing a program stored in advance in a ROM (Read Only Memory), or an FPGA (Field- Realized by a hardware data processing device configured using Programmable Gate Array (ASIC) or Application Specific Integrated Circuit (ASIC), or a data processing device combining a predetermined hardware configuration and software configuration Anything may be used. As shown in FIG. 1, the scrambler 100 includes a data input unit 10, a pattern generation unit 11, a multiplication value determination unit 12, a multiplication processing unit 13, and a data output unit 14.

  The data input unit 10 captures a data string to be scrambled into the scrambler 100 from the outside as data to be scrambled. Here, the data sequence captured by the data input unit 10 is a symbol data sequence composed of multi-level symbols including at least one set of predetermined positive and negative values having the same absolute value in the range. As a specific example of such a symbol data string, any symbol data string having symbol values of (+3), (+1), (−1), and (−3) may be used. In this symbol data string, two sets of a positive value (+3) and a negative value (−3) whose absolute value is 3 and a positive value (+1) and a negative value (−1) whose absolute value is 1 are in a range. Will be included. The data input unit 10 sequentially reads out data of a predetermined area to be scrambled one symbol at a time from among data having a frame structure stored in a predetermined frame buffer or memory, for example, and a multiplication processing unit 13 may be supplied.

  The pattern generation unit 11 includes, for example, a logic circuit for generating a PN code, and generates a scramble pattern including binary bit strings “1” and “0”. The scramble pattern generated by the pattern generation unit 11 is supplied to the multiplication value determination unit 12 sequentially, for example, bit by bit.

  The multiplication value determination unit 12 is a multiplication used to scramble the data to be scrambled in correspondence with the bit value in each bit included in the binary bit string constituting the scramble pattern generated by the pattern generation unit 11. Determine the value. Here, the multiplication value determining unit 12 determines a positive or negative multiplication value corresponding to the bit value of each bit included in the binary bit string constituting the scramble pattern. As a specific example, the multiplication value determination unit 12 determines “+1” as the multiplication value if the bit value is “1” corresponding to each bit in the scramble pattern, and the bit value is “0”. If there is, “−1” is determined as the multiplication value. That is, the multiplication value determination unit 12 sets the multiplication value to a positive value when the value in each bit of the binary number included in the scramble pattern is a value (for example, “1”) defined in advance as a non-inversion action value. When the value in each bit included in the scramble pattern is a value (for example, “0”) defined in advance as an inversion action value, the multiplication value is determined to be “−1”, which is a negative value. The multiplication value determined by the multiplication value determination unit 12 is notified to the multiplication processing unit 13.

  The multiplication processing unit 13 performs multiplication of each symbol data included in the symbol data sequence supplied from the data input unit 10 and the multiplication value determined by the multiplication value determination unit 12. The data obtained by the multiplication in the multiplication processing unit 13 is stored in the data output unit 14 from the scrambler 100 as scrambled data, for example, stored in the address of the frame buffer read by the data input unit 10. Is output.

  Next, the operation of the scrambler 100 having the above configuration will be described. FIG. 2 is a flowchart showing an example of processing executed by the scrambler 100. When the processing shown in FIG. 2 is started, first, the data input unit 10 inputs data (symbol data) symbolized into multilevel symbols from the outside to the scrambler 100 as data to be scrambled (step S100). ). Further, the pattern generation unit 11 generates a PN code sequence or the like that becomes a scramble pattern (step S101).

  For example, when the scramble pattern generated by the pattern generation unit 11 in step S101 is sequentially supplied bit by bit, the multiplication value determination unit 12 uses the scramble target data corresponding to the supplied bit value. A multiplication value for scrambling certain symbol data is determined (step S102). Subsequently, the multiplication processing unit 13 performs multiplication of the scramble target data captured by the data input unit 10 in step S100 and the multiplication value determined by the multiplication value determination unit 12 in step S102 (step S103). ). At this time, the multiplication processing unit 13 multiplies the scramble target data for one symbol by the multiplication value determined corresponding to the 1-bit bit value included in the scramble pattern to the number of symbols represented by the scramble target data. Run sequentially until it reaches.

  For example, symbol data (scramble target data) for N symbols supplied from the data input unit 10 to the multiplication processing unit 13 is In [i] (N is a natural number, and 0 ≦ i <N), and the multiplication processing unit 13 The symbol data for N symbols sent from to the data output unit 14 is Out [i]. Further, an N-bit scramble pattern supplied from the pattern generation unit 11 to the multiplication value determination unit 12 is S [i]. In this case, the process of step S102 and step S103 is realizable, for example, when a microcomputer system provided with CPU executes a program as shown in FIG. The program shown in FIG. 3 is a source program when C language is used as the programming language.

  Data indicating a value obtained by the multiplication by the multiplication processing unit 13 is output from the scrambler 100 by the data output unit 14 as scrambled symbol data (step S104). Note that the processing of each step shown in FIG. 2 does not have to be performed by selecting any one of the processings sequentially, and each part of the scrambler 100 shares the processing, so that a plurality of processings are performed. May be executed in parallel.

  The scrambler 100 that realizes the configuration and operation as described above can be applied to, for example, the transceivers 101 and 102 that configure the transmission / reception system as shown in FIG. A specific example in which the scrambler 100 is applied to the transceivers 101 and 102 will be described below.

  The transceivers 101 and 102 have substantially the same configuration as each other, and transmit and receive information data indicating, for example, voice and images via an external transmission path 110 including an external packet network. It is something to do between. Each of the transceivers 101 and 102 includes a transmission device 20 and a reception device 30. For example, the transmission device 20 generates a modulated wave signal obtained by performing multi-level modulation such as 4-level FSK modulation on a carrier wave having a predetermined frequency, and transmits the modulated wave signal to the destination reception device 30 via the transmission line 110. To do. The reception device 30 receives the modulated wave signal transmitted from the transmission device 20 as the transmission source via the transmission path 110, and restores information data indicating sound and images.

  As shown in FIG. 4, each of the transmission devices 20 of the transceivers 101 and 102 includes an information data generation unit 21, an interleave processing unit 22, a baseband signal generation unit 23, in addition to the scrambler 100 described above. A modulation unit 24 and a high-frequency output unit 25 are provided. As shown in FIG. 4, the receiving devices 30 of the transceivers 101 and 102 each include a high frequency input unit 31, a demodulation unit 32, a symbol determination unit 33, a descrambler 34, and a deinterleave processing unit 35. And an information data restoring unit 36.

  The information data generation unit 21 generates information data indicating sound and images captured from, for example, an external environment or an external device. Alternatively, the information data generation unit 21 may output information data by reading information data stored in advance in a predetermined storage device. Here, the information data generated by the information data generation unit 21 may be decomposed into a plurality of frame columns. For example, each frame includes audio data and image data representing audio waveforms and pixel data obtained by dividing audio and images at a constant cycle (for example, every 20 milliseconds).

  Further, the information data generation unit 21 classifies the information data included in each frame into bit data with high importance and bit data with low importance according to a predetermined procedure. As a specific example, out of 44-bit data (encoded audio data) obtained by encoding speech, 18-bit partial data having the highest auditory importance specified according to a predetermined standard is important. It is classified into the most important voice data which is bit data having a high degree. On the other hand, the 26-bit partial data having the highest auditory importance after the most important voice data in the encoded voice data is classified into the unprotected voice data which is the bit data having the lower importance.

  One frame of information data includes 23-bit protection data and 5-bit error detection data in addition to the most important audio data and unprotected audio data. The error detection data is classified into bit data having high importance. The protection data includes 18-bit voice protection data and 5-bit error detection data protection data. The value of each bit constituting the protection data may be “1”.

  The interleave processing unit 22 performs interleaving on the information data generated by the information data generating unit 21. At this time, the interleave processing unit 22 generates 2-bit symbol data corresponding to a symbol in 4-level FSK modulation based on the information data received from the information data generation unit 21.

  More specifically, bit data having high importance is assumed to be protected data, and each bit is divided as shown in FIG. Then, as shown in FIG. 5B, 2-bit data is generated by combining the bits constituting the protection data on a one-to-one basis. The data generated at this time may be combined so that the bit constituting the protection data becomes the lower bit. On the other hand, the bit data having a low importance level is assumed to be unprotected data, and as shown in FIG. As shown in FIG. 5 (C), the interleave processing unit 22 performs the 2-bit data obtained by the division process on the protected data and the addition process of the redundant bit data and the 2-bit data obtained by the division process on the unprotected data. A symbol data string is supplied to the baseband signal generation unit 23 in a predetermined order including portions where bit data are alternately arranged.

  The baseband signal generation unit 23 converts the symbol data sequence supplied from the interleave processing unit 22 into a baseband signal used for quaternary root Nyquist FSK modulation. For example, the baseband signal generated by the baseband signal generator 23 can form an eye pattern as shown in FIG. In the baseband signal shown in FIG. 6, the instantaneous value converges to one of four values at a point (Nyquist point) having a constant phase within one symbol section (section representing information for one symbol). . These four values (symbol values) are (+3), (+1), (−1), and (−3) in order from the largest value, assuming that the second value from the largest value is (+1). Are arranged at equal intervals. Note that the signal itself generated by the baseband signal generation unit 23 may be a digital signal such as an impulse signal forming a symbol data string. By limiting the band of this signal, as shown in FIG. Any signal that can be a baseband signal may be used.

  For example, as shown in FIG. 6, the baseband signal generation unit 23 converts the symbol “11” (2-bit data having the value “11”) included in the symbol data string into a symbol whose symbol value is (−3). The symbol “10” is converted into a symbol interval whose symbol value is (−1), the symbol “00” is converted into a symbol interval whose symbol value is (+1), and the symbol “10” is converted into a symbol interval. “01” is converted into a symbol interval whose symbol value is (+3). By this conversion, the four types of symbols form a Gray code sequence in which the hamming distance between adjacent symbols is 1 when the symbol values are arranged in the order of high (or low) symbol values. In addition, by this conversion, a symbol interval having a symbol value of (−3) or (+3) is formed corresponding to a symbol having a lower one digit “1”.

  Here, since the values of the respective bits constituting the protection data are all “1”, any symbol including bit data with high importance has a symbol value of (+3) or (−3). Is converted into a symbol interval. That is, the symbol value of the symbol obtained by adding the protection data as redundant bit data to the bit data having high importance has the minimum difference between the symbol values of two different symbols as the redundant bit data. It is set to be larger than the minimum value when a symbol is generated without adding. That is, the Euclidean distance in the protected data is set to be larger than that of the unprotected data. In the specific example shown in FIG. 6, the symbol value of the symbol obtained by adding redundant bit data can take the maximum value or the minimum value of the range, but without adding redundant bit data. The symbol value of the obtained symbol can take all values included in the range.

  By adding protection data as redundant bit data to such highly important bit data, the possible symbol values are limited, while the symbol value interval (Euclidean distance) is substantially expanded. Yes. Thereby, the signal-to-noise ratio can be improved. In addition, by the processing in the interleave processing unit 22, symbol intervals corresponding to symbol data including bit data having high importance and symbol intervals corresponding to symbol data including bit data having low importance are arranged alternately. Will include the part. As a result, bit data with high importance is dispersed in the baseband signal, and even when the modulated wave signal is affected by fading during transmission, there is a risk that many pieces of bit data with high importance will be lost together. Can be reduced.

  The baseband signal generated by the baseband signal generation unit 23 in this way is supplied to the scrambler 100. The scrambler 100 scrambles the baseband signal by executing processing as shown in FIG. 2, for example, sequentially for one symbol and one bit of the scramble pattern. The baseband signal scrambled by the scrambler 100 is supplied to the modulation unit 24. The modulation unit 24 may perform band limitation on the baseband signal scrambled by the scrambler 100. Then, the carrier wave is frequency-modulated (4-value FSK modulation) using this signal. The modulated wave signal obtained at this time is supplied to the high-frequency output unit 25. The high frequency output unit 25 performs power amplification of the modulated wave signal supplied from the modulation unit 24 and sends it to the transmission line 110.

  In the receiving apparatus 30, the high frequency input unit 31 supplies the signal to the demodulation unit 32 by performing amplification of the signal received via the transmission path 110. The demodulation unit 32 restores the baseband signal by detecting the reception signal supplied from the high frequency input unit 31. This baseband signal is supplied to the symbol determination unit 33.

  Based on the instantaneous value at each Nyquist point of the baseband signal received from the demodulation unit 32, the symbol determination unit 33 determines a symbol represented by the symbol section including each Nyquist point. Based on the determination result, the scrambled symbol data string is reproduced. The symbol data string reproduced at this time is supplied to the descrambler 34.

  The descrambler 34 interleaves the symbol data sequence received from the symbol determination unit 33 with the multiplication value corresponding to the scramble pattern, similarly to the scrambler 100, by the interleave processing unit 22. The symbol data string in the selected state is reproduced. The symbol data sequence reproduced by the descrambler 34 is supplied to the deinterleave processing unit 35.

  The deinterleave processing unit 35 reproduces the information data sequence by performing a reverse process to the interleave processing unit 22 on the symbol data sequence received from the descrambler 34. For example, the deinterleave processing unit 35 determines whether each symbol data is classified into bit data having high importance or bit data having low importance based on the order of each symbol in the frame. judge. At this time, the symbol data classified as bit data having high importance is separated into, for example, upper 1 bit and lower 1 bit, and upper 1 bit data is extracted. On the other hand, the entire 2-bit data is extracted for the symbol data classified as bit data with low importance. The data extracted in this way are associated with each other and supplied to the information data restoration unit 36.

  The information data restoration unit 36 configures and restores the data string received from the deinterleave processing unit 35 as information data. For example, the information data restoration unit 36 has a lookup table that describes the correspondence between the data string received from the deinterleave processing unit 35 and the information data. By referring to this table, the deinterleave processing unit The information data corresponding to the data string received from 35 is restored.

  In the transmission apparatus 20 to which the scrambler 100 as described above is applied, it is assumed that symbol data as shown in FIG. 7A is supplied from the baseband signal generation unit 23 to the scrambler 100. Here, when band limiting of the baseband signal is performed without scrambling the symbol data as shown in FIG. 7A, a baseband signal having a waveform as shown in FIG. 8A is obtained. It is done. In the baseband signal having a waveform as shown in FIG. 8A, the signal level is biased to a positive region. For this reason, the modulation by the modulation unit 24 is biased, and energy concentration occurs in the modulated wave signal.

  Therefore, in the scrambler 100, the pattern generation unit 11 generates a scramble pattern as shown in FIG. 7B, for example. Corresponding to this scramble pattern, the multiplication value determination unit 12 determines a multiplication value as shown in FIG. 7C, for example, and notifies the multiplication processing unit 13 of the determination. The multiplication processing unit 13 performs multiplication of each symbol value in the symbol data as shown in FIG. 7A and each multiplication value as shown in FIG. Based on the multiplication result, the data output unit 14 sends, for example, symbol data indicating an output symbol as shown in FIG. 7D to the baseband signal generation unit 23.

  When the band of the baseband signal is limited with respect to the symbol data after being scrambled in this way, a baseband signal having a waveform as shown in FIG. 8B is obtained. In the baseband signal having a waveform as shown in FIG. 8B, the signal level is dispersed in both positive and negative regions. Thereby, the bias in the modulation by the modulation unit 24 can be eliminated, and the energy in the modulated wave signal can be dispersed. Further, the symbol data after being scrambled is greatly different from the symbol data before being scrambled. If the receiving device 30 on the receiving side cannot know the scramble pattern generated by the pattern generation unit 11 included in the transmitting device 20 on the transmitting side, the symbol data cannot be correctly restored. Thereby, the confidentiality of information is securable.

  As described above, according to the present invention, “+1” or “−1” corresponding to the bit value of each bit included in the binary bit string constituting the scramble pattern generated by the pattern generation unit 11. The multiplication value of the positive value or the negative value is determined. Then, the multiplication processing unit 13 is a multi-value symbol including a predetermined positive value and negative value pair having the same absolute value, such as (+3), (+1), (−1), and (−3). The multiplication of the symbol data representing each symbol value in the configured symbol data sequence and the multiplication value determined by the multiplication value determination unit 12 is executed. Thus, the symbol data string can be scrambled by a simple operation of multiplying the symbol value by the multiplication value. In addition, since multiplication is performed not on a bit basis but on a symbol basis, the contents of the functional channel change and the positions of important bit elements change, for example, when voice data is changed to data for communication control. Even in such a case, it is possible to scramble with simple processing without changing the processing content.

  In the above embodiment, the four-value root Nyquist FSK modulation method is used as the multi-value modulation method. However, the present invention is not limited to this. For example, a multi-value modulation method having four or more values or a PSK is used. The present invention can also be applied to the case where an arbitrary multilevel modulation method is used, such as a (Phase Shift Keying) modulation method.

  In addition, the scrambler 100 according to the present invention can be realized using a normal computer system, not a dedicated system. For example, a recording medium (for example, an optical disc, a magneto-optical device) that stores a program for realizing the configuration and function as the above-described scrambler 100 in a microcomputer system mounted on a communication device that performs communication using a multi-level modulation method. The program is installed from a disk, a magnetic disk, an IC memory, or the like. Thereby, the scrambler 100 which performs the above-mentioned process can be comprised.

  Further, for example, these programs may be uploaded to an information processing device (for example, a server device) on a telecommunications network and distributed via a communication line, and a carrier wave is modulated by an electric signal representing these programs. Then, the obtained modulated wave signal may be transmitted, and a device that has received the modulated wave signal may perform demodulation to obtain the program. The above-described processing can be executed by activating these programs and executing them in the same manner as other application programs under the control of a predetermined OS (Operating System).

  When the OS shares a part of the processing, or when the OS forms a part of the constituent elements of the present invention, a program excluding the part may be stored in the recording medium. Also in this case, in the present invention, it is assumed that a program for executing each function or step executed by the computer is stored in the recording medium.

DESCRIPTION OF SYMBOLS 10 Data input part 11 Pattern generation part 12 Multiplication value determination part 13 Multiplication process part 14 Data output part 20 Transmission apparatus 21 Information data generation part 22 Interleaving process part 23 Baseband signal generation part 24 Modulation part 25 High frequency output part 30 Reception apparatus 31 High-frequency input unit 32 Demodulation unit 33 Symbol determination unit 34 Descrambler 35 Deinterleave processing unit 36 Information data restoration unit 100 Scrambler 101, 102 Transceiver 110 Transmission path

Claims (4)

Pattern generation means for generating a scramble pattern;
Multiplication value determining means for determining a positive or negative multiplication value corresponding to the bit value of each bit included in the binary bit string constituting the scramble pattern generated by the pattern generating means;
High priority data is supplied with predetermined data, each bit of bit data with high importance is divided and redundant bit data is added, while bit data with low importance has a predetermined number of bits. Symbol data generating means for generating a symbol data string representing a string of multi-level symbols including at least one set of predetermined positive and negative values having equal absolute values in the range by dividing,
Multiplication processing means for performing multiplication between the symbol data and the multiplication value determined corresponding to the bit value of each bit in the scramble pattern by the multiplication value determination means,
A scrambler characterized by that. The multiplication value determining means determines −1 as a multiplication value when the bit value included in the scramble pattern is a predetermined bit value as an inversion operation value, and the bit value included in the scramble pattern has a non-inversion operation. When the value is a predetermined bit value, +1 is determined as the multiplication value.
The scrambler according to claim 1. A scramble processing method by a data processing device,
A pattern generation step for generating a scramble pattern;
A multiplication value determining step for determining a positive or negative multiplication value corresponding to the bit value of each bit included in the binary bit string constituting the scramble pattern generated in the pattern generation step;
High priority data is supplied with predetermined data, each bit of bit data with high importance is divided and redundant bit data is added, while bit data with low importance has a predetermined number of bits. A symbol data generation step for generating a symbol data string representing a string of multi-valued symbols including at least one set of predetermined positive and negative values having equal absolute values in the range by dividing;
A multiplication processing step of executing multiplication of the symbol data and a multiplication value determined corresponding to the bit value of each bit in the scramble pattern in the multiplication value determination step;
A scramble processing method characterized by the above. On the computer,
A pattern generation step for generating a scramble pattern;
A multiplication value determining step for determining a positive or negative multiplication value corresponding to the bit value of each bit included in the binary bit string constituting the scramble pattern generated in the pattern generation step;
High priority data is supplied with predetermined data, each bit of bit data with high importance is divided and redundant bit data is added, while bit data with low importance has a predetermined number of bits. A symbol data generation step for generating a symbol data string representing a string of multi-valued symbols including at least one set of predetermined positive and negative values having equal absolute values in the range by dividing;
A multiplication processing step of performing multiplication of the symbol data and the multiplication value determined corresponding to the bit value of each bit in the scramble pattern in the multiplication value determination step;
A program for executing processing including

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