JP4506701B2 - Multilayer varistor array - Google Patents

Description

  The present invention relates to a multilayer varistor array.

Conventionally, a varistor element body formed by laminating a plurality of varistor layers, first to eighth external electrodes formed on the outer surface of the varistor element body, a first varistor element body and a first varistor layer A first internal electrode electrically connected to the external electrode, a second internal electrode disposed in the varistor element body and electrically connected to the second external electrode, and disposed in the varistor element body And a third internal electrode electrically connected to the third external electrode, a fourth internal electrode disposed in the varistor element body and electrically connected to the fourth external electrode, and a varistor element body And a fifth internal electrode electrically connected to the fifth external electrode and a sixth internal electrode disposed in the varistor element body and electrically connected to the sixth external electrode; , Arranged in the varistor element body and electrically with the seventh external electrode A seventh internal electrode connected to the varistor element body and an eighth internal electrode electrically connected to the eighth external electrode, the first internal electrode and the second internal electrode Each has a first opposing region that faces each other through a varistor layer, and the third internal electrode and the fourth internal electrode respectively have a second opposing region that faces each other through a varistor layer. The fifth internal electrode and the sixth internal electrode each have a third opposing region facing each other through the varistor layer, and the seventh internal electrode and the eighth internal electrode are A multilayer varistor array having fourth opposing regions that face each other through layers is known (see, for example, Patent Document 1).
JP 2000-331805 A

  In recent years, there has been an increasing demand for downsizing electronic components mounted on a mounting substrate in order to reduce the size of electronic devices.

  However, the conventional multilayer varistor array as described in Patent Document 1 requires twice as many external electrodes as the opposing region of each internal electrode. Since these external electrodes need to be formed on the outer surface of the varistor element body in a state of being insulated from each other, it is necessary to ensure a certain size of the varistor element body. For this reason, it has been difficult for conventional multilayer varistor arrays to satisfy recent demands for miniaturization of electronic components.

  An object of the present invention is to provide a multilayer varistor array that can be made smaller than before.

  The multilayer varistor array according to the present invention includes a multilayer body formed by laminating a plurality of functional layers including at least one varistor layer that exhibits voltage nonlinearity, and an outer surface of the multilayer body in an insulated state. The formed first to sixth external electrodes, a first internal electrode disposed in the multilayer body and electrically connected to the first external electrode, and a second external body disposed in the multilayer body A second internal electrode electrically connected to the electrode, a third internal electrode disposed in the laminate and electrically connected to the third external electrode, and a fourth internal electrode disposed in the laminate. A fourth internal electrode electrically connected to the external electrode, a fifth internal electrode disposed in the laminate and electrically connected to the fifth external electrode, and disposed in the laminate. A sixth internal electrode electrically connected to the sixth external electrode; The first internal electrode and the third internal electrode each have a first opposing region facing each other through the varistor layer, and the second internal electrode and the third internal electrode are each a varistor. Each of the fourth internal electrode and the sixth internal electrode has a third opposing region that opposes each other via the varistor layer, and each of the second opposing regions that oppose each other through the layer. The fifth internal electrode and the sixth internal electrode each have a fourth facing region facing each other through the varistor layer.

  In the multilayer varistor array according to the present invention, the first internal electrode is electrically connected to the first external electrode, the second internal electrode is electrically connected to the second external electrode, and the third internal electrode The electrode is electrically connected to the third external electrode, the fourth internal electrode is electrically connected to the fourth external electrode, the fifth internal electrode is electrically connected to the fifth external electrode, The sixth inner electrode is electrically connected to the sixth outer electrode. The first internal electrode and the third internal electrode each have a first opposing region facing each other through the varistor layer, and the second internal electrode and the third internal electrode are the varistor layer. And the fourth internal electrode and the sixth internal electrode each have a third opposing region opposite to each other via the varistor layer, and a fifth opposing region via the varistor layer. The internal electrode and the sixth internal electrode each have a fourth opposing region opposing each other with the varistor layer interposed therebetween. Therefore, the first to sixth external electrodes need only be provided for the first to fourth opposing regions, and the number of external electrodes twice as many as the opposing regions is necessary. The number of external electrodes can be reduced as compared with the multilayer varistor array. As a result, the size of the stacked body can be reduced by the amount of the external electrodes reduced, and the stacked varistor array can be made smaller than before.

  The stacked body is formed by stacking a plurality of functional layers including a plurality of varistor layers, and the first and second internal electrodes are formed together on one varistor layer of the plurality of varistor layers. The fourth and fifth internal electrodes are preferably formed together in another varistor layer different from the one varistor layer among the plurality of varistor layers. In this way, since the number of varistor layers required to form the stacked body can be reduced, the stacked varistor array can be further downsized.

  In addition, it is preferable that the third internal electrode is further formed on another varistor layer, and the sixth internal electrode is further formed on one varistor layer. In this way, since the number of varistor layers required to form the stacked body can be further reduced, the stacked varistor array can be further reduced in size.

  The stacked body has first and second outer surfaces that extend in a direction along the stacking direction of the functional layers and face each other, and first to third external electrodes are formed on the first outer surface, The fourth to sixth external electrodes are formed on the second outer surface, and the first and second opposing regions have the first outer surface and the second outer surface when viewed from the stacking direction of the functional layers. The third and fourth opposing regions are located together in a region between the intermediate position between the surface and the second outer surface, and the third and fourth opposing regions are located between the intermediate position and the first outer surface when viewed from the stacking direction of the functional layer. It is preferred that they are located together in a region between the surface.

  In such a multilayer varistor array, after forming a laminate in which a functional layer including at least one varistor layer mainly composed of ZnO or the like is formed, a conductive material that becomes each external electrode in a predetermined region on the outer surface of the laminate. It is formed by transferring and baking the paste, and performing electroplating (here, for example, barrel plating) on the conductor after baking. However, there is a slight gap at the interface between the varistor layer and each internal electrode formed on the varistor layer, and the conductor after baking has a large number of pores. Furthermore, the plating solution may enter the gaps at the interfaces between these varistor layers and the respective internal electrodes through the pores of the conductor, and the plating solution may penetrate into the gaps due to capillary action.

  By the way, in barrel plating, a current is passed between the anode electrode (anode) and the cathode electrode (cathode) while stirring the laminate and the dummy medium in the plating solution in the barrel. Metal is plated on the surface of a conductor connected to the cathode electrode via a dummy medium. At this time, since the plating solution has entered the gap at the interface between the varistor layer and each internal electrode, hydrogen is generated in the plating solution that has entered the gap at the same time as plating is performed on the conductor. Will be. Then, since hydrogen has an extremely high reducibility, the Schottky barrier at the grain boundary of the ZnO particles constituting the varistor layer is damaged by the reducing action at the portion where the plating solution has penetrated. As a result, in particular, the voltage nonlinearity may be deteriorated by losing the Schottky barrier in each facing region.

  However, as described above, when the first and second opposing regions are viewed from the stacking direction of the functional layer, the intermediate position between the first outer surface and the second outer surface and the second outer surface The first and second opposing regions can be arranged away from the first outer surface through which the plating solution enters. Similarly, the third and fourth opposing regions are regions between the first outer surface and the intermediate position between the first outer surface and the second outer surface when viewed from the stacking direction of the functional layers. Therefore, the third and fourth opposing regions can be arranged so as to be separated from the second outer surface through which the plating solution enters. As a result, it is possible to suppress degradation of voltage nonlinearity due to penetration of the plating solution.

The first internal electrode is electrically connected to the first external electrode via a first lead conductor extending so as to be drawn to the first outer surface, and the second internal electrode is connected to the first external electrode. The third lead electrode is electrically connected to the second external electrode via a second lead conductor extending so as to be drawn to the outer surface, and the third inner electrode extends so as to be drawn to the first outer surface. The fourth external electrode is electrically connected to the third external electrode via a conductor, and the fourth internal electrode is electrically connected to the fourth external electrode via a fourth lead conductor extending so as to be drawn to the second outer surface. The fifth internal electrode is electrically connected to the fifth external electrode via a fifth lead conductor extending so as to be drawn to the second outer surface, and the sixth internal electrode is Through a sixth lead conductor extending so as to be drawn to the outer surface of 2 A portion other than the end portion of the first to third lead conductors, which is electrically connected to the sixth external electrode and is wider than the width of the end portion on the first outer surface side of the first to third lead conductors. The width of the portion other than the end portion of the fourth to sixth lead conductors is wider than the width of the end portion on the second outer surface side of the fourth to sixth lead conductors. Is preferably set to be wide. If it does in this way, since the width | variety of the edge part of the lead conductor exposed to each outer surface of a laminated body becomes narrower than another part, the penetration | invasion amount of the plating solution to the laminated body is suppressed. Even if the plating solution penetrates until it reaches each facing area, the plating solution diffuses in parts other than the ends of the lead conductors that are wide, so the amount of penetration of the plating solution into the laminated body is constant. In this case, the amount of plating solution per unit area of each internal electrode is reduced. Therefore, it is possible to further suppress deterioration of voltage nonlinearity due to penetration of the plating solution.

  According to the present invention, it is possible to provide a multilayer varistor array that can be made smaller than before.

  Preferred embodiments of the present invention will be described with reference to the drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and a duplicate description is omitted.

(First embodiment)
The configuration of the multilayer varistor array 100 according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a perspective view showing the multilayer varistor array according to the first embodiment. FIG. 2 is an exploded perspective view of the varistor element body constituting the multilayer varistor array according to the first embodiment.

  As shown in FIG. 1, the multilayer varistor array 100 includes a varistor element body 10 having a substantially rectangular parallelepiped shape, and the varistor element body 10 constitutes a main body of the multilayer varistor array 100.

  In addition, the multilayer varistor array 100 includes first to third external electrodes 12A to 12C formed on the first outer surface 10a of the varistor element body 10, and first electrodes formed on the second outer surface 10b. 4 to 6 external electrodes 12D to 12F. The first to third external electrodes 12A to 12C extend in a strip shape in the stacking direction of varistor layers A1 to A6 (hereinafter simply referred to as “stacking direction”), and both ends of the first to third external electrodes 12A to 12C rotate around the upper surface 10e and the lower surface 10f. Formed. The fourth to sixth external electrodes 12D to 12F extend in a strip shape in the stacking direction, and both end portions thereof are formed to wrap around the upper surface 10e and the lower surface 10f.

  The external electrodes 12A to 12F are transferred to the first and second outer surfaces 10a and 10b, the upper surface 10e, and the lower surface 10f of the varistor element body 10 after transferring electrode pastes mainly composed of Ag, Cu, or Ni, respectively, to a predetermined temperature. It is formed by baking (for example, 700 to 800 ° C.) and further plating such as Cu, Ni, and Sn by electroplating such as barrel plating. The first, second, fourth and sixth external electrodes 12A, 12B, 12D and 12E function as input / output electrodes, respectively, and the third and fourth external electrodes 12C and 12F function as ground electrodes, respectively. .

  The varistor element body 10 has first and second outer surfaces 10a and 10b facing each other, third and fourth outer surfaces 10c and 10d facing each other, and an upper surface 10e and a lower surface 10f facing each other. The outer shape is defined by these surfaces 10a to 10f. In the varistor element body 10, for example, the length in the longitudinal direction can be set to about 1.6 mm, the width can be set to about 0.8 mm, and the thickness can be set to about 0.5 mm.

  As shown in FIG. 2, the varistor element body 10 includes a plurality of (six layers in the first embodiment) varistor layers A1 to A6 that exhibit voltage nonlinearity (hereinafter referred to as “varistor characteristics”). It is formed by being laminated by the lamination method. In the actual laminated varistor array 100, the boundaries between the varistor layers A1 to A6 are integrated so as not to be visually recognized. The varistor layers A1 to A6 contain ZnO (zinc oxide) as a main component, and include rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, and alkali metal elements as subcomponents. It consists of a simple substance such as (K, Rb, Cs) and an alkaline earth metal element (Mg, Ca, Sr, Ba) or an element containing these oxides. The varistor layers A1 to A6 can each have a thickness of about 30 μm.

  On the surface of the varistor layer A3, a first internal electrode 14A, a second internal electrode 14B, and a sixth internal electrode 14F each having a substantially rectangular shape are formed so as to be insulated from each other. Therefore, each internal electrode 14A, 14B, 14F is arranged in the varistor element body 10, respectively. The first inner electrode 14A is integrally formed with one end of the first lead conductor 16A drawn toward the end surface A3a of the varistor layer A3 that becomes the first outer surface 10a of the varistor element body 10. ing. A second lead conductor 16B drawn toward the end surface A3a of the varistor layer A3 is integrally formed at one end of the second internal electrode 14B. A sixth lead conductor 16F drawn toward the end face A3b of the varistor layer A3 that becomes the second outer surface 10b of the varistor element body 10 is integrally formed on the sixth inner electrode 14F at the center thereof. Has been.

  The other end of the first lead conductor 16A that is not connected to the first internal electrode 14A is exposed at the end face A3a of the varistor layer A3, and is physically and electrically connected to the first external electrode 12A. Yes. The other end of the second lead conductor 16B that is not connected to the second internal electrode 14B is exposed at the end face A3a of the varistor layer A3, and is physically and electrically connected to the second external electrode 12B. Yes. The other end of the sixth lead conductor 16F that is not connected to the sixth internal electrode 14F is exposed at the end face A3b of the varistor layer A3, and is physically and electrically connected to the sixth external electrode 12F. Yes. Therefore, the first inner electrode 14A is electrically connected to the first outer electrode 12A via the first lead conductor 16A, and the second inner electrode 14B is electrically connected to the first outer electrode 12B via the second lead conductor 16B. The second external conductor 12B is electrically connected, and the sixth internal electrode 14F is electrically connected to the sixth external electrode 12F via the sixth lead conductor 16F.

  On the surface of the varistor layer A4, a third internal electrode 14C, a fourth internal electrode 14D, and a fifth internal electrode 14E each having a substantially rectangular shape are formed so as to be insulated from each other. Therefore, each internal electrode 14C, 14D, 14E is arranged in the varistor element body 10, respectively. A third lead conductor 16C drawn toward the end face A4a of the varistor layer A4 that becomes the first outer surface 10a of the varistor element body 10 is integrally formed in the center portion of the third inner electrode 14C. Has been. A fourth lead conductor 16D drawn toward the end face A4b of the varistor layer A4 is integrally formed at one end of the fourth internal electrode 14D. A fifth lead conductor 16E drawn toward the end surface A4b of the varistor layer A4 that becomes the second outer surface 10b of the varistor element body 10 is integrally formed at one end of the fifth internal electrode 14E. ing.

  The other end of the third lead conductor 16C that is not connected to the third internal electrode 14C is exposed at the end face A4a of the varistor layer A4, and is physically and electrically connected to the third external electrode 12C. Yes. The other end of the fourth lead conductor 16D that is not connected to the fourth inner electrode 14D is exposed at the end face A4b of the varistor layer A4, and is physically and electrically connected to the fourth outer electrode 12D. Yes. The other end of the fifth lead conductor 16E that is not connected to the fifth internal electrode 14E is exposed at the end face A4b of the varistor layer A4, and is physically and electrically connected to the fifth external electrode 12E. Yes. Therefore, the third inner electrode 14C is electrically connected to the third outer electrode 12C via the third lead conductor 16C, and the fourth inner electrode 14D is connected to the third outer electrode 12C via the fourth lead conductor 16D. The fourth external conductor 12D is electrically connected, and the fifth internal electrode 14E is electrically connected to the fifth external electrode 12E via the fifth lead conductor 16E.

  Here, the first internal electrode 14A and the third internal electrode 14C each have a first opposing region 18A that is opposed to each other via the varistor layer A3. The second internal electrode 14B and the third internal electrode 14C each have a second facing region 18B facing each other through the varistor layer A3. The fourth internal electrode 14D and the sixth internal electrode 14F each have a third facing region 18C facing each other via the varistor layer A3. The fifth internal electrode 14E and the sixth internal electrode 14F have fourth opposing regions 18D that face each other via the varistor layer A3. In the first embodiment, the first and second opposing regions 18A and 18B have the first intermediate position M and the first position between the first outer surface 10a and the second outer surface 10b when viewed from the stacking direction. It is located in the 1st field D1 which is a field between the outer surface 10a of this. Further, when the third and fourth opposing regions 18C and 18D are viewed from the stacking direction, the intermediate position M between the first outer surface 10a and the second outer surface 10b and the second outer surface 10b It is located in the 2nd field D2 which is the field between. In addition, these 1st-4th opposing area | regions 18A-18D are the parts each shown with the oblique line in FIG.

  Each internal electrode 14A-14F and each lead conductor 16A-16F contain a conductive material. Although it does not specifically limit as a electrically conductive material contained in each internal electrode 14A-14F and each extraction conductor 16A-16F, It is preferable to consist of Pd or an Ag-Pd alloy. Each of the internal electrodes 14A to 14F and the lead conductors 16A to 16F can have a thickness of about 2 μm, for example.

  As described above, in the multilayer varistor array 100 according to the first embodiment, the first to third external electrodes 12A to 12C are formed on the first outer surface 10a, and the second outer surface 10b has the first Fourth to sixth external electrodes 12D to 12F are formed. The first internal electrode 14A is electrically connected to the first external electrode 12A, the second internal electrode 14B is electrically connected to the second external electrode 12B, and the third internal electrode 14C is connected to the first external electrode 12B. 3 external electrode 12C, the fourth internal electrode 14D is electrically connected to the fourth external electrode 12D, and the fifth internal electrode 14E is electrically connected to the fifth external electrode 12E. The sixth inner electrode 14F is electrically connected to the sixth outer electrode 12F. The first internal electrode 14A and the third internal electrode 14C have first opposing regions 18A that face each other via the varistor layer A3, and the second internal electrode 14B and the third internal electrode 14C The internal electrode 14C has second opposing regions 18B that are opposed to each other via the varistor layer A3, and the fourth internal electrode 14D and the sixth internal electrode 14F are interposed through the varistor layer A3. Each of the fifth internal electrode 14E and the sixth internal electrode 14F has a fourth counter region 18D that faces each other via the varistor layer A3. is doing. Therefore, the multilayer varistor array 100 according to the first embodiment only needs to include the first to sixth external electrodes 12A to 12F with respect to the first to fourth opposing regions 18A to 18D. As a result, the number of external electrodes can be reduced as compared with the conventional multilayer varistor array that requires twice as many external electrodes as the number of internal electrode pairs. As a result, the size of the varistor element body 10 can be reduced by an amount corresponding to the reduction in the number of external electrodes, and the stacked varistor array 100 can be integrated while achieving a smaller size than in the prior art. .

(Second Embodiment)
Next, the configuration of the multilayer varistor array 200 according to the second embodiment will be described with reference to FIGS. 1 and 3. FIG. 3 is an exploded perspective view of the varistor element body constituting the multilayer varistor array according to the second embodiment. Below, it demonstrates centering around difference with the multilayer varistor array 100 which concerns on 1st Embodiment, and the overlapping description is abbreviate | omitted.

  On the surface of the varistor layer A2, first and second internal electrodes 14A and 14B each having a substantially rectangular shape are formed so as to be insulated from each other. The first inner electrode 14A is integrally formed with one end of a first lead conductor 16A led out toward the end surface A2a of the varistor layer A2 serving as the first outer surface 10a of the varistor element body 10. ing. A second lead conductor 16B drawn toward the end face A2a of the varistor layer A2 is integrally formed at one end of the second internal electrode 14B.

  A third internal electrode 14C having a substantially rectangular shape is formed on the surface of the varistor layer A3. A third lead conductor 16C drawn toward the end face A3a of the varistor layer A3, which becomes the first outer surface 10a of the varistor element body 10, is formed integrally with the third inner electrode 14C at the center thereof. Has been.

  On the surface of the varistor layer A4, fourth and fifth internal electrodes 14D and 14E each having a substantially rectangular shape are formed so as to be insulated from each other. The first inner electrode 14D is integrally formed with one end of the first lead conductor 16D drawn toward the end surface A4b of the varistor layer A4 that becomes the second outer surface 10b of the varistor element body 10. ing. A fifth lead conductor 16E drawn toward the end face A4b of the varistor layer A4 is integrally formed at one end of the fifth internal electrode 14E.

  A sixth internal electrode 14F having a substantially rectangular shape is formed on the surface of the varistor layer A5. A sixth lead conductor 16F drawn toward the end face A5b of the varistor layer A5 that becomes the second outer surface 10b of the varistor element body 10 is integrally formed in the center portion of the sixth internal electrode 14F. Has been.

  In the second embodiment, the first and second opposing regions 18A and 18B have an intermediate position M and a second position between the first outer surface 10a and the second outer surface 10b when viewed from the stacking direction. It is located in 2nd area | region D2 which is an area | region between the outer surfaces 10b. Further, when the third and fourth opposing regions 18C and 18D are viewed from the stacking direction, the intermediate position M between the first outer surface 10a and the second outer surface 10b and the first outer surface 10a It is located in the 1st field D1 which is the field between. Each of these facing regions 18A to 18D is a portion indicated by hatching in FIG.

  As described above, in the multilayer varistor array 200 according to the second embodiment, as in the multilayer varistor array 100 according to the first embodiment, the multilayer varistor array 100 is integrated while achieving a reduction in size. Can be achieved.

  In the multilayer varistor array 200 according to the second embodiment, the first and second opposing regions 18A and 18B are both located in the second region D2. The third and fourth opposing regions 18C and 18D are both located in the first region D1. Therefore, each opposing area | region 18A-18D will be arrange | positioned in the varistor element | base_body 10 so that it may leave | separate from the 1st outer surface 10a or the 2nd outer surface 10b which plating solution penetrate | invades. As a result, the plating solution enters the gaps at the interfaces between the varistor element body 10 and the internal electrodes 14A to 14F and the lead conductors 16A to 16F through the pores of the conductors that form the external electrodes 12A to 12F. Therefore, it is possible to suppress deterioration of the varistor characteristics.

(Third embodiment)
Next, the configuration of the multilayer varistor array 300 according to the third embodiment will be described with reference to FIGS. 1 and 4. FIG. 4 is an exploded perspective view of the varistor element body constituting the multilayer varistor array according to the third embodiment. Below, it demonstrates centering around difference with the multilayer varistor array 100 which concerns on 1st and 2nd embodiment, and the overlapping description is abbreviate | omitted.

  The first to third lead conductors 16A to 16C are drawn to the first outer surface 10a, end portions 16Aa to 16Ca on the first outer surface 10a side, and the end portions 16Aa to 16Ca and the first end portions 16Aa to 16Ca. To third connecting electrodes 16Ab to 16Cb for connecting the third inner electrodes 14A to 14C, respectively. Further, the fourth to sixth lead conductors 16D to 16F are respectively drawn from the second outer surface 10b by the end portions 16Da to 16Fa on the second outer surface 10b side, and the end portions 16Da to 16Fa. Each of the connecting portions 16Db to 16Fb connecting the fourth to sixth inner electrodes 14D to 14F is provided. And the width of each connection part 16Ab-16Fb which is parts other than each edge part 16Aa-16Fa of each extraction conductor 16A-16F becomes wider than the width | variety of each edge part 16Aa-16Fa, as FIG. 4 shows. Is set to

  As described above, in the multilayer varistor array 300 according to the third embodiment, as in the multilayer varistor array 100 according to the first embodiment, the multilayer varistor array 100 is integrated while achieving a reduction in size. Can be achieved.

  Further, in the multilayer varistor array 300 according to the third embodiment, it is possible to suppress the deterioration of the varistor characteristics, similarly to the multilayer varistor array 200 according to the second embodiment.

  Furthermore, in the multilayer varistor array 300 according to the third embodiment, the widths of the connection portions 16Ab to 16Fb of the lead conductors 16A to 16F are set to be wider than the widths of the end portions 16Aa to 16Fa. Therefore, it is possible to suppress the penetration amount of the plating solution into the varistor element body 10. Even if the plating solution penetrates until it reaches each of the opposing regions 18A to 18D, the plating solution diffuses in each of the connection portions 16Ab to 16Fb of the wide lead conductors 16A to 16F. When the amount of penetration into the element body 10 is constant, the amount of plating solution per unit area of each internal electrode 14A to 14F is reduced. Therefore, it is possible to further suppress the deterioration of the varistor characteristics due to the penetration of the plating solution.

  Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments. For example, in the multilayer varistor array 100 according to the first embodiment, the first, second and sixth internal electrodes 14A, 14B, 14F are formed on the same varistor layer A3, and the third, fourth and fifth The internal electrodes 14C, 14D, and 14E are formed on the same varistor layer A4, but are not limited thereto. That is, as shown in FIG. 5, the first and second internal electrodes 14A and 14B are formed on the varistor layer A2, the third internal electrode 14C is formed on the varistor layer A3, and the fourth and fifth The internal electrodes 14D and 14E may be formed on the varistor layer A4, and the sixth internal electrode 14F may be formed on the varistor layer A5. Further, as shown in FIG. 6, the first internal electrode 14A is formed on the varistor layer A2, the third internal electrode 14C is formed on the varistor layer A3, and the second internal electrode 14B is formed on the varistor layer A4. The fourth internal electrode 14D is formed on the varistor layer A5, the sixth internal electrode 14F is formed on the varistor layer A6, and the fifth internal electrode 14E is formed on the varistor layer A7. It may be.

  In the first embodiment, the first to third inner electrodes 14A to 14C are drawn to the first outer surface 10a side by the first to third lead conductors 16A to 16C, respectively. It may be drawn to the outer surface 10b side. Further, in the first embodiment, the fourth to sixth inner electrodes 14D to 14F are drawn to the second outer surface 10b side by the fourth to sixth lead conductors 16D to 16F. It may be drawn to the surface 10a side.

  In the first to third embodiments, the varistor element body 10 is formed by laminating the varistor layers A1 to A8. However, a layer sandwiched by at least a pair of internal electrodes forming the opposing region is a varistor layer. It only has to be.

  In the first to third embodiments, the third internal electrode 14C has the first and second opposing regions 18A and 18B that face the first and second internal electrodes 14A and 14B through the varistor layer, respectively. The sixth internal electrode 14F has third and fourth opposing regions 18C and 18D that face the fourth and fifth internal electrodes 14D and 14E through the varistor layer. In addition, the sixth internal electrodes 14C and 14F may further have three or more opposing regions by opposing the other internal electrodes.

It is a perspective view which shows the lamination type varistor array which concerns on 1st Embodiment. It is a disassembled perspective view of the varistor element body constituting the multilayer varistor array according to the first embodiment. It is a disassembled perspective view of the varistor element body which comprises the laminated varistor array which concerns on 2nd Embodiment. It is a disassembled perspective view of the varistor element body which comprises the multilayer varistor array which concerns on 3rd Embodiment. It is a perspective view which shows the modification of the multilayer varistor array which concerns on 1st Embodiment. It is a perspective view which shows another modification of the multilayer varistor array which concerns on 1st Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Varistor element | base_body, 10a ... 1st outer surface, 10b ... 2nd outer surface, 12A-12F ... 1st-6th external electrode, 14A-14F ... 1st-6th internal electrode, 16A- 16F ... first to sixth lead conductors, 18A to 18D ... first to fourth opposing regions, 100, 200, 300 ... multilayer varistor array, A1-A8 ... varistor layer, D1 ... first region, D2 ... second region, M ... intermediate position.

Claims (3)

A laminated body formed by laminating a plurality of functional layers including a plurality of varistor layers expressing voltage nonlinearity;
First to sixth external electrodes respectively formed on the outer surface of the laminate in a state of being insulated from each other;
A first internal electrode disposed in the laminate and electrically connected to the first external electrode;
A second internal electrode disposed in the laminate and electrically connected to the second external electrode;
A third internal electrode disposed in the laminate and electrically connected to the third external electrode;
A fourth internal electrode disposed in the laminate and electrically connected to the fourth external electrode;
A fifth internal electrode disposed in the laminate and electrically connected to the fifth external electrode;
A sixth internal electrode disposed in the laminate and electrically connected to the sixth external electrode;
The first internal electrode and the third internal electrode each have a first opposing region facing each other through the varistor layer,
The second internal electrode and the third internal electrode each have a second opposing region facing each other through the varistor layer,
The fourth internal electrode and the sixth internal electrode each have a third opposing region facing each other through the varistor layer,
The fifth internal electrode and the sixth internal electrode each have a fourth opposing region facing each other through the varistor layer,
The first and second internal electrodes are formed together in one varistor layer of the plurality of varistor layers;
The fourth and fifth internal electrodes are formed together in another varistor layer different from the one varistor layer among the plurality of varistor layers;
The third internal electrode is further formed on the other varistor layer;
The multilayer varistor array, wherein the sixth internal electrode is further formed on the one varistor layer. A plurality of functional layers including at least one varistor layer that exhibits voltage non-linearity are stacked, and have first and second outer surfaces that extend in a direction along the stacking direction of the functional layers and face each other. A laminate,
First to third external electrodes respectively formed on the first outer surface in a state of being insulated from each other;
Fourth to sixth external electrodes respectively formed on the second outer surface in a state of being insulated from each other;
A first internal electrode disposed in the laminate and electrically connected to the first external electrode;
A second internal electrode disposed in the laminate and electrically connected to the second external electrode;
A third internal electrode disposed in the laminate and electrically connected to the third external electrode;
A fourth internal electrode disposed in the laminate and electrically connected to the fourth external electrode;
A fifth internal electrode disposed in the laminate and electrically connected to the fifth external electrode;
A sixth internal electrode disposed in the laminate and electrically connected to the sixth external electrode;
The first internal electrode and the third internal electrode each have a first opposing region facing each other through the varistor layer,
The second internal electrode and the third internal electrode each have a second opposing region facing each other through the varistor layer,
The fourth internal electrode and the sixth internal electrode each have a third facing region facing each other through the varistor layer,
The fifth internal electrode and the sixth internal electrode each have a fourth opposing region facing each other through the varistor layer,
Said first and second opposing region, the intermediate position and the first outer surface between said between said first outer surface when viewed from the laminating direction of the functional layer second outer surface Located in the area between,
The stacked type, wherein the third and fourth opposing regions are located together in a region between the intermediate position and the second outer surface when viewed from the stacking direction of the functional layers. Varistor array. The laminate is formed by laminating a plurality of functional layers including a plurality of varistor layers,
The first and second internal electrodes are formed together in one varistor layer of the plurality of varistor layers;
3. The stacked type according to claim 2, wherein the fourth and fifth internal electrodes are formed together in another varistor layer different from the one varistor layer among the plurality of varistor layers. Varistor array.

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