JP4506330B2 - Synchronization control method and synchronization signal output apparatus using the synchronization control method - Google Patents

Description

  The present invention relates to a synchronization control method and a synchronization signal output apparatus using the synchronization control method.

  A conventional synchronization signal output device will be described with reference to FIG. The synchronization signal output device 10 shown in FIG. 9 instructs the operation timing of the connected device 20 based on the highly accurate timing obtained by connecting to an ISDN (Integrated Services Digital Network), that is, the timing signal received from the outside. The synchronization signal Sig1 is generated and output to the connection device 20. The connected device 20 operates according to the synchronization signal Sig1.

For reference, an invention related to a frame synchronization method between base stations of a mobile communication system is disclosed in Patent Document 1.
Japanese Patent No. 3406745

  Recently, ADSL (Asymmetric Digital Subscriber Line) has begun to spread in place of ISDN. However, even if it is attempted to synchronize as usual with ADSL, the data format and communication speed differ between ISDN and ADSL, so of course, if the synchronization signal output device 10 is not changed, synchronization with ADSL is not possible and the synchronization signal Sig1 is also generated. Can not. Therefore, it is necessary to develop a synchronization signal output device 10 that uses a new synchronization control method that can synchronize with ADSL, but in order to make it an ADSL compatible version, a higher-performance timing acquisition function than the current product of the ISDN compatible version Therefore, the synchronization signal output device 10 becomes expensive and unsuitable for spreading the synchronization signal output device 10. For example, a method of extracting time information from a received wave by a GPS (Global Positioning System) is conceivable. However, since a system using GPS is expensive in the first place, it is also unsuitable for spreading the synchronization signal output device 10.

  The present invention is intended to solve such a problem, and the object of the present invention is to provide a synchronization that can output an accurate synchronization clock with an inexpensive configuration without using ISDN, ADSL, or GPS. A control method and a synchronization signal output device using the synchronization control method are provided.

In order to solve the above problem, in the synchronous control method according to claim 1,
Based on the timing signal received from the outside, a synchronization signal output device that generates a synchronization signal that instructs the operation timing of the connected device and outputs the generated synchronization signal to the connected device,
An antenna and an RF section;
The generation timing of the unique word signal included in the control signal of the TDMA signal emitted from the plurality of PHS base stations detected from the output of the RF unit is monitored for each PHS base station, and the current status is the only one according to the base station selection command from the control means The current signal reading timing is selected so as to eliminate the difference between the generation timing of the unique word signal included in the control signal of the TDMA signal from the reference station and the current signal reading timing. A TDMA unit that self-corrects and outputs a corrected reference signal synchronized with the corrected read timing;
A self-machine operation / connection device reference clock generator capable of variably generating a clock signal for the self-machine operation / connection device that is a reference of the operation timing within the own device and also a reference of the synchronization signal;
When receiving a plurality of the differences before correction for a plurality of PHS base stations from the TDMA unit, to the TDMA unit to select the PHS base station that has the smallest difference among the plurality of differences as the reference station. Outputs the base station selection command, and if the timing of the clock signal for the own operation / connection device is late or early with respect to the corrected reference signal, it is for the own operation / connection device so that it is synchronized with the corrected reference signal. Control means for causing the own device operation / connection device reference clock generation unit to control the timing for generating the clock signal,
The unique word signal of the control signal issued by the PHS base station is monitored, and only one reference station can be selected from the plurality of PHS base stations during the same period. A synchronization signal is output to the connected device so as to synchronize with the obtained unique word signal .

The receiver, that is, the synchronization signal output device monitors the unique word signal included in the control signal generated by the PHS base station, and the generation timing of the synchronization signal generated by the own device is later than the timing of receiving the unique word signal. Alternatively, as soon as possible, the generation timing of the synchronization signal generated by itself is corrected so as to synchronize with the timing of receiving the unique word signal from the PHS base station. The synchronization signal generation timing can be accurately maintained with a simple hand. That is, an accurate synchronous clock can be generated with an inexpensive configuration. At this time, if there is only one PHS base station that is the source of synchronization, this PHS base station itself will suffer from a functional failure, causing a communication trouble, or entering into a maintenance time zone and becoming unable to communicate. Then, during the period until the communication function is restored, the synchronization signal output device may not be able to output the synchronization signal to the connected device, and the operation of the connected device may not be able to be controlled. Since a synchronization signal is output to the connected device while only one PHS base station suitable for the reference station can be selected from the base stations (during the same period), the operation control of the connected device as described above is performed. The possibility of being worried about the impossible situation can be reduced.

To help understanding of the present invention, the first reference embodiment of the synchronous signal output device reference to FIGS, the second reference embodiment referring to FIGS. 5 and 6, the synchronous control method according to the present invention One embodiment used will be described below with reference to FIGS. In addition, since the connection apparatus which acquires a synchronizing signal from a synchronizing signal output device is not different from what was described in the column of background art, description is abbreviate | omitted below.

(First reference form)
FIG. 1 is an explanatory diagram of a synchronization signal output device according to the present embodiment , FIG. 2 is an explanatory diagram of a unique word signal included in a control signal of a TDMA signal detected by the synchronization signal output device, and FIG. FIG. 4 is a block diagram showing the internal configuration of the output device, and FIG. 4 is a flowchart showing the operation of the synchronization signal output device.

  As illustrated in FIG. 1, the synchronization signal output device 10 monitors a unique word signal of a control signal emitted from a base station 30 of a PHS (Personal Handyphone System) and synchronizes with the unique word signal. The synchronization signal Sig1 is output to (not shown).

Prior to the description of the synchronization signal output device 10, the unique word signal of the control signal generated by the PHS base station 30 will be described with reference to FIG. The PHS communication system that is widely used in Japan mainly adopts TDMA-TDD (Time Division Multiple Access-Time Division Duplex). As one form, there are a total of 8 slots of 4 slots for transmission and 4 slots for reception. A form in which a one-cycle substantially regular call and communication is performed is adopted. Each slot is used as a so-called CCH control channel that plays a role of a control signal of a TDMA signal, or a so-called TCH communication channel. FIG. 2A shows a time chart in which only the control channel CCH is extracted from the eight slots, and it should be noted that the eight slots are connected in time series. In the first and second reference embodiments and one embodiment of the present invention, it is assumed that the control channel CCH is wirelessly transmitted from the PHS base station 30 at a constant period (for example, approximately 100 msec).

  As shown in FIG. 2 (b), the detailed configuration of the control channel CCH conforms to the RCR STD-28 standard. In the time series, the ramp bit R, the start symbol SS, the preamble PR, the unique word UW, the channel identification Each part of CI, a source identification code used as a base station identification code, information I defining control contents, CRC, and guard bits is continuously made into one frame. Here, as for the part of the unique word UW, it is a standard that the code promised between the supplier providing the PHS base station 30 and the supplier providing the synchronization signal output apparatus 10 is arbitrarily determined and set. Allowed above. Such a control channel CCH consists of a total of 240 bits including a total of 16 guard bits.

  A synchronization signal output apparatus 10 using such a control channel CCH will be described with reference to the block diagram of FIG.

  The synchronization signal output device 10 includes an antenna 1a and an RF unit 1b, a TDMA unit 2, a local device reference clock generation unit 3 called TCXO, a connected device reference clock generation unit 4, and a control unit 5 including a CPU. It is prepared for.

  The antenna 1a and the RF unit 1b receive radio waves from the PHS base station 30, convert them to electrical signals, and demodulate them.

  The TDMA unit 2 receives the output of the RF unit 1b and demodulates it, for example, by time division processing. Further, the TDMA unit 2 corresponds to the unique word UW among the control signals corresponding to the control channel CCH of the TDMA signal. A unique word signal is detected. Then, the generation timing of the detected unique word signal is monitored, and the current signal reading timing is self-corrected so as to eliminate the difference between the generation timing of the unique word signal and the current signal reading timing.

  That is, the TDMA unit 2 includes a bit counter (not shown) that counts a total of 240 bits representing the control channel CCH, and operates according to the clock signal supplied from the own reference clock generation unit 3. Since the clock signal supplied from the own device reference clock generation unit 3 varies in the first place, the TDMA unit 2 compares the bit count value of the unique word signal obtained via the RF unit 1b with the default value, and the difference between the two values is obtained. Is recognized, the generation timing of the unique word signal obtained via the RF unit 1b is made normal, and it is determined that the clock signal supplied from the own reference clock generation unit 3 is late or early. Then, the TDMA unit 2 sets the bit count value to the default value (the total bit count number default value of 240 or the bit of the unique word signal while the clock signal supplied from its own reference clock generation unit 3 is in a slow or early state. The unique word signal reading timing is shift-corrected earlier or later so as to match the count number default value). Such shift correction itself only shifts or updates the operation timing of the TDMA unit 2 itself earlier or later. The TDMA unit 2 further controls the operation timing after correction of the TDMA unit 2 itself by control means described later. 5, the corrected reference signal Sig 2 synchronized with the corrected reading timing is output to the control means 5.

  The own reference clock generation unit 3 called TCXO is an oscillation block including an oscillator that generates a spontaneous clock signal Sig 3 that is a reference of operation timing in the synchronization signal output device 10. The self-equipment reference clock generator 3 does not employ a high-performance and high-accuracy one for the purpose of inexpensively configuring the synchronization signal output device 10 in the first place. For this reason, as described above, the clock signal supplied from the own reference clock generator 3 has variations in the generation cycle.

  The connected device reference clock generation unit 4 includes a D / A converter 4a, a VCTCXO 4b, a first-stage frequency divider circuit 4c, and a second-stage frequency divider circuit 4d. With this control input, it is possible to variably generate the connected device clock signal Sig4 which becomes the reference of the synchronization signal Sig1.

  The D / A converter 4a changes the conversion rate of the D / A conversion by the voltage control input Sig5 from the control means 5, and outputs an analog voltage waveform whose waveform changes as a result to the VCTCXO 4b. The VCTCXO 4b is an oscillation block including an oscillator that changes an oscillation cycle according to an analog voltage waveform input from the D / A converter 4a. The oscillation cycle of this VCTCXO 4b is not interlocked with that of its own reference clock generator 3, and is determined solely by the VCTCXO 4b. Note that the VCTCXO 4b, like the own reference clock generator 3, does not employ a high-performance and high-accuracy one for the purpose of configuring the synchronization signal output device 10 at low cost. For this reason, the clock signal Sig4 for connected devices has a variation in the generation cycle, similarly to the clock signal (spontaneous clock signal Sig3) given from the own device reference clock generation unit 3. The first-stage frequency dividing circuit 4c divides the oscillation cycle of the VCTCXO 4b, and the frequency-divided output from the first-stage frequency dividing circuit 4c is further divided by the second-stage frequency dividing circuit 4d. .

  The control means 5 includes a CPU and controls the overall operation within the synchronization signal output device 10. Similar to the TDMA unit 2, the control unit 5 receives the spontaneous clock signal Sig 3 from the own device reference clock generation unit 3 and determines the operation speed.

  The control means 5 receives the corrected reference signal Sig2 from the TDMA unit 2 and takes in the frequency-divided output of the first-stage frequency dividing circuit 4c and separates the corrected reference signal Sig2 and the first-stage frequency dividing circuit 4c. Measure whether there is a deviation in the timing of both the circumferential output. If it is determined that there is a deviation, the control means 5 inputs a new voltage control input Sig5 to the D / A converter 4a in order to eliminate the deviation. That is, the control means 5 uses the corrected reference signal Sig2 as a reference, and if the timing of the connected device clock signal Sig4 indirectly measured from the frequency-divided output of the first-stage frequency dividing circuit 4c is late or early, the synchronization signal Sig1 Therefore, the connection device reference clock generation unit 4 is controlled to generate the connection device clock signal Sig4 in synchronization with the corrected reference signal Sig2.

  A schematic operation of the synchronization control in the control means 5 of the synchronization signal output apparatus 10 configured as described above will be described below with reference to FIG.

  The control means 5 always counts the pulse output, which is the frequency-divided output by the first-stage frequency divider 4c, and calculates the product of this pulse count value and a predetermined fixed time interval (predetermined time between pulses). (Step S1).

  Next, the control means 5 inquires of the TDMA unit 2 whether or not the TDMA unit 2 has detected a unique word signal corresponding to the unique word UW (step S2), and repeats steps S1 and S2 until it can be detected. If the unique word signal can be detected in step S2, the bit count result of the unique word signal in the bit counter of the TDMA unit 2 is referred to and it is detected whether or not the number of bits has been counted (step S3). ).

  If you cannot count with the specified number of bits and the bit count result of the unique word signal is more or less than the specified number of bits, you can count from the start bit to the end bit of the unique word signal without excess or deficiency. Therefore, the start timing and end timing of the bit count are different from the prediction on the frame format of the control channel CCH in FIG.

  Therefore, the control means 5 next compares the calculated time value, which is the calculation result in step S1, with the specified period 100 msec of the control channel CCH (step S4), and the calculated time value is larger than the specified period 100 msec. For example, it can be seen that the pulse count value in step S1 is larger than the specified value, in other words, the oscillation cycle of VCTCXO4b is too early, so that a new voltage control input Sig5 is set so as to delay the oscillation cycle of VCTCXO4b. Is input to the D / A converter 4a (step S5).

  On the other hand, if the calculated time value is smaller than the prescribed period of 100 msec in step S4, it can be seen that the pulse count value in step S1 is less than the prescribed value, in other words, the oscillation cycle of VCTCXO4b is too late. Therefore, a new voltage control input Sig5 is input to the D / A converter 4a so as to accelerate the oscillation cycle of the VCTCXO 4b (step S6).

  After step S5 or step S6, the control means 5 causes the TDMA unit 2 to reset and rewrite the bit counter value to the specified value (240 bit number) (step S7), and after clearing the pulse count value in step S1 (Step S8), the operation is returned immediately before step S1.

  If the bit count of the unique word signal matches the specified bit number in step S3, the count from the start bit to the end bit of the unique word signal can be performed without excess or deficiency. Since it is completed and there is no problem, the next operation is moved to step S8.

  As described above, the synchronization signal output apparatus 10 according to the present embodiment monitors the unique word signal of the control signal (control channel CCH) issued by the PHS base station 30, and sends it to the connection device 20 so as to synchronize with the unique word signal. The synchronization signal Sig1 is output.

In the first reference embodiment described above, the control unit 5 obtains the timing of generating the connected device clock signal Sig4 by taking in the divided output of the first-stage divider circuit 4c. The reference form is not limited to this, and instead of capturing the frequency-divided output of the first-stage frequency dividing circuit 4c, the frequency-divided output of the second-stage frequency dividing circuit 4d, that is, the synchronization signal Sig1 may be captured by the control means 5. Good. In general, however, if the output of an oscillation source such as the VCTCXO 4b is taken into the control means 5 such as a CPU without being divided, the operating frequency is too fast for the control means 5 and may adversely affect the operation. If possible, it is desirable that the frequency dividing output of the first-stage frequency dividing circuit 4c or the frequency-divided output of the second-stage frequency dividing circuit 4d, that is, the synchronization signal Sig1 is taken into the control means 5 as in this embodiment.

(Second reference form)
Figure 5 is a block diagram showing the internal configuration of the synchronization signal output apparatus of the present reference embodiment, FIG. 6 is a flowchart showing the operation of the synchronizing signal output device.

The synchronization signal output device of this reference form is different from that of the above-mentioned first reference form in that the own reference clock generator 3 is also used as the VCTCXO 4b, and the own reference clock generator 3 is not required. This is the point. However, since the oscillator employed as the VCTCXO 4b also defines the operating frequency of the control means 5 and the operating frequency of the TDMA unit 2, the oscillation frequency band of the VCTCXO 4b as the control means 5 and the TDMA unit 2 is used. Note that it is necessary to have something that is fully operational. Hereinafter, only points to be particularly noted will be described, and those not particularly described are the same as those in the first reference embodiment described above.

  The TDMA unit 2 includes an internal register 2a instead of the bit counter in the first embodiment that counts a total of 240 bits representing the control channel CCH. The TDMA unit 2 includes the internal reference clock generator 3 in the first embodiment. It operates according to the clock signal supplied from the VCTCXO 4b instead of the supplied clock signal. The TDMA unit 2 writes the bit count value of the unique word signal obtained via the RF unit 1b into the internal register 2a.

Further, the synchronization signal output device 10 includes a connected device reference clock generation unit 6 that is used for own device operation. The own device operation / connection device reference clock generation unit 6 is capable of variably generating the own device operation / connection device clock signal Sig6 which is a reference of the operation timing in the synchronization signal output device 10 and also a reference of the synchronization signal Sig1. It is. However, in this reference embodiment, the own device operation / connection device reference clock generation unit 6 is the same as the connection device reference clock generation unit 4 in the first reference embodiment, and the own device operation / connection device clock signal Sig6 is the first. This is the same as the connection device clock signal Sig4 in one reference form.

Furthermore, the control unit 5, the same corrected reference signal Sig2 with the first reference embodiment with reference, as early or timing of the clock signal Sig6 own Mobile work shared connection device is slow, synchronized to the corrected reference signal Sig2 Thus, the timing for generating the clock signal Sig6 for the own device operation / connection device is controlled by the own device operation / connection device reference clock generation unit 6.

  A schematic operation of the synchronization control in the control means 5 of the synchronization signal output apparatus 10 configured as described above will be described below with reference to FIG.

  The control means 5 inquires of the TDMA unit 2 whether or not the TDMA unit 2 has detected the unique word signal corresponding to the unique word UW (step S11), and repeats step S11 until it can be detected. Is detected, the data arrangement of the unique word signal in the internal register 2a of the TDMA unit 2 is referred to, and whether or not the data can be stored at the prescribed arrangement position following the preamble PR described in FIG. Is detected (step S12).

  If the data could not be stored at the specified arrangement position, it means that the count from the start bit to the end bit of the unique word signal could not be performed without excess or deficiency, so the frame format of the control channel CCH in FIG. In the above, the start timing and end timing of the bit count are different from the prediction.

  Therefore, the control means 5 next reads the internal register 2a of the TDMA unit 2 (step S13) and compares it with the specified value (step S14). If the recorded value of the internal register 2a is larger than the specified value, the internal register 2a is read. It can be seen that the pulse count value represented by the recorded value of 2a is larger than the specified value. In other words, the oscillation cycle of the VCTCXO4b is too early, so that a new voltage control input is made to slow down the oscillation cycle of the VCTCXO4b. Sig5 is input to the D / A converter 4a (step S15).

  On the other hand, if the recorded value of the internal register 2a is smaller than the specified value in step S14, it can be understood that the pulse count value represented by the recorded value of the internal register 2a is less than the specified value, in other words, the oscillation cycle of the VCTCXO 4b. Therefore, a new voltage control input Sig5 is input to the D / A converter 4a so as to make the oscillation cycle of the VCTCXO 4b faster (step S16).

  The control means 5 returns the operation immediately after step S1 after step S15 or step S16. In step S12, if the data can be stored at the specified arrangement position, the unique bit signal can be counted from the start bit to the end bit without excess or deficiency, and there is no problem in reading timing. Therefore, the next operation is moved immediately before step S11.

As described above, the synchronization signal output device 10 according to the present reference embodiment uses the unique word of the control signal (control channel CCH) generated by the PHS base station 30 without using the own reference clock generator 3 in the first reference embodiment. The signal is monitored, and a synchronization signal Sig1 is output to the connection device 20 so as to synchronize with the unique word signal.

( One embodiment according to the present invention )
FIG. 7 is an explanatory diagram of a synchronization signal output device according to an embodiment of the present invention , and FIG. 8 is a flowchart showing the operation of the synchronization signal output device.

In the first or second reference form described above, there is only one PHS base station 30 that is the source of synchronization, and this PHS base station 30 itself falls into a functional failure and causes a communication trouble, or during a maintenance window. If communication becomes impossible after entering, the synchronization signal output device 10 cannot output the synchronization signal Sig1 to the connection device 20 until the communication function is restored, and the operation of the connection device 20 cannot be controlled. It is possible. In order to avoid this situation, the synchronization signal output device 10 of the embodiment according to the present invention is different from that of the second reference embodiment described above in that a PHS suitable for being a reference station among a plurality of PHS base stations. The point is that a synchronization signal is output to the connected device while only one base station can be selected (during the same period). Hereinafter, only points to be particularly noted will be described, and those not particularly described are the same as those of the second reference embodiment described above.

  As illustrated in FIG. 7, the TDMA unit 2 monitors the unique word signals of the control signals emitted from the plurality of PHS base stations 30-1, 30-2 and 30-3, and selects the base station from the control means 5. The reference station 40 (for example, 30-1) which is the only PHS base station that is currently received is selected according to the command, the generation timing of the unique word signal included in the control signal of the TDMA signal from the reference station 40, and the current signal reading The current signal reading timing is self-corrected so as to eliminate the difference from the timing, and a corrected reference signal Sig2 synchronized with the corrected reading timing is output.

  When the control means 5 receives the plurality of differences before correction for the plurality of PHS base stations from the TDMA unit 2, the control means 5 determines the PHS base station 30-1 having the smallest difference among the plurality of differences as a reference station. The base station selection command is output to the TDMA unit 2 so as to select 40, and if the timing of the clock signal Sig6 for the self-operation / connection device is late or early with reference to the corrected reference signal Sig2, the corrected reference signal Sig2 The own device operation / connection device reference clock generation unit 6 is controlled to generate the own device operation / connection device clock signal Sig6.

  In the synchronization signal output device 10, the difference in signal reading timing of the unique word signals received from the plurality of PHS base stations occurs between the synchronization signal output device 10 and each PHS base station. This is because there is of course a difference in communication distance, and a plurality of PHS base stations do not have a difference in transmission timing with each other but perform transmission at the same timing. In addition, as shown in FIG. 2B, in order to identify one base station from among a plurality of PHS base stations, a source identification code used as a base station identification code in the detailed configuration of the control channel CCH. , It can be determined whether or not it is a desired PHS base station.

  A schematic operation of the synchronization control in the control means 5 of the synchronization signal output apparatus 10 configured as described above will be described below with reference to FIG. FIG. 8 is a schematic operation of the synchronous control in the control means 5. The main process of the control means 5 is separate, and the process corresponding to FIG. 8 is preferably called and activated as an interrupt processing routine (for example, every 625 μsec). .

  The control means 5 inquires of the TDMA unit 2 whether or not the TDMA unit 2 has detected the unique word signal corresponding to the unique word UW (step S21), and if it has been detected, the PHS selected as the reference station 40 It is identified whether or not it is a unique word signal received from a base station (for example, reference numeral 30-1) (step S22). If it is from a PHS base station 30-1, the received unique word signal and unique word signal The signal is compared with the prescribed bit value of the signal, and the difference is calculated and stored (step S23). If the control means 5 is not from the PHS base station 30-1 in step S22, but is from the PHS base station 30-2 or 30-3 that is the next candidate (step S24). Again, the received unique word signal is compared with the specified bit value of the unique word signal, and the difference is calculated and stored (steps S25 and S26). In FIG. 8, steps S25 and S26 are shown to be serially processed. However, steps S25 and S26 may be independent parallel processing, and step S25 is not necessarily required to reach step S26. In step S24, if it is not from the next-point candidate PHS base station 30-2 or 30-3, the control unit 5 moves the process immediately after step S23.

  The control means 5 shifts the process immediately after step S25 or S26 to immediately after step S23, and when the reference station 40 cannot be received from the reference station 40 after a certain period of time has elapsed since the reference station 40 was identified in step S22 (step S22). S27), it is determined that communication with the PHS base station 30-1 employed as the reference station 40 has been interrupted by some accident, and the PHS base station 30-2 or 30-3 that is the next candidate is Based on the results of steps S25 and S26, the one having the unique word signal detection timing closest to the PHS base station 30-1 (for example, the PHS base station 30-2) is selected (step S28).

  Immediately after step S27, immediately after step S28, or when the unique word signal has not been detected in step S21, the control means 5 terminates the above-described interrupt processing routine of FIG. Repeat. The control means 5 that has returned from the interrupt processing routine of FIG. 8 to the main processing performs main processing including communication and data communication including the processing of FIG. 6, in which case the selection is made in FIG. It operates so as to synchronize with the reference station 40 which is any one of 1, 30-2 and 30-3.

  As described above, the synchronization signal output device 10 outputs the synchronization signal Sig1 to the connection device 20 while allowing only one reference station 40 to be selected from the plurality of PHS base stations 30-1, 30-2, and 30-3. is there. In this way, it is possible to select the PHS base station that will be most easily synchronized among the PHS base stations 30-1, 30-2, and 30-3 that can be supplemented with the current situation, and for communication with the current reference station 40. Even when communication is impossible due to a trouble, the next point candidate of the reference station 40 can be selected through step S28, so communication is not interrupted compared to the case where only one PHS base station is communicated with the other party, Therefore, it is possible to avoid a state in which the synchronization signal Sig1 cannot be output to the connection device 20.

  FIG. 8 shows an example in which the PHS base station 30-1 is selected as the initial reference station 40. However, if the initial reference station 40 selects the one that can receive signals with the strongest received radio wave intensity. Of course, a PHS base station that can receive the second and third strongest received radio waves may be used as a target for determining whether or not it is a corresponding station in step S24 as a reference station candidate. Even if it does in this way, after all, after passing through step S25, S26, S28, the new reference station 40 will be determined with the shift | offset | difference of a reception timing instead of the intensity | strength of a received radio wave.

In addition, the flowcharts 4, 6, and 8 in the first and second reference embodiments described above and the embodiment according to the present invention are schematic operations of the synchronization control in the control unit 5. There is a separate main process, and the processes corresponding to the flowcharts of FIGS. 4, 6, and 8 are preferably called and activated as interrupt processing routines (for example, every 625 μsec). That is, immediately after step S8 in FIG. 4, the operation is not returned immediately before step S1 and the interrupt process is terminated. If the process does not proceed to step S3 in step S2, the operation is not returned immediately before step S1 but immediately after step S8. Similarly, immediately after step S15 in FIG. 6 or immediately after step S16, the interrupt processing is terminated without returning to the operation immediately before step S11, and the process does not proceed to step S12 in step S11. The operation is not returned immediately before step S11, but immediately after step S15 or immediately after step S16, and the interrupt process is terminated. If the process does not proceed to step S13 in step S12, the operation is not returned immediately before step S11 and immediately after step S15. Or, immediately after step S16, interrupt processing is terminated. Thus, immediately after step S27 in FIG. 8 or immediately after step S28, the interrupt process is terminated without returning the operation immediately before step S28. If the process does not proceed to step S22 in step S21, the process immediately after step S27 or Immediately after step S28, the interrupt process is terminated.

By doing so, the PHS existing general-purpose PHS receiver configuration (transmission / reception processing) only needs to be handled a little, so that the first and second embodiments described above and the embodiment according to the present invention can be used. It is easy to develop the described synchronization signal output device 10 at a low cost.

It is explanatory drawing of the synchronous signal output device of a 1st reference form . It is explanatory drawing of the unique word signal contained in the control signal of the TDMA signal detected with a synchronous signal output device same as the above. It is a block diagram showing the internal structure of a synchronous signal output device same as the above. It is a flowchart showing operation | movement of a synchronous signal output device same as the above. It is a block diagram showing the internal structure of the synchronous signal output device of the 2nd reference form . It is a flowchart showing operation | movement of a synchronous signal output device same as the above. It is explanatory drawing of the synchronizing signal output device of one Embodiment of this invention . It is a flowchart showing operation | movement of a synchronous signal output device same as the above. It is explanatory drawing of the conventional synchronous signal output device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a Antenna 1b RF part 2 TDMA part 3 Own apparatus reference clock generation part 4 Connected apparatus reference clock generation part 5 Control means 6 Connected apparatus reference clock generation part used for own apparatus operation | movement 10 Synchronous signal output device 20 Connected apparatus 30, 30-1, 30-2, 30-3 PHS base station 40 Reference station Sig1 Synchronous signal Sig2 Corrected reference signal Sig3 Spontaneous clock signal Sig4 Clock signal for connected equipment Sig6 Clock signal for connected equipment used for own equipment

Claims (1)

Based on the timing signal received from the outside, a synchronization signal output device that generates a synchronization signal that instructs the operation timing of the connected device and outputs the generated synchronization signal to the connected device,
An antenna and an RF section;
The generation timing of the unique word signal included in the control signal of the TDMA signal emitted from the plurality of PHS base stations detected from the output of the RF unit is monitored for each PHS base station, and the current status is the only one according to the base station selection command from the control means The current signal reading timing is selected so as to eliminate the difference between the generation timing of the unique word signal included in the control signal of the TDMA signal from the reference station and the current signal reading timing. A TDMA unit that self-corrects and outputs a corrected reference signal synchronized with the corrected read timing;
A self-machine operation / connection device reference clock generator capable of variably generating a clock signal for the self-machine operation / connection device that is a reference of the operation timing within the own device and also a reference of the synchronization signal;
When receiving a plurality of the differences before correction for a plurality of PHS base stations from the TDMA unit, to the TDMA unit to select the PHS base station that has the smallest difference among the plurality of differences as the reference station. Outputs the base station selection command, and if the timing of the clock signal for the own operation / connection device is late or early with respect to the corrected reference signal, it is for the own operation / connection device so that it is synchronized with the corrected reference signal. Control means for causing the own device operation / connection device reference clock generation unit to control the timing for generating the clock signal,
The unique word signal of the control signal issued by the PHS base station is monitored, and only one reference station can be selected from the plurality of PHS base stations during the same period. A synchronization signal output device that outputs a synchronization signal to a connected device so as to synchronize with the obtained unique word signal.

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