JP4505930B2 - Local lattice strain measuring method and manufacturing method of micro device using the same - Google Patents

Local lattice strain measuring method and manufacturing method of micro device using the same Download PDF

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JP4505930B2
JP4505930B2 JP2000059414A JP2000059414A JP4505930B2 JP 4505930 B2 JP4505930 B2 JP 4505930B2 JP 2000059414 A JP2000059414 A JP 2000059414A JP 2000059414 A JP2000059414 A JP 2000059414A JP 4505930 B2 JP4505930 B2 JP 4505930B2
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lattice strain
kikuchi
electron beam
lattice
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JP2001249087A (en
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康之 後藤
吉男 菊地
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Fujitsu Ltd
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Fujitsu Ltd
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Description

【0001】
【発明の属する技術分野】
本発明は、収束電子線を用いて結晶基材の局所領域の格子歪を簡便且つ高精度で測定することを可能にする局所格子歪測定方法とそれを利用した微小な装置の製造方法に関する。
【0002】
【従来の技術】
集積回路装置等の高集積・微細化の進展に伴って素子製造工程途中で結晶基材に局所的に発生する格子歪が素子の特性やその信頼性に与える影響が大きくなることが知られており、特に、近年、半導体デバイスの素子分離にSTI構造が用いられるようになって局所的な格子歪の影響がより一層強くなっている。そのため、結晶基材の局所領域の格子歪を簡便且つ高精度で測定する方法の実用化が望まれている。
【0003】
局所領域の格子歪を測定する方法として、顕微ラマン分光法が一般に知られているが、この方法では1μm を超える空間分解能を得ることが困難なため、サブミクロンオーダの最小寸法を有する半導体デバイスの製造に対して有効な方法とはなり得ない。
【0004】
一方、透過電子顕微鏡は数nmのオーダーにまで電子線を収束することができるため、サブミクロンオーダの局所的な格子歪を評価するための有力な手段として用いることができ、その応用として収束電子線回折法が知られている。この方法では、結晶基材に電子線を収束して照射し、透過ディスクに現れる回折パターン(高次ラウエゾーン)をシミュレーションによって求めたパターンと比較することにより電子線の加速電圧と結晶基材の格子定数を算出するようにしている。
【0005】
【発明が解決しようとする課題】
収束電子線回折法は空間分解能や格子歪の測定精度の点で微細化された半導体デバイスの製造工程管理に適用することが可能である。しかし、従来の収束電子線回折法では、実際に得られたパターンとシミュレーションによって得られたパターンとを一致させる手順が複雑となるため半導体デバイスの製造工程管理に用いることが実用上難しいという問題があった。
【0006】
そこで、本発明では、結晶基材の格子歪を高い空間分解能で測定する簡単な方法を提供するとともに、この方法を利用して微小な素子の製造を行うことによって素子特性及びその信頼性を向上させることを目的とする。
【0007】
【課題を解決するための手段】
上記課題の解決は、電子線を収束して結晶基材の局所領域に照射し、スクリーン上に現れた透過電子線と回折電子線のうち、平行な欠損線と過剰線より成る菊地線の組の該欠損線と該過剰線との間の距離を計測し、その結果に基づいて該局所領域の格子歪を測定することを特徴とする局所格子歪測定方法、
あるいは、3次以上の高次菊地線を用い、該結晶基材を該菊地線に対して垂直な方向を軸に15度以内の角度で傾斜させて該菊地線の組の該欠損線と該過剰線との間の距離を計測することを特徴とする上記局所格子歪測定方法、
あるいは、上記局所格子歪測定方法による測定結果に基づいて選ばれた、格子歪の小さい結晶基材の中に、素子を形成することを特徴とする微小な装置の製造方法によって達成される。
【0008】
図1は本発明の原理説明図である。同図に模式的に示したように、収束電子線1を薄片化した結晶基材2の表面に垂直な方向からわずかに傾斜させて入射すると、互いに平行な欠損線と過剰線から成る線状の菊地線の組5、6がスクリーン4上に現れる。同図に見られるように、菊地線の組5、6の一方は、P点を通る格子面(図示せず)で回折されそのまま結晶基材2を透過した電子線と、P点を通る格子面で回折された後さらにR点を通る格子面3で回折されて結晶基材2を透過した電子線とが干渉することによって生じ、もう一方は、P点を通る格子面で回折されそのまま結晶基材2を透過した電子線と、P点を通る格子面で回折された後さらにQ点を通る格子面3で回折されて結晶基材2を透過した電子線とが干渉することによって生じる。
【0009】
そして、この菊地線の組をなす欠損線と過剰線の間の距離を計測し、その計測結果から格子定数の変化を測定することがきる。菊地線の組の間の距離は高次菊地線を用いるほど広がるため、その測定精度を高くすることができる。発明者の実験によれば、3次以上の高次菊地線を用いることにより1×10-3以上の測定精度が得られることがわかった。
【0010】
図1において、収束電子線1を結晶基材2に垂直に入射した場合には、いわゆる菊地バンドがスクリーン4上に現れる。これは、計測対象の格子面3に対応して現れる菊地線の組5、6の間の距離を計測する上での妨げとなるが、菊地バンドは高次になると強度が弱くなるため、前述のように高次菊地線を用いることによってその影響を避けることができる。
【0011】
一般にスクリーン4上には特定の格子面の計測に用いる菊地線に対して非平行な菊地線が多数現れるが、結晶基材を被測定格子面に応じた特定の方向にわずかに傾斜させ、さらに、3次以上の高次の菊地線を用いることによってこれらの菊地線の影響を避けることができる。傾斜角度を必要以上に大きくすると菊地線の強度が低下し測定が困難となる。発明者等は適切な傾斜角度の範囲が±15度以内であることを実験的に見いだした。
【0012】
さらに発明者等は、上記測定において、スクリーン上に明瞭な回折像を生じさせるためには、電子線を1mrad以上に収束する必要があることを実験により確かめた。
【0013】
また、素子製造工程における特定の工程の前後に上記測定方法を用いて結晶基材の局所的な格子歪の分布を測定し、その特定の工程が結晶基材に与える影響を評価し、その結果選ばれた格子歪の小さな結晶基材の中に素子を形成することによって素子の特性及び信頼性を向上させることが可能となる。
【0014】
【発明の実施の形態】
0.18μm のCMOSデバイス製造では、Siウェーハの素子分離構造としてSTI構造が用いられる。そこで、Siウェーハに対するSTI形成工程に本発明にかかる局所格子歪測定方法を適用し工程途中で格子歪を測定することにより工程管理を行う例について以下に説明する。
【0015】
図2(a)〜(e)は、(100)面を有するSiウェーハにSTI構造を形成する工程を示したものである。まず、同図(a)に示したように、Siウェーハ10の表面を熱酸化して膜厚3nmの熱酸化膜11を堆積し、続いてその上にCVD法を用いて膜厚100nmの窒化膜12を堆積する。さらに、続けて膜厚300nmのハードマスク用酸化膜13をCVD法を用いて堆積し、STI領域形成用のフォトレジストパターン14を形成する。
【0016】
ついで、同図(b )に示したように、レジストパターン14をマスクにして異方性ドライエッチングによりトレンチ15を形成する。そして、この上に同図( c) に示したように、CVD法により酸化膜16を堆積してトレンチ15の内部を埋め込む。
【0017】
ついで、同図(d )に示したように、窒化膜12をストッパーに用いてSiウェーハ10の表面をCMP法により平坦化する。そして、窒素雰囲気中で高温熱処理を行い酸化膜16を稠密化処理する。最後に、同図(e)に示したように、熱酸化膜11と窒化膜12をエッチングにより除去し、これによってSiウェーハ10にSTI構造が形成される。
【0018】
次に、上記STI形成工程の管理に本発明に係る局所格子歪測定方法を適用した結果について述べる。本実施例では、図2(c)で説明した工程を経たSiウェーハ、即ち、トレンチ15内を酸化膜16で埋め込んだ後熱処理を行う前のSiウェーハのうちの1枚を抜き取って第1回目の格子歪測定を行う。
【0019】
さらに、図2(d)で説明した工程を経たSiウェーハ、即ち、上記Siウェーハの表面をCMP法により平坦化し熱処理を行った後のSiウェーハのうちの3枚を抜き取ってそれぞれのSiウェーハに対して以下の3種の異なる条件で熱処理し、これらの熱処理を経たSiウェーハの各々について第2回目の格子歪測定を行う。熱処理条件は、窒素雰囲気中で(1)950℃、30分、(2)1000℃、30分、(3)1050℃、30分の3条件を用いた。そして、第1回目の測定結果と、第2回目の3種類の測定結果とを比較して熱処理前後のSiウェーハの格子歪の変化を調べ最適な熱処理条件を設定した。
【0020】
図3は上記Siウェーハに対する局所格子歪測定方法を説明する模式図及び回折像を示したものである。測定に用いた試料は、Siウェーハを機械研磨とイオンミリングを用いた通常の透過電子顕微鏡観察用試料と同様な方法で作成した。同図において、20は表面が(100)面のSiウェーハを表面に垂直な方向に薄片化して作成した測定用の試料を示したものであり、試料20の断面の面方位は〔1、−1、0〕である。試料表面21にはSTI23が形成されており、試料の厚みは0.3μm である。
【0021】
図3に示したように、収束電子線22を試料20の断面に対しわずかに傾けて照射すると、試料20を隔てて収束電子線22と反対側に配置した蛍光板24上に欠損線と過剰線からなる菊地線の組が現れる。ここでは、試料表面21に平行な(001)格子面の面間隔の測定には0012欠損線と0012過剰線を用い、また、試料表面21に垂直な(110)格子面の面間隔の測定には880欠損線と880過剰線を用いた。図3中には、10mradに収束した電子線22を照射したときに観測された回折像が示されている。発明者等は、1mrad 以上に収束した電子線を用いることによって明瞭な回折像が得られることを確かめた。
【0022】
図4(a)〜(c)は試料表面21に平行な(001)格子面の面間隔を測定する手順を示したものである。
【0023】
まず、試料20の断面に垂直に収束電子線22を入射させる条件を設定するため、蛍光板24上で菊地バンドが対称に現れるように収束電子線22の方位を調整する。図4(a)はスクリーン上で004菊地バンドが対称な位置に現れた状態を示したものであり、中心には透過電子線によるディスクが現れている。この状態から試料表面21に平行な方位で試料を傾斜させていくと、図4(b)に見られるように、3次菊地線の組、即ち、0012欠損線(点線で示されている)と0012過剰線(実線で示されている)が励起される。同図は0012欠損線が透過ディスクのほぼ中心を横切るまで試料20を傾斜させたときの状態を示したものであり、このときの傾斜角度は約3.5度であった。
【0024】
ついで、透過ディスク内に見える0012欠損線の配置を変えないようにして菊地線に垂直な軸を中心に直角方向に試料を傾斜させることによって他の菊地線が0012菊地線を妨害しない方位を設定した。図4(c)に見られるように、約10度傾斜させることで良好な回折像を得ることができた。
【0025】
次に、図5(a)〜(c)は試料表面21に垂直な(110)格子面の面間隔を測定する手順を示したものである。
【0026】
最初に、収束電子線を試料20の断面に垂直に入射させる方位を設定する。これは図4(a)と同様に蛍光板24上で菊地バンドが対称に現れるように収束電子線の入射方向を調整することによって設定できる。このときの状態を図5(a)に示している。ついで、試料表面21に平行な方位を保ったまま収束電子線22の入射中心から試料20をわずかに傾斜させ、同図(b)に見られるように、880欠損線(点線で現れている)と880過剰線(実線で示されている)を励起させた。これは、同図(a)に示した状態から菊地線を見ながら試料表面に平行な方位で傾斜させていき、880欠損線が透過ディスクのほぼ中心を横切る方位に現れるように設定することによって得られる。このときの傾斜角は約3.2度であった。
【0027】
ついで、透過ディスク内に見える880欠損線の配置を変えないようにして菊地線に垂直な軸を中心に試料20を傾斜させ、これによって他の菊地線が880菊地線を妨害しない方位を設定した。同図では約7度傾斜させることで良好な回折像を得ることができた。
【0028】
スクリーン上に現れた菊地線の組の間の距離計測については、スクリーンとして上述の蛍光板を用い、この蛍光板上に現れた菊地線を極微粒子の電子顕微鏡用のネガフィルムに焼き付け、得られた画像から菊地線間の距離を求める方法を用いることができる。発明者の実験によれば、大きさが5.9×8.2cmで分解能10μm 以上のネガフィルムを用いることにより1×10-3程度の計測精度を容易に得ることができた。
【0029】
さらに計測精度を向上させるためには、上記ネガフィルムで得られた画像に対し、別のネガフィルムに所定倍率で焼き付けを行った後スキャナーで読み込む方法、ネガフィルムで得られた画像をスキャナーで取り込む際にレンズ付きの拡大スキャナーを用いる方法、さらに、ネガフィルムで得られた画像をCCDカメラで取り込む方法等を用いることができる。これらの方法により1×10-4以上の計測精度を得ることができる。
【0030】
また、ネガフィルムに代えてイメージングプレートを用いて計測することもできる。たとえば、約25μの解像度を有するイメージングプレート上で菊地線の組の間を5cmの距離にして読み取ることにより1×10-3以上の計測精度を得ることができた。
【0031】
さらに、ネガフィルムに代えて解像度が約25μm のCCDカメラを用いても同様な計測精度が得られる。
【0032】
なお、上記実施例では、(100)面を有するSiウェーハに対して0012菊地線と880菊地線を用いることによりSiウェーハの表面に対してそれぞれ平行な格子面と垂直な格子面の間隔を求める方法について述べたが、(111)面を有するSiウェーハに対しては、12 -6 -6菊地線と0 -88菊地線を励起させることによりSiウェーハの表面に平行な格子面と垂直な格子面の間隔を求めることができる。
【0033】
図6(a)、(b)はSTI構造を有するSiウェーハに対して上述した測定によって得た格子歪の分布を示したものであり、矢印の交点が測定を行った局所領域の中心、矢印の長さが格子歪の大きさを表している。同図(a)は前述した熱処理前の第1回目の測定結果である。格子歪はトレンチのエッジ近傍で最大となり、その大きさは7×10-4となることがわかった。
【0034】
同図(b)は先に述べた熱処理条件(2)を用いて熱処理した後の第2回目の測定結果を示しており、トレンチのエッジ近傍における格子歪の最大値は7×10-4から2×10-4にまで低下することがわかった。先に述べた熱処理条件(1)、(3)を用いた場合の格子歪について同様な測定を行った結果、それぞれ最大で5×10-4、4×10-4となることがわかった。これは、熱処理条件(1)では熱回復が不十分で格子歪の緩和の度合いが弱く、また、熱処理条件(3)では、逆に過剰な熱処理によりSiウェーハ表面の酸化が促進されて格子歪が大きくなったことを示唆しており、格子歪を緩和する上で熱処理条件(2)が最適であることを示している。このことは以下に述べる実験結果からも確認することができる。
【0035】
図7は、上記STI形成工程を経たSiウェーハを用いて作成したMOSデバイスにおけるゲート酸化膜のリーク電流の熱処理条件依存性を示す実験結果である。面積0.1mm2 のゲート酸化膜を有するMOSデバイスに対して、0.05A/cm2 の電流を5秒間強制的に流して電気的なストレスを与えた後にゲート酸化膜へ印加される電場とリーク電流との関係を測定したものである。リーク電流の流れ始める電界が大きくなるほどリーク電流耐性が高いことを考慮すると、同図は、熱処理条件(2)を用いた場合に最もリーク電流に対する耐性が大きくなることを示しており、これは先に述べた格子歪の測定結果とも一致している。このことから、格子歪測定結果に基づいてリーク電流耐性を評価することが可能となる。
【0036】
以上のことから、製造工程途中で格子歪を測定することにより工程処理条件を最適化することができ、また、所定値以上の格子歪を有するSiウェーハを工程途中で排除することによりデバイス特性の向上及びデバイス信頼性の向上を図ることが可能となった。
【0037】
上記実施例は、本発明を半導体デバイスに適用した場合の実施態様を説明したものであるが、他のデバイスに適用しても同様の作用によって同様の効果を得ることができ、たとえば、LCD(液晶)表示装置、PDP(プラズマディスプレイ)装置、磁気ディスクヘッド、プリンタヘッド等、結晶基材の中に微小な素子を形成する必要のあるデバイスに適用可能である。
【0038】
【発明の効果】
以上のように本発明では、スクリーン上に現れた菊地線の組の間の距離を計測することにより、nm単位の高い空間分解能で且つ1×10-4程度の精度で格子歪を簡単に測定することが可能となり、また、この方法をサブミクロンオーダのLSI等の微小な装置の製造工程の管理に適用してデバイス特性及び信頼性を向上させることが可能となる。
【図面の簡単な説明】
【図1】 本発明の原理説明図
【図2】 STI形成工程を示す断面図
【図3】 本発明の実施例を説明する模式図及び観測された回折像
【図4】 格子歪測定手順を示す図(その1)
【図5】 格子歪測定手順を示す図(その2)
【図6】 格子歪の分布を示す断面図
【図7】 リーク電流の熱処理条件依存性を示す図
【符号の説明】
1、22 収束電子線 13 ハードマスク用酸化膜
2、20 試料 14 レジストパターン
3 格子面 15 トレンチ
4 スクリーン 16 酸化膜
5、6 菊地線 21 試料表面
10 Siウェーハ 23 STI
11 熱酸化膜 24 蛍光板
12 窒化膜
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a local lattice strain measurement method that makes it possible to measure a lattice strain in a local region of a crystal substrate simply and with high accuracy using a focused electron beam, and a method for manufacturing a micro device using the same.
[0002]
[Prior art]
With the progress of high integration and miniaturization of integrated circuit devices and the like, it is known that the lattice strain locally generated in the crystal substrate during the element manufacturing process has a greater effect on element characteristics and reliability. In particular, in recent years, the STI structure has been used for element isolation of semiconductor devices, and the influence of local lattice distortion has become even stronger. Therefore, it is desired to put to practical use a method for measuring the lattice strain in the local region of the crystal substrate simply and with high accuracy.
[0003]
Microscopic Raman spectroscopy is generally known as a method for measuring lattice strain in a local region. However, since it is difficult to obtain a spatial resolution exceeding 1 μm with this method, a semiconductor device having a minimum dimension on the order of submicron is used. It cannot be an effective method for manufacturing.
[0004]
On the other hand, the transmission electron microscope can converge an electron beam down to the order of several nanometers. Therefore, it can be used as an effective means for evaluating local lattice strains on the order of submicrons. Line diffraction methods are known. In this method, the electron beam is converged and irradiated on the crystal substrate, and the diffraction pattern (higher order Laue zone) appearing on the transmission disk is compared with the pattern obtained by simulation to determine the electron beam acceleration voltage and the crystal substrate lattice. A constant is calculated.
[0005]
[Problems to be solved by the invention]
The convergent electron beam diffraction method can be applied to manufacturing process management of a miniaturized semiconductor device in terms of spatial resolution and measurement accuracy of lattice distortion. However, in the conventional focused electron diffraction method, the procedure for matching the actually obtained pattern with the pattern obtained by the simulation is complicated, so that there is a problem that it is practically difficult to use it for manufacturing process management of semiconductor devices. there were.
[0006]
Therefore, the present invention provides a simple method for measuring the lattice strain of a crystal substrate with high spatial resolution, and improves device characteristics and reliability by manufacturing minute devices using this method. The purpose is to let you.
[0007]
[Means for Solving the Problems]
The solution to the above problem is to converge the electron beam to irradiate a local region of the crystal substrate, and among the transmitted electron beam and diffracted electron beam that appear on the screen, a set of Kikuchi lines consisting of parallel defect lines and excess lines. Measuring the distance between the deficient line and the excess line, and measuring the lattice strain of the local region based on the result,
Alternatively, a higher-order higher-order Kikuchi line is used, and the crystal substrate is inclined at an angle of 15 degrees or less about a direction perpendicular to the Kikuchi line, and the missing line of the Kikuchi line set and the Measuring the distance between the excess lines and measuring the local lattice strain,
Alternatively, it is achieved by a method for manufacturing a micro device characterized in that an element is formed in a crystal base material having a small lattice strain selected based on a measurement result obtained by the local lattice strain measurement method.
[0008]
FIG. 1 is a diagram illustrating the principle of the present invention. As schematically shown in the figure, when the convergent electron beam 1 is incident on the surface of the thinned crystal substrate 2 with a slight inclination from the direction perpendicular to the surface, a linear shape consisting of a deficient line and an excess line parallel to each other. No. 5 and 6 of Kikuchi Line appear on the screen 4. As seen in the figure, one of the pairs 5 and 6 of the Kikuchi line is an electron beam diffracted by a lattice plane (not shown) passing through the P point and transmitted through the crystal substrate 2 as it is, and a lattice passing through the P point. This occurs when the electron beam that has been diffracted by the surface and further diffracted by the lattice plane 3 passing through the R point and transmitted through the crystal substrate 2 interferes, and the other is diffracted by the lattice plane passing through the P point and is directly crystallized. This is caused by interference between the electron beam transmitted through the substrate 2 and the electron beam diffracted by the lattice plane 3 passing through the point P and then diffracted by the lattice plane 3 passing through the point Q and transmitted through the crystal substrate 2.
[0009]
Then, it is possible to measure the distance between the missing line and the excess line forming the set of the Kikuchi line, and measure the change in the lattice constant from the measurement result. Since the distance between pairs of Kikuchi lines increases as higher-order Kikuchi lines are used, the measurement accuracy can be increased. According to the inventor's experiment, it was found that a measurement accuracy of 1 × 10 −3 or more can be obtained by using a higher-order Kikuchi line of the third order or higher.
[0010]
In FIG. 1, a so-called Kikuchi band appears on the screen 4 when the convergent electron beam 1 is perpendicularly incident on the crystal substrate 2. This hinders the measurement of the distance between the pair 5 and 6 of the Kikuchi line that appears corresponding to the lattice plane 3 to be measured, but the strength of the Kikuchi band becomes weaker as it becomes higher. The influence can be avoided by using a high-order Kikuchi line.
[0011]
In general, many Kikuchi lines that are not parallel to the Kikuchi line used for measurement of a specific lattice plane appear on the screen 4, but the crystal base material is slightly inclined in a specific direction according to the measured lattice plane, By using higher-order Kikuchi lines higher than the third order, the influence of these Kikuchi lines can be avoided. If the inclination angle is increased more than necessary, the strength of the Kikuchi line will decrease, making measurement difficult. The inventors have experimentally found that an appropriate tilt angle range is within ± 15 degrees.
[0012]
Further, the inventors have confirmed through experiments that the electron beam must be converged to 1 mrad or more in order to produce a clear diffraction image on the screen in the above measurement.
[0013]
In addition, the local lattice strain distribution of the crystal base material is measured before and after the specific process in the element manufacturing process, and the influence of the specific process on the crystal base material is evaluated. It is possible to improve the characteristics and reliability of the element by forming the element in a selected crystal base material having a small lattice strain.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
In manufacturing a 0.18 μm CMOS device, an STI structure is used as an element isolation structure of a Si wafer. Therefore, an example in which process management is performed by applying the local lattice strain measurement method according to the present invention to the STI formation process for the Si wafer and measuring the lattice strain during the process will be described below.
[0015]
2A to 2E show a process of forming an STI structure on a Si wafer having a (100) plane. First, as shown in FIG. 1A, the surface of the Si wafer 10 is thermally oxidized to deposit a thermal oxide film 11 having a thickness of 3 nm, and then nitrided to a thickness of 100 nm by using the CVD method. A film 12 is deposited. Further, subsequently, a hard mask oxide film 13 having a thickness of 300 nm is deposited using the CVD method to form a photoresist pattern 14 for forming an STI region.
[0016]
Next, as shown in FIG. 2B, the trench 15 is formed by anisotropic dry etching using the resist pattern 14 as a mask. Then, as shown in FIG. 3C, an oxide film 16 is deposited by CVD to fill the trench 15 inside.
[0017]
Next, as shown in FIG. 4D, the surface of the Si wafer 10 is planarized by CMP using the nitride film 12 as a stopper. Then, the oxide film 16 is densified by high-temperature heat treatment in a nitrogen atmosphere. Finally, as shown in FIG. 4E, the thermal oxide film 11 and the nitride film 12 are removed by etching, whereby an STI structure is formed on the Si wafer 10.
[0018]
Next, the result of applying the local lattice strain measurement method according to the present invention to the management of the STI formation process will be described. In the present embodiment, one of the Si wafers that have undergone the process described in FIG. 2C, that is, the Si wafer that has been filled in the trench 15 with the oxide film 16 and that has not been subjected to the heat treatment, is extracted for the first time. Measure the lattice strain.
[0019]
Further, three Si wafers that have been subjected to the process described in FIG. 2D, that is, the Si wafer after the surface of the Si wafer is planarized by the CMP method and heat-treated are extracted to each Si wafer. On the other hand, heat treatment is performed under the following three different conditions, and the second lattice strain measurement is performed for each of the Si wafers subjected to these heat treatments. The heat treatment conditions were as follows: (1) 950 ° C., 30 minutes, (2) 1000 ° C., 30 minutes, (3) 1050 ° C., 30 minutes in a nitrogen atmosphere. Then, by comparing the first measurement result and the second measurement result, the change in lattice strain of the Si wafer before and after the heat treatment was examined, and the optimum heat treatment conditions were set.
[0020]
FIG. 3 shows a schematic diagram and a diffraction image for explaining a local lattice strain measuring method for the Si wafer. The sample used for the measurement was prepared by the same method as that for a normal transmission electron microscope observation sample using mechanical polishing and ion milling of a Si wafer. In the figure, reference numeral 20 denotes a measurement sample prepared by slicing a (100) surface Si wafer in a direction perpendicular to the surface, and the plane orientation of the cross section of the sample 20 is [1,- 1, 0]. An STI 23 is formed on the sample surface 21, and the thickness of the sample is 0.3 μm.
[0021]
As shown in FIG. 3, when the convergent electron beam 22 is irradiated with being slightly inclined with respect to the cross section of the sample 20, a defect line and an excess line are formed on the fluorescent plate 24 arranged on the opposite side of the convergent electron beam 22 across the sample 20. A pair of Kikuchi Lines will appear. Here, the 0012 deficit line and the 0012 excess line are used for the measurement of the plane spacing of the (001) lattice plane parallel to the sample surface 21, and the plane spacing of the (110) lattice plane perpendicular to the sample surface 21 is used. Used an 880 deficit line and an 880 excess line. FIG. 3 shows a diffraction image observed when the electron beam 22 converged to 10 mrad is irradiated. The inventors have confirmed that a clear diffraction image can be obtained by using an electron beam converged to 1 mrad or more.
[0022]
FIGS. 4A to 4C show a procedure for measuring the plane spacing of the (001) lattice plane parallel to the sample surface 21. FIG.
[0023]
First, in order to set conditions for allowing the convergent electron beam 22 to be incident perpendicularly to the cross section of the sample 20, the orientation of the converged electron beam 22 is adjusted so that the Kikuchi band appears symmetrically on the fluorescent plate 24. FIG. 4A shows a state in which the 004 Kikuchi band appears at a symmetrical position on the screen, and a disk made of a transmission electron beam appears at the center. When the sample is tilted from this state in a direction parallel to the sample surface 21, as shown in FIG. 4B, a set of tertiary Kikuchi lines, that is, a 0012 deficit line (indicated by a dotted line). And the 0012 excess line (shown as a solid line) are excited. This figure shows the state when the sample 20 is tilted until the 0012 defect line crosses almost the center of the transmission disk, and the tilt angle at this time is about 3.5 degrees.
[0024]
Next, set the orientation so that other Kikuchi lines do not interfere with the 0012 Kikuchi line by tilting the sample in the direction perpendicular to the axis perpendicular to the Kikuchi line without changing the arrangement of the 0012 missing line visible in the transmission disk. did. As can be seen in FIG. 4C, a good diffraction image could be obtained by tilting about 10 degrees.
[0025]
Next, FIGS. 5A to 5C show a procedure for measuring the spacing of the (110) lattice plane perpendicular to the sample surface 21. FIG.
[0026]
First, the direction in which the focused electron beam is incident perpendicularly to the cross section of the sample 20 is set. This can be set by adjusting the incident direction of the convergent electron beam so that the Kikuchi band appears symmetrically on the fluorescent plate 24 as in FIG. The state at this time is shown in FIG. Next, the sample 20 is slightly tilted from the center of incidence of the convergent electron beam 22 while maintaining an orientation parallel to the sample surface 21, and as shown in FIG. 5B, an 880 defect line (appears as a dotted line). And the 880 excess line (indicated by the solid line) was excited. This is done by inclining in the direction parallel to the sample surface while looking at the Kikuchi line from the state shown in FIG. 5A, and setting so that the 880 defect line appears in the direction crossing almost the center of the transmission disk. can get. The inclination angle at this time was about 3.2 degrees.
[0027]
Next, the sample 20 was tilted about the axis perpendicular to the Kikuchi line so as not to change the arrangement of the 880 missing lines visible in the transmission disk, and the direction in which the other Kikuchi lines did not interfere with the 880 Kikuchi lines was set. . In the figure, a favorable diffraction image could be obtained by tilting about 7 degrees.
[0028]
For distance measurement between Kikuchi line pairs that appeared on the screen, the above-mentioned fluorescent plate was used as a screen, and the Kikuchi lines that appeared on this fluorescent plate were baked on a negative film for a microscopic electron microscope. Can be used to obtain the distance between the Kikuchi lines. According to the inventor's experiment, it was possible to easily obtain a measurement accuracy of about 1 × 10 −3 by using a negative film having a size of 5.9 × 8.2 cm and a resolution of 10 μm or more.
[0029]
In order to further improve the measurement accuracy, the image obtained with the above negative film is printed on another negative film at a predetermined magnification and then read with a scanner. The image obtained with the negative film is captured with a scanner. In some cases, a method using a magnifying scanner with a lens, a method of capturing an image obtained with a negative film with a CCD camera, or the like can be used. Measurement accuracy of 1 × 10 −4 or more can be obtained by these methods.
[0030]
Moreover, it can replace with a negative film and can also measure using an imaging plate. For example, it was possible to obtain a measurement accuracy of 1 × 10 −3 or more by reading with a distance of 5 cm between the pairs of Kikuchi lines on an imaging plate having a resolution of about 25 μm.
[0031]
Furthermore, the same measurement accuracy can be obtained even if a CCD camera having a resolution of about 25 μm is used instead of the negative film.
[0032]
In the above-described embodiment, by using the 0012 Kikuchi line and the 880 Kikuchi line for the Si wafer having the (100) plane, the intervals between the lattice planes parallel to and perpendicular to the surface of the Si wafer are obtained. Although the method has been described, for a Si wafer having a (111) plane, a lattice perpendicular to the lattice plane parallel to the surface of the Si wafer is obtained by exciting the 12 −6 −6 Kikuchi and 0 −88 Kikuchi lines. The distance between the surfaces can be determined.
[0033]
FIGS. 6A and 6B show the lattice strain distribution obtained by the above-described measurement for the Si wafer having the STI structure. The intersection of the arrows indicates the center of the local region where the measurement is performed, and the arrows Represents the magnitude of the lattice strain. FIG. 4A shows the first measurement result before the heat treatment described above. It was found that the lattice strain was the maximum near the edge of the trench, and the magnitude was 7 × 10 −4 .
[0034]
FIG. 4B shows the second measurement result after the heat treatment using the heat treatment condition (2) described above, and the maximum value of the lattice strain near the edge of the trench is 7 × 10 −4. It was found to drop to 2 × 10 −4 . As a result of performing the same measurement on the lattice strain when the heat treatment conditions (1) and (3) described above were used, it was found that the maximum values were 5 × 10 −4 and 4 × 10 −4 , respectively. This is because the thermal recovery is insufficient under the heat treatment condition (1) and the degree of relaxation of the lattice strain is weak, and under the heat treatment condition (3), the oxidation of the Si wafer surface is promoted by the excessive heat treatment and the lattice strain is reversed. This indicates that the heat treatment condition (2) is optimal for relaxing the lattice strain. This can be confirmed from the experimental results described below.
[0035]
FIG. 7 shows the experimental results showing the dependence of the leakage current of the gate oxide film on the heat treatment conditions in a MOS device fabricated using the Si wafer that has undergone the STI formation step. An electric field applied to a gate oxide film after applying an electrical stress by forcing a current of 0.05 A / cm 2 for 5 seconds to a MOS device having a gate oxide film with an area of 0.1 mm 2 This is a measurement of the relationship with the leakage current. Considering that the leakage current resistance increases as the electric field at which the leakage current begins to flow increases, this figure shows that the resistance against leakage current is maximized when the heat treatment condition (2) is used. This also agrees with the measurement result of the lattice strain described in 1. From this, it becomes possible to evaluate the leakage current resistance based on the lattice strain measurement result.
[0036]
From the above, process processing conditions can be optimized by measuring the lattice strain during the manufacturing process, and device characteristics can be improved by eliminating Si wafers having a lattice strain of a predetermined value or more during the process. It has become possible to improve the device reliability.
[0037]
The above embodiment describes an embodiment in which the present invention is applied to a semiconductor device. However, even if it is applied to other devices, the same effect can be obtained by the same action. For example, the LCD ( The present invention can be applied to a device that needs to form minute elements in a crystal substrate, such as a liquid crystal display device, a PDP (plasma display) device, a magnetic disk head, and a printer head.
[0038]
【The invention's effect】
As described above, in the present invention, by measuring the distance between the pairs of Kikuchi lines that appear on the screen, the lattice strain can be easily measured with a high spatial resolution in nm units and with an accuracy of about 1 × 10 −4. In addition, it is possible to improve the device characteristics and reliability by applying this method to the management of the manufacturing process of a micro device such as an LSI of submicron order.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention. FIG. 2 is a cross-sectional view showing an STI formation process. FIG. 3 is a schematic diagram illustrating an embodiment of the present invention and an observed diffraction image. Figure to show (the 1)
FIG. 5 is a diagram showing a procedure for measuring lattice strain (No. 2)
FIG. 6 is a cross-sectional view showing the distribution of lattice strain. FIG. 7 is a view showing the dependence of leakage current on heat treatment conditions.
1, 22 Convergent electron beam 13 Oxide film for hard mask 2, 20 Sample 14 Resist pattern 3 Lattice surface 15 Trench 4 Screen 16 Oxide film 5, 6 Kikuchi Line 21 Sample surface
10 Si wafer 23 STI
11 Thermal oxide film 24 Fluorescent screen
12 Nitride film

Claims (3)

電子線を1mrad以上に収束して結晶基材の局所領域に照射し、スクリーン上に現れた透過電子線と回折電子線のうち、平行な欠損線と過剰線より成る菊地線の組の該欠損線と該過剰線との間の距離を計測し、その結果に基づいて該局所領域の格子歪を測定することを特徴とする局所格子歪測定方法。And converging the electron beam or the 1mrad irradiating a localized area of the crystal base, of the transmitted electron beam and the diffracted electron beam appearing on a screen, a set of 該欠loss of Kikuchi lines consisting of parallel-deficient lines and excessive line A local lattice strain measuring method, comprising: measuring a distance between a line and the excess line; and measuring a lattice strain of the local region based on the result. 3次以上の高次菊地線を用い、該結晶基材を該菊地線に対して垂直な方向を軸に15度以内の角度で傾斜させて該菊地線の組の該欠損線と該過剰線との間の距離を計測することを特徴とする請求項1記載の局所格子歪測定方法。Using a higher-order Kikuchi line of 3rd order or more, and tilting the crystal base material at an angle of 15 degrees or less about a direction perpendicular to the Kikuchi line, the missing line and the excess line of the Kikuchi line set The local lattice strain measuring method according to claim 1 , wherein a distance between the two is measured. 請求項1又は2記載の局所格子歪測定方法による測定結果に基づいて選ばれた、格子歪の小さい結晶基材の中に、素子を形成することを特徴とする微小な装置の製造方法。  A method for manufacturing a microscopic device, wherein an element is formed in a crystal base material having a small lattice strain selected based on a measurement result obtained by the local lattice strain measuring method according to claim 1.
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JPH07169811A (en) * 1993-12-16 1995-07-04 Sumitomo Sitix Corp Precise measurement of deviation in surface bearing of bonded wafer
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JPH07169811A (en) * 1993-12-16 1995-07-04 Sumitomo Sitix Corp Precise measurement of deviation in surface bearing of bonded wafer
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