JP4483074B2

JP4483074B2 - Digital video signal processor

Info

Publication number: JP4483074B2
Application number: JP2000360617A
Authority: JP
Inventors: 操手嶋; 寛加藤; 毅川上; 睦拡森家; 隆寛渡辺; 和弘飛谷
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 2000-11-28
Filing date: 2000-11-28
Publication date: 2010-06-16
Anticipated expiration: 2020-11-28
Also published as: JP2002165110A

Description

【０００１】
【発明の属する技術分野】
本発明は、デジタル放送受信機及びデジタル映像信号を扱う機器において、走査期間中のデジタル映像信号がある特定の範囲外の値を取らない演算を実施できるデジタル映像信号処理装置に関するものである。
【０００２】
【従来の技術】
近年急速に、デジタル化された映像信号や音声信号を用いたデジタル放送やDVDなどの記録媒体が広まっており、衛星放送やケーブルテレビの為のチューナーボックスやDVDデコーダーの様なAV機器は、デジタル映像信号やデジタル音声信号を処理する為の機能を有するようになってきている。
【０００３】
一般にデジタル映像信号は、８ビットもしくは10ビットのデジタル信号で現わされる。本願では8ビットで現わされるデジタル映像信号を例に取り、８ビット場合のデジタル映像信号とアナログ映像信号の関係を図１２に示す。８ビットのデジタル映像信号では、10進数で０〜２５５までの値を持ち、この内アナログ映像信号の走査期間における０％の黒から１００％の白までの映像信号は１６〜２３５までの値で現わされる場合が多い。
【０００４】
【発明が解決しようとする課題】
しかしながら、デジタル映像信号における０〜１５までの信号、又は２３６〜２５５までの信号は、高精細映像信号(HD信号)と標準精細信号(SD信号)との色マトリックス変換などのデジタル信号処理や放送局側の信号処理によっては、走査期間中にも使われる場合がある。
【０００５】
それら走査期間中の０〜１５及び２３６〜２５５までのデジタル映像信号をアナログ映像信号へ変換した場合、変換後のアナログ映像信号には０％の黒よりも低い(ペデスタルよりも低い)映像信号や１００％の白よりも高い映像信号が含まれる事になる。
【０００６】
チューナーボックスやDVDデコーダーなどに接続されたディスプレイ装置では、図１３に示す様に走査期間中に０％の黒よりも低い(ペデスタルよりも低い)信号が含まれた場合、同期分離回路において同期閾値レベルよりも低い値である事により同期とみなされ、同期分離回路が正常に動作しなくなる場合がある。また、１００％の白よりも高い映像信号が含まれた場合、白つぶれ等の不具合を発生する場合がある。
【０００７】
【課題を解決するための手段】
この課題を解決するために本発明のデジタル映像信号処理装置は、デジタル映像信号の走査期間中に含まれるある特定の範囲外の値を検出し、この信号をある特定の範囲内のデジタル映像信号に補正する。
【０００８】
【発明の実施の形態】
本発明のデジタル映像信号処理装置は、図１に示すデジタル信号の受信部１と、デジタル信号のデコード部２と、デコード部２から出力されたデジタル映像信号の走査期間中に含まれるある特定の範囲外の値を検出する検出部３と、検出部３からの検出信号ｄｓをもとにデジタル映像信号との演算結果がある特定範囲外の値を取らない演算を実施できる演算部４とからなる。
【０００９】
（実施の形態１）
以下、本発明の請求項２の一実施形態について説明する。図２にデジタル映像信号に含まれるある特定値以下の値を検出する検出部３の一実施形態を示す。本検出部では、デジタル映像信号8ビット(最下位ビットをビット０、最上位ビットをビット７とする)の入力に対し、ビット４からビット７までの上位４ビットが０となる図４に示される走査期間中の０〜１５までのデジタル映像信号を検出し、０〜１５までのデジタル映像信号がある場合、検出信号ｄｓを１、０〜１５までのデジタル映像信号がない場合、検出信号ｄｓを０とする。
【００１０】
次に、図３にデジタル映像信号に含まれるある特定値以下の値を切り捨てる演算部４の一実施形態を示す。本演算部では、図２で示された検出部で走査期間中に０〜１５までのデジタル映像信号が検出された場合、検出部３から出力された検出信号ｄｓをもとに、ビット０からビット３までの下位４ビットを全て０にしビット４を１にする事により、０〜１５までの信号を切り捨て、デジタル映像信号を１６とする。本実施例による演算部での入力と出力のデジタル映像信号を図４に示す。
【００１１】
（実施の形態２）
以下、本発明の請求項３の一実施形態について説明する。検出部は図２で示される走査期間中の０〜１５までのデジタル映像信号を検出するものとする。検出部において走査期間中に０〜１５までのデジタル映像信号が検出された場合、演算部ではデジタル映像信号に対し次式で表される演算を行なう。
【００１２】
【数１】

【００１３】
この演算により、０〜２５５の振幅を持つデジタル映像信号は１６〜２５５までの振幅のデジタル映像信号へ変換される。本実施例による演算部での入力デジタル映像信号と出力デジタル映像信号を図５に示す。
【００１４】
（実施の形態３）
以下、本発明の請求項５の一実施形態について説明する。図６にデジタル映像信号に含まれるある特定値以上の値を検出する検出部３の一実施形態を示す。本検出部では、デジタル映像信号8ビットの入力に対し、ビット４からビット７までの上位４ビットが１で、かつビット０からビット３までの下位４ビットの内少なくとも一つが１となる図８に示される走査期間中の２４１〜２５５までのデジタル映像信号を検出し、２４１〜２５５までのデジタル映像信号がある場合、検出信号ｄｓを１、２４１〜２５５までのデジタル映像信号がない場合、検出信号ｄｓを０とする。
【００１５】
次に、図７にデジタル映像信号に含まれるある特定値以上の値を切り捨てる演算部４の一実施形態を示す。本演算部では、図６で示された検出部で走査期間中に２４１〜２５５までのデジタル映像信号が検出された場合、検出部６から出力された検出信号ｄｓをもとに、ビット０からビット３までの下位４ビットを０にする事により、２４１〜２５５までの信号を切り捨て、デジタル映像信号を２４０とする。本実施例による演算部での入力と出力のデジタル映像信号を図８に示す。
【００１６】
（実施の形態４）
以下、本発明の請求項６の一実施形態について説明する。検出部は図６で示される２４１〜２５５までのデジタル映像信号を検出するものとする。検出部において走査期間中に２４１〜２５５までのデジタル映像信号が検出された場合、演算部ではデジタル映像信号に対し次式で表される演算を行なう。
【００１７】
【数２】

【００１８】
この演算により、０〜２５５の振幅を持つデジタル映像信号は０〜２４０までの振幅のデジタル映像信号へ変換される。本実施例による演算部での入力と出力のデジタル映像信号を図９に示す。
【００１９】
（実施の形態５）
以下、本発明の請求項８の一実施形態について説明する。図２及び図３に示される走査期間中の０〜１５までのデジタル映像信号を検出する検出部と走査期間中の０〜１５までのデジタル映像信号を切り捨てる演算部と、図６及び図７に示される走査期間中の２４１〜２５５までのデジタル映像信号を検出する検出部と走査期間中の２４１〜２５５までのデジタル映像信号を切り捨てる演算部とを併せ持つことにより、走査期間中の０〜１５及び２４１〜２５５までのデジタル映像信号を切り捨て、１６〜２４０までのデジタル映像信号とする事ができる。本実施例による演算部での入力と出力のデジタル映像信号を図１０に示す。
【００２０】
（実施の形態６）
以下、本発明の請求項９の一実施形態について説明する。検出部は図２及び図６で示される走査期間中の０〜１５及び２４１〜２５５までのデジタル映像信号を検出するものとする。検出部において走査期間中に０〜１５及び２４１〜２５５までのデジタル映像信号が検出された場合、演算部ではデジタル映像信号に対し次式で表される演算を行なう。
【００２１】
【数３】

【００２２】
この演算により、０〜２５５の振幅を持つデジタル映像信号は１６〜２４０までの振幅のデジタル映像信号へ変換される。本実施例による演算部での入力と出力のデジタル映像信号を図１１に示す。
【００２３】
【発明の効果】
以上のように、本発明により、デジタル映像信号の走査期間中に含まれるある特定範囲外の値を検出し、この信号をある特定の範囲内のデジタル映像信号に補正する事ができる。
【図面の簡単な説明】
【図１】本発明のデジタル映像信号処理回路を示す図
【図２】請求項２における検出部３の一実施形態を示す図
【図３】請求項２における演算部４の一実施形態を示す図
【図４】請求項２における演算部４での入出力デジタル映像信号の例を示す図
【図５】請求項３における演算部４での入出力デジタル映像信号の例を示す図
【図６】請求項５における検出部３の一実施形態を示す図
【図７】請求項５における演算部４の一実施形態を示す図
【図８】請求項５における演算部４での入出力デジタル映像信号の例を示す図
【図９】請求項６における演算部４での入出力デジタル映像信号の例を示す図
【図１０】請求項８における演算部４での入出力デジタル映像信号の例を示す図
【図１１】請求項９における演算部４での入出力デジタル映像信号の例を示す図
【図１２】 8ビットの場合のデジタル映像信号とアナログ映像信号の例を示す図
【図１３】走査期間中におけるペデスタルよりも低い映像信号の例を示す図
【符号の説明】
１受信部
２デコード部
３検出部
４演算部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital video signal processing apparatus capable of performing a calculation that does not take a value outside a certain range in a digital video signal during a scanning period in a digital broadcast receiver and a digital video signal handling device.
[0002]
[Prior art]
In recent years, recording media such as digital broadcasts and DVDs using digitalized video signals and audio signals have become widespread, and AV equipment such as tuner boxes and DVD decoders for satellite broadcasting and cable TV are digital. It has come to have a function for processing video signals and digital audio signals.
[0003]
Generally, a digital video signal is expressed as an 8-bit or 10-bit digital signal. In the present application, a digital video signal represented by 8 bits is taken as an example, and the relationship between the digital video signal and the analog video signal in the case of 8 bits is shown in FIG. The 8-bit digital video signal has a decimal value from 0 to 255, and the video signal from 0% black to 100% white in the scanning period of the analog video signal has a value from 16 to 235. It often appears.
[0004]
[Problems to be solved by the invention]
However, the digital video signal from 0 to 15 or the signal from 236 to 255 is digital signal processing such as color matrix conversion between high definition video signal (HD signal) and standard definition signal (SD signal) or broadcasting. Depending on the signal processing on the station side, it may be used even during the scanning period.
[0005]
When digital video signals of 0 to 15 and 236 to 255 during the scanning period are converted into analog video signals, the converted analog video signals include video signals lower than 0% black (lower than the pedestal) A video signal higher than 100% white is included.
[0006]
In a display device connected to a tuner box, a DVD decoder or the like, when a signal lower than 0% black (lower than the pedestal) is included in the scanning period as shown in FIG. If the value is lower than the level, it is regarded as synchronization, and the synchronization separation circuit may not operate normally. In addition, when a video signal higher than 100% white is included, a problem such as whiteout may occur.
[0007]
[Means for Solving the Problems]
In order to solve this problem, the digital video signal processing apparatus of the present invention detects a value outside a certain range included in the scanning period of the digital video signal, and uses this signal as a digital video signal within a certain range. To correct.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
The digital video signal processing apparatus according to the present invention includes a digital signal receiving unit 1, a digital signal decoding unit 2, and a specific video signal output from the decoding unit 2 shown in FIG. From the detection unit 3 that detects a value outside the range, and the calculation unit 4 that can perform an operation that does not take a value outside a specific range based on a detection result ds from the detection unit 3 and a digital video signal. Become.
[0009]
(Embodiment 1)
An embodiment of claim 2 of the present invention will be described below. FIG. 2 shows an embodiment of the detection unit 3 that detects a value equal to or less than a specific value included in the digital video signal. In this detection unit, for the input of digital video signal 8 bits (the least significant bit is bit 0 and the most significant bit is bit 7), the upper 4 bits from bit 4 to bit 7 are 0, as shown in FIG. When a digital video signal from 0 to 15 in the scanning period is detected and there is a digital video signal from 0 to 15, the detection signal ds is 1, and when there is no digital video signal from 0 to 15, the detection signal ds Is set to 0.
[0010]
Next, FIG. 3 shows an embodiment of the calculation unit 4 that truncates values below a certain value included in the digital video signal. In this calculation unit, when a digital video signal of 0 to 15 is detected during the scanning period by the detection unit shown in FIG. 2, from the bit 0 based on the detection signal ds output from the detection unit 3. By setting all the lower 4 bits up to bit 3 to 0 and setting bit 4 to 1, the signals from 0 to 15 are discarded and the digital video signal is set to 16. FIG. 4 shows input and output digital video signals in the arithmetic unit according to this embodiment.
[0011]
(Embodiment 2)
An embodiment of claim 3 of the present invention will be described below. It is assumed that the detection unit detects digital video signals from 0 to 15 during the scanning period shown in FIG. When the detection unit detects a digital video signal of 0 to 15 during the scanning period, the calculation unit performs a calculation represented by the following expression on the digital video signal.
[0012]
[Expression 1]

[0013]
By this calculation, a digital video signal having an amplitude of 0 to 255 is converted into a digital video signal having an amplitude of 16 to 255. FIG. 5 shows an input digital video signal and an output digital video signal in the arithmetic unit according to this embodiment.
[0014]
(Embodiment 3)
An embodiment of claim 5 of the present invention will be described below. FIG. 6 shows an embodiment of the detection unit 3 that detects a value greater than a specific value included in the digital video signal. In this detection unit, for the input of 8 bits of the digital video signal, the upper 4 bits from bit 4 to bit 7 are 1, and at least one of the lower 4 bits from bit 0 to bit 3 is 1. When digital video signals from 241 to 255 during the scanning period shown in FIG. 6 are detected and there are digital video signals from 241 to 255, the detection signal ds is detected when there are no digital video signals from 1,241 to 255. The signal ds is set to 0.
[0015]
Next, FIG. 7 shows an embodiment of the calculation unit 4 that truncates a value greater than a specific value included in the digital video signal. In the present calculation unit, when digital video signals from 241 to 255 are detected during the scanning period by the detection unit shown in FIG. 6, from the bit 0 based on the detection signal ds output from the detection unit 6. By setting the lower 4 bits up to bit 3 to 0, signals 241 to 255 are discarded, and the digital video signal is set to 240. FIG. 8 shows input and output digital video signals in the arithmetic unit according to this embodiment.
[0016]
(Embodiment 4)
An embodiment of claim 6 of the present invention will be described below. The detection unit detects digital video signals 241 to 255 shown in FIG. When the detection unit detects digital video signals 241 to 255 during the scanning period, the calculation unit performs a calculation represented by the following expression on the digital video signal.
[0017]
[Expression 2]

[0018]
By this calculation, a digital video signal having an amplitude of 0 to 255 is converted into a digital video signal having an amplitude of 0 to 240. FIG. 9 shows input and output digital video signals in the arithmetic unit according to this embodiment.
[0019]
(Embodiment 5)
An embodiment of claim 8 of the present invention will be described below. 2 and 3, a detection unit that detects digital video signals from 0 to 15 during the scanning period, a calculation unit that truncates digital video signals from 0 to 15 during the scanning period, and FIGS. By combining a detection unit that detects digital video signals from 241 to 255 during the scanning period shown and a calculation unit that truncates the digital video signals from 241 to 255 during the scanning period, The digital video signals 241 to 255 can be cut off to obtain digital video signals 16 to 240. FIG. 10 shows input and output digital video signals in the arithmetic unit according to this embodiment.
[0020]
(Embodiment 6)
An embodiment of claim 9 of the present invention will be described below. The detection unit detects digital video signals from 0 to 15 and 241 to 255 during the scanning period shown in FIGS. 2 and 6. When the detection unit detects digital video signals of 0 to 15 and 241 to 255 during the scanning period, the calculation unit performs a calculation represented by the following expression on the digital video signal.
[0021]
[Equation 3]

[0022]
By this calculation, a digital video signal having an amplitude of 0 to 255 is converted into a digital video signal having an amplitude of 16 to 240. FIG. 11 shows input and output digital video signals in the arithmetic unit according to this embodiment.
[0023]
【The invention's effect】
As described above, according to the present invention, it is possible to detect a value outside a specific range included in the scanning period of the digital video signal, and to correct this signal to a digital video signal within a specific range.
[Brief description of the drawings]
FIG. 1 is a diagram showing a digital video signal processing circuit of the present invention. FIG. 2 is a diagram showing an embodiment of a detection unit 3 in claim 2. FIG. 3 is an embodiment of a calculation unit 4 in claim 2. FIG. 4 is a diagram showing an example of an input / output digital video signal in the arithmetic unit 4 in claim 2. FIG. 5 is a diagram showing an example of an input / output digital video signal in the arithmetic unit 4 in claim 3. FIG. 7 is a diagram showing an embodiment of the detection unit 3 in claim 5. FIG. 7 is a diagram showing an embodiment of the calculation unit 4 in claim 5. FIG. 8 is an input / output digital image in the calculation unit 4 in claim 5. FIG. 9 is a diagram showing an example of an input / output digital video signal in the arithmetic unit 4 in claim 6. FIG. 10 is an example of an input / output digital video signal in the arithmetic unit 4 in claim 8. FIG. 11 is a diagram illustrating input / output digital video signals in the calculation unit 4 according to claim 9; Figure [EXPLANATION OF SYMBOLS] showing an example of a low video signal than the pedestal in FIG. 13 during scanning of an example of a digital video signal and an analog video signal in the case of FIG. 12 shows 8 bits indicating examples
1 Receiving unit 2 Decoding unit 3 Detection unit 4 Calculation unit

Claims

A digital signal receiving unit; a digital signal decoding unit output from the receiving unit; and a detection unit for detecting a value less than a specific value included in a scanning period of the digital video signal output from the decoding unit; A digital video signal processing apparatus having a calculation unit capable of performing a calculation that does not take a value less than a specific value as a result of calculation with the digital video signal during the scanning period.

2. The digital video signal processing apparatus according to claim 1, further comprising: an arithmetic unit capable of performing an operation that does not take a value less than a specific value during a scanning period by discarding a value less than a specific value. Digital video signal processing device.

2. The digital video signal processing apparatus according to claim 1, further comprising: an arithmetic unit capable of performing an arithmetic operation that does not take a value less than a specific value during a scanning period by multiplying a predetermined constant. Video signal processing device.

A digital signal receiving unit; a digital signal decoding unit output from the receiving unit; and a detection unit for detecting a value greater than a specific value included in a scanning period of the digital video signal output from the decoding unit; A digital video signal processing apparatus having a calculation unit capable of performing a calculation that does not take a value greater than a certain value as a result of calculation with the digital video signal during the scanning period.

5. The digital video signal processing apparatus according to claim 4, further comprising an arithmetic unit capable of performing an operation that does not take a value greater than a specific value during a scanning period by discarding a value greater than a specific value. Digital video signal processing device.

5. The digital video signal processing apparatus according to claim 4, further comprising an arithmetic unit capable of performing an arithmetic operation that does not take a value greater than a specific value by multiplying a constant by a constant. Video signal processing device.

A digital signal receiving unit, a digital signal decoding unit output from the receiving unit, a value less than or equal to a certain value included in a scanning period of the digital video signal output from the decoding unit, and a certain value or more A digital image having a detection unit for detecting the value of the signal, and a calculation unit capable of performing a calculation that does not take a value that is less than or equal to a certain value as a result of the calculation of the digital image signal during the scanning period. Signal processing device.

8. The digital video signal processing apparatus according to claim 7, wherein a value less than a certain value and a value less than a certain value, and a value less than a certain value during a scanning period, and a certain value or more by truncating a value less than a certain value and a value exceeding a certain value. A digital video signal processing apparatus having a calculation unit capable of performing a calculation that does not take a value of.

8. The digital video signal processing apparatus according to claim 7, wherein the digital video signal during the scanning period can be calculated to take a value less than a certain value and a value not exceeding a certain value by multiplying by a constant. A digital video signal processing apparatus comprising: