JP4476183B2 - OOB signal detection circuit - Google Patents

Description

  The present invention relates to an OOB signal detection circuit used for detecting an OOB signal in a serial ATA standard OOB sequence.

  In recent years, a new high-speed serial transfer protocol standard has been formulated as a method for connecting a personal computer (hereinafter referred to as “PC”) and a storage device such as a hard disk. These make it possible to transfer serial data at a high speed of 1.5 Gbps to 3.0 Gbps, as represented by serial ATA.

  In the serial ATA standard, negotiation called “OOB sequence” is performed before data transfer. FIG. 5 is a diagram for explaining an OOB sequence at power-on. As shown in FIG. 5, when the PC is powered on, the host-side physical layer controller (hereinafter referred to as “PHY”) of the PC first transmits a “COMRESET” signal to the device-side PHY of the storage device. To do. When the device-side PHY receives the “COMREST” signal, the device-side PHY transmits a “COMINIT” signal to the device-side PHY. Next, when the host-side PHY receives the “COMINIT” signal, the host-side PHY transmits a “COMWAKE” signal to the device-side PHY. The device-side PHY receives the “COMWAKE” signal, and receives “COMWAKE” from the host-side PHY. "Signal. As described above, the negotiation is performed by repeating the operation in which the other PHY detects each signal transmitted from the host-side PHY or the device-side PHY. When this negotiation is performed normally, data transfer is started. The COMRESET signal, the COMWAKE signal, and the COMINIT signal are collectively referred to as “OOB signal”.

  FIG. 6 shows the waveform of each OOB signal. Each OOB signal is composed of a burst period in which data is continuously transmitted and a space period in a common mode level state in which data is not transmitted. As shown in FIG. 6, the burst period and the space period of the COMRESET signal and the COMINIT signal are 106.7 ns and 320 ns, respectively, and the burst period and the space period of the COMWAKE signal are 106.7 ns, respectively.

  The detection of the OOB signal is usually performed by detecting the burst period and the space period. For the detection of the OOB signal, a dedicated receiver called a squelch receiver having characteristics different from those of a normal differential receiver is used. When the differential signal of the OOB signal corresponding to the burst period is input, the squelch receiver outputs a low (L) level signal, and the OOB signal corresponding to the common mode level corresponding to the space period is input. Then, a high (H) level signal is output. In general, the burst period and the space period are detected from the output signal of the squelch receiver, and when the burst period and the space period defined for a certain OOB signal are detected three or more times in succession, the OOB signal is detected. Is considered detected.

表１に示されるように、ＣＯＭＲＥＳＥＴ信号及びＣＯＭＩＮＩＴ信号のスペース期間は、標準（ｔｙｐｉｃａｌ）値である３２０．０ｎｓを中心として３１０．４ｎｓから３２９．６ｎｓの範囲で検出されることが好ましい。しかし、実際には、スペース期間をこの範囲で検出することは困難であるため、規格値として、３０４ｎｓ〜３３６ｎｓの範囲が規定されている。一方、ＣＯＭＷＡＫＥ信号についても、スペース期間は、１０６．７ｎｓを中心として１０３．５ｎｓから１０９．９ｎｓの範囲で検出されることが好ましいが、実際には、規格値として、１０１．３ｎｓ〜１１２ｎｓの範囲が規定されている。さらに、ＣＯＭＲＥＳＥＴ信号及びＣＯＭＩＮＩＴ信号のディテクタオフ閾値として、最小値１７５ｎｓ及び最大値５２５ｎｓがそれぞれ規定されている。これは、ＣＯＭＲＥＳＥＴ信号の検出動作において、ＣＯＭＲＥＳＥＴ信号のバースト期間を検出してから、１７５ｎｓが経過する前若しくは５２５ｎｓが経過した後に検出されるバースト期間は無効であることを定めている。同様に、ＣＯＭＷＡＫＥ信号のディテクタオフ閾値として規定された最小値５５ｎｓ及び最大値１７５ｎｓは、ＣＯＭＷＡＫＥ信号の検出動作において、ＣＯＭＷＡＫＥ信号のバースト期間を検出してから、５５ｎｓが経過する前若しくは１７５ｎｓが経過した後に検出されたバースト期間は無効であることを定めている。 Next, the space period of the OOB signal will be described. Table 1 shows the standard value of the space period of each OOB signal.

As shown in Table 1, it is preferable that the space period of the COMRESET signal and the COMINIT signal is detected in a range of 310.4 ns to 329.6 ns centering on 320.0 ns which is a typical value. However, in practice, since it is difficult to detect the space period in this range, a range of 304 ns to 336 ns is defined as a standard value. On the other hand, for the COMWAKE signal, the space period is preferably detected in the range of 103.5 ns to 109.9 ns centering on 106.7 ns, but actually, the standard value is in the range of 101.3 ns to 112 ns. Is stipulated. Further, a minimum value of 175 ns and a maximum value of 525 ns are respectively defined as detector-off threshold values for the COMRESET signal and the COMINIT signal. This stipulates that in the detection operation of the COMRESET signal, the burst period detected before 175 ns has elapsed after the detection of the burst period of the COMRESET signal or after 525 ns has elapsed. Similarly, the minimum value 55 ns and the maximum value 175 ns defined as the detector off threshold of the COMWAKE signal are detected before the 55 ns have passed or 175 ns have passed since the detection of the burst period of the COMWAKE signal in the COMWAKE signal detection operation. The burst period detected later is determined to be invalid.

  FIG. 7 is a circuit diagram showing a configuration example of a conventionally known serial ATA standard OOB signal detection circuit. As shown in FIG. 7, the OOB signal detection circuit 100 includes a three-stage flip-flop FF. When the OOB signal detection circuit 100 detects the space period of the COMINIT signal three times continuously using the flip-flop FF, the OOB signal detection circuit 100 sets the detection signal ComI to the H level and detects the space period of the COMWAKE signal three times continuously. The detection signal ComW is set to H level. When the OOB signal detection circuit 100 detects the burst period of the COMINIT signal or the COMWAKE signal, it resets the first-stage flip-flop FF. Here, the space period of the OOB signal is detected by detecting a period from the time when the squelch signal SQO changes from the L level to the H level to the next time when the squelch signal SQO changes from the H level to the L level. The OOB signal detection circuit 100 sets the detection signal ComI to the H level when this period is in the range of 253 ns to 431 ns centering on 320 ns, and when this period is in the range of 84.4 ns to 143 ns centering on 106.7 ns The detection signal ComW is set to H level.

  Note that the conventional serial interface has a counter that counts with a high-speed clock and measures the pulse width of the serial clock, and the counter that starts with the load signal from the control circuit and counts with the clock at the next stage It has a comparator that compares the counter value with the compare register value and outputs a compare match signal. The compare match signal becomes the reset signal for the edge detection circuit, and the edge detection circuit is set by the edge of the serial clock. In some cases, the output is configured as an error detection signal (see, for example, Patent Document 1).

  Further, some conventional serial receivers detect an edge of a serial data input signal with an edge detection circuit, and measure a data width of α (α is a positive integer) bit with a measurement counter (for example, Patent Documents). 2).

Further, in the conventional figure recognition apparatus, a plurality of circumferential masks arranged concentrically in an image shape are set for binary image data, and black pixels between the foreground area and the background area of the circle figure to be extracted are set. A mask / pixel counter that counts a number from a circumferential mask, a matching degree conversion circuit that converts a count value into a matching degree of a circular figure, and an edge detector that detects the edge of a circular figure using the matching degree (For example, refer to Patent Document 3).
JP 2001-273199 A JP 2003-134098 A JP 2003-150967 A

  In the conventional OOB signal detection circuit 100 shown in FIG. 7, a predetermined burst period and a predetermined OOB signal are determined using a time constant of a circuit including a resistor Rn (n is an integer of 0 or more and 4 or less) and a capacitor Cn. Each space period is detected. Therefore, the resistance value of the resistor Rn and the capacitance value of the capacitor Cn are very important, and there is a problem that the accuracy required for the resistor Rn and the capacitor Cn becomes very high. In other words, if the accuracy of the resistor Rn and the capacitor Cn is poor, there is a problem that the predetermined burst period and the predetermined space period of the OOB signal cannot be accurately detected.

  Further, when the resistor Rn and the capacitor Cn are built in the integrated circuit, the circuit scale becomes large and the area becomes large. On the other hand, when the resistor Rn and the capacitor Cn are externally attached, the number of pins and components are increased. There was a problem that disadvantages such as an increase in cost occurred.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an OOB signal detection circuit with high accuracy, low cost, and a small circuit scale.

The OOB signal detection circuit according to the present invention is a serial ATA standard OOB signal detection circuit that detects the OOB signal by detecting the burst period and the space period of the OOB signal using the input squelch signal. is there. The OOB signal detection circuit includes an edge detection unit that detects a rising edge and a falling edge of the input squelch signal, and a predetermined one of the rising edge and the falling edge by the edge detection unit. A first period detecting unit that detects a first period from when one edge is detected to when the other second edge is detected; and the second edge is detected by the edge detecting unit. A second period detecting unit that detects a second period from when the first edge is detected until the first edge is detected, and the first period detected by the first period detecting unit includes the second period detecting unit Whether or not it is a predetermined burst period of the OOB signal, and whether or not the second period detected by the second period detector is a predetermined space period of the OOB signal Determining respective first and second respective period of the can in the case of a predetermined burst period and a predetermined space period of the said respective, and a determination detection unit for detecting the said OOB signal. Hereinafter, this OOB signal detection circuit is referred to as a “first OOB signal detection circuit”.
In the first OOB signal detection circuit, the determination detection unit is configured such that each of the first and second periods is the predetermined burst period and the predetermined space period continuously for a predetermined number of times. In addition, the OOB signal is detected. Hereinafter, this OOB signal detection circuit is referred to as a “second OOB signal detection circuit”.
In the first or second OOB signal detection circuit, each of the first and second period detection units counts based on a predetermined clock signal, thereby corresponding to each of the first and second periods. Are detected, and the respective count values respectively indicating the first and second periods are output. Hereinafter, this OOB signal detection circuit is referred to as a “third OOB signal detection circuit”.
In any one of the first to third OOB signal detection circuits, the determination detection unit outputs a storage unit that stores a plurality of predetermined setting values, and the first and second period detection units output respectively. Each count value is compared with each corresponding setting value, and whether the first period is the predetermined burst period according to the magnitude relationship between each count value and each corresponding setting value And a determination unit that determines whether or not the second period is the predetermined space period. Hereinafter, this OOB signal detection circuit is referred to as a “fourth OOB signal detection circuit”.

  Preferably, in the fourth OOB signal detection circuit, the determination unit is configured such that the count value output from the first period detection unit is smaller than a set value for setting the maximum burst period of the OOB signal. The first period is determined to be the predetermined burst period, and the count value output from the second period detection unit is greater than a set value for setting the minimum space period of the OOB signal. When it is larger and smaller than a set value for setting the maximum space period of the OOB signal, it is determined that the second period is the predetermined space period. Hereinafter, this OOB signal detection circuit is referred to as a “fifth OOB signal detection circuit”.

  Preferably, in any of the first to fifth OOB signal detection circuits, the edge detection unit includes a waveform shaping unit that shapes the waveform of the input squelch signal.

  According to the OOB signal detection circuit of the present invention, an edge detection unit that detects a rising edge and a falling edge of an input squelch signal, and a first one of a predetermined one of a rising edge and a falling edge by the edge detection unit. A first period detecting unit that detects a first period from when an edge is detected until the other second edge is detected; and a first edge after the second edge is detected by the edge detecting unit A second period detecting unit for detecting a second period until the first period is detected, whether the first period detected by the first period detecting unit is a predetermined burst period of the OOB signal, and It is determined whether or not the second period detected by the second period detector is a predetermined space period of the OOB signal, and each of the first and second periods is the OOB signal. In the case where the predetermined burst period and the predetermined space period are included, the determination detection unit that detects the OOB signal is provided, so that an OOB signal detection circuit with high accuracy and low cost and a small circuit scale can be realized. it can.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of an OOB signal detection circuit according to Embodiment 1 of the present invention. As shown in FIG. 1, the OOB signal detection circuit 1 includes a waveform shaping circuit unit 2, an edge detection circuit unit 3, a control circuit unit 4, a burst period measurement up counter 5, a space period measurement up counter 6, and a storage unit. 7 and a determination circuit unit 8. The waveform shaping circuit unit 2 and the edge detection circuit unit 3 form an edge detection unit, and the storage unit 7 and the determination circuit unit 8 form a determination detection unit. Further, the control circuit unit 4 and the burst period measuring up counter 5 constitute a first period detecting unit, and the control circuit unit 4 and the space period measuring up counter 6 constitute a second period detecting unit. The OOB signal detection circuit 1 can be provided in both the PC and the storage device. Hereinafter, a case where the OOB signal detection circuit 1 is provided in the PC will be described.

  The waveform shaping circuit unit 2 performs waveform shaping of the squelch signal SQO received from the squelch receiver twice to thereby generate two waveform shaping signals rSQBUF (hereinafter simply referred to as “rSQB”) [0] and rSQB [1]. Generate and output. The edge detection circuit unit 3 detects the rising edge and the falling edge of the squelch signal SQO using the waveform shaping signals rSQB [0] and rSQB [1], respectively. When the edge detection circuit unit 3 detects the falling edge of the squelch signal SQO, the edge detection circuit unit 3 sets the falling edge detection signal rDWEDGE (hereinafter simply referred to as “rDWE”) to be output to the control circuit unit 4 to the H level. When the rising edge of SQO is detected, the rising edge detection signal rUPEDEGH (hereinafter simply referred to as “rUPE”) output to the control circuit unit 4 is set to the H level.

  When the H level falling edge detection signal rDWE is output from the edge detection circuit unit 3, the control circuit unit 4 outputs an enable signal rDCONTEN (hereinafter simply referred to as “rDCNTN”) to the burst period measurement up counter 5. The burst period measuring up counter 5 starts counting at the level. When the rising edge detection signal rUPE at H level is output from the edge detection circuit unit 3, the control circuit unit 4 outputs an enable signal rSCONTEN (hereinafter simply referred to as “rSCNTN”) for the space period measurement up counter 6. At the H level, the space period measurement up counter 6 starts counting.

  The burst period measuring up counter 5 starts counting when the enable signal rDCNTN becomes H level, and continues counting until the rising edge of the squelch signal SQO is detected. That is, the count result indicates a period (hereinafter referred to as “first period”) from when the falling edge of the squelch signal SQO is detected until the next rising edge is detected. The burst period measuring up counter 5 outputs the count result as a count signal rDCOUNT (hereinafter simply referred to as “rDCNT”). The space period measuring up counter 6 starts counting when the enable signal rSCNTN becomes H level, and continues the counting until the falling edge of the squelch signal SQO is detected. That is, the count result indicates a period (hereinafter referred to as “second period”) from when the rising edge of the squelch signal SQO is detected until the next falling edge is detected. The space period measuring up counter 6 outputs the count result as a count signal rSCOUNT (hereinafter simply referred to as “rSCNT”).

  The determination circuit unit 8 compares the value of the count signal rDCNT output from the burst period measurement up counter 5 with the corresponding set value stored in the storage unit 7, so that the first period is a burst of the OOB signal. Judge whether it is within the specification of the period. Similarly, by comparing the value of the count signal rSCNT output from the space period measuring up counter 6 with the corresponding set value stored in the storage unit 7, the second period is the standard of the space period of the OOB signal. It is determined whether it is inside. When the determination circuit unit 8 detects the burst period and the space period of the same OOB signal three times in succession, it outputs a predetermined detection signal indicating that the OOB signal has been detected.

  The setting values stored in the storage unit 7 are the setting value BURSTMAX that sets the maximum burst period of the COMINIT signal and the COMWAKE signal, the setting value COMINITMAX that sets the maximum space period of the COMINIT signal, and the minimum space period of the COMINIT signal. There are five set values: COMMITMIN, a set value COMWAKEMAX for setting the maximum space period for the COMWAKE signal, and a set value COMWAKEMIN for setting the minimum space period for the COMWAKE signal. For example, when the set value BURSTMAX is 14h, the maximum burst period is 143ns, when the set value COMINITMAX is 40h, the maximum space period of the COSMINIT signal is 431ns, and when the set value COMINITMIN is 24h, the minimum space of the COMINIT signal is The period is 253 ns. When the setting value COMWAKEMAX is 14 h, the maximum space period of the COMWAKE signal is 143 ns. When the setting value COMWAKEMIN is 0 Bh, the minimum space period of the COMWAKE signal is 84.4 ns.

  Next, the operation of the OOB signal detection circuit 1 shown in FIG. 1 will be described. FIG. 2 is a timing chart for explaining an OOB sequence at power-on. In FIG. 2, the TXP signal and the TXM signal are differential signals transmitted by the host side PHY, and the RXP signal and the RXM signal are differential signals received by the host side PHY. As shown in FIG. 2, the host side PHY transmits a COMRESET signal when the PC is powered on and the reset is released, that is, when the reset signal RST becomes H level, and then the COMINIT signal is transmitted from the device side PHY. Receive. Next, the host side PHY transmits a COMWAKE signal, and then receives the COMWAKE signal from the device side PHY. The waveform of the squelch signal SQO varies when the squelch receiver receives the COMINIT signal and the COMWAKE signal, respectively. Hereinafter, an operation in which the OOB signal detection circuit 1 detects the OOB signal using the squelch signal SQO will be described in detail. Hereinafter, as an example, an operation in which the OOB signal detection circuit 1 detects the COMINIT signal will be described.

  First, the operation when the OOB signal detection circuit 1 detects the burst period of the COMINIT signal will be described. FIG. 3 is an enlarged view of a part of the timing chart in FIG. 2, and shows a timing chart when the host-side PHY receives a burst period of the COMINIT signal. A squelch signal SQO output from a squelch receiver (not shown) is first input to a two-stage flip-flop (not shown) in the waveform shaping circuit unit 2. The waveform shaping circuit unit 2 synchronizes the squelch signal SQO with the operation clock signal CLK generated inside the OOB signal detection circuit 1 using the two-stage flip-flops. As a result, the waveform shaping circuit unit 2 generates the synchronization signal SQOSYN. Further, the waveform shaping circuit unit 2 generates the waveform shaping signals rSQB [0] and rSQB [1] by inputting the synchronization signal SQOSYN to another two-stage flip-flop (not shown). Here, the waveform shaping signal rSQB [0] is a signal delayed by one clock from the synchronization signal SQOSYN, and the waveform shaping signal rSQB [1] is a signal delayed by one clock from the waveform shaping signal rSQB [0]. . The waveform shaping circuit unit 2 outputs the generated waveform shaping signals rSQB [0] and rSQB [1] to the edge detection circuit unit 3, respectively. If there is a possibility that noise may enter the squelch signal SQO, the waveform shaping circuit unit 2 may perform filter processing such as moving average processing.

  The edge detection circuit unit 3 outputs the waveform when the waveform shaping signals rSQB [0] and rSQB [1] output from the waveform shaping circuit unit 2 satisfy the condition of rSQB [1: 0] = 2′b01. When the shaping signal rSQB [0] is at L level (“0”) and the waveform shaping signal rSQB [1] is at H level (“1”), the falling edge of the squelch signal SQO is detected. This detection is performed, for example, by inputting each waveform shaping signal rSQB [0], rSQB [1] to a flip-flop.

When detecting the falling edge of the squelch signal SQO, the edge detection circuit unit 3 sets the falling edge detection signal rDWE to the H level. The falling edge detection signal rDWE becomes L level again when one clock of the internal clock signal CLK elapses. When the falling edge detection signal rDWE becomes H level, the control circuit unit 4 sets the enable signal rDCNTN of the burst period measurement up counter 5 to active, that is, H level. The burst period measuring up counter 5 counts up based on the internal clock signal CLK only when the signal rDCNTN is active and the waveform shaping signal rSQB [0] is at L level. The burst period measuring up counter 5 outputs the count value as the count result to the determination circuit unit 8 as the count signal rDCNT. For example, when the frequency of the internal clock signal CLK is 150 MHz and the count value is N (natural number), the burst period is (N + 2) / (150 × 10 ⁶ ) seconds. The count value is held until the next count operation is started.

  The determination circuit unit 8 compares the count value output from the burst period measurement up counter 5 with the set value stored in the storage unit 7. The setting value used here is the setting value BURSTMAX that sets the maximum burst period of the COMINIT signal. This set value BURSTMAX is, for example, 14h when setting a maximum burst period of 143 ns. As shown in FIG. 3, the counting up by the burst period measuring up counter 5 is completed at 0Eh. The determination circuit unit 8 compares the count value 0Eh with the set value BURSTMAX stored in the storage unit 7. When the count value is smaller than the set value BURSTMAX, the determination circuit unit 8 determines that the first period detected by the count-up is a burst period of the COMINIT signal, and the burst enable signal rBURSTEN (hereinafter simply “rBRSTN”). To the H level. On the other hand, if the count value is larger than the set value BURSTMAX, the burst enable signal rBRSTN is set to L level. Here, detection of the OOB signal is continued when the burst enable signal rBRSTN is at the H level, but detection of the OOB signal is interrupted when the burst enable signal rBRSTN is at the L level. The enable signal rDCNTN for the burst period measuring up counter 5 becomes L level when the burst enable signal rBRSTN becomes L level.

  Next, the operation when the OOB signal detection circuit 1 detects the space period of the COMINIT signal will be described. FIG. 4 is an enlarged view of a part of the timing chart in FIG. 2, and shows a timing chart when the host-side PHY receives the space period of the COMINIT signal. When the space period of the OOB signal is detected, the edge detection circuit unit 3 determines that the waveform shaping signals rSQB [0] and rSQB [1] satisfy the condition of rSQB [1: 0] = 2′b10, that is, When the waveform shaping signals rSQB [0] and rSQB [1] are at the H level (“1”) and the L level (“0”), the rising edge of the squelch signal SQO is detected. This detection is performed, for example, by inputting each waveform shaping signal rSQB [0], rSQB [1] to a flip-flop. When detecting the rising edge of the squelch signal SQO, the edge detection circuit unit 3 sets the rising edge detection signal rUPE to the H level. The rising edge detection signal rUPE becomes L level again after one clock of the internal clock signal CLK has elapsed.

When the rising edge detection signal rUPE becomes H level, the control circuit unit 4 sets the enable signal rSCNTN of the space period measurement up counter 6 to active, that is, H level. The space period measurement up counter 5 counts up based on the internal clock signal CLK only when the enable signal rSCNTN is active and the waveform shaping signal rSQB [0] is at the H level. The space measurement up counter 6 outputs the resulting count value to the determination circuit unit 8 as the count signal rSCNT. For example, when the frequency of the internal clock signal CLK is 150 MHz and the count value is M (natural number), the space period is (M + 2) / (150 × 10 ⁶ ) seconds. The count value is held until the next count operation is started.

  The determination circuit unit 8 compares the count value counted by the space period measurement up counter 6 with the set value stored in the storage unit 7. The setting values used here are the setting value COMINITMAX that sets the maximum space period of the COMINIT signal, the setting value COMINITMIN that sets the minimum space period of the COMINIT signal, the setting value COMWAKEMAX that sets the maximum space period of the COMWAKE signal, and the COMWAKE signal Is a set value COMWAKEMIN for setting the minimum space period. As shown in FIG. 4, the count-up by the space period measurement up counter 6 is completed at 2Eh. The determination circuit unit 8 compares the count value 2Eh with each set value COMINITMAX, COMINITMIN, COMWAKEMAX, COMWAKEMIN stored in the storage unit 7, and the count value is set for each set value COMINITMAX, COMINITMIN, COMWAKEMAX, COMWAKEMIN. If each is large, each comparison result signal rINITMAX, rINITMIN, rWAKEMAX, rWAKEMIN is set to H level, and if small, each is set to L level.

  When the count-up by the space period measuring up counter 6 is completed, the determination circuit unit 8 determines whether or not the second period of the squelch signal SQO detected by the count-up is the COMINIT signal space period. Here, the determination circuit unit 8 may detect the end of the count-up when the falling edge detection signal rDWE becomes H level. The determination circuit unit 8 determines that the second period is the space period of the COMINIT signal if the comparison result signals rINITMAX and rINITMIN are at the L level and the H level when the count-up is completed. Further, when the burst enable signal rBRSTN is at the H level, the determination circuit unit 8 sets the detection signal Coml to the H level when the space period of the COMINIT signal is detected three times in succession. Here, while the burst enable signal rBURSTN is at the H level, since the first period detected by the burst period measuring up counter 5 is determined to be the burst period of the COMINIT signal, the burst enable signal rBRSTN is at the H level. Detecting the COMINIT signal space period three times continuously between levels is the same as detecting the COMINIT signal burst period and space period three times in succession.

  In order to realize such an operation, the determination circuit unit 8 may use, for example, a 3-bit shift register. In this case, the determination circuit unit 8 inputs data “1” to the shift register when the falling edge detection signal rDWE signal becomes H level immediately after detecting the space period of the COMINIT signal. Thereafter, the determination circuit unit 8 inputs data “0” or “1” to the shift register every time the falling edge detection signal rDWE becomes H level. Here, when the falling edge detection signal rDWE is at the H level, the determination circuit unit 8 inputs the data “1” to the shift register if the comparison result signals rINITMAX and rINITMIN are at the L level and the H level, respectively. Otherwise, data “0” is input to the shift register. In this way, when the space period of the COMINIT signal is detected three times in succession, the data rDECTINIT [2: 0] stored in the shift register becomes 7h. When the data rDECTINIT [2: 0] becomes 7h, the determination circuit unit 8 sets the detection signal Coml to the H level. The space period measurement up counter 6 enable signal rSCNTN becomes L level when the detection signal Coml changes from H level to L level.

  Note that the determination circuit unit 8 determines that the squelch detected by counting up when the comparison result signals rWAKEMAX and rWAKEMIN are at the L level and the H level, respectively, when the counting up by the space period measuring up counter 6 is completed. It is determined that the second period of the signal SQO is a space period of the COMWAKE signal. Further, when the determination circuit unit 8 detects the space period of the COMWAKE signal three consecutive times while the BURSTN signal is at the H level, the determination circuit unit 8 sets the detection signal ComW to the H level. Here, while the BURSTN signal is at the H level, since the first period detected by the burst period measuring up counter 5 is determined to be the burst period of the COMWAKE signal, the burst enable signal rBRSTN is at the H level. In the meantime, detecting the space period of the COMWAKE signal three times in succession is the same as detecting the burst period and the space period of the COMWAKE signal three times in succession.

  When the determination circuit unit 8 uses, for example, a 3-bit shift register, data “1” is input to the shift register when the edge detection signal rDWE signal becomes H level immediately after the space period of the COMWAKE signal is detected. . Thereafter, the determination circuit unit 8 inputs data “1” or “0” to the shift register every time the falling edge detection signal rDWE becomes H level. Specifically, when the falling edge detection signal rDWE is at the H level, if the comparison result signals rWAKEMAX and rWAKEMIN are at the L level and the H level, respectively, the data “1” is input to the shift register, and otherwise If there is, data “0” is input to the shift register. In this way, when the space period of the COMWAKE signal is detected three times in succession, the data rDECTINIT [2: 0] stored in the shift register becomes 7h. When the data rDECTWAKE [2: 0] becomes 7h, the determination circuit unit 8 sets the detection signal ComW to the H level. The end of the count-up by the space period measuring up counter 6 may be detected by an arbitrary method, and may be detected, for example, when the falling edge detection signal rDWE becomes H level.

  As described above, since the OOB signal detection circuit 1 according to the first embodiment is configured by a digital circuit, the OOB signal detection circuit 1 is higher in accuracy and lower in cost than the conventional OOB signal detection circuit configured by an analog circuit. is there. In addition, since a resistor, a capacitor, and the like are not incorporated, the circuit scale is smaller than that of a conventional OOB signal detection circuit.

  In the OOB signal detection circuit according to the first embodiment, the accuracy of signal detection can be increased by increasing the internal operating frequency. On the other hand, there is a problem that the operating current increases as the internal operating frequency increases. However, in the OOB signal detection circuit according to the first embodiment, the setting value for signal detection can be stored in the storage unit. Optimum settings of accuracy and operating current are possible, and such problems can be solved.

It is a block diagram which shows the structural example of the OOB signal detection circuit by Embodiment 1 of this invention. It is a timing chart for demonstrating the OOB sequence at the time of power-on It is a timing chart when the host side PHY is receiving the burst period of a COMINIT signal. It is a timing chart when the host side PHY is receiving the space period of a COMINIT signal. It is a figure for demonstrating the OOB sequence at the time of power-on. It is the figure which showed the waveform of the OOB signal. It is a circuit diagram which shows the structural example of the OOB signal detection circuit of the serial ATA specification known conventionally.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 OOB signal detection circuit 2 Waveform shaping circuit part 3 Edge detection circuit part 4 Control circuit part 5 Burst period measurement up counter 6 Space period measurement up counter 7 Storage part 8 Judgment circuit part

Claims (3)

In the serial ATA standard OOB signal detection circuit for detecting the OOB signal by detecting the burst period and the space period of the OOB signal using the input squelch signal,
An edge detection unit for detecting a rising edge and a falling edge of the input squelch signal, and
A first period detection for detecting a first period from when a predetermined first edge of the rising edge and falling edge is detected by the edge detection unit to when the other second edge is detected And
A second period detection unit that detects a second period from when the second edge is detected by the edge detection unit to when the first edge is detected;
Whether or not the first period detected by the first period detector is a predetermined burst period of the OOB signal, and the second period detected by the second period detector is It is determined whether or not the OOB signal is a predetermined space period, and the OOB signal is detected when the first and second periods are the predetermined burst period and the predetermined space period, respectively. A determination detection unit,
The first and second period detectors detect the corresponding first and second periods by counting based on a predetermined clock signal, respectively, and the first and second periods Output each count value indicating
The determination detection unit detects the OOB signal when each of the first and second periods is the predetermined burst period and the predetermined space period continuously for a predetermined number of times,
The determination detection unit includes a storage unit that stores a plurality of predetermined setting values;
Each count value output from each of the first and second period detectors is compared with each corresponding set value, and each count value and each set value corresponding to each count value are compared with each other. A determination unit that determines whether or not one period is the predetermined burst period and whether or not the second period is the predetermined space period;
OOB signal detection circuit comprising: a. The determination unit determines that the first period is the predetermined burst period when the count value output from the first period detection unit is smaller than a set value for setting the maximum burst period of the OOB signal. Judgment,
When the count value output from the second period detector is larger than a set value for setting the minimum space period of the OOB signal and smaller than a set value for setting the maximum space period of the OOB signal, 2. The OOB signal detection circuit according to claim 1, wherein the period of 2 is determined to be the predetermined space period . The edge detection unit, OOB signal detection circuit according to claim 1 or 2, characterized in that it comprises a waveform shaping unit for shaping the waveform of the said squelch signal input.

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