JP4472426B2 - Bus bridge circuit - Google Patents

Description

  The present invention relates to a bus bridge circuit provided between a first system bus and a second system bus.

  In recent years, system LSIs mounted on mobile phones have been desired to realize applications that require real-time performance. A typical application that requires real-time performance is typically operation processing. In the case of an application that requires real-time performance, it is necessary to finish a specific process within a certain period of time. Therefore, if you want the CPU using the cache to perform such a process, set the cache hit rate to It is necessary to estimate accurately or with sufficient margin. However, it is difficult to accurately estimate the cache hit rate at the stage of LSI design and development, where no software development has been performed, and it is difficult to install a cache with sufficient capacity due to cost and power consumption issues. .

  In such a case, the solution is to enable the CPU cache only for program areas that require high real-time performance, and disable the CPU cache for other program areas that do not require much real-time performance. Thus, a means for limiting the area of the main memory in which the cache is enabled and improving the cache hit rate within the range can be considered.

  With this means, even after LSI design is completed, a certain degree of flexibility can be dealt with by means of software design. However, even such a method has the following problems. Even if a CPU that runs on a real-time OS for embedded devices is equipped with a cache, the bus control unit is compared to a CPU with an MMU (memory management unit) that is equipped with Linux, etc. If the cache is enabled, access from the CPU is continuous (burst transfer), but for disabled areas, it is single (single transfer). In many cases.

  On the other hand, as the main memory, as the processing capacity of the system LSI is improved, a large-capacity memory commensurate with it has been demanded. However, it is difficult to have such a large-capacity memory inside the system LSI, and generally an external SDRAM (Synchronous Dynamic Random Access Memory) is often used. SDRAM is a DRAM that operates in synchronization with a clock, and realizes high-speed access by so-called burst access. Specifically, if a command is input once, data can be sequentially read from a plurality of consecutive addresses. However, when random access is made to discrete addresses, burst transfer cannot be used effectively, and the access speed is greatly reduced.

  Considering these CPU characteristics and main memory characteristics, the CPU cache is enabled only for program areas that require high real-time performance as described above, and other program areas that do not require much real-time performance, as described above. Even if the cache hit rate can be improved by disabling the cache to improve the area where high real-time performance is required, the cache must be disabled for other areas. As a result, the side-by-side (single transfer) access occurs and the access efficiency to the SDRAM is greatly reduced.

As means for solving the above problems, for example, there is means for improving the access speed by providing a buffering function in the memory control circuit (see, for example, Patent Document 1). If the CPU is improved in performance and a prefetch buffer is provided in the CPU as an auxiliary function of the cache, continuous transfer to the system bus can be secured (see, for example, Patent Document 2). Similarly, if a secondary cache is provided outside the CPU in order to improve the performance of the CPU, continuous transfer to the system bus can be secured (for example, see Patent Document 3).
JP 2001-175534 A JP-A-6-28180 JP-A-10-187532

  However, with the means described in Patent Document 1, there is a situation in which a sequentially changing address peculiar to the instruction access of the CPU cannot be used well. Further, the means described in Patent Documents 2 and 3 do not consider the case where the cache is disabled, and there is a situation that the demerit of the increase in area due to the high performance of the CPU is large. It is an object of the present invention to provide a bus bridge circuit that can prevent a decrease in access speed.

  A bus bridge circuit according to the present invention is a bus bridge circuit provided between a first system bus and a second system bus, and discriminates a specific read access supplied from the first system bus. Means, a data buffer, an address tag for temporarily storing an address of data stored in the data buffer, and a specific read access supplied from the first system bus, when stored in the address tag If the address and the address of the read access are compared, and the comparison result does not match, the read access is generated for the second system bus, and the data read from the main memory is stored in the data buffer If the comparison result is coincident, the data stored in the first data buffer is changed to the first data buffer. And a control unit which performs the system bus to receive and passes control.

  According to the above configuration, when the specific read access supplied from the first system bus is determined, the address stored in the address tag is compared with the address of the read access. By controlling the data stored in the data buffer via the first system bus, the data stored in the data buffer can be transferred without accessing the second system bus. A decrease in speed can be prevented.

  In the present invention, when the control result of the comparator does not match the address stored in the address tag and the address of the read access, and the comparison result of the comparator does not match, In response to the read access, the data read from the main memory is stored in the data buffer. If the comparison result is coincident, the data stored in the first data buffer is stored in the first buffer. And a control circuit for performing control to be transferred to the system bus.

  In the present invention, the determination unit determines a read access to an address in a specific range of the main memory as the specific read access. The determination unit determines the specific read access based on control information supplied from the first system bus.

  In the present invention, the control unit functions to convert the protocol of the first system bus into the protocol of the second system bus, and the control unit includes the first system bus and the second system bus. And the function of matching the operating frequency.

  In the present invention, the determination means determines an instruction fetch access from the CPU connected to the first system bus to the main memory connected to the second system bus as the specific read access.

  In the present invention, it is preferable to provide a buffer for temporarily storing read data and write data for the main memory when data access is issued from the CPU.

  According to the present invention, the data stored in the data buffer can be transferred without accessing the second system bus, so that the access speed can be prevented from decreasing.

  FIG. 1 shows an example of a bus configuration system to which a bus bridge circuit 3 according to an embodiment of the present invention is applied. The first system bus 2 and the second system bus 5 are connected via the bus bridge circuit 3 of the present embodiment. The first system bus 2 is connected to the CPU 1 including the cache memory 9 and the block A4, and the second system bus 5 is connected to the SDRAM memory 8 as the main memory via the SDRAM controller 6. In addition, the block B7 is connected. In this system, the program of the CPU 1 is arranged in the SDRAM 8, and the CPU 1 operates by fetching instruction data from the SDRAM 8.

  Here, the first system bus 2 and the second system bus 5 will be described. When the first system bus 2 and the second system bus 5 have different bus protocols depending on the purpose of use, The bus frequency may be different. For this reason, the bus bridge circuit 3 between the first system bus 2 and the second system bus 5 usually requires a certain amount of data buffering in order to achieve matching of protocols and matching of different operating frequencies. It becomes.

  On the other hand, the CPU 1 connected to the first system bus 2 has a built-in cache memory 9, and can select cacheable or non-cacheable for each area. In addition, the instruction bus and the data bus are internally separated, and the cache memory 9 is provided for each of the instruction and data. However, both buses are connected to the first system bus 2 in a combined form. For the cacheable area, the cache functions, so that burst transfer is executed for the first system bus 2, but for the non-cacheable area, the cache does not function. Single transfer is performed for the first system bus 2.

  FIG. 2 is a block diagram showing a schematic configuration of the bus bridge circuit 3 for explaining the embodiment of the present invention. As shown in FIGS. 1 and 2, the bus bridge circuit 3 of the present embodiment includes a first system bus 2 to which a CPU 1 having a cache memory 9 is connected and an SDRAM 8 to which a SDRAM 8 is connected via an SDRAM controller 6. The first bus interface 10 provided between the two system buses 5 and having a discrimination function for discriminating a specific read access supplied from the first system bus, and the capacity of one line of the cache memory 9 The address stored in the address tag 12 when the data buffer 13, the address tag 12 for temporarily storing the address of the data stored in the data buffer 13, and the specific read access supplied from the first system bus 2 are determined. And the read access address are compared, and if the comparison result does not match, the read address is read from the second system bus 5. Control for generating access and storing the data read from the SDRAM 8 in the data buffer 13, and when the comparison result is coincident, the data stored in the data buffer 13 is transferred to the first system bus 2. Part 16.

  The control unit 16 compares the address stored in the address tag 12 with the read access address, and the comparison result of the comparator 11 does not match the second system bus 5. A read access is generated, the data read from the SDRAM 8 is stored in the data buffer 13, and when the comparison result is coincident, the data stored in the data buffer 13 is controlled to be transferred to the first system bus 2. And a control circuit 14.

  The bus bridge circuit 3 controls the bus by a first bus interface 10 connected to the first system bus 2 and a second bus interface 15 connected to the second system bus 5.

  The address received by the first bus interface 10 is sent to the comparison circuit 11 and compared with the address tag 12. The comparison result of the comparison circuit 11 is transmitted to the control circuit 14, and the control circuit 14 operates the second bus interface 15 and the first bus interface 10 based on the information, and writes data to the data buffer 13, or Read data.

  Next, the operation of the bus bridge circuit 3 will be described with reference to FIG. 1 and FIG. First, when the CPU 1 accesses the non-cacheable area of the SDRAM 8, the bus bridge circuit 3 accepts it through the first bus interface 10 and determines what kind of access it is.

  Specifically, it is determined by the control information on the first system bus 2 whether it is a write, a read, an instruction fetch, or a data access. If there is no such information in the protocol of the first system bus 2, the address is observed, and it is determined whether the internal address tag 12 or the like is to be operated depending on whether the access area is applicable.

  After determining the specific access as described above, if it is determined that it is a desired access, specifically, an instruction fetch from the CPU 1, the internal address tag 12 and the first system bus 2 Are compared by the comparison circuit 11.

  The reason for discriminating that it is an instruction fetch is that, if only an instruction fetch is used, the address change is approximately sequential and the probability of matching with the address tag 12 is high. If they are handled together with data access, the access addresses are different, so the address tag 12 and the access address do not match each time, and the efficiency may be greatly reduced. is expected. In the case of data access, it is necessary to solve the problem of coherency between the data buffer 13 in the bus bridge circuit 3 and the SDRAM 8.

  The address comparison result is transmitted to the control circuit 14, and different control is performed depending on whether the comparison coincides or does not coincide. In the case of the comparison match, the second bus interface 15 is not activated, and the data in the data buffer 13 is transferred to the first bus interface 10. At this time, the data buffer 13 holds the same number of words as one line of the cache memory 9 in the CPU 1. As a result, the same operation can be performed on the cacheable area. If the comparison does not match, the second bus interface 15 is activated and read access is performed on the second system bus 5. The data read from the second system bus 5 is stored in the data buffer 13 and then transferred to the first bus interface 10.

  At this time, read access to the second system bus 5 is burst transfer because data corresponding to the capacity of the data buffer 13 is read at a time. Even if the access from the first bus interface 10 is less than the capacity of the data buffer 13, for example, single transfer, burst transfer is performed to the second system bus 5. As a result, even when a memory adopting a burst transfer system such as SDRAM 8 is connected to the second system bus 5, it is possible to access without lowering the transfer efficiency.

  FIG. 3 is a timing chart of the first system bus 2 and the second system bus 5. A more specific operation will be described with reference to the timing chart shown in FIG. First, the signals shown in FIG. 3 will be described. The clock (1) and the clock (2) are clock signals of the first system bus 2 and the second system bus 5, respectively. The operating frequency of the second system bus 5 is twice that of the one system bus 2.

  Address (1) and address (2) indicate addresses to be accessed. Write (1) and write (2) are signals indicating that they are write when they are “H”. The transfer type (1) and transfer type (2) are signals indicating whether the access is single transfer or burst transfer, and the burst length is some.

  Wait (1) and wait (2) are signals output from the slave side. When “L”, the master side needs to wait. Data (1) and data (2) are read data, and the read data for address A is represented as D (A). The address tag (1) is the value of the address tag 12 in the bus bridge circuit 3.

  Next, the operation in FIG. 3 will be described in time series in units of clock cycles. In the first cycle, read access to address A is started on the first system bus 2. In the bus bridge circuit 3, it is first determined whether this access is a specific access, that is, an instruction access.

  Although this determination method is not described in the timing chart, if a control information signal is separately obtained, it is determined based on the control signal. If not, the value of address A is a specific area. Judgment by whether or not.

  As for this specific area, if there is a mapping area in the address space, two or more types of addresses are allocated to the same address in the memory, so that the bus bridge circuit 3 can be specified depending on which one is used. The access discrimination function can be operated by software.

  If it is recognized that the access is specific access, the internal address tag (1) is compared with the address (1) to be accessed at present. In this case, the address tag (1) does not match because the B address is held.

  However, note that the address tag is smaller than the number of bits of the address (1) by the capacity of the data buffer 13 built in the bus bridge circuit 3. That is, when the capacity of the data buffer 13 is, for example, 8 words (1 word = 4 bytes), the number of bits corresponding to the lower 5 bits of the address (1) is the number of bits of the address tag (1).

  In the second cycle, since the address comparison result is inconsistent, the data buffer 13 is replaced, so that the wait (1) is set to “L” from the bus bridge circuit 3 for the first system bus 2. On the other hand, on the second system bus 5, burst transfer for the capacity of the data buffer 13 is started while the standby state is set.

  Here, since the capacity of the data buffer 13 is 8 words, the transfer type (2) is 8 bursts. In this regard, even though the transfer type (1) of access to the first system bus 2 is single, the access of the second system bus 5 is burst transfer, and the SDRAM 8 is efficiently It is a transfer form that can be used.

  After the third cycle, the first system bus 2 is in a standby state until the read transfer of the second system bus 5 is completed.

  In the seventh cycle, the read transfer of the second system bus 5 is completed, and data is output from the data buffer 13 to the first system bus 2. Here, the data buffer 13 has a capacity of 8 words, and it becomes a problem which word is taken out, but it depends on the address (1).

  That is, the lower 5 bits of the address A of the previous cycle determine which data is extracted from the data buffer 13, and in this cycle, the first data D (A) of the data buffer 13 is extracted. .

  In the seventh cycle, attention should be paid to the fact that access to the address A + 4 has started for the first system bus 2, and it is determined that the access is a specific access as in the first cycle. Compared with the tag (1), in this case, unlike the first cycle, the comparison result is the same.

  In the case of coincidence as described above, the data of D (A + 4) stored in the data buffer 13 can be output to the data (1) in the next cycle. Also, access to the second system bus 5 is not started.

  As will be apparent from the 8th cycle onward, since all subsequent accesses match the internal address tag (1) (note that the lower 5 bits are not compared), the access to the second system bus 5 is similarly performed. No access has occurred.

  As described above, the access to the second system bus 5 always forms a burst transfer, and the comparison by the address tag 12 does not cause unnecessary access to the second system bus 5. It is possible to improve the performance.

  As described above, according to the bus bridge circuit 3 of the present embodiment, when a specific read access supplied from the first system bus 2 is determined, the address stored in the address tag 12 is compared with the read access address. On the other hand, if the comparison result is coincident, control is performed to transfer the data stored in the data buffer 13 to the CPU 1 via the first system bus 2, so that the cache memory 9 of the CPU 1 is disabled. It is possible to prevent a decrease in the access speed of the SDRAM 8 with respect to the area.

  Further, according to the bus bridge circuit 3 of the present embodiment, the specific read access is discriminated based on whether or not the read access is made to an address within a specific range of the SDRAM 8, so that the cache memory 9 of the CPU 1 is disabled. Can be easily determined, and a decrease in the access speed of the SDRAM 8 can be prevented.

  Further, according to the bus bridge circuit 3 of the present embodiment, the control unit 16 determines specific read access based on the control information supplied from the first system bus 2, so that the cache memory 9 of the CPU 1 is disabled. It is possible to easily determine the area that is being accessed, and to prevent a decrease in the access speed of the SDRAM 8.

  The bus bridge circuit of the present invention has the effect of preventing the access speed from being lowered because the data stored in the data buffer can be transferred without accessing the second system bus. This is useful as a bus bridge circuit or the like provided between one system bus and the second system bus.

1 is a system configuration diagram showing a bus configuration to which a bus bridge circuit according to an embodiment of the present invention is applied. 1 is a block diagram showing a schematic configuration of a bus bridge circuit according to an embodiment of the present invention. The timing chart which shows the access timing of the 1st system bus and the 2nd system bus.

Explanation of symbols

1 CPU
2 First system bus 3 Bus bridge circuit 4 Block A
5 Second system bus 6 SDRAM controller 7 Block B
8 SDRAM
DESCRIPTION OF SYMBOLS 9 Cache memory 10 1st bus interface 11 Comparison circuit 12 Address tag 13 Data buffer 14 Control circuit 15 2nd bus interface 16 Control part

Claims (8)

A bus bridge circuit provided between a first system bus to which a CPU incorporating a cache memory is connected and a second system bus to which a main memory is connected ;
Discrimination means for discriminating a specific read access supplied from the first system bus;
A data buffer;
An address tag for temporarily storing an address of data stored in the data buffer;
When a specific read access supplied from the first system bus is determined, the address stored in the address tag is compared with the address of the read access, and if the comparison result does not match, the second The read access to the system bus is generated, the data read from the main memory is stored in the data buffer, and if the comparison result is coincident, the data stored in the first data buffer is A control unit for performing control to pass to the first system bus,
The determining means determines a read access to an area where the cache memory of the CPU is disabled among the read accesses to the main memory as the specific read access,
The bus bridge circuit , wherein the control unit generates the specific read access as a burst transfer for the second system bus when the specific read access is a single transfer . The bus bridge circuit according to claim 1, wherein the control unit includes:
A comparator that compares the address stored in the address tag with the address of the read access;
If the comparison result of the comparator does not match, the read access is generated for the second system bus, the data read from the main memory is stored in the data buffer, and the comparison result is not matched. In this case, a control circuit that performs control to transfer the data stored in the data buffer to the first system bus;
A bus bridge circuit comprising: The bus bridge circuit according to claim 1, wherein the determination unit includes:
A bus bridge circuit that determines a read access to an address in a specific range of the main memory as the specific read access. The bus bridge circuit according to claim 1, wherein the determination unit includes:
A bus bridge circuit that determines the specific read access based on control information supplied from the first system bus. The bus bridge circuit according to claim 1, wherein the control unit includes:
A bus bridge circuit having a function of converting a protocol of the first system bus into a protocol of the second system bus. The bus bridge circuit according to claim 1, wherein the control unit includes:
A bus bridge circuit having a function of matching operating frequencies of the first system bus and the second system bus. The bus bridge circuit according to any one of claims 1 to 6, wherein the determination unit includes:
A bus bridge circuit that determines an instruction fetch access from a CPU connected to the first system bus to a main memory connected to the second system bus as the specific read access. The bus bridge circuit according to claim 7, wherein
A bus bridge circuit comprising a buffer for temporarily storing read data and write data for the main memory when data access is issued from the CPU.

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