JP4467959B2 - Digital switch and level conversion digital switch - Google Patents

Description

The present invention relates generally to digital logic level conversion, and more particularly to a digital switch that performs digital switching and logic level conversion between a circuit having a first logic supply and another circuit having a different logic supply from the circuit , and The present invention relates to a level conversion digital switch.

  Bidirectional switch networks are often used to isolate or connect specific ports of a parallel data interface. This type of switch may also be used to isolate or connect isolated data lines. This type of device is often referred to as a “bus switch”, especially when a large number of switches are used in parallel. A bus switch is not only useful for isolating a particular device, but can also be used when one or more devices share a particular bus connection. In this type of configuration, the bus switch can be used, for example, to create a multi-port memory.

  Another common application of bus switches is live insertion (hot plug) application. A desirable feature of the bus switch component in such an application is that the bus switch should not interfere with the bus signal and the bus switch itself should not be damaged in any way. This type of device could also be used as a multiplexer or demultiplexer with multiple inputs for one output (or vice versa).

  In addition, since more and more mixed logic level circuits are available, the bus switch can translate logic levels between a system that utilizes a first logic supply and a second system that operates with a second logic supply. Is a convenient and cheap way to do. As is known in the art, a high speed bidirectional switch having a low on-resistance can be realized with a single NMOS transistor. One series-connected NMOS bus switch converts the input voltage level to an output voltage level determined by a value obtained by subtracting the threshold voltage from the gate voltage of the NMOS transistor.

  This type of circuit works well when the supply voltage is 3.3V or 2.5V and level conversion is performed between 3.3V and 2.5V, or between 2.5V and 1.8V. Function. In the example given above, the output voltage is approximately one Vtn (NMOS transistor threshold voltage) lower than the first logic supply voltage, which is approximately equal to the second logic supply voltage. When one NMOS structure is used, as long as the input voltage is the gate voltage minus the NMOS threshold voltage (Vgate−Vtn), clamping is performed at the output.

  It may be desirable to connect an analog to digital converter (ADC) operating at a supply voltage of 3.3 volts to a digital signal processor (DSP) using a 1.8 volt supply. The level translation network allows the two devices to operate with different logic supplies, but can interface. Without proper level translation, the DSP input can be overstressed or damaged.

  However, when converting between 3.3V and 1.8V, consider that this series connected NMOS transistor can no longer provide the desired interface between the two different supply voltages. I must. Therefore, there is a need for a level translation bus switch that can provide logic level translation even when the difference in logic supply exceeds a certain threshold voltage, such as a one-step logic supply voltage. The desired level translation switch is simple to build using modern integrated circuit processes, but should exhibit a relatively small component count, have minimal die area, and save power supply current.

Accordingly, in order to solve the above problems, the present invention has an object to provide a digital switch and a level conversion digital switch that exhibit a relatively small component count, have a minimum die area , and save power supply current. And

  These and other requirements (a solution to the above problem) are books that provide switching and level conversion between a first system and a second system in which an NMOS transistor operates using different logic supply voltages. Filled by the inventive level conversion digital switch. If the supply voltage of the first system is greater than the supply voltage of the second system, the gate of the NMOS transistor is driven by a voltage lower than the logic supply voltage of the first system.

According to one aspect of the present invention, an improved digital switch is a bidirectional signal path between a first system operating with a first logic supply voltage and a second system operating with a second logic supply voltage. Including a switching element. This improvement includes a drive circuit that provides a control voltage for the switching element, the control voltage being lower than the first logic supply voltage. Preferably, the switching element comprises an NMOS transistor, the second logic supply voltage amplitude than the first logic supply voltage is rather low, drive circuit, the lower than the first logic supply voltage a second supply voltage A voltage selection unit to generate, and a control unit to operate by the second supply voltage and generate a control voltage for the switching element. The voltage selection unit includes an NMOS transistor having a drain connected to the digital switch supply voltage and supplying a second supply voltage that is lower by about one NMOS threshold voltage than the digital switch supply voltage to the source.

  In another form of the invention, the controller supplies the second supply such that the control voltage at the logic output is switched between the second supply voltage and the digital switch supply reference potential in response to the switch control input signal. Includes logic that is at least partially activated by voltage. Preferably, the logic operated at least in part by the second supply voltage includes at least one inverter. Generally, the digital switch supply reference potential is ground, but is a negative supply voltage when the control unit is configured to perform a divided power supply operation.

  In yet another aspect of the invention, the NMOS transistor drain may be connected to a digital switch supply voltage and the NMOS transistor gate may be connected to a voltage different from the digital switch supply voltage. Preferably, unlike the digital switch supply voltage, the voltage connected to the NMOS transistor gate is relatively independent of temperature variations and digital switch supply voltage amplitude variations.

  The improved digital switch is responsive to a select logic control input signal between a second supply voltage that is approximately equal to the digital switch supply voltage and a second supply voltage that is approximately one NMOS threshold voltage lower than the digital switch supply voltage. It may further include a selection logic unit for performing selection between them.

  Preferably, the selection logic portion is responsive to the first selection logic control input and the switching element has a first system having a logic supply voltage Vcc1 and a second having a logic supply voltage Vcc2 approximately equal to Vcc1-Vtn. A first system in which a first level conversion mode for level conversion with the system is selected, and a selection logic unit is responsive to a second selection logic control input and the switching element has a logic supply voltage Vcc1 And select a second level translation mode that performs level translation between the second system having a logic supply voltage Vcc2 approximately equal to Vcc1-2 * Vtn (Vtn is approximately equal to the NMOS transistor threshold voltage).

  According to another aspect of the invention, the level translation digital switch is a bidirectional signal path between a first system operating with a first logic supply voltage and a second system operating with a second logic supply voltage. And a driving circuit, the driving circuit having a drain connected to the digital switch supply voltage and having a second supply voltage that is approximately one NMOS threshold voltage lower than the digital switch supply voltage as a source. A control unit including a voltage selection unit including an NMOS transistor to be supplied and logic that is at least partially operated by a second supply voltage, and generates a control voltage of the switching element, the control voltage being converted into a switch control input signal And a controller that switches between the second supply voltage and the digital switch supply reference potential in response.

  According to yet another aspect of the invention, the level translation digital switch is a bidirectional signal between a first system operating with a first logic supply voltage and a second system operating with a second logic supply voltage. NMOS transistor switching element providing a path and a drive circuit having a drain connected to the digital switch supply voltage and supplying a second supply voltage to the source which is approximately one NMOS threshold voltage lower than the digital switch supply voltage A control unit for generating a control voltage for the switching element, the control voltage being responsive to the switch control input signal, including a voltage selection unit including an NMOS transistor and a logic that is at least partially activated by a second supply voltage. And a drive circuit including a controller that switches between a second supply voltage and a digital switch supply reference potential; A selection logic for selecting between a second supply voltage approximately equal to the digital switch supply voltage and a second supply voltage that is approximately one NMOS threshold voltage lower than the digital switch supply voltage in response to the selection logic control input signal Part.

  Further objects, features, and advantages of the present invention will be described from the following description of the embodiments and drawings according to the present invention.

  The improved digital and level conversion digital switches according to the present invention exhibit a relatively small component count, minimize die area, and save power supply current.

  A level-converting digital switch will now be described that has distinct advantages over the prior art. FIG. 1 shows a prior art level converting digital switch, generally designated by reference numeral (100). Using this prior art circuit (100), one NMOS bus switch MN1 (101) supplies an output voltage following the input voltage up to the value of Vgate-Vtn. As the input voltage increases further, the output voltage is clamped at Vgate-Vtn.

  The input voltage at node A is Vccl, as shown in FIG. 1, which is the logic supply voltage for system 1 (102). Since Vgate is equal to the logic supply voltage of system 1 (102), the output voltage at node B (system 2 (103) supply voltage) subtracts the NMOS threshold voltage of about 0.8 volts from the Vccl voltage. Can be obtained by: This circuit (100) has a supply voltage (Vcc) of 3.3V or 2.5V and performs level conversion between 3.3V and 2.5V or between 2.5V and 1.8V. Works well when done, but the circuit (100) is not sufficient when the required level conversion is about 2 * Vtn rather than about Vtn.

  When performing a level conversion between 3.3V and 1.8V with a supply voltage of 3.3V, to achieve the required level conversion between A and B, the NMOS bus switch MN1 (101 It is necessary to generate a voltage lower than Vcc for driving the gate. FIG. 2 illustrates the use of a second NMOS transistor MN2 (201) that generates a second supply voltage Vx (202) that is one NMOS threshold voltage below Vcc (203). The voltage Vcc (203) may be referred to as a digital switch supply voltage. Vx (202) is used as a positive supply voltage for inverter INV1 (204). Of course, in normal operation, NMOS transistor MN2 (201) requires proper stable biasing, which is provided by a current source (205) having a value of Ibias. In practice, this current source (205) is provided by a current mirror circuit well known in the art.

  When the NMOS transistor MN1 (101) is on, INV1 (204) is Vx (202), and this voltage Vx (202) drives the gate (104) of the transistor MN1 (101). As a result, voltage conversion between the nodes A and B becomes possible. In this case, node B has a maximum voltage that is Vx (202) minus one NMOS threshold voltage or Vtn. The voltage at node B is actually 2 * Vtn lower than Vcc (203). With this configuration, logic level conversion from 3.3V to 1.8V becomes possible. Nodes A and B are interchangeable, so that the circuit of FIG. 2 is bidirectional.

  In the circuit of FIG. 3, an independent voltage Vgen (301) is applied to the gate of transistor MN2 (201) and is designed to provide maximum performance under different power supply and temperature conditions. Vgen (301) is typically supplied by a circuit that generates a fixed output voltage independent of power supply voltage variations or temperature variations. For example, Vgen (301) can be supplied by a standard voltage regulator or a voltage reference IC. It is desirable to make Vgen (301) as independent of parameter variations as possible. This is because the more stable voltage at the gate of MN2 (201) makes Vx (202) more stable, which also reduces voltage fluctuations at the output. In this context, of course, “more stable” means less dependent on temperature and digital switch supply voltage Vcc (203).

  FIG. 4 is a schematic diagram of a network for performing digital switching and logic conversion according to the present invention. The MN3 (401) is a switch that performs an actual level conversion between the nodes A and B. The Vgate voltage (402) determines the maximum output voltage obtained from the output of the network, specifically, Vgate-Vtn. Of course, the threshold voltage Vtn in this case is the threshold voltage of the NMOS transistor MN3 (401) that performs actual switching.

  The control input BE (403) determines whether the transistor MN3 (401) is on or off. In the present exemplary embodiment, the control signal BE (403) passes through a series of three inverters INV1 (404), INV2 (405) and INV3 (406). The number of inverters may be different. In fact, the logic through which the control input signal BE (403) propagates may be constructed using other logic elements such as, for example, AND gates or OR gates well known in the art.

  In a preferred embodiment of the present invention, INV3 (406) occupies a larger die area than INV2 (405), and INV2 (405) is larger than INV1 (404). Since the size gradually increases in this way, INV3 (406) is an inverter large enough to drive the gate of the large NMOS transistor MN3 (401). The inverter INV3 (406) is operated by the voltage generated on the chip (ie, Vx (407)). It should be noted that such a gradual increase in the size of the inverter is a normal practical design and not a requirement for the present invention to function well.

  It is clear that the inverter INV3 (406) switches between Vx (407) and ground in response to the control input signal BE (403), but the inverter or other transmission through which the control input signal BE (403) propagates The logic may also be configured for split power supply operation. In this case, the control unit of the circuit is operated by the second supply voltage Vx (407) and the negative supply voltage Vss (not shown in FIG. 4), so that the inverter INV3 (406) (or another NMOS transistor MN3 (401) The device selected to drive the gate of) switches between Vx and Vss in response to the control input signal BE (403). As a general principle, it may be said that the inverter INV3 (406) switches between the second supply voltage and the digital switch supply reference potential. In the case of one supply operation, the digital switch supply potential is ground. In the case of split supply operation, the digital switch supply potential is a negative supply voltage.

  Vx (407) is generated using transistors MN0 (408) and MN1 (409) with capacitor C0 (410). SELB (symbol (701) shown in FIG. 7) controls whether MN0 (408) and MN1 (409) or MP0 (symbol (703) shown in FIG. 7) is on, as will be described in detail later. To do. MN1 (409) is a very small device with respect to channel size that sets the bias current through MN0 (408). Then, MN0 (408) clamps the voltage Vx (407) with Vcc−Vtn, and uses this voltage Vx (407) as the supply source of INV3 (406). Since INV3 (406) is a standard inverter, the output of INV3 (406) corresponding to Vgate (402) is between 0 volt and Vx (407) according to control voltage input BE (403). Is switched. Thus, a method for changing the voltage Vgate (402) of the gate of MN3 (401) is provided. The voltage Vx (407) can be used as a source for other inverters and can be used to activate other circuits.

  FIG. 7 shows the selection logic part of the network of FIG. The digital input signal SELB (701) indicates whether the network of FIG. 4 performs conversion from 3.3V to 2.5V or 3.3V to 1.8V (supply voltage is 3.3V). to decide. If SELB 701 is in a high logic state, the network of FIG. 4 is configured to perform a 3.3V to 2.5V conversion. When SELB (701) is in a low logic state, the network of FIG. 4 performs a 3.3V to 1.8V conversion.

  When SELB (701) is high, transistor MP0 (703) is on. This means that Vx (407) is connected to Vcc (411) via the transistor MP0 (703). When the gate-source voltage Vgs is −Vcc, MP0 (703) is completely on. Since MP0 (703) is constructed so as to have a large channel region, the voltage drop is small. This means that Vx (407) is approximately equal to Vcc, which is the supply voltage applied to INV3 (symbol (406) shown in FIG. 4).

  On the other hand, when SELB (701) is in a low logic state, both MN0 (408) and MN1 (409) are turned on. MN1 (409) is used to set the bias current through MN0 (408). Vx (407) is set to Vcc-Vtn0 (the threshold voltage of MN0 (408)). This is because of the level conversion effect of MN0 (408). This voltage Vx (407) at Vcc-Vtn0 is a voltage used as a supply source of INV3 (reference numeral (406) shown in FIG. 4).

  MN1 (409) only sets the bias current so that MN0 (408) has a known Ids (drain-source current) through it. This bias current can be generated, for example, using a resistor or a current source. C0 (410) is a large capacitor used to keep Vx (407) as stable as possible during switching if the transient current is large. During these large switching currents, the voltage Vx (407) may change, but C0 (410) acts as a “liver” to be as stable as possible. Capacitor C0 (410) is preferably included, but is not so limited, and the circuit operates without C0 (410).

  A schematic diagram of a typical inverter, such as inverters INV1 (404), INV2 (405), and INV3 (406), is shown in FIG. 6 and denoted by reference numeral (600). Each inverter consists of a p-channel MOSFET (601) connected to a supply voltage (603) and then to an n-channel MOSFET (602) to ground. The input voltage (604) is connected to the gates of both devices (601), (602) and the output signal (605) is derived from the junction of the drains of the two devices.

  When a high level input signal (604) is applied, transistor (601) is turned off and transistor (602) is turned on, producing a logic low output signal close to 0 volts. Conversely, a low logic level appearing at input (604) turns on transistor (601) and turns off transistor (602). Thus, the output voltage (605) is a logic high level signal substantially equal to the supply voltage (603).

  The graph shown in FIG. 5 shows that the output voltage (502) (node B shown in FIG. 4) is approximately 1.V as the input voltage (501) (node A shown in FIG. 4) increases from 0 volts to 3.3 volts. It shows how it is clamped at 8 volts. The simulation of the network of FIG. 4 that produced the graph of FIG. 5 is based on a nominal model of all circuit elements, Vcc equal to 3.3 volts and a temperature of 25 degrees.

  Thus, an improved digital switch or level conversion digital switch according to the present invention having distinct advantages over the prior art has been described herein. It will be apparent to those skilled in the art that modifications may be made without departing from the spirit and scope of the invention. Accordingly, it is not intended that the invention be limited, except as necessary in light of the appended claims.

  The present invention can be applied to, for example, a digital switch that performs digital switching and logic level conversion between a plurality of circuits connected to a network.

It is a figure which shows the level conversion digital switch of a prior art. It is a figure which shows one Embodiment of the level conversion digital switch concerning this invention. It is a figure which shows another embodiment of the level conversion digital switch concerning this invention. It is a schematic diagram of the network which performs the digital switching and logic conversion concerning this invention. FIG. 5 is a graph showing how the output voltage shown in FIG. 4 is clamped as the input voltage increases. It is a schematic diagram of a typical CMOS inverter. It is a figure which shows the selection logic part of the network shown in FIG.

Explanation of symbols

100 circuit 101 NMOS bus switch MN1
102 System 1
103 System 2
104 Gate 201 Second NMOS transistor MN2
202 Second supply voltage Vx
203 Digital switch supply voltage Vcc
204 Inverter INV1
205 Current source 301 Independent voltage Vgen
401 NMOS transistor MN3
402 Vgate voltage 403 Control input BE
404 Inverter INV1
405 Inverter INV2
406 Inverter INV3
407 Second supply voltage Vx
408 Transistor MN0
409 Transistor MN1
410 Capacitor C0
411 Vcc
501 Input voltage 502 Output voltage 600 Inverter 601 p-channel MOSFET
602 n-channel MOSFET
603 Supply voltage 604 Input voltage 605 Output signal 701 SELB
702 Inverter 703 Transistor MP0
A Node B Node

Claims (27)

An improved digital switch including a switching element that provides a bi-directional signal path between a first system operating with a first logic supply voltage and a second system operating with a second logic supply voltage. ,
A drive circuit for supplying a control voltage for the switching element, the control voltage being lower than the first logic supply voltage;
A voltage selector for generating a second supply voltage lower than the first logic supply voltage; and a controller for generating a control voltage for the switching element, wherein the drive circuit is operated by the second supply voltage. And an improved digital switch.   The improved digital switch of claim 1, wherein the second logic supply voltage has a lower amplitude than the first logic supply voltage.   The improved digital switch of claim 1, wherein the switching element comprises an NMOS transistor. Wherein the voltage selecting unit has a drain connected to a digital switch supply voltage, the approximately one from the digital switch supply voltage NMOS threshold voltage lower second supply voltages to claim 1 including a NMOS transistor for supplying a source Improved digital switch as described. At least in part by the second supply voltage so that the control unit switches the control voltage at the logic output between the second supply voltage and the digital switch supply reference potential in response to a switch control input signal. The improved digital switch of claim 4 including logic that operates automatically. 6. The improved digital switch of claim 5 , wherein the logic that is at least partially activated by the second supply voltage includes at least one inverter. The improved digital switch of claim 5 , wherein the digital switch supply reference potential is ground. The improved digital switch according to claim 5 , wherein the control unit is configured to perform at least a partial power supply operation, and the digital switch supply reference potential is a negative supply voltage. 5. The improved digital switch of claim 4 , wherein the NMOS transistor drain is connected to a digital switch supply voltage and the NMOS transistor gate is connected to a voltage different from the digital switch supply voltage. 10. The improved digital switch of claim 9 , wherein unlike the digital switch supply voltage, the voltage connected to the NMOS transistor gate is relatively independent of amplitude variation and temperature variation of the digital switch supply voltage. . In response to a selection logic control input signal, a selection is made between a second supply voltage that is approximately equal to the digital switch supply voltage and a second supply voltage that is approximately one NMOS threshold voltage lower than the digital switch supply voltage. The improved digital switch of claim 4 , further comprising a selection logic unit. The selection logic portion is responsive to a first selection logic control input and the switching element has a first system having a logic supply voltage Vcc1 and a second system having a logic supply voltage Vcc2 approximately equal to Vcc1-Vtn. A first level conversion mode for performing level conversion between the first and second switching elements, and the selection logic unit is responsive to a second selection logic control input, and the switching element has a first logic supply voltage Vcc1. selecting a system and a second level conversion mode for performing level conversion between the second system having a Vcc1-2 * approximately equal logic supply voltage Vtn Vcc2 (Vtn is approximately equal to the NMOS transistor threshold voltage) according Item 12. The improved digital switch according to Item 11 . A switching element providing a bidirectional signal path between a first system operating with a first logic supply voltage and a second system operating with a second logic supply voltage, and a drive circuit;
The drive circuit has a drain connected to a digital switch supply voltage, and includes a voltage selection unit including an NMOS transistor that supplies a source with a second supply voltage that is lower by about one NMOS threshold voltage than the digital switch supply voltage; A controller that includes logic that is at least partially activated by the second supply voltage and generates a control voltage for the switching element, the control voltage being responsive to a switch control input signal; And a controller for switching between the digital switch supply reference potential and a level conversion digital switch. 14. The level conversion digital switch according to claim 13 , wherein the amplitude of the second logic supply voltage is lower than that of the first logic supply voltage. The level conversion digital switch according to claim 13 , wherein the switching element includes an NMOS transistor. 14. The level conversion digital switch of claim 13 , wherein the logic that is at least partially activated by the second supply voltage includes at least one inverter. 14. The level conversion digital switch according to claim 13 , wherein the digital switch supply reference potential is ground. 14. The level conversion digital switch according to claim 13 , wherein the control unit is configured to perform at least a partial power supply operation, and the digital switch supply reference potential is a negative supply voltage. 14. The level conversion digital switch according to claim 13 , wherein the NMOS transistor drain is connected to a digital switch supply voltage, and the NMOS transistor gate is connected to a voltage different from the digital switch supply voltage. 20. The level conversion digital switch according to claim 19 , wherein unlike the digital switch supply voltage, the voltage connected to the NMOS transistor gate is relatively independent of amplitude fluctuation and temperature fluctuation of the digital switch supply voltage. In response to a selection logic control input signal, a selection is made between a second supply voltage that is approximately equal to the digital switch supply voltage and a second supply voltage that is approximately one NMOS threshold voltage lower than the digital switch supply voltage. The level conversion digital switch according to claim 13 , further comprising a selection logic unit. The selection logic portion is responsive to a first selection logic control input and the switching element has a first system having a logic supply voltage Vcc1 and a second system having a logic supply voltage Vcc2 approximately equal to Vcc1-Vtn. A first level conversion mode for performing level conversion between the first and second switching elements, and the selection logic unit is responsive to a second selection logic control input, and the switching element has a first logic supply voltage Vcc1. selecting a system and a second level conversion mode for performing level conversion between the second system having a Vcc1-2 * approximately equal logic supply voltage Vtn Vcc2 (Vtn is approximately equal to the NMOS transistor threshold voltage) according Item 22. The level conversion digital switch according to Item 21 . An NMOS transistor switching element providing a bidirectional signal path between a first system operating with a first logic supply voltage and a second system operating with a second logic supply voltage;
A voltage selector including an NMOS transistor having a drain connected to a digital switch supply voltage and supplying a source with a second supply voltage that is approximately one NMOS threshold voltage lower than the digital switch supply voltage; and the second supply A controller that includes logic that is at least partially activated by a voltage to generate a control voltage for the switching element, the control voltage being responsive to a switch control input signal to the second supply voltage and the digital switch supply reference A drive circuit including a controller that switches between potentials;
In response to a selection logic control input signal, a selection is made between a second supply voltage that is approximately equal to the digital switch supply voltage and a second supply voltage that is approximately one NMOS threshold voltage lower than the digital switch supply voltage. A level conversion digital switch including a selection logic unit. 24. The level conversion digital switch according to claim 23 , wherein the second logic supply voltage has an amplitude lower than that of the first logic supply voltage. The level conversion digital switch according to claim 23 , wherein the digital switch supply reference potential is ground. 24. The level conversion digital switch according to claim 23 , wherein the control unit is configured to at least partially perform a divided power supply operation, and the digital switch supply reference potential is a negative supply voltage. The selection logic portion is responsive to a first selection logic control input and the switching element has a first system having a logic supply voltage Vcc1 and a second system having a logic supply voltage Vcc2 approximately equal to Vcc1-Vtn. A first level conversion mode for performing level conversion between the first and second switching elements, and the selection logic unit is responsive to a second selection logic control input, and the switching element has a first logic supply voltage Vcc1. selecting a system and a second level conversion mode for performing level conversion between the second system having a Vcc1-2 * approximately equal logic supply voltage Vtn Vcc2 (Vtn is approximately equal to the NMOS transistor threshold voltage) according Item 24. The level conversion digital switch according to Item 23 .

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