JP4456084B2 - Control device and firmware active exchange control method thereof - Google Patents

Description

  The present invention relates to a control device such as a disk control device and its firmware active exchange control method, and in particular, it is possible to exchange controller firmware in a control device in a state where input / output (I / O) request processing from a host device is continued. Related to the technology.

  A disk control device such as a disk array device processes I / O requests from a host processor (hereinafter referred to as a host), which is a host device, by a CPU and firmware comprising a group of instructions executed by the CPU. A certain disk unit is controlled. When it is necessary to expand the function of the disk controller or to correct a bug in the firmware, it is necessary to update the firmware. If the disk controller can be taken offline at this time and the firmware can be updated, it will be relatively easy. The firmware can be replaced with a new one.

  However, in an environment where the disk control device cannot be taken offline, such as a 24-hour operation system, so-called active replacement is required in which the firmware is revised without blocking the host I / O.

  A controller firmware hot replacement method in a conventional disk array apparatus will be described below. In the active replacement of controller firmware in a disk array device, for example, the following methods (1) to (3) below have been used to update the firmware without blocking the host I / O path. It was.

  (1) By making a busy response with the link of the disk array device to the host interface kept UP, the host is made to retry the I / O request. During this time, the firmware is revised. Before detecting the I / O retry timeout on the host side, the firmware revision is completed and I / O transmission / reception is continued.

  (2) Store I / O in the buffer during firmware revision. As in the method (1) above, before the host detects an I / O response timeout, the firmware revision is completed, after which the I / O is processed and a response is returned.

  (3) If there is an environment where the firmware cannot be revised without blocking the host I / O path using either method (l) or (2) above, the operator manually switches the path, Prevents path blockage by updating the firmware from a controller that has no path connection.

  The following Patent Document 1 is a document describing a conventional technique for realizing non-stop maintenance. In the technique described in Patent Document 1, non-stop operation and non-stop maintenance are realized by a plurality of redundant disk drive control devices that control a disk device.

The technique described in Patent Document 1 realizes a load balancing function in two control devices, and when uploading firmware to the control device, the device that mainly transmits and receives I / O is switched. , Upload firmware for each device. As a system, since a control device that has not uploaded firmware performs I / O transmission / reception, I / O seems to be continuing from the host device. However, while the firmware is being uploaded, the control device goes down and does not accept any I / O.
Japanese Patent Laying-Open No. 2005-122863

  In the controller firmware hot replacement of the conventional apparatus by the methods (1) to (3) described above, the following problems occur.

[Problems with method (l)]
With method (l) above, the firmware revision is completed within the I / O retry timeout time on the host side, and it appears that I / O continues. However, during the firmware revision, the I / O cannot be processed due to the busy response, and the corresponding I / O is retained. Also, since the I / O retry timeout time on the host side varies depending on the system request, the timeout may be detected on the host side depending on the system.

[Problems with method (2)]
In the method (2), since the buffer in the disk control device is limited, I / O is lost when a buffer full occurs. There is also the same problem as the method (1) above.

[Problems with method (3)]
When the method (3) above is used, it is troublesome for the operator to perform, and it also involves human error.

  Further, in the technique of Patent Document 1, the control device is down during firmware uploading and does not accept I / O at all, but the control device itself is not down even during firmware uploading. , I / O can be accepted.

  The present invention solves the above-described problems. In particular, by using a multi CPU and an I / O control table, I / O path switching from a host device and a busy response to the host device are not required, and I / O processing delay is reduced. An object of the present invention is to realize controller firmware active exchange in a control device such as a disk that can suppress and continuously transmit and receive I / O.

In order to solve the above-described problem, the first invention is a control device that executes an I / O process for a lower-level device in response to an I / O request from a host (high-level device). Stores a plurality of processors (CPUs) that process O, a plurality of firmware for operating each processor stored in the memory, and distribution control information that determines to which processor I / O requests from the host are allocated The I / O processing is completed for the I / O control table and an I / O processing instruction including input / output destination address information to be processed by receiving an I / O request from the host for each processor. An I / O processing instruction list to be stored, and a control means for controlling the current firmware revision by the processor and firmware. In response to these firmware revision instructions, the distribution control information in the I / O control table is updated to a state in which the distribution of I / O requests to the processor subject to firmware revision is prohibited, and the I / O processing instruction list There was confirmed that there are no more I / O processing instructions to hold, have row control to perform revision of firmware, processors that do not become a revised target firmware, I / O check start request during revision firmware In response to this notification, the I / O processing instruction held in the I / O processing instruction list is referred to, and the I / O to be processed by the local processor is the same as the input / output destination address information. In addition, the processor subjected to the firmware revision check whether there is an unprocessed I / O processing instruction, and the same input / output destination address Against the process to guarantee the ordering of I / O, and performs until further notice of the I / O check end request.

According to the first invention, by using the I / O control table, the I / O request from the host is automatically distributed to other processors when the firmware is revised, and the firmware is revised with minimal influence on the host. can do. In addition, the I / O processing instruction list that holds the I / O processing instruction including the input / output destination address information can complete all the accepted I / O processes and can also perform the I / O processing to the same input / output destination address. It is possible to prevent inconsistency in the order of / O.

A second invention is a control device that executes I / O processing for a lower-level device in response to an I / O request from a host, and a plurality of processors that process I / O requested from the host, A plurality of firmware for operating each processor stored in the memory, an I / O control table for storing distribution control information for deciding to which processor an I / O request from the host is allocated, and for each processor, An I / O processing instruction list that holds an I / O processing instruction including input / output destination address information that is processed upon receipt of an I / O request from the host, and the processor completes the I / O processing, and a processor And a control means for controlling the current firmware revision by the firmware, the control means in response to an external firmware revision instruction, The distribution control information in the O control table is updated to a state in which the distribution of I / O requests to the processor subject to the firmware revision is prohibited, the firmware revision is controlled, and the firmware revision target when I / O processing instructions list since the processor holds the I / O processing instructions, have rows interrupt notification for transfer their I / O processing instructions for the other processors, the other processor In response to a notification of an I / O check start request at the time of firmware revision, the I / O processing address of the I / O to be processed by the own processor is the same I / O processing instruction, and the firmware revision target The new processor checks whether there is an unprocessed I / O processing instruction, and the I / O order for the same input / output destination address The process to ensure, and performing until a I / O check end of request notice.

  According to the second aspect of the invention, since the I / O processing instruction list held in the I / O processing instruction list is transferred to another processor, it is possible to take over the firmware of the firmware in addition to the effects of the first aspect of the invention. There is an effect that the revision can be executed immediately when a revision request is received from the outside.

  According to a third aspect of the present invention, in the second aspect of the present invention, when the one of the plurality of processors is down, the control means sends the distribution control information in the I / O control table to the down processor. When the I / O processing instruction list of the down processor is updated to a state in which the distribution of the I / O request is prohibited, and the I / O processing instruction list of the down processor holds the I / O processing instruction, An interrupt notification for taking over the O processing instruction is performed.

  According to the third aspect of the present invention, the control means for updating the firmware is used, and the I / O processing instruction being processed by the down processor can be taken over to another processor. The impact on the host can be reduced.

  According to the present invention, I / O path switching from the host device is not required, a busy response to the host device is not required, I / O processing delay is suppressed, and I / O transmission / reception can be continuously performed. The active exchange of the controller firmware in the control device such as a disk can be realized.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration example of a disk control apparatus according to the present invention. The disk control device 1 controls input / output (I / O) between the host device 2 as a host device and the disk device 3 as a lower device. The disk control device 1 is connected to a maintenance terminal 4 that uploads firmware (hereinafter referred to as firmware UP) when the firmware is revised.

  The I / O from the host 2 is received by channel adapters (CA) 110 and 111 that serve as an interface with the host 2 and transferred to the I / O control unit 12 that controls the I / O. The I / O control unit 12 analyzes the I / O and accesses the disk device 3 via drive interfaces (DI: Drive Interface) 150 and 151 which are interfaces with the disk device 3. Is called.

  Here, the I / O control unit 12 has a plurality of CPUs, and firmwares 140 and 141 for performing I / O control by the respective CPUs 130 and 131 operate. The firmware 140, 141 exists in the memory of the disk control device 1, and its archive is stored in the pre-deployment firmware storage unit 19 composed of a flash memory or the like, and when the device is booted, that is, when the power to the device is turned on. Expanded on the memory when the device is reset.

  Further, the memory of the disk control device 1 is provided with a shared information area for storing information shared by each control unit such as the I / O control table 160. In addition to the I / O control unit 12, the monitoring control unit 18 that monitors each control unit does not operate during normal operation, but controls interrupts that cause another CPU (firmware) to process I / O when the firmware is revised or abnormal There is an I / O processing re-interrupt control unit 17 to perform.

  When firmware revision is performed in the disk controller 1, the firmware cannot process I / O until the revision process is completed. In the control method according to the present embodiment, I / O control is shifted to one CPU (firmware), and firmware revisions are sequentially performed on a CPU basis. In order to solve the above-described problems of the prior art, the number of CPUs (firmware) to be controlled by I / O is not a single number, but an I / O control table on which information on CPUs (firmware) for controlling I / O is placed 160 is used. In this control method, the I / O control table 160 is dynamically changed to update the firmware, so that path switching from the host 2 side is performed without causing I / O stop / delay. It is characterized by using no method. Details will be described next.

  Hereinafter, for the sake of easy understanding, the CPU 130 is represented as CPU # 0, the CPU 131 is represented as CPU # 1, the firmware 140 on the CPU # 0 side is represented as firmware # 0, and the firmware 141 on the CPU # 1 side is represented as firmware # 1.

  FIG. 2 shows the state of the disk controller 1 before the firmware revision. FIG. 3 shows the state of the memory 10 and the pre-deployment firmware storage unit 19 in the disk controller 1.

  As shown in FIG. 3, on the memory 10, there is firmware # 0 operating on CPU # 0, firmware # 1 operating on CPU # 1, and a shared information area 16 holding control information. is there. Here, the shared information area 16 includes an I / O control table 160 indicating which CPU (firmware) controls I / O from the host 2. There are a plurality of CPUs in charge of I / O control. For example, when one CPU (firmware) goes down, there is no need to stop I / O once and newly construct control information of the device. However, the operation can be continued. Further, it is possible to load balance the CPU to be I / O controlled by this I / O control table 160.

  In the normal state, the channel adapter 110 or 111 that has received I / O from the host 2 raises an interrupt to each CPU (firmware) in charge of I / O based on the I / O control table 160, and Take a mechanism to control O. In the example of FIG. 2, as shown in the I / O control table 160, the CPU # 0 (firmware # 0) controls the I / O # 0 from the host 2, and the I / O # 1 from the host 2 is the CPU. # 1 (firmware # 1) is set to be controlled.

  When a firmware revision instruction is received from the outside of the maintenance terminal 4 or the like, as shown in FIG. 3, the new firmware is deployed from the pre-deployment firmware storage unit 19 to an empty area of the memory, and at the same time, the I / O control table 160 Update. By updating the I / O control table 160, I / O control is shifted to one CPU (firmware) side, and firmware revision is performed.

  Next, the I / O control table 160 serving as a base for I / O control will be described. In order to determine which CPU is in charge of I / O from the host 2, the disk devices and logical volumes (hereinafter referred to as LUNs) that the respective CPUs # 0 and # 1 are in charge of are clarified. The CPU in charge is determined by determining which LUN the I / O accesses. This determination method is a method also performed in the prior art.

  In this embodiment, as described above, the number of CPUs (firmware) responsible for LUNs is not one, but a plurality of priority levels are provided for processing I / O. The CPU in charge (firmware) that controls the I / O, its status and priority information are set in the I / O control table 160, and the I / O is controlled based on this information. In other words, in this control method, each CPU is ready to operate as long as it has access to the LUN in charge. However, all interrupts to the CPU for I / O are normally given priority in the I / O control table 160. Therefore, when there is a CPU (firmware) with a high priority, the CPU (firmware) with a low priority does not process the I / O in charge of the CPU in principle.

  The difference from the existing conventional apparatus will be described. In an existing device, a CPU in charge of a certain LUN is unique. For this reason, when changing the CPU in charge of I / O, the host I / O is temporarily stopped, the control information inside the system is reconstructed, and when this is completed, the host I / O processing is resumed. On the other hand, by using the control method according to the present embodiment, the CPU in charge can be quickly switched by changing the I / O control table 160 without stopping the host I / O.

  Next, the mechanism of the control method according to this embodiment will be described in more detail. FIG. 4 is a diagram for explaining an I / O control method in a normal state.

  First, when the CA (# 0) 110 or CA (# 1) 111 receives the I / O from the host 2, the CA reads the I / O from the I / O control table 160 existing in the shared information area 16 on the memory 10. The CPU of the I / O control unit 12 with high priority in charge of I / O is determined, and a message (interrupt notification) is transmitted to the corresponding CPU # 0 or CPU # 1 so as to process the I / O. This message (interrupt notification) is stored in the message queues 50 and 51 of each CPU and processed by firmware # 0 and # 1.

  In addition, the CA 110 or CA 111 transmits a message (interrupt notification) to the I / O control unit 12 and simultaneously sends an I / O processing command (information about what information is read / written to which address of which LUN). Register in the I / O processing instruction lists 60 and 61. This list also exists in the shared information area 16 on the memory. The instructions in the list are deleted when the CPU of the I / O control unit 12 completes the processing. In a normal state, that is, in a normal operating state, I / O control is not performed using the I / O processing instructions in this list.

  The operation when the disk controller 1 receives a firmware revision instruction from the external maintenance terminal 4 in the above state will be described next. FIG. 5 is a diagram for explaining an I / O control method after a firmware revision instruction.

  When there is a firmware revision instruction, first, the I / O control table 160 is changed to switch the CPU of the I / O control unit 12 in charge of I / O. In this example, since the CPU # 0 (firmware # 0) performs the firmware revision, as shown in FIG. 5, the state of the CPU # 0 on the I / O control table 160 is changed from “Active” (in operation) to “ “Pending” (pending) state is set and the priority is invalidated. The CPU in charge of controlling I / O # 0 has the highest priority.

  As a result, after the I / O control table 160 is changed, no message (interrupt notification) for performing I / O processing is sent from the CAs 110 and 111 to the CPU # 0, which is the CPU on the firmware revision side. For this reason, it is possible to continue the processing without stopping or delaying the I / O control even after the firmware revision instruction.

  CPU # 0 on the firmware revision side must complete all the I / O processing sent to its own CPU before the firmware revision instruction (that is, before the change of I / O control table 160). . After all this is completed, the actual firmware revision operation is started by resetting the CPU # 0 (firmware # 0) or the like. For this reason, the firmware revision process is put on standby until the I / O process accepted before the revision instruction is completed.

  Here, one problem occurs. In the transition state after the change of the I / O control table 160, an I / O message addressed to the block address of the same LUN as the I / O processed by the CPU # 0 that performs the firmware revision is displayed in the I / O control table. This is a case where the priority is increased by updating 160 and the message is transmitted to the CPU # 1 which is newly in charge. In this case, inconsistency may occur in the order of I / O to the same block.

  Therefore, in order to solve this problem, the firmware # 1 of the CPU # 1 has accessed the I / O in the transitional state just before the I / O control table 160 is updated (originally assigned to the CPU # 0). The CPU # 0 on the firmware revision side checks whether or not it is being processed, and processes the I / O. In order to perform this check, the I / O processing instruction list (which may be mapping information or the like) 60 is checked simultaneously with the transmission of a message (interrupt notification) from the CAs 110 and 111 to the I / O control unit 12. If processing can be performed by this check, I / O processing is continued. If processing is not possible (if there is an I / O addressed to the block address of the same LUN), CPU # 0 is given the highest priority first. Send a message to make it happen. Thus, processing can be performed without breaking the order of I / O processing and without affecting other I / O. Instead of sending a message to CPU # 0, an I / O request issued after the access destination block competes is temporarily requeued to message queue 51 of CPU # 1, etc. You may make it wait for predetermined time.

  When the revision of the firmware of CPU # 0 is completed, the I / O control table 160 is returned to the original state shown in FIG. Thereafter, if revision of the new firmware for CPU # 1 is executed in the same manner, both firmware # 0 and # 1 of CPU # 0 and CPU # 1 are revised to the new firmware.

  The above method is a method for entering the firmware revision process (reset, etc.) after the CPU performing the firmware revision completes all the I / O processing queued before receiving the firmware revision instruction. According to another control method, the firmware revision operation can be started immediately after receiving the firmware revision instruction. By using this method, not only shortening the firmware revision time, but even if the firmware goes down due to a firmware failure, etc. and the CPU on one side unexpectedly falls into a state where it cannot be used, processing continues without blocking the path. can do. This control method will be described below.

  FIG. 6 is a diagram for explaining an I / O control method when an abnormality occurs or when firmware revision is immediately executed. An example will be described in which the CPU # 0 is down (or the firmware update operation is started immediately without processing the queued I / O).

  When a failure occurs in CPU # 0 (firmware # 0) and it goes down, the monitoring control unit 18 detects this. Thereafter, since CPU # 0 becomes unusable, the I / O control table 160 is updated. In FIG. 6, the state of the CPU # 0 (firmware # 0) is updated from the “Active” state (in operation) to the “Down” state. As a result, the I / O # 0 from the host 2 is not allocated to the down CPU # 0 but is allocated to the CPU # 1.

  Next, the monitoring control unit 18 causes the I / O processing reinterrupt control unit 17 to reprocess the down I / O of the CPU # 0 in order to process the I / O processing instruction assigned to the CPU # 0. Ask. The I / O processing re-interrupt control unit 17 that has received this checks the I / O processing instruction list 60 on the CPU # 0 side, confirms the existence of unprocessed / uncompleted I / O processing, and then stores this information. A message (interrupt notification) is created and transmitted to cause CPU # 1 to perform I / O processing. Receiving this, CPU # 1 performs these I / O processes.

  Again, the order of I / O processing is a problem. However, if access to the same LUN block address is performed in the same manner as described above, priority can be given to the I / O processing that has been re-interrupted to avoid inconsistency in order. it can.

  FIG. 7 is a processing sequence when the I / O control method of FIG. 5 is used, and shows an example of a sequence when the CPU # 0 side that performs firmware revision processes all the I / O that has already been accepted. ing.

  When CPU # 0 receives a firmware revision request (S1), it requests I / O check start to CPU # 1. Subsequently, the I / O control table 160 is updated, and the new firmware stored in the pre-deployment firmware storage unit 19 is deployed (S2). Thereafter, the completion of the I / O processing of the own CPU # 0 is checked by looking at the I / O processing instruction list 60 (S3).

  On the other hand, CPU # 1, which has received the I / O check start request, checks whether the CPU # 0 accesses the block address of the same LUN as the I / O being processed by the CPU # 1. Processing is started (S4), and if there is an access to the block address of the same LUN, I / O priority processing is requested to the I / O processing unit of CPU # 0, and processing completion report from CPU # 0 , The I / O processing is performed. This check is continued until an I / O check end request is received from CPU # 0.

  In CPU # 0, if the completion of all I / O processing is confirmed by checking the I / O processing instruction list 60, an I / O check end request is sent to CPU # 1, and then the firmware is revised by resetting, etc. Is started (S5). That is, the operation by the new firmware developed on the memory 10 is started.

  Normally, after the firmware revision of CPU # 0 is normally completed, a firmware revision request is subsequently sent to CPU # 1, and the firmware revision process is similarly performed for CPU # 1.

  FIG. 8 shows a processing sequence when the I / O control method of FIG. 6 is used, and shows an example of a sequence when an abnormality occurs in CPU # 0. The sequence when CPU # 0 immediately executes the firmware revision is basically the same.

  When the monitoring control unit 18 detects that CPU # 0 is down (S10), it makes an I / O check start request to CPU # 1. Subsequently, the I / O control table 160 is updated (S11), and a re-interrupt process start request is made to the I / O process re-interrupt control unit 17.

  CPU # 1, which has received the I / O check start request, checks whether access to the block address of the same LUN as the unprocessed I / O is performed by CPU # 0 with respect to the I / O processed by CPU # 1 (S12), if there is an access to the block address of the same LUN, the I / O processing is temporarily suspended.

  The I / O processing re-interrupt control unit 17 that has received the re-interrupt processing start request refers to the I / O processing instruction list 60 for CPU # 0, and if the presence of unprocessed I / O is confirmed, the control is performed. Therefore, the CPU # 1 is notified of an I / O processing interrupt (S13). CPU # 1 receives this notification and performs I / O processing that has not been processed by CPU # 0. The I / O processing re-interrupt control unit 17 similarly performs unprocessed I / O processing until the I / O processing instruction list 60 of the CPU # 0 becomes NULL (empty), and the I / O processing instruction list 60 Is confirmed to be NULL (empty), the end of the re-interrupt processing is notified to the monitoring control unit 18 (S14). Upon receiving the notification, the monitoring control unit 18 transmits an I / O check end request to the CPU # 1, and completes the processing related to the unprocessed I / O of the CPU # 0.

  In the case of CPU # 0 firmware revision instead of CPU # 0 down, the firmware revision can be started immediately after updating the I / O control table 160 in S11.

  In the above embodiment, an example in which there are two CPUs and firmware has been described, but even if there are three or more, I / O control and firmware revision are performed in the same manner using the present invention. It is clear that we can do it without explaining it. Further, although the example of firmware active maintenance in the disk control device has been described, the firmware active replacement control method according to the present invention can be applied in the same way as long as it is not limited to the disk control device and is a similar peripheral device control device. it can.

  In the above-described embodiment, the monitoring control unit 18 and the I / O processing re-interrupt control unit 17 may be assigned to one specific CPU (firmware). As this method, for example, one CPU (firmware) that is active among a plurality of CPUs (firmware) is selected as a master for main control, and the monitoring control unit 18 and I / O processing re-interrupt control are selected. A method for realizing the unit 17 by a CPU (firmware) as a master is used. In this case, when the firmware revision is performed for the CPU (firmware) serving as the master, the master is transferred to another CPU (firmware) in advance. Even when the master CPU (firmware) goes down, when it is detected, the master is switched so that another predetermined CPU (firmware) becomes the master.

It is a figure which shows the structural example of a disk control apparatus. It is a figure which shows the state of the disk control apparatus before firmware revision. It is a figure which shows the state of the memory in a disk control apparatus, and the firmware storage part before expansion | deployment. It is a figure explaining the I / O control method in a normal state. It is a figure explaining the I / O control method after a firmware revision instruction | indication. It is a figure explaining the I / O control method at the time of abnormality or performing firmware revision immediately. It is a figure which shows the example of a sequence when CPU side which performs firmware revision processes all I / O. It is a figure which shows the example of a processing sequence in the case of abnormality or performing firmware revision immediately.

Explanation of symbols

1 disk controller 2 host 3 disk device 4 maintenance terminal 10 memory 110, 111 channel adapter (CA)
12 I / O control unit 130, 131 CPU
140,141 Firmware 150,151 Drive interface (DI)
16 Shared information area 160 I / O control table 17 I / O processing reinterrupt control unit 18 Monitoring control unit 19 Firmware storage unit before deployment

Claims (5)

A control device that executes I / O processing for a lower-level device in response to an I / O request from a higher-level device,
A plurality of processors for processing I / O requested by the host device;
A plurality of firmware for operating each of the processors stored in a memory;
I / O control information storage means for storing distribution control information for determining to which processor the I / O request from the host device is distributed;
An I / O processing instruction including input / output destination address information to be processed by receiving an I / O request from the host device is held for each processor until the I / O processing is completed. / O processing instruction holding means;
Control means for controlling revision of the current firmware by the processor and the firmware,
In response to an external firmware revision instruction, the control means prohibits the distribution of I / O requests to the processor subjected to firmware revision by using the distribution control information in the I / O control information storage means. updates to the I / O processing instruction holding means to ensure that the no longer I / O processing instructions to hold, have row control to perform revision firmware,
The processor that is not subject to firmware revision refers to the I / O processing instruction held by the I / O processing instruction holding means in response to the notification of the I / O check start request at the time of firmware revision. Checks whether the I / O to be processed is the same I / O processing instruction as the input / output destination address information and the processor to which the firmware is revised has no unprocessed I / O processing instruction. A control device that performs processing for guaranteeing the order of I / O with respect to the same input / output destination address until an I / O check end request is notified . A control device that executes I / O processing for a lower-level device in response to an I / O request from a higher-level device,
A plurality of processors for processing I / O requested by the host device;
A plurality of firmware for operating each of the processors stored in a memory;
I / O control information storage means for storing distribution control information for determining to which processor the I / O request from the host device is distributed;
An I / O processing instruction including input / output destination address information to be processed by receiving an I / O request from the host device is held for each processor until the I / O processing is completed. / O processing instruction holding means;
Control means for controlling revision of the current firmware by the processor and the firmware,
In response to an external firmware revision instruction, the control means prohibits the distribution of I / O requests to the processor subjected to firmware revision by using the distribution control information in the I / O control information storage means. To the other processor when the I / O processing instruction holding means of the processor subject to the firmware revision holds the I / O processing instruction. There line an interrupt notification to take over the I / O processing instructions Te,
In response to the notification of the I / O check start request at the time of the firmware revision, the other processor has the same I / O processing instruction as the I / O to be processed by the own processor and the input / output destination address information. Notification of an I / O check end request to check whether there is an unprocessed I / O processing instruction in the processor subject to firmware revision, and to guarantee the I / O order for the same input / output destination address A control device characterized by performing until there is . The control device according to claim 2,
Further, when one of the plurality of processors is down, the control means distributes the distribution control information in the I / O control information storage means to distribute the I / O request to the down processor. To update to a prohibited state and allow the other processor to take over the I / O processing instruction when the I / O processing instruction holding means of the down processor holds the I / O processing instruction A control device that performs an interrupt notification. Multiple processors that process I / O requested from the host device, multiple firmware for operating each processor stored in the memory, and to which processor the I / O request from the host device is distributed I / O control information storage means for storing distribution control information for determining I / O including I / O destination address information to be processed by receiving an I / O request from the host device for each processor A control device comprising I / O processing instruction holding means for holding an O processing instruction until the I / O processing is completed, and executing I / O processing for the lower device in response to an I / O request from the upper device Firmware active exchange control method in
By updating the distribution control information in the I / O control information storage means in response to an external firmware revision instruction, to a state in which the distribution of the I / O request to the processor subjected to the firmware revision is prohibited. , The process of causing other processors to take charge of subsequent I / O requests from the host device,
A processor that is not subject to firmware revision refers to an I / O processing instruction held by the I / O processing instruction holding means in response to a notification of an I / O check start request at the time of firmware revision, and Checks whether the I / O to be processed is the same I / O processing instruction as the input / output destination address information and the processor to which the firmware is revised has no unprocessed I / O processing instruction. A process of guaranteeing the I / O order for the same input / output destination address until an I / O check end request is notified;
And confirming that there is no longer any I / O processing instruction held by the I / O processing instruction holding means, and executing a revision of the firmware of the processor to which the firmware is to be revised. A firmware active exchange control method for a control device. Multiple processors that process I / O requested from the host device, multiple firmware for operating each processor stored in the memory, and to which processor the I / O request from the host device is distributed I / O control information storage means for storing distribution control information for determining I / O including I / O destination address information to be processed by receiving an I / O request from the host device for each processor A control device comprising I / O processing instruction holding means for holding an O processing instruction until the I / O processing is completed, and executing I / O processing for the lower device in response to an I / O request from the upper device Firmware active exchange control method in
By updating the distribution control information in the I / O control information storage means in response to an external firmware revision instruction, to a state in which the distribution of the I / O request to the processor subjected to the firmware revision is prohibited. , The process of causing other processors to take charge of subsequent I / O requests from the host device,
Executing a revision of the firmware of the processor to which the firmware is to be revised;
When the I / O processing instruction holding means of the processor holds an I / O processing instruction, and performs an interrupt notification for taking over the I / O processing instruction to another processor ;
In response to a notification of an I / O check start request when the firmware is revised, the other processor has the same I / O processing instruction as the I / O to be processed by the own processor and the input / output destination address information. Notification of an I / O check end request to check whether there is an unprocessed I / O processing instruction in the processor subject to firmware revision, and to guarantee the I / O order for the same input / output destination address firmware swapping control method of a control apparatus characterized by having the steps carried out until there is.

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