JP4448917B2 - Semiconductor integrated circuit device, data processing device, and microcomputer - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, a data processing device, and a microcomputer, and particularly to a technology that is effective when used for a high-performance, high-functionality device suitable for a home game machine or a portable information communication terminal device. is there.

There is a single-chip microcomputer in which a central processing unit and peripheral circuits such as a direct memory access control device (DMAC) and various timers are configured in one semiconductor integrated circuit device. As an example of such a single chip microcomputer, there is, for example, “Hitachi Single Chip RISC Microcomputer SH7032, SH7034 Hardware Manual” issued by Hitachi, Ltd. in March 1993.
Hitachi, Ltd., published in March 1993 “Hitachi Single-Chip RISC Microcomputer SH7032, SH7034 Hardware Manual”

  With the progress of semiconductor technology, a large number of semiconductor elements can be formed on one semiconductor substrate. As a result, the peripheral circuit is formed on one semiconductor substrate with the central processing unit as a center, and high performance and multiple functions can be achieved. However, it has been found that if a large number of peripheral circuits are simply built in for high performance and multi-functionality, inconvenience occurs from the viewpoint of operation speed, power consumption, and the like. Further, enhancement of the three-dimensional image processing function is inevitable for future microcomputers.

  One object of the present invention is to provide a semiconductor integrated circuit device, a data processing device, and a microcomputer that realize high performance and high functionality.

  Another object of the present invention is to provide a semiconductor integrated circuit device, a data processing device, and a microcomputer that realize high speed and low power consumption.

  Another object of the present invention is to provide a semiconductor integrated circuit device, a data processing device and a microcomputer which are easy to use.

  Another object of the present invention is to provide a semiconductor integrated circuit device, a data processing device, and a microcomputer that can be accessed by expanding the operation margin of a synchronous dynamic RAM with a simple configuration.

  Still another object of the present invention is to provide a semiconductor integrated circuit device, a data processing device, and a microcomputer capable of performing three-dimensional image processing at high speed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical outline of the invention disclosed in the present application will be briefly described as follows. That is, a central processing unit, a control circuit having an interface function of an externally connected memory, a first clock signal for the central processing unit, and a synchronous DRAM (hereinafter simply referred to as SDRAM) connected to the outside. A clock generation circuit capable of forming a plurality of clock signals including a second clock signal to be supplied to a first clock terminal of the synchronous DRAM, a first terminal for supplying the second clock signal to the clock terminal of the synchronous DRAM, and the synchronization A second terminal for outputting a clock enable signal for the eggplant DRAM and a third terminal for outputting a select signal for the synchronous DRAM are provided. The control circuit outputs the clock enable signal to the synchronous DRAM via the second terminal and the select signal via the third terminal in synchronization with the second clock signal. .

  The SDRAM can be accessed directly by expanding the operation margin.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. In other words, the internal bus is divided into three, a central processing unit is connected to the first bus, a fixed-point product-sum calculator is connected to the first bus, and a fixed-point is connected to the second bus. Connect the system divider.

  According to the above-described means, the product-sum operation processing can be performed at a high speed with a small number of cycles by connecting a fixed-point product-sum operation unit to the first bus, and the second bus has a fixed-point method. Thus, another product-sum calculation process can be performed in parallel with the division process of the calculation result, so that three-dimensional image processing can also be performed at high speed.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, at least one of a free running timer, a serial communication interface, or a watchdog timer is provided as a peripheral module connected to the third bus.

  According to the above-described means, as a peripheral module connected to the third bus, it is not directly involved in speeding up data processing such as a free running timer, a serial communication interface or a watchdog timer, Peripheral modules can be made into a low-speed bus cycle, and existing peripheral modules can be used as they are without following the speedup of the central processing unit, so that design efficiency and power consumption in the peripheral modules can be reduced. .

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, each circuit block is configured by a full static CMOS circuit, and an operation mode controller including a register for controlling supply / stop of a clock pulse is provided for each circuit block.

  According to the above-described means, the clock can be supplied only to the necessary circuit block, so that the power consumption can be reduced.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the external bus interface has an interface function that allows direct access to the burst read mode and single write mode of the synchronous dynamic RAM, the dynamic RAM, and the pseudo static RAM.

  According to the above-described means, since a synchronous dynamic RAM, a dynamic RAM, a pseudo static RAM, and the like can be directly connected by an external bus interface, usability can be improved.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, as the external bus interface, a clock pulse whose phase is advanced with respect to the clock pulse of the central processing unit is formed and supplied to the clock terminal of the synchronous dynamic RAM.

  According to the above-described means, the synchronous dynamic RAM can be accessed by the clock pulse whose phase is advanced with respect to the clock pulse of the central processing unit, so that the operation margin can be expanded.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the data read in the burst mode of the synchronous dynamic RAM, the data of one block of the cache memory, and the unit data transfer by the direct memory access controller are made consistent.

  According to the above-described means, the data read in the burst mode of the synchronous dynamic RAM, the data of one block of the cache memory, and the unit data transfer by the direct memory access control device are made the same data amount, thereby improving the efficiency. Good data transfer is possible.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in the external bus interface, the central processing unit is activated by accessing a specific address space, and both the row address strobe signal, the column address strobe signal and the write enable signal are set to the low level, and a part of the address signal is set. A memory control signal generation circuit for generating a control signal necessary for setting the operation mode setting of the synchronous dynamic RAM is provided.

  According to the above-described means, the mode setting of the synchronous dynamic RAM can be easily performed by the central processing unit.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the cache memory is composed of a plurality of tag memories and corresponding data memories, and the tag memory and the data memory use CMOS static memory cells, and a CMOS as a sense amplifier for amplifying the read signal. A CMOS sense amplifier composed of a latch circuit and a power switch MOSFET composed of a P-channel MOSFET and an N-channel MOSFET for supplying an operating current to the CMOS latch circuit is used.

  According to the above-described means, by configuring the sense amplifier using the CMOS latch circuit, it is possible to reduce the power consumption because the direct current does not flow after the signal amplification.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, only the data memory corresponding to the hit signal from the tag memory is activated.

  According to the above-described means, only the data memory corresponding to the hit signal from the tag memory is activated, so that the power consumption can be reduced.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the plurality of data memories can be directly accessed by the central processing unit by disabling the transmission of hit signals from the tag memory for all or a part by the cache controller.

  According to the above-described means, all or a part of the plurality of data memories of the cache memory can be used as the built-in RAM, so that it can be adapted to usage according to various requests of users.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a single-chip microcomputer including a central processing unit and a cache memory, a CMOS static memory cell is used as a memory element as a cache memory, and a CMOS latch circuit and such a CMOS latch circuit are used as a sense amplifier for amplifying the read signal. A CMOS sense amplifier including a power switch MOSFET including a P-channel MOSFET and an N-channel MOSFET for supplying an operating current is used.

  According to the above means, in a single-chip microcomputer including a central processing unit and a cache memory, after performing signal amplification with the sense amplifier by using a CMOS latch circuit in the amplification section of the sense amplifier of the cache memory, Since no direct current flows, power consumption can be reduced.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, only the data memory corresponding to the hit signal from the tag memory is activated.

  According to the above-described means, in a single-chip microcomputer with a built-in cache memory, it is possible to reduce power consumption by activating only the data memory corresponding to the hit signal.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. That is, when the slave mode is set according to the bus use right control signal, the first terminal is used for the bus request signal, the second terminal is used for the bus acknowledge signal, and when the master mode is set, the first terminal is used. For the bus grant signal, the second terminal is used by switching to the bus release signal.

  According to the above means, one single-chip microcomputer can be used as a slave mode or a master mode according to a bus use right control signal, and the same terminal is switched and used. It becomes simple and easy to use.

  The outline of another representative one of the inventions disclosed in the present application will be briefly described as follows. In other words, the central processing is a coordinate processing that converts a specific object-specific coordinate point to a coordinate with the specified viewpoint as the origin in cooperation with the perspective processing clipping processing and the product-sum calculator in the three-dimensional image processing This is performed by the apparatus, and at the same time, the perspective processing is performed on the coordinates after the coordinate conversion processing is completed by the divider.

  According to the above-described means, while performing the clipping process and the coordinate conversion process of the three-dimensional image process by the central processing unit and the product-sum calculator, the perspective process that spends a relatively long time in parallel with the clipping process and the coordinate conversion process is performed. As a result of using the divider, high-speed three-dimensional image processing can be realized.

  FIG. 1 is a block diagram showing an embodiment of a single chip microcomputer according to the present invention. Each circuit block shown in the figure is formed on a single substrate such as single crystal silicon by a known CMOS (complementary MOS) semiconductor integrated circuit manufacturing technique.

  The single-chip microcomputer in this embodiment is not particularly limited, but realizes high-performance arithmetic processing by a RISC (Reduced instruction set computer) type central processing unit CPU and simultaneously integrates peripheral devices necessary for the system configuration. It is a single-chip microcomputer for the new generation that has achieved low power consumption, which is essential for mobile device applications.

  The central processing unit CPU has a RISC type instruction set, and the basic instruction performs pipeline processing and operates in one instruction and one state (one system clock cycle), so that the instruction execution speed is dramatically improved. Can do. A multiplier MULT is incorporated so that product-sum operation processing indispensable for three-dimensional operation processing as will be described later is performed at high speed.

  An interrupt controller INTC, a direct memory access controller DMAC, a divider DIVU, timers FRT and WDT, and a serial communication interface SCI are incorporated as built-in peripheral modules so that a user system can be configured with the minimum number of parts. Furthermore, an external memory access support function with a built-in cache memory enables direct connection to a dynamic RAM (Latin Dam Access Memory), synchronous dynamic RAM, and pseudo-static RAM without glue logic.

  Centering on the high-speed central processing unit CPU as described above, the peripheral modules provided for high performance, high function, or multi-function can be efficiently used while fully demonstrating its performance and reducing power consumption. In order to operate, the internal bus is divided into three.

  The first bus is composed of an address bus AB1 and a data bus DB1, and is connected to a central processing unit CPU, a multiplier (multiply and accumulate arithmetic unit) MULT, and a cache memory. The multiplier MULT is connected only to the data bus DB1 of the first bus, and operates integrally with the central processing unit CPU to perform multiplication and addition. Therefore, since the first bus (AB1, DB1) is mainly used for data transfer between the central processing unit CPU and the cache memory, it can be called a cache address bus and a cache data bus. The cache memory includes a tag memory TAG, a data memory CDM, and a cache controller.

  The schematic configuration of the central processing unit CPU is as follows. The internal structure is 32 bits. The general-purpose register machine includes 16 32-bit general-purpose registers, three 32-bit control registers, and four 32-bit system registers. The RISC type instruction set uses a 16-bit fixed length instruction to improve code efficiency. By using a delayed branch method for unconditional / conditional branch instructions, pipeline disturbance during branching is reduced. Instruction execution is 1 instruction / 1 state, and at 28.7 MHz operation, it is as fast as 35 ns / instruction. The performance of the central processing unit CPU is determined by the operating frequency and the number of clocks per instruction execution (CPI: Cycles Per Instrument). Of these, it is convenient to set the operating frequency to 28.7 MHz as described above in order to share the clock with the video signal processing system for television when incorporated in a game machine. By the way, when non-interlaced image data is displayed on an NTSC color television, the video signal circuit usually has a color subcarrier frequency (8 times the clock of about 3.58 Mz (28.6 MHz). ).

  In this embodiment, since the central processing unit CPU is connected to the first bus (AB1 and DB1) to which only the cache memory (TAG, CAC, CDM) and the multiplier MULT are connected, the load capacity of the bus is greatly reduced. In addition, it is possible to simplify the bus drive circuit of the central processing unit CPU that performs high-speed operation as described above and to reduce power consumption.

  The second bus includes an address bus AB2 and a data bus DB2, and is connected to a divider DIVU, a direct memory access control device DMAC, and an external bus interface OBIF. At the time of a miss hit in the cache memory, the central processing unit CPU needs to access the external memory to capture data. Therefore, a function for transmitting the address signal of the first bus to the second bus is required. Further, if the first and second buses are separated as described above, there arises a problem that the memory access control device DMAC directly rewrites the contents of the data memory CDM of the cache memory due to a program mistake or the like.

  In this embodiment, the break controller UBC is used to solve the problems such as the miss hit in the cache memory and the data destruction of the cache memory. The break controller UBC is originally used for program debugging or the like. However, utilizing the fact that it is necessary to be connected to the first bus and the second bus, the break controller UBC is provided with a transceiver circuit to prevent a miss hit in the cache memory. Sometimes, the address signal of the first bus is transmitted to the address bus AB2 of the second bus so as to access the external memory. In addition, the address signal on the second bus is monitored, and rewriting is directly monitored on the data memory CDM by the memory access control device DMAC.

  The third bus includes an address bus AB3 and a data bus DB3, and is not particularly limited, but is connected to a free running timer FRT, a serial communication interface SCI, a watchdog timer WDT, and an operation mode controller MC.

  The third bus is delayed in the bus cycle compared to the first and second buses. That is, paying attention to the fact that each of these peripheral modules does not improve the substantial performance and function even if the operation speed is increased, it is mounted on an existing single-chip microcomputer that operates at about 10 MHz. The one that is actually used is used as it is. By doing so, the design efficiency can be improved and the power consumption can be reduced by lowering the operating frequency.

  However, if this is done, data cannot be exchanged with the central processing unit CPU or the like as it is, so a bus state controller BSC is provided. When transferring a signal (data signal) from the third bus to the second bus, the bus state controller BSC transmits the signal as it is. This is because the clock signal used for the third bus cycle is formed by dividing the system clock for determining the first and second bus cycles in the pulse generation circuit CPG. Can be transmitted to the second bus as it is. On the other hand, when the bus state controller BSC transmits the signal of the second bus to the third bus, the signal is delayed and transmitted in synchronization with the third clock pulse as necessary. .

  The outline of the interrupt controller INTC is as follows. The external interrupt has five external interrupt terminals consisting of NMI and / IRL0 to / IRL3 as described later. The 15 external interrupt levels can be set by the / IRL0 to / IRL3 terminals. In this specification and some drawings, / (slash) attached to an alphabetic symbol represents a bar signal whose low level is an active level. In the drawing, according to the conventional description method, the bar signal is provided with a line on the alphabetical signal name or terminal name.

  There are 11 internal interrupt factors: 2 by the direct memory access controller, 1 by the divider DIVU, 3 by the free running timer FRT, 1 by the watchdog timer WDT, and 4 by the serial communication interface SCI. The A vector number can be set for each internal interrupt factor.

  By adopting the bus division method as described above, the length of each bus can be shortened or the number of elements connected thereto can be reduced, so that the load capacity of the bus is greatly reduced, and the central processing unit CPU High-speed data processing becomes possible with low power consumption. Further, when the DMAC is provided as the direct memory access control device in the user break controller, a function of detecting erroneous cache data rewrite by the direct memory access control device DMAC by the above-described bus separation is provided. So reliability is not compromised.

  In addition, if the bus cycle immediately affects the performance or function, such as the central processing unit CPU, cache memory, and direct memory access control device DMAC, it is connected to the bus of the high-speed bus cycle as described above and free. Those whose bus cycle does not directly affect data processing, such as the running timer FRT, serial communication interface SCI or watchdog timer WDT, are intended to be connected to the third bus of the slow bus cycle. . Accordingly, it is not necessary to develop and design a high-speed type peripheral module following the increase in the speed of the central processing unit CPU, and the existing one can be used as it is, so that the design efficiency can be improved. In addition, since the operation clock can be lowered, the power consumption can be reduced.

  2 and 3 show pin arrangement diagrams of a single-chip microcomputer according to the present invention. FIG. 2 shows the left half, and FIG. 3 shows the right half. In order to clarify the relationship between them, the central portion is shown to overlap in FIGS. 2 and 3. In this embodiment, a plastic QFP package having 144 pins is used.

  Typical terminal functions are as follows. In FIG. 2 and FIG. 3, one terminal has a plurality of meanings and is switched according to the operation mode, and is divided by / (slash). In this specification, the meaning of the bar signal is used as described above. Therefore, the symbol “/” in FIGS. 2 and 3 is replaced with “*”.

  As a power supply system, Vcc is a power supply and Vss is a ground (ground potential). For operation mode control, MD0 to MD2 are used to select a clock, MD3 and MD4 are used to specify the bus size of the CS0 space, and MD5 is used to specify a slave / master mode which will be described later. For the address bus, A0 to A26 are address terminals, for the data bus, D0 to D31 are input / output data terminals.

  For bus control, / CS0 to / CS3 are chip select output signals. / BS is a bus start signal. RD * / WR is a read * write signal. / RAS * / CE is a row address strobe signal when a dynamic RAM and a synchronous dynamic RAM are used, and a chip enable signal when a pseudo static RAM is used. / CAS * / OE is a column address strobe signal when the synchronous dynamic RAM is used, an output enable signal and a refresh control signal when the pseudo static RAM is used.

  / WE0 represents the least significant byte write for the basic interface, / WE1 represents the third byte write for the basic interface, / WE2 represents the second byte write for the basic interface, / WE3 represents the most significant byte write for the basic interface, In addition, it is also used as a CAS for selecting each byte when using a dynamic RAM and as a maximum for each byte when using a synchronous dynamic RAM. / RD is a read pulse signal and is connected to the OE terminal of the device. / WAIT is a hardware wait input. / BEN is an external data buffer enable signal, and RD * / WR is used to control the direction of the data buffer.

  / BACK * / BRLS is selectively used as a bus use permission input (bus acknowledge signal) when the slave mode is set by the terminal MD5, and as a bus release request input (bus release signal) when the master mode is set. / BREQ * / BGR is selectively used as a bus use right request output (bus request signal) when the slave mode is set by the terminal MD5, and as a bus use permission output (bus grant signal) when set in the master mode. CKE is a clock enable signal of the synchronous dynamic RAM.

  For resetting, / RESET is a reset terminal. / IRL0 to / IRL3 are interrupt level input signals. NMI is a non-maskable interrupt input, and IVECF is an interrupt vector fetch output.

  For the clock, EXTAL is a crystal input terminal. XTAL is a crystal input terminal * multiplication clock input. CKPACK is a clock pause acknowledge output. CKPREQ is a clock pause request input. CKIO is a clock input / output. CAP1 and CAP2 are PLL capacitor connection terminals. Vss (PLL) and Vcc (PLL) are power supply terminals of the PLL.

  For DMAC, / DREQ0 and / DREQ1 are DMA transfer request inputs and correspond to channel 1 and channel 2. / DACK0 and / DACK1 are DMA transfer acceptance outputs and correspond to channel 1 and channel 2. For SCI, TXD0 is a transmission data output, RXD0 is a reception data input, and SCK0 is a serial clock input / output. For FRT, FTOA is an output compare A output and FTOB is an output compare B output. FTCI is a counter clock input, and FTTI is an input capture input. For WDT, / WDTOVF is a watchdog timer overflow output.

  FIG. 4 shows a block diagram of an embodiment of the operation mode controller MC. The mode control unit is provided with a standby control register, a bus width setting register, and a frequency change register. The output of the bus width setting register is decoded by a combinational logic circuit to form an 8-bit, 16-bit, or 32-bit bus width setting signal, and the bus width is set to the bus state controller BSC.

  The frequency change register decodes the output signal by a combinational logic circuit, forms three control signals of x1, x2, and x4 with respect to the frequency f, and supplies the control signal to the oscillation circuit. Signals input from the mode setting terminals MD0 to MD2 are decoded by a combinational logic circuit to form seven mode setting signals, which are supplied to the oscillation circuit.

  Such clock operation modes include the use / non-use of the built-in oscillation module or the frequency multiplier, selection of clock output / no output, selection of synchronization / non-synchronization by PLL, CPU clock The above seven modes can be set by combining the selection of whether or not to change the phase of the output and the clock input from the outside by 90 °. The operation mode for changing the phase by 90 ° will be described later.

  Each circuit block of this embodiment is composed of a full static CMOS circuit except for a part. Therefore, in a circuit that does not need to operate, the state is maintained even if the clock supply is stopped, so basically the initial settings and necessary data are saved and It is possible to continue the operation from the state before the stop by re-inputting the clock without performing a process such as returning to the state. Since the cache memory constituted by the dynamic CMOS circuit has the clock phase adjusted so that the operation is started from the precharge when the clock supply is started, the cache memory can be accessed immediately after the stop is released.

  The standby control register designates a circuit block that does not need to perform the above-described operation, so that the FRT, WDT, and the DMAC, DIVU, and MULT shown as examples and the one block SYSC are shown. Control circuit STBY, DRTSTP, SCISTP, and MULTTSTP, DIVUSTP, DMACSTP, etc. control signals for stopping the clock input to peripheral modules such as SCI stop the clock input of the corresponding circuit block.

(Table 1)
┌─────┬───┬───┬──────┬───────┬───────┐
│ Mode │ CPG │ CPU │ CPU register │ Peripheral module │ Terminal │
├─────┼───┼───┼──────┼───────┼───────┤
│ Sleep │ Operate │ Stop │ Hold │ Operate │ Hold │
├─────┼───┼───┼──────┼───────┼───────┤
│Standby│Stop │Stop │ Hold │ Stop │ Hold or HiZ│
├─────┼───┼───┼──────┼───────┼───────┤
│Module│Action │Action │ Hold │ Specified │FRT, WDT, │
│Stop │ │ │ │ Things stop │SCI is HiZ │
└─────┴───┴───┴──────┴───────┴───────┘

  Table 1 shows a list of operation modes by the standby control register. In Table 1, HiZ means a high impedance state. When the module stop mode is designated, the clock input of the circuit block by the control signals STBY, DRTSTP, SCISTP, MULTTSTP, DIVUSTP, DMACSTP and the like is stopped.

  A method of canceling the sleep mode in which the central processing unit CPU stops operating is performed by an interrupt, a DMA address error, a power-on reset, and a manual reset. The standby mode canceling method in which the operation of the central processing unit CPU and peripheral modules inevitably stops due to the operation stop of the clock generation circuit CPG is performed by an NMI interrupt, a power-on reset, and a manual reset. On the other hand, the module stop mode is performed by resetting a predetermined bit of the standby control register to 0.

  By providing each mode as described above, only the circuit that needs to supply the clock including the operation of the clock generation circuit itself is supplied inside the single chip microcomputer. It is possible to reduce wasteful current consumption caused by charging / discharging the load capacitance. Thereby, it is possible to achieve low power consumption particularly required for a single-chip microcomputer mounted on a battery-driven portable device.

  FIG. 5 shows a block diagram of a basic embodiment of the break controller UBC. The break controller UBC requests a user break interrupt from the central processing unit CPU according to the contents of the bus cycle generated by the central processing unit CPU or the direct memory access control unit DMAC. By utilizing this function, a self-debugger can be constructed, which facilitates user program debugging. This break controller UBC has two channels, channel A and channel B. Channel B can be broken by designating data.

  BARAH and BARAL and BARBH and BARBL are break address registers for the A channel and the B channel. BAMRAH and BAMRAL and BAMRBH and BAMRBL are break address mask registers for the A channel and the B channel. As a result, it is possible to specify an address at which a break is made in the A channel and the B channel and to make a maximum for each bit.

  BDRBH and BDRBL are break data registers for the B channel. BDMRBH and BDMRBL are break data mask registers for the B channel. As a result, it is possible to specify the data to be broken in the B channel and to set the maximum for each bit.

  BBRA is a break bus cycle register A for the A channel, and BBRB is a break bus cycle register B for the B channel. BRCR is a break control register. As a result, in addition to the above address or data conditions, (1) one or both of the CPU cycle and peripheral cycle, and whether to include the bus cycle outside the chip at the time of bus release, or (2) instruction fetch Breaks can be made by combining conditions such as one or both of data access, (3) one or both of read or write, and (4) operand size (longword, word, byte access).

  FIG. 6 shows a detailed block diagram of an embodiment of the break controller UBC. In this embodiment, the following functions are added to the break controller UBC. As in the embodiment of FIG. 1, the central processing unit CPU, the direct memory access control unit DMAC, and the external bus interface OBIF are separated by bus separation. For this reason, when a miss hit occurs in the cache memory, it is necessary to access the external memory and take in the data.

  The bus transceiver transmits the address signal of the first address bus AB1 to the second address bus AB2 by the control signal C1. That is, when a miss hit occurs in the cache memory, the address signal of the address bus AB1 is transmitted to the address bus AB2 by the control signal C1, and the external memory can be accessed via the external bus interface OBIF. The data read from the external memory at this time is transmitted to the central processing unit CPU via the cache data memory CDM.

  In the figure, the register BARA is a combination of the two registers BARAH and BARAL. Similarly, the other registers BARB and BDRB and the mask registers BAMRA, BAMRB and BDMRB respectively corresponding to the registers BARB and BDRB are obtained by combining the two registers of FIG.

  In this embodiment, a Row address comparator is provided to speed up access to the synchronous dynamic RAM, dynamic RAM, and pseudo-static RAM. When the row address of each RAM is set in the Row address register and the same row address is designated, a hit signal Hit is generated from the comparator and the word line of each RAM is connected via the bus state controller BSC. The high-speed operation is performed by accessing in the selected state.

  As described above, the break controller UBC is connected to the first bus and the second bus, and performs a comparison operation with the address set in the register. Therefore, the address of data stored in the cache memory is set using a comparator and an address register connected to the second bus. In this way, it is possible to monitor the destruction of data caused by the direct memory access controller DMAC erroneously writing to the address stored in the cache memory. In other words, if the internal bus is divided to increase the speed and power consumption of the internal circuit and no allowance is provided as in this embodiment, the cache memory data is destroyed even if the cache memory is destroyed. The processing device CPU cannot be detected, and the system has a serious defect.

  FIG. 7 shows a block diagram of an embodiment of the bus state controller BSC. The bus state controller BSC manages the address space and outputs a control signal through the external bus interface OBIF as necessary so that optimum access is possible in the eight spaces. Thereby, it is possible to directly connect various memories such as a dynamic RAM, a synchronous dynamic RAM, and a pseudo static RAM, and a peripheral LSI.

  The area control unit performs management by dividing the address space into four. In other words, the address space is 4 Gbytes on the architecture, but the memory space is 256 Mbytes. This space is divided into two and one is accessed via the cache memory, and the other is not via the cache memory. The space to be accessed is physically accessed to the same 128 Mbyte space. A 128-Mbyte physical space is divided into four partial spaces (CS0 space to SC3 space), and each space has a maximum linear 32 Mbytes. For each of the spaces CS0 to CS3, designation of a memory type such as a dynamic RAM, a synchronous dynamic RAM, a pseudo static RAM, and a burst ROM can be set. CS0 is designated as normal space and burst ROM, CS1 is designated as normal space, CS2 is designated as normal space and synchronous dynamic RAM, and CS3 is designated as normal space and synchronous dynamic RAM, dynamic RAM and pseudo-static RAM. Can be used.

  The cache control space includes an associative purge space (128 Mbytes) corresponding to the physical space for the cache purge, an address array read / write space (128 Mbytes) for reading and writing the address array (tag address), and a data array. A cache forced read / write space for forcibly reading and writing is provided.

  In addition, the bus width (8 bits, 16 bits, or 32 bits) can be selected for each space. A control signal corresponding to the space can be output. The weight control unit can control insertion of wait states for each space. Also, since the bus cycle differs between the high-speed internal bus (second bus) and the low-speed peripheral bus (third bus), the internal bus signals are transferred when the internal bus signals are transferred to the peripheral bus. When transferring to the bus, a wait is inserted for synchronization.

  In the memory control unit, a refresh function is provided, and CAS before RAS refresh and self refresh are provided. The refresh interval can be set by clock selection of the refresh counter.

  It has an interface that can be directly connected to a dynamic RAM. That is, row address / column address multiplex output, burst transfer at the time of reading, high-speed page mode for continuous access, RAS down mode for non-continuous same row address access, and generation of TP cycle for securing RAS precharge time are possible. Is done. It also has an interface that can be directly connected to a synchronous dynamic RAM. Multiplex output of row address / column address, memory access by burst read and single write, and continuous column access by bank active mode are enabled.

  Generation of a control signal for mode setting for the address strobe signals / RAS, / CAS, synchronous dynamic RAM and dynamic RAM necessary for controlling the dynamic RAM and synchronous dynamic RAM is a memory control signal. This is performed by the generation circuit MCTG. That is, when the area control unit detects that the access is to the space to which the dynamic RAM or the synchronous dynamic RAM is allocated, the control signal is generated accordingly. As described later, when the CPU accesses a specific address, the mode setting for the synchronous dynamic RAM is detected by the area control unit, and the memory control signal generation circuit is activated to control the mode setting control signal. Is generated.

  In the bus usage right controller, the matata / slave mode is switched by the high level / low level input from the terminal MD5. In the master mode, an external bus release request is received by / BRLS and / BGR, and a bus use permission signal is output. In the slave mode, the same terminal is used as / BACK and / BREQ. In other words, a bus use right request signal is output, and the master side bus is accessed in response to the bus use permission signal.

  In FIG. 7, BCR1 and BCR2 provided corresponding to the area control unit are bus control registers. WCR provided corresponding to the wait control unit is a wait state control register. MCR provided corresponding to the memory control unit is an individual memory control register. RTCSR is a refresh control / status register. RTCNT is a refresh timer counter. RTCOR is a refresh time constant register. By reading 1 bit of BCR1, the input value of the terminal MD5 can be read, and the software can be identified as the master mode or the slave mode.

  FIG. 8 is a block diagram for explaining an example of connection between a bus state controller BSC and a synchronous dynamic RAM (hereinafter referred to as SDRAM) by an external bus interface OBIF. The figure also shows a connection example of a static RAM (hereinafter referred to as SRAM) as a basic memory.

  FIG. 9 is a bus cycle waveform diagram for explaining the burst read operation of the SDRAM. Although omitted in the figure, the clock enable signal CKE is set to the high level, and the clock CKIO is input to the SDRAM. The phase of the clock φ of the central processing unit CPU is delayed by 90 ° with respect to this clock CKIO. In other words, when viewed from the central processing unit CPU side, the phase of the SDRAM clock is advanced by 90 °. In order to form a clock having such a phase relationship, in the clock generation circuit, a basic clock having a frequency four times the clock φ is formed by a frequency dividing circuit, and the frequency is divided by ¼. The clock φ is formed, and the SDRAM clock CKIO having a 90 ° phase shift is formed. / BS is a strobe signal for monitoring the bus cycle and is not connected to the SDRAM.

  In the first cycle Tr, the signal / CSn corresponding to the space to which the SDRAM is allocated is set to the low level, the row address strobe signal / RAS is set to the low level, and the row address is captured. In the next cycle Tc1, the column address strobe signal / CAS is set to the low level to fetch the column address. In synchronization with this, / BS is also set to the low level. As described above, in response to the signals / CSn, / RAS, / CAS and the address which are output from the central processing unit CPU side in synchronization with the rising edge of the clock φ, each of the above signals is synchronized with the rising edge of the clock CKIO in the SDRAM. A sufficient operation margin can be ensured by the 90 ° phase shift. That is, the SDRAM can take in an external signal with sufficient setup time and hold time.

  In the third cycle Tc2, / CAS and / BS are reset to high level. Then, data D31 to D0 are continuously read from the SDRAM over the fourth and subsequent cycles of Td1 to Td4. With such burst read, 4 × 4 = 16 bytes of data can be read.

  FIG. 10 is a bus cycle waveform diagram for explaining the single write operation of the SDRAM. In the first cycle Tr, the signal / CSn corresponding to the space to which the SDRAM is allocated is set to the low level, the row address strobe signal / RAS is set to the low level, and the row address is captured. Further, the signal RD * / WR instructing the write operation is set to the low level. In the next cycle Tc1, the column address strobe signal / CAS is set to the low level to fetch the column address. In synchronization with this, / BS is also set to the low level, the data D31 to D0 are taken in, and the selected memory cell is written. Thus, 4 bytes are written in two cycles.

  FIG. 11 is a waveform diagram for explaining the basic bus cycle. By this basic bus cycle, memory access such as the SRAM and ROM is performed. In the basic bus cycle, it is performed by two states such as T1 and T2. In the figure, the case of a read operation by / RD and the case of a write operation by / WEn are shown together.

  FIG. 12 is a block diagram for explaining an example of connection between the bus state controller BSC and a dynamic RAM (hereinafter referred to as DRAM) by the external bus interface OBIF. The DRAM shown in the figure has a × 16 bit configuration, and upper and lower byte accesses can be made by a two-CAS method (/ UCAS * / LCAS).

  FIG. 13 is a bus cycle waveform diagram for explaining the high-speed page mode of the DRAM. In the high-speed page mode, the row address is fixed, in other words, the word line is selected and the column address is sequentially input in synchronization with the column address strobe signal / CAS to read data or Writing is performed continuously. In this case, the row page reset operation can be omitted and the high-speed page mode can be automatically set by the hit signal Hit from the Row address comparator provided in the break controller UBC. A similar operation can be performed in the SDRAM.

  FIG. 14 is a block diagram for explaining an example of connection between a bus state controller BSC and a pseudo static RAM (hereinafter referred to as PSRAM) using an external bus interface OBIF. Single chip microcomputer MCU side output / RAS * / CE is connected to PSRAM chip enable terminal / CE, MPU side output / CAS * / OE is connected to PSRAM output enable * refresh control terminal / OE * / RFSH To do. The PSRAM write enable terminal / WE is connected to the MCU terminal / WEj in the same manner as the SRAM. Then, the MCU terminal / CSn is supplied to the SRAM chip select terminal / CS. That is, the PSRAM is allocated to the CS3 space by the above-described space division, and the SRAM at this time is allocated to the other space.

  FIG. 15 is a block diagram showing an embodiment in which a multiprocessor connection is made using a single chip microcomputer according to the present invention. The single-chip microcomputer MCU of this embodiment can be set to the master mode and the slave mode by inputting a low level / high level to the mode setting terminal MD5. By utilizing this function, one of the same two single-chip microcomputers can be set to the master mode and the other can be set to the slave mode to constitute a multiprocessor system.

  A device in which a high level (“1”) is input to the terminal MD5 is a single-chip microcomputer S-MCU in the slave mode. A device in which a low level (“0”) is input to the terminal MD5 is a master mode single chip microcomputer M-MCU. The master M-MCU is connected to a peripheral LSI such as a main memory via a main bus.

  That is, in a normal microcomputer system, a main bus constructed in the system stores a memory control unit for accessing a high-speed memory such as a main memory or an expansion memory, a DRAM or SDRAM as a main memory, and a basic control program. ROM, a keyboard controller with a keyboard connected to the tip, and the like. Further, a display adapter is connected to the main bus, and a display such as a CRT or LCD is connected to the tip of the display adapter. The main bus is connected to a parallel port, a serial port such as a mouse, a flexible disk drive, and a buffer controller for converting the main bus into a hard disk interface. The expansion RAM and the main memory are connected to the bus from the memory control unit. In the figure, an example in which these are simplified and only SDRAM is provided as the main memory is shown.

  The S-MCU on the slave side is not particularly limited, but a local bus is provided, and a local peripheral LSI such as a local memory is provided as necessary. This local peripheral LSI can be omitted. The address, data, and control signal on the S-MCU side are connected to corresponding signal lines on the main bus side via the bus buffer. Corresponding to the mode setting as described above, a terminal used as / BREQ on the S-MCU side is connected to a terminal used as / BRLS on the M-MCU, and a terminal used as / BGR on the M-MCU side Connected to terminal used as / BACK of S-MCU.

  The signal / BGR output from the M-MCU is also input to the output enable terminal / OE and the gate terminal / G of the bus buffer. As a result, when the S-MCU receives permission to use the main bus, the bus buffer is activated and the address signal of the slave S-MCU is supplied to the main bus side, so that peripheral LSIs on the main bus can be accessed. Made possible.

  At this time, the clock CKIO output from the M-MCU and input to the S-MCU has a phase advanced by 90 ° with respect to the internal clock φ of the S-MCU as in the case of accessing the SDRAM. As a result, the operation margin of signal transmission supplied to the main bus through the bus buffer can be increased. That is, by setting the phase difference as described above, the setup time and hold time of the signal transmitted through the latched bus buffer can be sufficiently secured as in the case of accessing the SDRAM.

  In this embodiment, one single-chip microcomputer can be selectively used as a master mode or a slave mode by mode setting, and the same terminal is used by switching between a master and a slave, so that the number of terminals can be reduced. it can.

  FIG. 16 shows a timing chart when the SDRAM on the main bus is accessed from the S-MCU. When / BREQ is output from the slave side and / BACK is set to low level by the bus use permission signal from the main side, the row address (ROW) and the column address (COLUMN) are output as in the case of accessing the SDRAM. On the master side, the address and command are transmitted with a delay (one clock) output through the latched bus buffer, and the read data is transmitted to the slave side with a delay through the latched bus buffer. .

  FIG. 17 is a block diagram showing one embodiment of a cache memory built in a single chip microcomputer according to the present invention. The figure also shows the central processing unit CPU and the bus state controller. The cache memory of this embodiment executes the output of the corresponding data from the address input in 1.5 cycles. The data replacement algorithm uses an LRU (Least Recently Used) method.

  The circuit configuration of the cache memory is roughly composed of a cache tag (address array), cache data (data array), and a cache controller. The cache tag stores a part of an address called an address tag, and the cache data stores data corresponding to the address tag stored in the cache tag. As a result, when a part of the address stored in the cache tag matches the corresponding address from the central processing unit CPU, a hit signal is output from the cache tag and the cache data selected in parallel is output. The data read from the CPU is taken into the central processing unit CPU. If there is a miss hit, an external main memory is accessed through the break control UBC and the external bus interface.

  In FIG. 17, the cache control register CCR has control bits such as cache enable, instruction fill prohibition, data fill prohibition, two-way mode, and way designation, and is used for setting the operation mode.

  FIG. 20 is a conceptual diagram showing the operation of the cache memory according to the present invention. The address signal is composed of 32 bits A31 to A0. 16 bytes corresponding to 4 bits of the addresses A3 to A0 are taken as one line. A line is a chunk of data associated with one associative address. 64 entries are provided by 6 bits of the address signals A9 to A4. Then, 19-bit address signals A28 to A10 are written in the cache tag as tag addresses. Three bits from the address signals A31 to A29 are used for designating an access space.

  LRU information is provided corresponding to 64 entries of 0 to 63. The LRU information is composed of 6 bits. Information relating to past accesses used for determination of LRU replacement is represented by 6 bits. There are 64 combinations represented by 6 bits, but 24 combinations are used with an initial value of 0. And it is combined so that the least significant bit is used when used as 2 ways. That is, when 2 of the 4 ways are used as the built-in RAM, the way 3 is used for replacement due to a miss hit if the least significant bit is 0, and the way 2 is used if it is 1. . The LRU information in the 4-way mode is rewritten by 24 combinations that satisfy this condition.

  When the tag address read from the cache tag matches the 19-bit address signal consisting of A28 to A10 output from the central processing unit CPU and the valid bit V is 1, a hit signal is output and the cache 16-byte data is read from the data. Of the 16 bytes, 4 bytes (32 bits) are designated by 2-bit addresses A3 and A2 and read to the central processing unit CPU.

  FIG. 18 is a block diagram showing one embodiment of the cache memory according to the present invention. The cache tag includes a decoder, an address array, and a comparator. The address array is composed of four corresponding to the four ways, and the address A9-A4 is inputted, and one of 64 entries is selected. Each entry stores 19 bits corresponding to the address tag, an address signal, and one valid bit. Therefore, the address array corresponding to one way is (19 + 1) × 64. A 6 × 64 LRU information storage unit is commonly provided corresponding to the four ways.

  The latch circuit that holds the address signal by the pulse φ1 is used for storing an address when a miss-hit occurs because the central processing unit CPU outputs the address signal by a pipeline operation. The address tag read from the address array and the 19-bit address signal A28-A10 corresponding to the address input are input to the comparator.

  The hit signals of the four comparators provided corresponding to the four ways are supplied to the cache controller. The LRU information corresponding to the selected entry among the 64 entries is supplied to the cache controller. If a hit signal is not output from the four ways, one way used for replacement is determined by the LRU information. The address tag read from the address array is output as diagnostic data by the selector.

  A 7-bit address signal consisting of the address signals A9 to A3 among the address inputs is input to the decoder of the data array. The data array consists of 32 bits × 2 × 128. Address signal A9-A4 corresponds to the 64 entries, and address signal A3 selects upper 32 × 2 bit data or lower 32 × 2 bit data in one line (32 × 4). Is done. Thus, by making the configuration of the data array vertically long, the number of complementary data lines as will be described later is reduced, and the output of data in units of 32 bits is simplified.

  In this embodiment, although not particularly limited, a hit signal is input from the cache controller to the decoder of the data array. As a result, the power consumption can be reduced by selecting the word line only for the way corresponding to the hit signal in the four ways in the decoder. Further, only the sense amplifier of the data array corresponding to the hit signal is operated. Since the current consumption in the sense amplifier is relatively large, the hit signal may be used only for controlling the sense amplifier. That is, the decoder of the data array sets the word lines of the four ways for high-speed reading, precedes the read operation from the memory cell, waits for the hit signal, and operates the sense amplifier. Reading from the array may be performed at high speed. The 32 × 2 bit data read from the way corresponding to the hit signal is output as 32 bit data through a selector selected by the address signal A2 output through the cache controller.

  The comparator of the address tag is operated by the timing signal φ1, while the output selector of the data array is operated by the timing signal φ2 delayed by a half cycle with respect to the timing signal φ. Therefore, there is no problem even if the data array word line is selected or the sense amplifier is controlled by the hit signal. The aligner provided in the output unit is used when outputting data in units of 8 bits and 16 bits corresponding to the output data width.

  Of the four ways, ways 0 and 1 can be used as the built-in RAM. In this mode, hit signals of address tags corresponding to ways 0 and 1 are invalidated. Access to ways 0 and 1 in this mode is performed by the forced read / write function of the data array. That is, in the forced read / write function, the cache controller selects a way by a selection signal that changes to a hit signal, and reads / writes data.

  When the two ways 1 and 2 are used as the internal RAM as described above, the 6-bit LRU information is written in the same way as the 4-way, but the replacement way is selected only for the lowest 1 bit. Referring to FIG. 4, if it is 0, way 3 is selected, and if it is 1, way 2 is selected. Thus, the replacement algorithm can be simplified by sharing the specific bit of the LRU information in the 2-way mode and the 4-way mode.

  FIG. 19 shows a circuit diagram of an embodiment of the data array. In the figure, two pairs of complementary data lines, two word lines, four memory cells provided at the intersection thereof, output selection thereof, and a sense amplifier are exemplarily shown as representatives. In the figure, a P-channel MOSFET is distinguished from an N-channel MOSFET by adding an arrow to the channel portion.

  As representatively, as an example, a circuit symbol is attached to the element, the input and output of the two CMOS inverter circuits composed of the P-channel MOSFETs Q1 and Q2 and the N-channel MOSFETs Q3 and Q4 are cross-connected to each other to latch the circuit. It is said. N-channel transmission gate MOSFETs Q5 and Q6 are provided between the pair of input / output nodes of the latch circuit and the complementary data lines DL0 and / DL0. The gates of these transmission gate MOSFETs Q5 and Q6 are connected to the word line W0. Other memory cells are also constituted by the same CMOS static memory cells as described above.

  The complementary data lines DL0, / DL0 are provided with N-channel type precharge MOSFETs Q7, Q8. A precharge signal PC is supplied to the gates of these MOSFETs Q7 and Q8. An equalizing CMOS switch is provided between the complementary data lines DL0 and / DL0. The CMOS switch includes an N-channel MOSFET Q9 and a P-channel MOSFET Q10 connected in parallel. A data line equalize signal DEQ is supplied to the gate of the N-channel MOSFET Q9, and the signal DEQ is supplied to the gate of the P-channel MOSFET Q10. Is inverted and supplied by the inverter circuit N1. The equalize MOSFET may be composed of only an N channel type MOSFET or a P channel type MOSFET.

  The two pairs of complementary data lines DL0, / DL0 and DL1, / DL1 are connected to one sense amplifier through a CMOS switch. That is, the data line DL0 is common through the N-channel MOSFET Q11 and the P-channel MOSFET Q13 connected in parallel, and the data line DL1 is also common through the N-channel MOSFET Q16 and the P-channel MOSFET Q18 connected in parallel. Connected to data line CDL0. The data line / DL0 is common via an N-channel MOSFET Q12 and a P-channel MOSFET Q14 connected in parallel, and the data line / DL1 is similarly shared via an N-channel MOSFET Q17 and a P-channel MOSFET Q19 connected in parallel. Connected to data line / CDL0. These CMOS switches are supplied with a selection signal SEL in an intersecting manner, whereby either one of the complementary data lines DL0, / DL0 or DL1, / DL1 is selected. The signal SEL is formed by the address signal A2, for example.

  The common data lines CDL0, / CDL0 are connected to the input of a sense amplifier composed of a CMOS latch circuit. The sense amplifier is formed into a latch circuit by cross-connecting the inputs and outputs of two CMOS inverter circuits composed of P-channel MOSFETs Q22 and Q23 and N-channel MOSFETs Q24 and Q25. An operating voltage VCC is applied to the sources of the P-channel MOSFETs Q22 and Q23 via a P-channel switch MOSFET Q26, and the sources of the N-channel MOSFETs Q24 and Q25 are connected to an N-channel switch MOSFET Q27. Circuit ground potential. A sense amplifier operation signal / SAC is supplied to the gate of the P-channel MOSFET Q26, and a sense amplifier operation signal SAC is supplied to the gate of the N-channel MOSFET Q27.

  An equalizing N-channel MOSFET Q20 and a P-channel MOSFET Q21 are provided in parallel on the common data lines CDL0 and / CDL0 which are the inputs of the sense amplifier. A sense amplifier equalize signal SEQ is supplied to the gate of the N-channel MOSFET Q20, and the signal SEQ is inverted and supplied by the inverter circuit N3 to the gate of the P-channel MOSFET Q21. Since the sense amplifier of this embodiment is constituted by a latch circuit having a high sensitivity and a positive feedback loop, the input levels are matched by the equalize MOSFETs Q20 and Q21 before the operation is started by the signals / SAC and SAC. When the potential difference between the common data lines CDL0 and / CDL0 has a predetermined potential according to the stored information from the selected memory cell, it is amplified by the signal signals / SAC and SAC, and the common data line CDL0 is amplified. And / CDL0 is amplified to high level / low level. These signals are output through a read path (not shown). The equalizing MOSFET may be composed of only an N channel type MOSFET or a P channel type MOSFET.

  When the CMOS latch type sense amplifier as described above is used, when the potentials of the common data lines CDL0 and / CDL0 become high level / low level by the amplification operation, a steady DC current does not flow in the CMOS latch circuit. Therefore, low power consumption can be achieved. If the sense amplifier operation signals SAC and / SAC are generated by the hit signal as described above, only the sense amplifier corresponding to one of the four ways operates, and the current consumption Can be greatly reduced to about 1/4.

  The common data lines CDL0 and / CDL0 are connected to a write amplifier via N-channel MOSFETs Q28 and Q29 that are switch-controlled by a write selection signal WS. The write amplifier is composed of inverter circuits N4 to N7, and an output signal of the CMOS inverter circuit N4 receiving the input data D0 is made a complementary write signal through the driving inverter circuit N7, the inverting inverter circuit N5, and the driving inverter circuit N6. This complementary write signal is transmitted to the common data lines CDL0 and / CDL0 through the switch MOSFETs Q28 and Q29.

  As described above, the data array of one way is provided with 32 sets of one sense amplifier and one write amp for the two pairs of complementary data lines as described above. As a result, the memory array section is composed of 32 × 2 complementary data lines and 128 word lines, and 32-bit data is input / output.

  FIG. 21 is a block diagram showing one embodiment of the direct memory access control device DMAC incorporated in the single chip microcomputer according to the present invention. In this embodiment, two channels, CH0 and CH1, are provided. Two circuit blocks are provided corresponding to the channels CH0 and CH1, respectively. Numbers 0 and 1 attached to the symbols of the circuit blocks are circuits corresponding to the channels CH0 and CH1.

  The circuits provided corresponding to the two channels CH0 and CH1 as described above are as follows. SAR0,1 are source address registers. Each of these SAR0 and 1 consists of 32 bits, and the start address of the DMA transfer source is set. These SARs 0 and 1 always hold the next transfer address value in accordance with an address calculation condition set separately during operation or after the end of transfer.

  DARs 0 and 1 are destination address registers. Each of these DARs 0 and 1 is made up of 32 bits, and a DMA transfer destination start address is set. These DARs 0 and 1 always hold the next transfer address value in accordance with an address calculation condition set separately during operation or after completion of transfer.

  TCR0,1 are transfer count registers, each of which is made up of 32 bits, and the DMA transfer count is set, and the remaining transfer count is held during operation or after the transfer is completed. To be. When all zeros (all "0") are set, it is 2 24 times (maximum transfer count). VCRs 0 and 1 and VCRs 2 and 3 are vector registers each corresponding to two channels CH0 and 1. Each of the VCR0 to VCR3 is composed of 8 bits, and an interrupt vector address of the DMAC is set. Setting is performed from the central processing unit CPU, and the central processing unit CPU performs vector fetch when an interrupt occurs.

  The following circuit blocks are common to the channels CH0 and CH1. DMAOR is a DMA operation register, and CHCR0 and CHCR0 are channel control registers provided corresponding to the DMAOR. AU is an address calculator, and DEC is a decrementer with an all-zero detector. MDB0 to MDB3 are 4-stage data buffers for 128-bit transfer. Data transfer corresponding to one line of the cache memory is performed by the data buffers MDB0 to MDB4, and data transfer of 4 cycles × 32 bits is performed to the SDRAM by burst read. In addition to the above, DMA request / select registers 0 and 1, a transfer sequence control circuit, a host interface, a priority control circuit, and the like are provided.

  As described above, the consistency between the number of unit data of the cache memory, the number of read data by the burst read of the SDRAM, and the data buffer of the DMAC makes it possible to connect between the SDRAM by the DMAC and another memory or peripheral LSI. Data transfer can be performed efficiently.

  FIG. 22 is a schematic block diagram showing one embodiment of the DMAC and its peripheral part according to the present invention. It is connected to the internal bus B2 of the single chip microcomputer according to the present invention. Although not shown in the figure, the data between the external memory connected to the external bus B4 via the interface OBIF and the cache memory and the peripheral modules provided in the bus B2 is omitted. Perform the transfer.

  The address mode includes a dual address mode and a single address mode. In the dual address mode, the access of the transfer source and the transfer destination is divided into two bus cycles, and an address is output for each of them. In the single address mode, the external memory is addressed and the external I / O device is accessed by the / DACK signal and DMA transfer is performed in one bus cycle.

  The bus mode includes a cycle steal mode and a burst mode. In the cycle steal mode, the bus right is released after the completion of one word DMA transfer, and the bus right is transferred to another bus master. In the burst mode, when the bus right is acquired, the transfer continues continuously until the transfer end condition is satisfied. However, when the / DREQ terminal is sampled at a level in the external request mode, transfer is performed according to the terminal.

  Transfer requests include external requests, requests from built-in peripheral modules, and auto requests. An external request can activate channel CH0 with the / DREQ0 terminal and channel CH1 with / DREQ1. The sampling of the / DEQ0,1 terminal can select the falling edge and the level. The request from the built-in peripheral module includes the built-in SCI0 reception data full and the built-in SCI transmission data line empty. These requests are automatically cleared by initiating a DMA transfer cycle. The auto request starts a transfer operation by setting the DE bit of the channel control register CHCRn (0, 1) of the DMAC.

  When the DMAC has a transfer request for a plurality of channels simultaneously, the transfer channel is determined according to the priority order. The priority includes a fixed priority mode and a change mode. In the priority order fixed mode, the priority order between the channels does not change. Two channels, 1 or 0, can be fixedly prioritized. In the alternate mode, the priority order is changed between the channels CH0 and CH1, and the timing of changing the priority order is the end of one transfer unit (byte or word) in the transfer of the channel CH0 or the channel CH1 in the round robin method. It is said that when you did.

  FIG. 23 shows a block diagram of an embodiment of the divider DIVU. The divider DIVU of this embodiment can perform a signed 64-bit / 32-bit or 32-bit / 32-bit division to obtain a 32-bit quotient and a 32-bit remainder. When an overflow or underflow occurs in the operation, an interrupt can be generated for the central processing unit CPU as specified.

  In the figure, JR is a divisor register, HRL 32 is a 32-bit dividend register L, HRH is a multiplicand register H, and HRL is a dividend register L, and a 64-bit multiplicand can be input together. . BAR is a remainder register and BSR is a quotient register. CONT is a control register, and VCT is an interrupt vector register. When the dividend and divisor are set from the central processing unit CPU, the multiplier DIVU of this embodiment starts division and automatically calculates the quotient in BSR and the remainder in BAR in approximately 37 cycles. finish. If an overflow or underflow occurs, an internal interrupt signal is generated as specified.

  The multiplier DIVU performs division for about 38 cycles while being disconnected from the internal bus B2. Therefore, the central processing unit CPU or the like can perform data processing using the internal bus in parallel.

  FIG. 24 is an explanatory diagram for explaining the concept of 3D image processing for displaying a 3D object on a 2D display screen by perspective. The figure shows an example of displaying an ancient Greek-style temple on a two-dimensional screen.

  Points p1, p2, etc. that specify the temple have coordinates of x1, y1 and z1, x2, y2, z2 with respect to the origin of the temple. First, the data processing is performed by using the coordinates corresponding to the new directions X ′, Y ′, and Z ′ axes with the unique coordinates of the points p1, p2, etc. specifying each temple as the origin. To change. This is the coordinate conversion process. In other words, the coordinates of each point that identifies the temple are replaced with relative coordinates corresponding to the position at which the temple is viewed from which angle.

(Formula 1)
┌─T00 T01 T02 T03 ─┐
│ T10 T11 T12 T13 │
[x1 ', y1', z1 ', 1] = [x1, y1, z1,1] │ │
│ T20 T21 T22 T23 │
└─T30 T31 T32 T33 ─┘

  In the above formula 1, x1 ′, y1 ′, z1 ′ are the transformed coordinates of the temple point p1, and x1, y1, z1 are the coordinates corresponding to the unique origin of the temple. From the determinant of the above equation 1, it can be obtained by a product-sum operation such as x1 ′ = x1 · T00 + y1 · T10 + z1 · T20 + 1 · T30. Similarly, y1 ′ = x1 · T01 + y1 · T11 + z1 · T21 + 1 · T31 is obtained, and z1 ′ = x1 · T02 + y1 · T12 + z1 · T22 + 1 · T32 is obtained.

  As described above, the coordinate transformation point p1 is transformed as p1 ′, and then the coordinate coordinates x1 ″ and y1 ″ of the intersection point where the straight line connecting the point P and each coordinate p1 ′ intersects the display screen S are displayed on the display screen S. The top point. For this reason, the coordinates x1 ″ and y1 ″ are obtained from the ratio of the distance between the two-dimensional screen S with respect to the origin P and the relative coordinates p1 ′ of the temple. Therefore, the perspective processing for obtaining the coordinates on the display screen is performed by division processing.

  The coordinates on each two-dimensional screen obtained as described above are determined whether the coordinates are inside or outside the screen S, and if two points are inside the screen S, they become a straight line connecting them, When one point or both are off the screen, whether or not the line passes through the screen S depending on whether there are points on the upper, lower, left, and right four screens or the diagonally upper and lower four screens centering on the screen S A straight line corresponding to the point deviating from the screen is drawn. Such a process is called a clipping process. Clipping is a process for determining whether or not there are points in a total of eight screens in the vertical and horizontal directions and diagonally up and down with the screen S as the center. The plane is separated from the points x1 ″, y1 ″ and the like obtained by division. This is executed by repeating the comparison between the X and Y boundary addresses.

  The division performed by the digital circuit is performed by repeating the subtraction. Therefore, the division operation time is inevitably long. That is, if the conversion process, the perspective process, and the clip process are sequentially performed as in the conventional case, when a moving image consisting of 60 images per second is drawn, only a moving image that is about an animation can be drawn with a conventional microcomputer. Can not. When drawing a stereoscopic image, the curved surface is expressed by a combination of triangles, and the density of the video signal that can be expressed in proportion to the number of triangles that can be drawn in 1/60 second is determined. In a conventional high-speed microcomputer that operates with a high-frequency clock such as 28.7 MHz, when the clipping process is omitted, the number of triangles that can be drawn at 1/60 is about 500 to 900. It is said that the number of triangles is about 500, and a planar moving image about animation can be drawn.

  FIG. 25 is a signal processing diagram for explaining the three-dimensional image processing method using the single chip microcomputer according to the present invention. In the figure, the three-dimensional image processing is divided into coordinate conversion processing, perspective processing, and clip processing, and the relationship with each circuit block that processes them is shown in time series.

  In this embodiment, the perspective processing that takes the most time in the image processing, the coordinate conversion processing, and the clipping processing are performed in parallel. However, as for the order of processing, focusing on one point as described above, since parallel processing is not performed, the clip processing is performed with a delay of one as follows.

  The central processing unit CPU and the multiplier MULT perform coordinate conversion processing using a product-sum operation command. When the central processing unit CPU fetches and decodes the product-sum command, it is transmitted to the multiplier MULT to execute the operation, and the data multiplied by the previous data is added and held in the register of the multiplier MULT. Thereby, a determinant product-sum operation process for the coordinate conversion is performed. While the coordinate conversion is performed on the n-th point by the central processing unit CPU and the multiplier MULT, the divider DIVU performs the perspective processing of the previously processed coordinate n-1 in parallel at the same time. To be.

  When the n-th coordinate conversion process is completed, the central processing unit CPU accesses the divider DIVU, fetches the result, and instructs the perspective process for the n-th coordinate after the conversion. As a result, the divider DIVU receives the nth coordinate data and starts the division operation. In parallel with the perspective processing for the n-th point by the divider DIVU, the central processing unit CPU performs the clipping process for the (n−1) -th point for which the perspective processing has been completed. Since this clipping process consists of data size comparison as described above, the above clipping process is performed by the comparison function built in the central processing unit CPU.

  When the clip process is finished for the (n-1) th point, the central processing unit CPU and the multiplier MULT perform a coordinate conversion operation for the (n + 1) th point. Hereinafter, by repeating the same operation, the coordinate processing by the central processing unit CPU and the multiplier MULT and the clipping processing by the central processing unit CPU can be performed simultaneously and in parallel with the perspective processing by the divider DIVU. The most time-consuming perspective processing can be eliminated. The divider DIVU provided in the single-chip microcomputer of this embodiment spends about 38 cycles for one division. On the other hand, in the coordinate transformation described above, the sum of products is performed four times for each point of x, y, and z, and each is calculated in a pumpline manner. Further, since the clip process is a comparison of the magnitudes of 8 times, it almost coincides with the above division process in terms of time.

  In this embodiment, a product-sum operation with a fixed point is performed. Corresponding to this, the division operation also performs division by the fixed point method. In this way, when the fixed-point method is adopted, there is no accuracy compensation, but the normalization processing necessary for the floating-point method can be omitted, so that the speed of multiplication and division can be increased. With regard to accuracy, treatment can be performed by software. That is, it is not an exaggeration to say that a division operation in the microcomputer is not necessary other than the perspective processing in the three-dimensional image processing. Therefore, in the single chip microcomputer of this embodiment, the system is configured on the assumption of the most frequently used three-dimensional image processing.

  A system in which the single chip microcomputer of this embodiment is operated at 28.7 MHz as described above, and three-dimensional image processing is performed in parallel with the coordinate conversion and clip processing as described above in parallel with them. By taking it, the number of triangles that can be drawn in 1/60 second can be greatly improved to about 2400. This value means the ability to draw a moving image close to a live action on the screen.

  The above numerical value (about 2400) shows the case where there is no clip processing as described above. In the three-dimensional arithmetic processing method of this embodiment, even if clip processing is included, time is spent on far-reaching processing as compared to coordinate conversion processing, so that most of the clipping processing can be assigned to the difference time. The processing capability is only slightly reduced compared to the case where there is no processing. On the other hand, in the conventional method in which the coordinate conversion, the perspective processing, and the clip processing are performed in the order, the number of triangles that can be reliably processed is reduced by the time required for the clip processing. For this reason, when the 3D image processing method according to the present invention is compared with the 3D image processing method using a conventional microcomputer including the clip processing, the difference in processing capability is further increased.

  In the three-dimensional image processing system according to the present invention, in the single chip microcomputer as shown in FIG. 1, the divider may be connected to the same first bus as the multiplier. Further, the bus configuration may be configured by one bus other than the one that divides the bus as described above. Alternatively, the divider may be provided as an external LSI. Thus, the microcomputer system used for the above three-dimensional image processing can take various embodiments. The multiplier and divider may be of a floating point type.

  When the single-chip microcomputer according to the present invention is used in a consumer game machine, it is predicted that the program capacity will increase with the advancement of graphics processing and the program capacity will reach several megabytes. Even for instructions and data that are frequently accessed, the built-in ROM / RAM and built-in cache memory do not have sufficient capacity. For this reason, the speed of the external memory interface greatly affects the performance.

  Therefore, in the single chip microcomputer according to this embodiment, as described above, the average access time is shortened by combining the synchronous DRAM and the 4-way set associative cache having a capacity of 4 Kbytes. It is. The built-in cache memory can also function as a RAM as described above.

  The 4-way set associative is a cache mapping method in which there are four entries that can be stored in the cache memory for data at a certain address. In direct mapping, an entry to be stored for an address is uniquely determined. A full associative can store all entries. In the set associative, there are entries that can be stored in the number of ways. As the direct mapping, set associative, and full associative become, the replacement of the cache memory reduces the probability that an entry with a high probability of being accessed in the near future is evicted from the cache. A fully associative cache address array must use an associative memory, whereas a direct mapping and set associative address array can be implemented with a combination of normal memory and comparison circuitry.

  Consumer game machines and portable information communication devices are cheaper in product unit price than personal computers and workstations. For this reason, in a single-chip microcomputer used for a home game machine or the like, not only the price of the chip itself but also the peripheral circuits to be externally attached need to be inexpensive. In order to reduce the average access time (average time until the CPU obtains desired data) at low cost, the cache memory is incorporated as described above.

  When the clock frequency of the central processing unit CPU is 28.7 MHz as described above, the time required for one cycle is 35 ns. For this reason, continuous access for each cycle is not possible in the DRAM high-speed page mode with a RAS access time of 60 ns. One cycle can be extended to 70 ns if the DRAM has a two-way interleave configuration and is accessed alternately in the high-speed page mode. However, it is difficult to design the timing of the data buffer that avoids the collision of data read alternately from the two ways. In addition, considering the delay in the data buffer, continuous access for each cycle is practically impossible.

  Therefore, in a single-chip microcomputer, if the width of the external data bus is 64 bits, it can be directly connected to a main memory having a two-bank configuration, and a data buffer becomes unnecessary. On the other hand, the number of pins increases and the package cost increases. In addition, the chip area may increase due to restrictions on the bonding pad spacing. For this reason, reducing the average access time using a fast page mode DRAM has a significant adverse effect. If SRAM is used, continuous access for each cycle is possible, but it is not worth the cost. In order to reduce the average access time at a low cost, it is most appropriate to use a built-in cache memory as in the above embodiment.

  The effectiveness of the built-in cache memory was examined through simulations on the cache miss rate and average access time. In the single-chip microcomputer according to the present invention, in order to reduce the power consumption by reducing the bus drive as much as possible, the structure in which the access to the internal cache memory and the access to the main memory are started in parallel is not adopted. Then, access to the main memory is started after a cache miss is found. Since the access to the internal cache memory and the access to the main memory are not started at the same time, the cache search time becomes an overhead when a cache miss occurs. This leads to an increase in average access time. When the miss rate is high, there is a risk that the average access time is increased due to the overhead as compared with the case where the cache memory is not provided.

  Since there is no game program trace data, the following data (Smith AJ, “Line (Block) Size Choice for CPU Cache Memories,” IEEE Trans. On Computers, vol. 36, no. 9, Sep. 1987, pp. 1063-1075). FIG. 26 to FIG. 28 are characteristic diagrams showing the relationship between the line size and the miss rate when the miss rate and capacity of the instruction / data mixed type cache memory are changed.

  The line size is a unit for storing data in the cache memory, and is also called a block size. In order to enable partial writing, if no valid bit is provided for each byte, word or long word in the line, valid data must be stored in all lines. Replacement at the time of a cache miss needs to be performed in units of lines. For this reason, if the line size is increased, the time required for replacement increases.

  In the single-chip microcomputer according to the present invention, as described above, it takes one cycle for internal cache memory access and two cycles for external memory access (when the cache line size is 4 bytes). If the miss rate exceeds 50%, the average access time becomes 2 cycles or more, which is rather slow.

  Due to the chip size limitation, the area that can be allocated to the cache memory is about 4 Kbytes. As shown in FIGS. 26 to 28, if the cache capacity is 4K bytes, even if the line size is as small as 4 bytes, the miss rate is 33% or less and the cache memory is effective.

  Like the single-chip microcomputer according to the present invention, the architecture of a 16-bit fixed length RISC microcontroller is expected to have a smaller code size than a 32-bit fixed length RISC processor. When the same number of instructions are executed when the code size is small, the number of fetched bytes is reduced and the cache memory miss rate is lowered.

  Actually, even if the 32-bit RISC architecture is changed to 16 bits, the code size does not become 1/2. Since the range of values that can be incorporated into the instruction as immediate data is reduced, it is necessary to use a plurality of instructions in order to set a constant having a large value. Since the number of bits as the instruction code is insufficient, there is a case where one instruction becomes two instructions in order to change the three operand address to two addresses. In addition, since there are not enough designated bits in the register, the number of registers must be reduced from 32 to 16, and an instruction for saving and restoring the register may be added.

  Therefore, in order to verify these, the code size generated for the single-chip microcomputer according to the present invention was examined. As a result, Drystone was 968 bytes, SPECint benchmark li was 33,042 bytes, and SPECint benchmark eqntott was 6, It was 992 bytes. In the case of a 32-bit fixed length RISC processor, they are 1,680 bytes, 51,440 bytes, and 10,832 bytes, respectively, which are 55 to 74% higher than the 16-bit fixed length.

  According to Bunda J. and Athas W., "16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors," ISCA'20 Proceedings, May 16-19, 1993, pp. 237-246 When a certain DLX is converted to 16 bits, the code size is reduced to 2/3 and the number of executed instructions is increased by 15%, but the instruction transfer amount is reduced by 35%. Further, it has been reported that the performance improvement by the 16-bit conversion is more remarkable when a low-speed memory is connected.

  As described above, the cache memory built in the single-chip microcomputer according to the present invention employs the instruction / data mixed type 4-way set associative system. The line size is 16 bytes considering direct connection with the synchronous DRAM. There is only one access path between the CPU and the cache memory, and a Harvard architecture that uses different access paths for instructions and data is not used. As in the previous embodiment, if one access path is used, instruction fetch and data access cannot be processed with the same clock, but this problem can be solved by placing it at the appropriate address of the instruction with data access. Can be avoided.

  That is, since the instruction has a fixed length of 16 bits, when the memory is accessed in units of 32 bits, only one instruction fetch is required for every two instructions. Therefore, as shown in FIG. 29, when an instruction involving loading and storing from the memory is placed at the even word boundary (address 4n), instruction fetch and data access do not compete even if there is only one access path. In this way, by using one access path, the degree of freedom of the cache configuration can be increased. That is, any of an instruction / data mixed type cache, an instruction / data separation type cache, and an instruction or data only cache can be realized.

  In FIG. 29, an address for storing an instruction is set to an appropriate value so as to avoid contention with memory access. Instruction fetch is performed in units of 32 bits. If an instruction with memory access is placed at address 4n, instruction fetch at 4n + 6 and memory access do not overlap. When placed at address 4n + 2, they overlap, causing a pipeline stall. Execution of instructions after address 4n + 4 must be delayed by one cycle.

  A comparison between the instruction / data mixed type and the instruction / data separation type is as follows. This is because the instruction-only cache and the data-only cache can be realized by changing the replacement logic of the instruction / data mixed type cache.

  As shown in FIG. 26, the miss rate of the instruction / data mixed type cache having the capacity of 4 Kbytes is 12% when the line size is 16 bytes. In the case of a separate type in which a 2 Kbyte cache is prepared for each instruction and data, as shown in FIGS. 27 and 28, the instruction miss rate is 15% and the data miss rate is 12%. Further, instruction fetch is more frequent than data access, has a large effect on CPI, and wants to reduce the instruction miss rate as much as possible. Therefore, an instruction / data mixed type cache memory is used.

  The 4-way set associative was decided in consideration of the trade-off between error rate, power consumption, and chip area. In the direct mapping method, when the cache capacity is small, thrashing frequently occurs depending on the program, and there is a high possibility that cache misses will continue. Although it is possible to avoid thrashing by adjusting the address where instructions and data are stored, tuning at the assembler level is required. The development method of writing individual programs in C language and collecting them with the linker is not suitable for the times. Further, the full associative cache memory has a problem that the chip area increases and the power consumption is large.

  Therefore, as a result of examining the set associative method, it is as follows. If the cache capacity is 4 Kbytes, increasing the number of ways up to 4 ways will greatly reduce the miss rate. On the other hand, the difference between 4-way and 8-way is as small as 0.2%. In order to further reduce the miss rate, the use of LRU as a line replacement algorithm was also examined. However, in 8-way, 28-bit LRU information must be prepared for each entry. 5% of the total cache memory is occupied by LRU information, which affects the cost. Incidentally, in the case of 4 ways as in this embodiment, the LRU information only needs 6 bits, so the ratio to the whole can be reduced to 1%.

  The interface circuit with the synchronous DRAM provided in the single chip microcomputer according to the present invention is for shortening the time required for line replacement at the time of a cache miss. The replacement of a line that takes 8 cycles with an existing DRAM becomes 6 cycles when a synchronous DRAM is used.

  As shown in FIG. 30, if the line size is too large, the average access time is increased. If the line size is increased to some extent, the miss rate of the cache memory is lowered, so that the average access time is shortened. If the value is too large, the time required for data transfer from the external memory becomes long, and the average access time increases. In the figure, the CPU operating frequency is 28.7 MHz, the SRAM access time is 60 ns, and the DRAM access time is 70 ns. An example is shown in which the cycle time of the DRAM high-speed page mode is 45 ns, and the synchronous DRAM has a maximum operating frequency of 66 MHz.

  If the cache memory capacity is the same, the cache memory miss rate will be lower if the line size is increased to some extent. This is because replacement is performed in units of lines at the time of a cache miss, and the same effect as cache memory prefetching can be expected. Therefore, it is better to increase the line size until the line size becomes too large and the number of entries is insufficient. However, just increasing the line size and lowering the miss rate does not necessarily lead to a reduction in average access time. This is because, once a mistake is made, the time required for line replacement increases as the line size increases.

  The single-chip microcomputer according to the present invention stops executing instructions until the line replacement is completed. This is because accessing the cache during line replacement requires complex control. In order to reduce CPI, we want to replace the line as quickly as possible. Therefore, a memory having a high transfer rate of data (block data) corresponding to the line size is required, and high-speed page mode DRAM, synchronous DRAM, and Rambus-compliant DRAM were examined.

  Among them, the synchronous DRAM and the Rambus-compliant DRAM adopt a method in which one row is collectively read out to a buffer in the chip, and then sequentially transferred in synchronization with a clock input. The second and subsequent data can be transferred without being restricted by the internal operation of the memory. Rambus compliant DRAMs can transfer data in cycles up to 2 ns. However, Rambus-compliant DRAMs have different signal levels from existing CMOS chips. The ROM and peripheral I / O cannot be directly connected to signal pins. Although the signal level of the input / output interface of the single-chip microcomputer according to the present invention can be adjusted to the Rambus-compliant DRAM, there is a problem that the versatility is lost at present.

  In the single chip microcomputer according to the present invention, the cache memory is accessed in units of 32 bits. Even if a Rambus-compliant DRAM is operated with a clock faster than the operating frequency of the CPU to capture data, it cannot be directly written into the cache memory. Therefore, a buffer is required in the chip, resulting in an increase in cost. In the DRAM of the high-speed page mode, the block transfer speed cannot be improved greatly because the cycle time of the CAS signal for selecting the column address becomes a bottleneck.

  The synchronous DRAM has a maximum data transfer speed of 16 ns / cycle, but the signal level is the same LVTTL as that of the memory having a power supply voltage of + 3.3V. Signal pins other than the control signal can be directly connected to the peripheral circuit. Since only the rising edge of the clock is used, there are less restrictions on the clock.

  In the single chip microcomputer according to the present invention, an interface with a synchronous DRAM is incorporated from the above examination. When the synchronous DRAM is in a bank active state corresponding to the RAS access of the high-speed page mode DRAM, the row address cycle can be omitted. It is possible to shorten the first access time. Further, the inside is divided into two banks, and a bank active state can be set for each independent row address. When an instruction is placed at a lower address in the memory and data is placed at a higher address, there is a high probability that the access time can be shortened even if instructions and data accesses are mixed. This is one of the reasons for adopting the synchronous DRAM interface.

  As a result of considering the use of the synchronous DRAM, the line size of the cache memory is 16 bytes, and the average access time is 1.72 cycles from FIG.

  In the single-chip microcomputer according to the present invention, in order to simplify the control of the cache memory, the write-through method is adopted for data writing. This is because the copy-back method is said to have a higher miss rate than the write-through method.

  However, with the write-through method, an overhead occurs when writing to the main memory. This is because the existing synchronous DRAM has the same transfer block size at the time of reading and writing. Even when data of one word (4 bytes) is written, a write operation for one line (16 bytes) must be performed. A cycle occurs from 3 cycles for each writing. In the synchronous DRAM, the next access can be forcibly started in the middle of the block access, but the interface circuit becomes complicated.

  Therefore, in the synchronous DRAM as shown in FIG. 8 or the like connected to the single chip microcomputer according to the present invention, reading is performed in units of blocks, but writing can be performed in units of words. -It has a light function.

  The single-chip microcomputer according to the present invention is directed to the use of portable information communication equipment in addition to home game machines. Since these devices are carried outdoors and used for battery operation, it is necessary to reduce the power consumed by the microcontroller as much as possible. It is necessary to suppress heat generation in order to fit in a low-priced plastic package.

  In order to reduce the power consumption in the cache memory, as shown in FIG. 31, the address array and the data array are operated with a ½ cycle shift, and based on the comparison result of the address array, four ways Only the sense amplifier of the hit way in the data array is moved. This figure corresponds to FIG.

  FIG. 32 shows the operation timing of the cache memory according to the present invention. In order to reduce the power consumption of the entire chip, the word line control is devised to reduce the current consumption by charging and discharging the bit lines. The data line is precharged during 1/2 cycle. Data is read in the next 1/2 cycle. That is, the word line driving according to the address decoding result, the reading to the data line of the memory cell, and the sense amplifier driving are simultaneously performed.

  Even if the sense amplifier of the way that does not hit is not moved, charging and discharging of the data line cannot be avoided if the word line of the way is started up. Therefore, we decided to launch only the word line of the hit way. For this purpose, it is necessary to determine the way hit before the timing of driving the word line. It is known from simulation that the way hit before the word line drive can be determined. With such a configuration, current consumption due to data line charging / discharging can be significantly reduced.

  Further, as in the embodiment of FIG. 19, the current mirror differential type sense amplifier is changed to a cross-coupled type sense amplifier to eliminate the through current of the sense amplifier. Cross-coupled sense amplifiers are difficult to drive. This is because if the sensing operation is not started after the potential difference between the data lines becomes significant, malfunction may occur. For this reason, a current mirror differential type has been conventionally used. In the present invention, a cross-couple type can be adopted by fine adjustment of the timing generation circuit system.

  When the cache memory is built in, the problem is how to implement the trace function of the in-circuit emulator. Debugging support by tracing can be achieved by accurately displaying the bus access before and after the time when the problem occurred. If the cache memory is built in, only the memory access that misses the cache memory is output to the external bus, so that correct trace data cannot be obtained.

  Therefore, the single chip microcomputer according to the present invention is provided with a mode in which the address and data are output to the bus for one cycle when a cache hit occurs in order to enable tracing when the cache memory is accessed. When used with a single processor, no memory access is performed when the cache is hit. In other words, the address and data are not output during tracing, and the external bus is free. Using this, trace data is output.

  On the other hand, when transferring data at a high bus usage rate using a DMA controller, or in multiprocessor systems, there is a possibility that the output of trace data and DMA transfer or memory access from other processors may compete. is there. In the worst case, when the DMA controller occupies the bus by performing dual address transfer, the trace performance is output after waiting for the interval between read and write, so the CPU performance is twice that of the memory actually connected instead of the cache. Equivalent to connecting a slow memory.

  Support for program debugging occupies an important position when developing a system using a microcontroller. The current programming leaves the assembler language and adopts an object-oriented programming language such as C ++ by adopting the C language and, for some applications, object-oriented. Under these circumstances, the statement execution stop and the symbolic variable reference function are indispensable for improving the work efficiency of the programmer.

  Unlike a personal computer or workstation that loads an OS or application program on the RAM, the microcontroller incorporated in the device often performs final debugging on the ROM. The program on the RAM can be easily stopped accurately by replacing the instruction at the designated address with a break instruction to stop execution. The stopping method is the same for the built-in cache memory. In ROM, instructions cannot be replaced.

  The single chip microcomputer according to the present invention is provided with a user break controller that detects an instruction fetch address and generates a break interrupt immediately before an instruction at a specified address in order to support an accurate stop of execution. The user break controller also includes a function for generating a break interrupt according to the data access address and data value. The break interrupt can be correctly generated even when the cache is hit and no external access is performed by incorporating the chip inside the chip.

  The address bus and data bus inside the chip are wired to almost all modules. Its capacitance is on the order of several pF. If each of the 32 address buses / data buses is driven in reverse polarity every cycle, the current consumption due to charge / discharge of electric charge exceeds 60 mA, and the delay increases as the capacitance increases.

  Therefore, in the single-chip microcomputer according to the present invention, as in the embodiment of FIG. 1 and the like, the internal bus is divided and the drive method is devised for each bus to reduce the charge / discharge current. . The internal bus of the chip can be divided into three types.

  FIG. 33 is a timing chart for explaining each bus cycle in the single chip microcomputer according to the present invention. Each signal of the cache bus (first bus in FIG. 1) and the internal bus (second bus in FIG. 1) changes in synchronization with the high level period of the clock and is connected to the outside of the chip. Each signal of the (fourth bus in FIG. 1) changes in synchronization with the low level period of the clock.

  When the CPU accesses data or instructions on the memory, the address signal is output to the cache address bus in synchronization with the clock signal and an access signal (not shown) for indicating that the access is performed is set to the high level. . In response to this, the cache searches the internal cache memory. When the access is a read to the memory and the data at the access address exists in the cache memory, the data read from the cache memory is output to the cache data bus in synchronization with the clock in the next cycle and the ready signal is set to the high level. Indicates that data access has been completed to the CPU. In the figure, the access at address A and the access at address A + 4 correspond to this.

  When there is no data in the cache memory, data outside the cache is accessed via the internal bus. In this figure, access to address C corresponds to this. That is, the CPU sends the address signal C to the cache address bus in cycle 4 and sets the access signal (not shown) to the high level. Since there is no data in the cache memory, the cache sets the ready signal to the low level in cycle 5 to notify the CPU that the data is not ready and sets the bus access signal of the internal bus to the high level.

  The external address interface receives the high level of the access signal, decodes the value of the internal address bus, and determines whether this is an access to the inside of the chip or an access to the outside. Since the address of the address signal C is external, the address signal C is immediately put on the external address bus and the external bus access signal is set to the high level.

  In the next cycle, since the data read preparation is not completed, the internal ready signal is set to low level to notify the cache that data preparation is not possible. In cycle 6 of read completion, the external interface outputs the read data to the internal data bus and sets the internal ready signal to the high level to notify the cache of the read completion. The cache writes the data of the internal bus to the cache memory and simultaneously outputs it to the cache data bus, and sets the cache ready signal to high level to notify the CPU of the completion of reading. During the period when the cache ready signal is at the low level (cycle 5 and cycle 6), the CPU stops updating the address bus.

  In the data write operation, there is no need to wait for the completion of external data write, so that the cache outputs the address signal B to the internal address bus through the break controller, as shown in the address B address, When the bus access signal is set to the high level, the cache ready signal connected to the CPU is maintained at the high level. Therefore, the CPU continues execution without waiting for completion of writing to the external bus.

  When accessing the free running timer FRT, serial communication interface SCI, and watchdog timer WDT, which are peripheral modules connected to the peripheral bus (third bus in FIG. 1), output from the cache address bus to the internal address bus via the cache The address signal B to be used becomes the address signal B of these peripheral modules. The address signal B is output to the peripheral address bus via the bus state controller BSC. At the same time, the bus access signal goes high.

  After the data output from the peripheral module to the peripheral data bus or the writing of the value on the data bus to the peripheral module is completed, the external bus interface sets the internal bus ready signal to the high level to notify the completion of the access. In the case of data reading, at this time, read data on the peripheral data bus is simultaneously output from the bus state controller BSC to the internal data bus.

  FIG. 34 is a timing chart for explaining the mode write operation of the synchronous DRAM. In the single chip microcomputer according to the present invention, although not particularly limited, the mode setting for the synchronous DRAM is realized as follows.

  Of the addresses FFF8000 to FFFFFFFF allocated for the built-in peripheral, when accessing (writing or reading) FFFF8000 to FFFFB000, the address is output as it is to the external bus and is connected to the synchronous DRAM / CS3 , / RAS, / CAS and / WE are simultaneously driven low for one clock cycle.

  The synchronous DRAM takes in the value of the address bus at the rising edge of the clock when the signals of these four control lines are at the low level, and writes it in the internal mode setting register as it is. Therefore, a desired mode can be easily set by accessing an appropriate address from FFFF8000 to FFFB000. The generation of the control signal at the timing as described above is formed by the memory control signal generation circuit MCTG. That is, an appropriate address decoder is provided in the area control unit of the external bus interface circuit, and a sequence state in which the signals of the four memory control lines are set to the low level according to the address decoding conditions as described above is provided. It is realized by doing so.

  FIG. 35 is a block diagram showing an embodiment of the synchronous DRAM (hereinafter simply referred to as SDRAM). The SDRAM shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

  The SDRAM of this embodiment includes a memory array 200A that constitutes a memory bank A (BANKA) and a memory array 200B that constitutes a memory bank (BANKB). Each of the memory arrays 200A and 200B includes dynamic memory cells arranged in a matrix, and according to the figure, the selection terminals of the memory cells arranged in the same column are coupled to word lines (not shown) for each column, Data input / output terminals of memory cells arranged in the same row are coupled to complementary data lines (not shown) for each row.

  One word line (not shown) of the memory array 200A is driven to a selected level in accordance with the decoding result of the row address signal by the row decoder 201A. Complementary data lines (not shown) of memory array 200A are coupled to sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplifier circuit that detects and amplifies a minute potential difference that appears on each complementary data line by reading data from the memory cell. In this case, the column switch circuit is a switch circuit for selecting a complementary data line and making it conductive to the complementary common data line 204. The column switch circuit is selectively operated according to the decoding result of the column address signal by the column decoder 203A. Similarly, a row decoder 201B, a sense amplifier and column selection circuit 202B, and a column decoder 203B are also provided on the memory array 200B side. The complementary common data line 204 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. The input terminal of the input buffer 210 and the output terminal of the output buffer 211 are connected to 16-bit data input / output terminals I / O0 to I / O15.

  The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. The row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of the column address counter 207. The column address counter 207 corresponds to the column address signal as the preset data, or its column address, according to the operation mode specified by a command to be described later. A value obtained by sequentially incrementing the signal is output to the column decoders 203A and 203B.

  The controller 212 is not particularly limited, but includes a clock signal CLK, a clock enable signal CKE, a chip select signal / CS, a column address strobe signal / CAS (a symbol / means that a signal to which this is attached is a row enable signal. ), External control signals such as row address strobe signal / RAS and write enable signal / WE, and control data from address input terminals A0 to A9 are supplied, based on the level change and timing of those signals. It forms an internal timing signal for controlling the operation mode of the SDRAM and the operation of the circuit block, and includes a control logic (not shown) and a mode register 30 for that purpose.

  The clock signal CLK is the SDRAM's macter clock, and other external input signals are significant in synchronization with the rising edge of the clock signal CLK. The chip select signal / CS instructs the start of the command input cycle according to its low level. When the chip select signal / CS is at a high level (chip non-selected state) or other inputs are meaningless. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. Each of the signals / RAS, / CAS, / WE has a function different from that of a corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle to be described later.

  The clock enable signal CKE is a signal that indicates the validity of the next clock signal. The rising edge of the next clock signal CLK is valid if the signal CKE is high level, and invalid when the signal CKE is low level. Further, although not shown, in the read mode, an external control signal for controlling output enable for the output buffer 211 is also supplied to the controller 212. When the signal is at a high level, for example, the output buffer 211 is brought into a high output impedance state.

  The row address signal is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of the clock signal CLK.

  The input from A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is low level, the memory bank BANKA is selected, and when it is high level, the memory bank BANKB is selected. The selection control of the memory bank is not particularly limited, but only the row decoder on the selected memory bank side is activated, all the column switch circuits on the non-selected memory bank side are not selected, only the input buffer 210 and the output buffer on the selected memory bank side It can be performed by a process such as connection to 211.

  An input of A8 in a precharge command cycle to be described later indicates a precharge operation mode for a complementary data line or the like, and its high level indicates that the objects of precharge are both memory banks, and its low level is A9. It is instructed that one of the memory banks instructed in is a target for precharge.

  The column address signal is defined by the levels of A0 to A7 in a read or write command (column address / read command, column address / write command described later) cycle synchronized with the rising edge of the clock signal CLK. The column address thus defined is used as a burst access start address.

Next, main operation modes of the SDRAM indicated by the command will be described.
(1) Mode register set command (Mo)
This is a command for setting the mode register 30, and is designated by / CS, / RAS, / CAS, / WE = low level, and data to be set (register set data) is given via A0 to A9. . The register set data is not particularly limited, but may be burst length, CAS latency, write mode, or the like. Although not particularly limited, the burst length that can be set is 1, 2, 4, 8, and full page (256), the CAS latency that can be set is 1, 2, and 3, and the write mode that can be set is burst. Light and single light.

  The CAS latency indicates how many cycles of the clock signal CLK are spent from the fall of / CAS to the output operation of the output buffer 211 in a read operation instructed by a column address / read command described later. An internal operation time for data reading is required until the read data is determined, and is used for setting it according to the frequency of use of the clock signal CLK. In other words, the CAS latency is set to a relatively large value when the clock signal CLK having a high frequency is used, and the CAS latency is set to a relatively small value when the clock signal CLK having a low frequency is used.

(2) Row address strobe / bank active command (Ac)
This is a command for enabling the instruction of the row address strobe and the selection of the memory bank by A9, which is instructed by / CS, / RAS = low level, / CAS, / WE = high level, and is supplied to A0 to A8 at this time. The address supplied is taken as a row address signal, and the signal supplied to A9 is taken in as a memory bank selection signal. The capturing operation is performed in synchronization with the rising edge of the clock signal CLK as described above. For example, when the command is designated, the word line in the memory bank designated by the command is selected, and the memory cells connected to the word line are respectively conducted to the corresponding complementary data lines.

(3) Column address / read command (Re)
This command is a command necessary for starting a burst read operation, and a command for giving an instruction of a column address strobe, which is indicated by / CS, / CAS = low level, / RAS, / WE = high level, At this time, the column address supplied to A0 to A7 is taken in as a column address signal. The column address signal thus fetched is supplied to the column address counter 207 as a burst start address. In the burst read operation instructed thereby, the memory bank and the word line in the row address strobe / bank active command cycle are selected before that, and the memory cell of the selected word line receives the clock signal CLK. Are sequentially selected according to the address signal output from the column address counter 207 and read continuously. The number of data continuously read out is the number specified by the burst length. Data read from the output buffer 211 is started after waiting for the number of cycles of the clock signal CLK defined by the CAS latency.

(4) Column address / write command (Wr)
When burst write is set in the mode register 30 as a mode of write operation, it is a command necessary to start the burst write operation, and when single write is set in the mode register 30 as a mode of write operation Is a command necessary to start the single write operation. Further, this command gives an instruction for column address strobe in single write and burst write. This command is instructed by / CS, / CAS, / WE = low level, / RAS = high level, and at this time, the address supplied to A0 to A7 is taken in as a column address signal. The column address signal thus fetched is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed thereby is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of the write data is started from the column address / write command cycle.

(5) Precharge command (Pr)
This is a command for starting a precharge operation for the memory bank selected by A8, A9, and is designated by / CS, / RAS, / WE = low level, / CAS = high level.

(6) Auto-refresh command This command is required to start auto-refresh, and is designated by / CS, / RAS, / CAS = low level, / WE, CKE = high level.

(7) Burst stop in full page command This command is required to stop the burst operation for a full page for all memory banks, and is ignored for burst operations other than full page. This command is indicated by / CS, / WE = low level, / RAS, / CAS = high level.

(8) No operation command (Nop)
This is a command for instructing that no substantial operation is performed, and is designated by / CS = low level, / RAS, / CAS, / WE high level.

  In the SDRAM, when a burst operation is performed in one memory bank, if another memory bank is specified in the middle of the SDRAM and a row address strobe / bank active command is supplied, one memory bank being executed The row address operation in another memory bank is enabled without affecting the operation in the bank. For example, an SDRAM has means for internally holding data, addresses, and control signals supplied from the outside, and the held contents, particularly addresses and control signals are not particularly limited, but are held for each memory bank. It has become. Alternatively, data for one word line in the memory block selected by the row address strobe / bank active command cycle is latched in advance in a latch circuit (not shown) for a read operation before a column-related operation. Yes.

  Therefore, as long as data does not collide at the data input / output terminals I / O0 to I / O15, during execution of a command that has not been processed, a command for a memory bank different from the memory bank to be processed by the command being executed is stored. It is possible to start the internal operation in advance by issuing a charge command and a row address strobe / bank active command.

  Since the SDRAM 22 can input / output data, addresses, and control signals in synchronization with the clock signal CLK, it is possible to operate a large-capacity memory similar to the DRAM at a high speed comparable to that of the SRAM. By specifying the number of data to be accessed for each word line by burst length, the built-in column address counter 207 sequentially switches the column system selection state and reads or writes a plurality of data continuously. It will be understood that it can be done.

  FIG. 36 is a block diagram for explaining an example of the product-sum operation for the three-dimensional image processing or the like. The product-sum operation is performed as follows by the CPU, the arithmetic unit (product-sum multiplier), the cache memory, and the cache memory control circuit.

  In the figure, a CPU decodes an instruction register IR that temporarily stores an instruction code read from a cache memory via a data bus (cache bus) DB1, and an instruction execution unit that decodes the read instruction code. And the like, and a control circuit that generates a control signal and the like, and an instruction execution unit that executes arithmetic processing. Inside the instruction execution unit, an address buffer AB, ALU (arithmetic logic unit), an internal register, a data input / output buffer DB, and the like are connected to the internal A bus, B bus, and C bus.

  The CPU reads the instruction code stored in the cache memory via the data bus DB1 and takes it into the instruction register IR. The fetched instruction code is decoded by the control circuit and outputs a control signal inside the CPU. By this control signal, the instruction execution unit is controlled to execute a desired operation.

  In this embodiment, a multiplier is connected to the CPU via a data bus DB1, a command control line COMD, and a wait control line WAIT, and a cache memory control circuit is connected to this multiplier via an internal state signal CC.

  A command control signal from the control circuit of the CPU is input to the multiplier, and the internal state of the multiplier is transmitted to the cache memory control circuit by the state signal CC, and the multiplier operation is performed by the state signal CC and the command control signal COMD. When the next calculation start command is issued during processing, a wait signal WAIT for waiting for the bus cycle is generated. This wait signal WAIT is input to the control circuit of the CPU.

  FIG. 37 is an explanatory diagram for explaining a product-sum instruction (MAC instruction). In the same figure, the product-sum operation corresponding to the determinant of Equation 1 is shown as an example in the three-dimensional image processing. In the figure, IF or if indicates instruction fetch, ID indicates decode, EX indicates operation or execution, MA indicates memory access, WB indicates write back, and mm indicates a state in which the multiplier is operating. Yes.

  To clear the contents of the multiply-accumulate register, a CLRMAC instruction is executed. This instruction clears the contents of the product-sum output register of the arithmetic unit. Subsequently, the first MAC (multiply-accumulate instruction) is executed. This sum-of-products instruction MAC ends in eight stages of if-ID-EX-MA-MA-mm-mm-mm. The second MA also starts the multiplier operation as well as reading the memory.

  The ID of the instruction next to the MAC instruction is stalled after one slot. Therefore, the ID of the second MAC instruction is stalled after one slot. As in this embodiment, when the MAC instruction is continuous, if the second MA of the MAC instruction competes with mm generated by the previous multiplication instruction, the bus cycle of the MA is mm. Is extended until it ends (indicated by M -------------------------------------------------------------------------------- In the figure, the portion surrounded by a dotted line indicates that the mm and MA are competing.

  The CPU control circuit sequentially fetches instructions using if-ID-EX-MA, decodes the MAC instruction, generates an address of a cache memory having data to be multiplied, and passes the memory address through an address buffer AB. The data is output to the address bus AB1, and data is output from the cache memory to the data bus DB1. The data to be calculated output on the data bus is not captured by the CPU, but is captured by the calculator based on the signal COMD from the CPU, performs calculations over three slots, and is stored in the output register.

  Hereinafter, the arithmetic unit performs a multiply-accumulate operation by adding a total of four multiplications corresponding to the determinant as described above and adding the multiplication result to the previous multiplication result in accordance with successive MAC instructions. Do. Finally, by the STS command, the calculation result is written back and coordinate conversion corresponding to one relative coordinate is performed.

  FIG. 38 shows a block diagram of an embodiment of the divider. In the figure, JR is a divisor register, a 32-bit wide register for storing the divisor, and has no special function. HRL is a dividend lower and quotient storage register, which stores the lower 32 bits of the dividend and stores the quotient 32 bits at the end of the operation. It is also used as a temporary register for storing intermediate results during computation. HRH is a register that stores the upper 32 bits of the dividend. In the case of 32 ÷ 32 arithmetic, the sign of the dividend is sign-extended, so that the MSB value of the HRL is copied to all bits of the HRH. When the calculation is completed, the remainder of the result is stored. It is also used as a temporary register for storing intermediate results during computation.

  CONT is a control register, and 2 bits to 31 bits out of 32 bits cannot be written, and only 0 reading is performed. Valid bits are the lower 2 bits of bit 1 and bit 0. Bit 0 is an OVF (overflow) flag. A value is set when an overflow or underflow occurs.

  Bit 1 is a flag that determines whether an interrupt is generated or prohibited when a value is set in bit 0. Bits 1 and 0 are performed by a 0 write from the bus master. In the state where the overflow interrupt is off, the MAX value is set to the quotient when an overflow occurs, and the MIN value is set to a quotient when an underflow occurs. When an overflow or underflow occurs with the overflow interrupt turned on, the calculation result is set as it is in the quotient.

  VCT is an interrupt vector, and is a register that stores an interrupt vector that is output when an overflow occurs with bit 1 of CONT set to 1. In the initial value, the upper 16 bits are 0, and the lower 16 bits are undefined.

  RAR is a surplus storage register, and is a 32-bit register that stores the surplus at the end of the operation. The difference from HRH is that it is not used as a temporary register for storing an intermediate result during an operation, and it is possible to save a value until the next operation is completed or until it is written from the bus master.

  RSR is a quotient long-term storage register, and is a 32-bit register that stores the quotient at the end of the operation. The difference from HLH is that it is not used as a temporary register for storing an intermediate result during an operation, and it is possible to save a value until the next operation is completed or until it is written from the bus master.

  FA & CLA is a full adder and carry look ahead, and performs a 32-bit adder, subtractor, carry presence and zero check. AUFA & AUCLA is a 1 adder, and 1 subtraction is performed by inverting the value with a selector attached before and after the adder. The LDMCA is a state control circuit, and includes a logic circuit that performs write control from the bus master to the multiplier built-in register, operation cycle control during the divider operation, and zero check of the operation result. LDMCB is an overflow processing circuit, and is a control logic circuit that performs processing when an overflow occurs in a division operation. LDPRM is an I / O control circuit, which is a control logic circuit that interfaces a divider and peripheral modules.

  FIG. 39 is a state transition diagram for explaining the operation of the divider. In the divider of this embodiment, there are a total of 42 states. “000000” at the top of the figure is in a ready state, and this state is obtained after resetting. Normal division processing is performed in 38 cycles from “000001” at the upper left to “001100” at the lower right. A branch from “100110” above the center of the left column is a process when an overflow occurs, and returns to the original state in two cycles from here. In addition, “000010” in the ready state is a save location at the time of a continuous write / read request.

  The division processing by the divider can be roughly classified into the following five. Each will be described below.

(1) Ready state (“000000”-“000010”)
“000000” is a normal ready state, and “000010” is a state that transitions only when a register read command is issued immediately after a register write command in accessing the divider from the bus master. In the divider configuration of this embodiment, when a register read instruction is issued immediately after a register write instruction from the bus master, a normal value cannot be output. Therefore, when a register read instruction is issued immediately after the register write instruction from the bus master, unlike the normal ready state “000000”, the bus master read bus cycle is extended to ensure time for normal read data to be prepared. For this purpose, “000010” is provided.

(2) Pre-division processing (“000001” − “100001”)
This is the preparation period before entering the non-regression algorithm. “000001” is a cycle for transferring data written from the bus master to the HRL in the divider, and “100001” is used in the first cycle of the non-regression method, “MSB (sign) of the previous calculation result”. Used to seek.

(3) Non-regression method (“1000011”-“001110”)
Non-regression processing is performed for 33 cycles. However, the 33rd cycle (“001110”) is slightly different from the others. Since the remainder of the result is obtained at the 32nd cycle, HRH does not capture data in this cycle.

(4) Post-division processing (“001110”-“001100”)
This is a post-processing cycle necessary for the non-regression method. In “001111”, addition (retraction) of the remainder is performed, and 1 addition is performed when the quotient is negative, and quotient / residue correction is performed when the dividend is divisible by negative in two states “001111” and “001101”. Yes. RAR and RSR are set by “001110” and “001100”.

(5) Overflow processing (“000110”-“000111”)
The “000110” state is indicated by a dotted line because the transition to the overflow state is performed by a circuit different from the circuit that normally controls the state transition. In addition, this state does not appear on the surface as one cycle (“100110” and “000110” each half cycle), and is represented by a dotted line. In “000111”, RAR and RSR are set.

  Thus, the divider spends a long time of 38 cycles for one division as described above. Thus, in spite of the fact that it takes a relatively long time for the division, the system shown in FIG. 1 and the parallel operation processing shown in FIG. 25 are performed. By performing the perspective processing by the division, the coordinate conversion by the product-sum operation, etc., and the clip processing at the same time, the substantial three-dimensional image processing can be significantly speeded up.

  FIG. 40 shows a layout diagram of an embodiment of the single chip microcomputer of FIG. In the figure, the main circuits of the circuit blocks in FIG. 1 are exemplarily shown as representatives. Each circuit block is arranged so that each bus is short and the connection relationship is easy according to the fact that the bus is divided into three as described above. The figure shows the first bus among the three divided buses, and it is understood that the other second and third buses are arranged adjacent to the corresponding circuit blocks. I want.

  The central processing unit CPU and the cache data portions CACHE-D1 and D2 of the cache memory are arranged across the first bus. The cache tag part CACHE-A and the cache control part CACHE-C of the cache memory are arranged side by side with the multiplier MULT. The central processing unit CPU, cache memory, and multiplier MULT occupy about the upper half of the chip.

  The bus state controller BSC is arranged so as to sandwich the central processing unit CPU between the cache data parts CACHE-D1 and D2. A break controller UBC, a divider DIVU, an interrupt control circuit INT1, INT2, a direct memory access control device DMAC, and its data buffers DATA1, DATA2 connected to a second bus (not shown) are concentrated in the lower left part of the chip. The

  Then, timers FRT and WDT connected to a third bus (not shown) and a serial communication interface SCI are arranged side by side. These peripheral modules have a relatively slow operation of the output circuit by slowing down the bus cycle. By using the existing circuit as it is, the occupied area can be reduced. Around the chip, an input buffer, an output buffer, and an input / output buffer corresponding to the above terminals are arranged.

  FIG. 41 shows an application example of the single chip microcomputer according to the present invention. FIG. 2A shows a block diagram, and FIG. 2B shows an external view. This embodiment is directed to a pen input portable microcomputer.

  In this embodiment, as shown in the block diagram of (A), the microcomputer is constituted by a single chip microcomputer as shown in FIG. 1, and it has an external memory (Memory) and an ASIC (specifically specified). It is composed of peripheral LSIs composed of application-specific ICs). As a terminal device, a display device in which a pen input function is added to an LCD and a voice input / output circuit are provided. As shown in the external view of (B), it is thin and light like a palmtop type or a notebook type, an LCD display unit is provided with a pen input unit, and a key input switch panel is provided.

  FIG. 42 is a block diagram showing an embodiment of the pen-input portable microcomputer shown in FIG. The single chip microcomputer MCU is driven by a battery. The microphone is used for voice input. A speaker is used for audio output.

  The NCU is an input / output interface for a telephone line, and performs data input or output by a telephone. As the microcomputer system, an LCD panel for performing display and pen input via an LCD controller is provided on an external bus. SDRAM or PSRAM is used as the external memory. These memories are backed up by the battery voltage as necessary.

  The mask ROM stores programs and character patterns for data processing. PCMCIAI / F is a Personal Computer Memory Card International Association interface. I / O is an extended peripheral interface such as a wireless LAN (local area network). The memory card (ROM card) and (RAM card) can be used as removable external memories.

The effects obtained from the above embodiment are as follows. That is,
(1) The internal bus is divided into three, a central processing unit and a cache memory are connected to the first bus, and a direct memory access control circuit and an external bus interface are connected to the second bus. The first bus and the second bus are provided with break controllers having a bus transceiver function for selectively connecting the first address bus and the second address bus, and the first and second buses are provided. A bus state controller that connects peripheral modules to the third bus, which is a low-speed bus cycle, and performs data transfer and synchronization between the second bus and the third bus. By providing, the load capacity of the signal transmission path is reduced, so that signal transmission can be performed at high speed and peripheral modules that do not require operation speed are separated. The effect that current consumption can be reduced is obtained.

(2) The internal bus is divided into three, a central processing unit is connected to the first bus, a fixed-point product-sum operation unit is connected to the first bus, and a fixed bus is connected to the second bus. By connecting a decimal-point divider, the product-sum operation can be performed at a high speed with a small number of cycles, and a fixed-point divider is connected to the second bus. Since division can be performed, an effect that three-dimensional image processing can be performed at high speed can be obtained.

(3) By providing at least one of a free running timer, a serial communication interface, or a watchdog timer as a peripheral module connected to the third bus, a peripheral that is not directly involved in increasing the speed of data processing A low-speed bus cycle for modules can be configured, and existing peripheral modules can be used as they are without following the increase in the speed of the central processing unit, so that design efficiency and power consumption in the peripheral modules can be reduced. The effect that it can be obtained.

(4) The above break controller has a function of monitoring the rewriting of data in the cache memory by the direct memory access control device, thereby achieving direct memory access control while achieving high speed and low power consumption by separating the internal bus. It is possible to monitor the destruction of the cache data due to the rewriting of the data in the cache memory by the apparatus.

(5) Each circuit block is configured by a full static CMOS circuit, and an operation mode controller including a register for controlling supply / stop of a clock pulse is provided for each circuit block. Since only the clock can be supplied, the effect of reducing power consumption can be obtained.

(6) The external bus interface has an interface function that allows direct access to the burst read mode and single write mode of the synchronous dynamic RAM, the dynamic RAM, and the pseudo static RAM, so that the synchronous dynamic RAM directly Since a dynamic RAM, a pseudo static RAM, and the like can be directly connected, an effect of improving usability can be obtained.

(7) By delaying the phase with respect to the clock pulse of the external bus interface and forming the clock pulse and supplying it to the central processing unit, the setup / hold time of the synchronous dynamic RAM can be secured and the operation margin can be expanded. The effect that it can be obtained.

(8) Efficient data can be obtained by providing consistency between the data read in the burst mode of the synchronous dynamic RAM, the data of one block of the cache memory, and the unit data transfer by the direct memory access control device. The effect that transfer becomes possible is acquired.

(9) In the external bus interface, the central processing unit is activated by accessing a specific address space, and both the row address strobe signal, the column address strobe signal and the write enable signal are set to the low level, and a part of the address signal By providing a memory control signal generation circuit for generating a control signal necessary for setting the operation mode setting of the synchronous dynamic RAM using the CPU, the mode setting of the synchronous dynamic RAM can be easily performed by the central processing unit. The effect that it can be obtained.

(10) The cache memory is composed of a plurality of tag memories and corresponding data memories. The tag memory and the data memory use CMOS static memory cells as sense amplifiers that amplify read signals. A DC current flows after signal amplification by using a CMOS sense amplifier comprising a CMOS latch circuit and a power switch MOSFET comprising a P-channel MOSFET and an N-channel MOSFET for supplying an operating current to the CMOS latch circuit. As a result, the power consumption of the cache memory can be reduced.

(11) Low power consumption can be achieved by activating both sense amplifiers or sense amplifiers and word lines provided in the plurality of data memories corresponding to the hit signal from the tag memory. The effect that it can plan is acquired.

(12) The above-mentioned plurality of data memories can be directly accessed by the central processing unit by disabling the transmission of hit signals from the tag memory in whole or in part by the cache controller, thereby satisfying various requests of users. The effect that it can be adapted to the usage.

(13) In a single-chip microcomputer including a central processing unit and a cache memory, a CMOS static memory cell is used as a memory element as a cache memory, and a CMOS latch circuit and a CMOS latch circuit as a sense amplifier for amplifying the read signal Built-in cache memory because a DC current does not flow after signal amplification with the sense amplifier by using a CMOS sense amplifier comprising a power switch MOSFET comprising a P-channel MOSFET and an N-channel MOSFET for supplying an operating current to The effect that the power consumption can be reduced is obtained.

(14) Although the plurality of data memories correspond to the hit signal from the tag memory, only the sense amplifier is activated, so that the power consumption of the single-chip microcomputer incorporating the cache memory can be reduced. The effect is obtained.

(15) When the slave mode is set according to the bus use right control signal, the first terminal is used for the bus request signal, the second terminal is used for the bus acknowledge signal, and when the master mode is set, the first terminal By switching the second terminal to the bus release signal and using the second terminal as the bus release signal, one single chip microcomputer can be used as the slave mode or the master mode according to the bus use right control signal, and the same terminal can be used. Since they are used by switching, the effects of reducing the number of external terminals and simplifying the connection and improving the usability can be obtained.

(16) A central processing unit performs a clipping process on the N−1th coordinate subjected to the perspective processing, and converts the N + 1th coordinate point unique to a specific object into a coordinate having the designated viewpoint as the origin. A central processing unit or a product of the central processing unit or the product thereof by performing a perspective process on the Nth coordinate after the coordinate conversion process is completed in parallel with the clipping process and the coordinate conversion process. An effect that high-speed three-dimensional image processing can be realized can be obtained by performing the perspective processing that consumes a relatively long time in parallel with the clipping processing and the coordinate conversion processing by the sum calculator by the divider.

(17) The central processing unit and the product-sum operation unit are connected to the first bus together with the cache memory, and the divider is connected to the second bus together with the direct memory access control circuit and the external bus interface. And a break controller having a bus transceiver function for selectively connecting the address bus of the first bus to the address bus of the second bus. A third bus to which peripheral modules having a low-speed bus cycle with respect to the bus cycle are connected, and a bus state controller that performs signal transfer and synchronization between the second bus and the third bus. By performing the above three-dimensional image processing with a single-chip microcomputer provided, high-speed three-dimensional image processing can be achieved with a relatively simple configuration. Effect that can be achieved.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the embodiment of FIG. 1, the central processing unit CPU does not have to be a RISC type processor, and various embodiments can be adopted. The single-chip microcomputer of this embodiment may be constituted by an ASIC in which each circuit block as described above is registered and necessary circuit blocks are mounted according to user specifications.

  The single-chip microcomputer in the present application is not limited to a narrow meaning of a microcomputer incorporating a ROM and a RAM, but is used in a broad sense such as a data processing device formed on one semiconductor substrate. Therefore, the single chip microcomputer according to the present application has a central processing unit, a product-sum calculator, and a divider, and at least the product-sum calculator and the divider can be processed in parallel, It can be expressed as a data processing device formed on a semiconductor substrate. Alternatively, an external memory capable of continuous reading is connectable, and the cache memory and the means capable of continuously reading data equal to the data length of one line from the external memory on the single semiconductor substrate. It can also be referred to as a data processing apparatus provided.

  Further, the data can be connected to an external memory capable of mode setting, and includes means on a single semiconductor substrate capable of being transferred to the memory via an external terminal other than the data bus terminal for setting the mode. It can also be called a processing device. Further, the data processing apparatus can be connected to an external memory for inputting and outputting addresses and data in synchronization with the clock, and the means for forming the clock necessary for the memory and the data processing apparatus is a single semiconductor. A data processing device formed on a substrate, or a central processing unit that accesses a memory in 32-bit units and executes a 16-bit fixed-length instruction, and an instruction / data mixed type cache memory, and loads from the memory It can also be referred to as a data processing device in which an instruction for storing is placed on an even word boundary.

  The present invention can be applied to the single chip microcomputer in the broad sense as described above and three-dimensional image processing using the same.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the internal bus is divided into three, a central processing unit and a cache memory are connected to the first bus, a direct memory access control circuit and an external bus interface are connected to the second bus, and the first bus The bus and the second bus are provided with a break controller having a bus transceiver function for selectively connecting the first address bus and the second address bus to the first and second bus cycles. On the other hand, the third bus, which is a low-speed bus cycle, is provided with a bus state controller for connecting peripheral modules and performing data transfer and synchronization between the second bus and the third bus. Since the load capacity of the signal transmission path is reduced, signal transmission can be performed at high speed, and peripheral modules that do not require operation speed are separated. It is possible to reduce the current consumption of.

  The internal bus is divided into three, a central processing unit is connected to the first bus, a fixed-point product-sum calculator is connected to the first bus, and a fixed-point method is connected to the second bus. By connecting this divider, the product-sum operation can be performed at a high speed with a small number of cycles, and a fixed-point divider is connected to the second bus. Since the result can be divided as it is, three-dimensional image processing can be performed at high speed.

  By providing at least one of a free-running timer, a serial communication interface, or a watchdog timer as a peripheral module connected to the third bus, it is for a peripheral module that is not directly involved in speeding up data processing. A low-speed bus cycle can be configured, and existing peripheral modules can be used as they are without following the increase in the speed of the central processing unit, so that design efficiency and power consumption in the peripheral modules can be reduced.

  The break controller has a function of monitoring the rewriting of data in the cache memory by the direct memory access control device, thereby increasing the speed and reducing the power consumption by separating the internal bus, and the cache by the direct memory access control device. It is possible to monitor the destruction of cache data due to rewriting of data in the memory.

  Each circuit block is configured by a full static CMOS circuit, and an operation mode controller including a register for controlling supply / stop of a clock pulse is provided for each circuit block, so that a clock is supplied only to a necessary circuit block. Since it can be supplied, power consumption can be reduced.

  The external bus interface has an interface function that allows direct access to the burst read mode and single write mode of the synchronous dynamic RAM, the dynamic RAM, and the pseudo static RAM, so that the synchronous dynamic RAM and the dynamic RAM can be directly used. In addition, since a pseudo static RAM or the like can be directly connected, usability can be improved.

  As an external bus interface, a synchronous dynamic RAM setup / hold time is formed by forming a clock pulse whose phase is advanced with respect to the clock pulse of the central processing unit and supplying it to the clock terminal of the synchronous dynamic RAM. Can be secured, and the operation margin can be expanded.

  Efficient data transfer is possible by providing consistency between the data read in the burst mode of the synchronous dynamic RAM, the data of one block of the cache memory, and the unit data transfer by the direct memory access control device. become.

  In the external bus interface, the central processing unit is activated by accessing a specific address space, and the row address strobe signal, the column address strobe signal and the write enable signal are all set to the low level, and a part of the address signal is used. By providing a memory control signal generation circuit for generating a control signal necessary for setting the operation mode setting of the synchronous dynamic RAM, the mode setting of the synchronous dynamic RAM can be easily performed by the central processing unit.

  The cache memory is composed of a plurality of tag memories and corresponding data memories. The tag memory and the data memory use CMOS static memory cells, and a CMOS latch circuit as a sense amplifier that amplifies the read signal. In addition, by using a CMOS sense amplifier composed of a power switch MOSFET composed of a P-channel MOSFET and an N-channel MOSFET for supplying an operating current to the CMOS latch circuit, a direct current can be prevented from flowing after signal amplification. It is possible to reduce power consumption in the cache memory.

  By activating only the sense amplifiers or sense amplifiers and word lines provided in the plurality of data memories corresponding to the hit signal from the tag memory, power consumption can be reduced.

  The above-mentioned plurality of data memories can be directly used by the central processing unit by disabling the transmission of hit signals from the tag memory in whole or in part by the cache controller, so that it can be used according to various requests of users. Can be adapted.

  In a single-chip microcomputer including a central processing unit and a cache memory, a CMOS static memory cell is used as a memory element as a cache memory, and a CMOS latch circuit as a sense amplifier for amplifying the read signal and an operating current in the CMOS latch circuit By using a CMOS sense amplifier composed of a power switch MOSFET composed of a P-channel MOSFET and an N-channel MOSFET for supplying DC, a direct current does not flow after signal amplification with the sense amplifier. Power consumption can be reduced.

  The plurality of data memories correspond to the hit signal from the tag memory, but only the sense amplifier or the sense amplifier and the word line are activated, thereby reducing the power consumption of the single-chip microcomputer incorporating the cache memory. be able to.

  When the slave mode is set according to the bus usage right control signal, the first terminal is used as a bus request signal and the second terminal is used as a bus acknowledge signal. When the master mode is set, the first terminal is used as a bus grant. By switching and using the second terminal as a bus release signal for each signal, one single-chip microcomputer can be used as a slave mode or a master mode according to the bus use right control signal, and the same terminal can be switched for use. As a result, the number of external terminals is reduced and the connection is simplified, improving usability.

  The central processing unit performs a clipping process on the (N−1) th coordinate subjected to the perspective processing, and performs a coordinate conversion process for converting the N + 1th coordinate point unique to a specific object into a coordinate having the designated viewpoint as the origin. A central processing unit or a product-sum operation unit is obtained by performing a perspective process on the Nth coordinate after the coordinate conversion process is completed in parallel with the clipping process and the coordinate conversion process. High-speed three-dimensional image processing can be realized by performing a perspective process that consumes a relatively long time in parallel with the clipping process and the coordinate conversion process by using a divider.

  The central processing unit and the product-sum operation unit are connected to the first bus together with the cache memory, and the divider is directly connected to the second bus together with the memory access control circuit and the external bus interface. And a break controller having a bus transceiver function for selectively connecting the address bus of the first bus to the address bus of the second bus, and the first and second bus cycles. A single bus provided with a third bus to which a peripheral module having a low-speed bus cycle is connected, and a bus state controller for performing signal transfer and synchronization between the second bus and the third bus. By performing the above three-dimensional image processing by the chip microcomputer, high-speed three-dimensional image processing is realized with a relatively simple configuration. It is possible.

  The present invention can be widely used for a semiconductor integrated circuit device, a data processing device, a microcomputer, and the like which are high performance and high function and suitable for a home game machine, a portable information communication terminal device, and the like.

1 is a block diagram showing an embodiment of a single chip microcomputer according to the present invention. FIG. It is a pin arrangement | positioning figure which shows the left half of one Example of the single chip microcomputer based on this invention. It is a pin arrangement | positioning figure which shows the right half of one Example of the single chip microcomputer based on this invention. 1 is a block diagram showing an embodiment of an operation mode controller MC built in a single chip microcomputer according to the present invention. FIG. It is a block diagram which shows one basic Example of the break controller UBC built in the single chip microcomputer based on this invention. It is a detailed block diagram showing an embodiment of a break controller UBC built in a single chip microcomputer according to the present invention. It is a block diagram showing an embodiment of a bus state controller BSC built in a single chip microcomputer according to the present invention. It is a block diagram showing a connection example of a synchronous dynamic RAM by a bus state controller BSC and an external bus interface OBIF built in the single chip microcomputer according to the present invention. FIG. 9 is a bus cycle waveform diagram for describing a burst read operation of the SDRAM of FIG. 8. FIG. 9 is a bus cycle waveform diagram for describing a single write operation of the SDRAM of FIG. 8. It is a wave form diagram for demonstrating the basic bus cycle in the single chip microcomputer based on this invention. It is a block diagram showing an example of connection between a dynamic RAM using a bus state controller BSC and an external bus interface OBIF built in a single chip microcomputer according to the present invention. FIG. 13 is a bus cycle waveform diagram for describing a high-speed page mode of the DRAM of FIG. 12. It is a block diagram showing a connection example of a pseudo-static RAM by a bus state controller BSC and an external bus interface OBIF built in the single chip microcomputer according to the present invention. It is a block diagram which shows one Example at the time of carrying out multiprocessor connection using the single chip microcomputer which concerns on this invention. FIG. 16 is a timing diagram for explaining a case where the SDRAM on the main bus is accessed from the S-MCU of FIG. 15. 1 is a block diagram showing an embodiment of a cache memory built in a single chip microcomputer according to the present invention. FIG. 1 is a block diagram showing an embodiment of a cache memory according to the present invention. FIG. 1 is a block diagram showing an embodiment of a cache memory built in a single chip microcomputer according to the present invention. FIG. It is an operation | movement conceptual diagram for demonstrating the cache memory concerning this invention. It is a block diagram showing an embodiment of the direct memory access control device DMAC built in the single chip microcomputer according to the present invention. It is a schematic block diagram which shows one Example of DAMC which concerns on this invention, and its peripheral part. It is a block diagram which shows one Example of the divider DIVU built in the single chip microcomputer based on this invention. It is explanatory drawing for demonstrating the concept of the three-dimensional image process for displaying a three-dimensional object on the display screen which consists of two dimensions by a perspective method. It is a signal processing diagram for demonstrating the three-dimensional image processing method using the single chip microcomputer based on this invention. FIG. 11 is a characteristic diagram for explaining an example of a relationship between a miss rate and a line size of a mixed instruction / data cache. FIG. 10 is a characteristic diagram for explaining another example of the relationship between the miss rate and the line size of the instruction / data mixed type cache. FIG. 10 is a characteristic diagram for explaining another example of the relationship between the miss rate and the line size of the instruction / data mixed type cache. It is explanatory drawing of the access with respect to a cache memory. It is a characteristic view for demonstrating the relationship between average access time and line size. 1 is a block diagram showing an embodiment of a cache memory according to the present invention. FIG. FIG. 32 is an explanatory diagram of the operation of the cache memory of FIG. 31. It is a timing diagram for explaining each bus cycle in the single chip microcomputer according to the present invention. FIG. 10 is a timing chart for explaining a mode setting operation of the SDRAM. It is a block diagram which shows one Example of SDRAM. It is a block diagram for demonstrating a product-sum operation. It is explanatory drawing of the product-sum operation for the coordinate transformation process of a three-dimensional image process. It is a block diagram which shows one Example of the divider concerning this invention. It is a state transition diagram for demonstrating operation | movement of the said multiplier. FIG. 2 is a layout diagram showing an embodiment of the single chip microcomputer of FIG. 1. It is a schematic block diagram showing an application example of a single chip microcomputer according to the present invention. 1 is a block diagram showing an embodiment of a pen-input portable microcomputer that is an application example of a single-chip microcomputer according to the present invention; FIG.

Explanation of symbols

CPU: Central processing unit, MULT: Multiplier, INTC: Interrupt controller, DMAC: Direct memory access control device, DIVU: Divider, FRM ... Free running timer, WDT ... Watchdog timer, SCI ... Serial communication interface, AB1 to AB4 ... Address bus, DB1 to DB4 ... Data bus, BSC ... Bus state controller, DMAC ... Direct memory access controller, OBIF ... External bus interface, MCTG ... Memory control signal generation circuit, UBC ... Break controller, INTC ... Interrupt controller, CDM Data memory (cache) TAG Tag memory (cache) CAC Cache controller CPG Pulse generation circuit
AB1 ... first address bus, DB1 ... first data bus, AB2 ... second address bus, DB2 ... second data bus, AB3 ... third address bus, DB3 ... third data bus, CB ... control bus, AB4 ... external Address bus, DB4 ... external data bus, B1 ... first bus, B2 ... second bus, B3 ... third bus, B4 ... fourth bus. MCU: Single chip microcomputer, DRAM: Dynamic RAM, SDRAM: Synchronous dynamic RAM, PSRAM: Pseudo static RAM, SRAM: Static RAM
S-MCU ... Slave side microcomputer, M-MCU ... Master side microcomputer.
Q1-Q29 ... MOSFET, N1-N7 ... CMOS inverter circuit, W0, W1 ... word line, DL0, / DL0-DL1, /DL1...complementary data line, CDL0, /CDL0...common data line.
IR ... Instruction register, AB ... Address buffer, DB ... Data buffer, JR ... Divisor register, HRL ... Dividend lower & quotient storage register, HRH ... Dividend upper & remainder storage register, CONT ... Control register, VCT ... Interrupt vector, RAR ... Long-term storage register, RSR ... Commercial long-term storage register, FA & CLA ... Full adder & carry look ahead, AUDA & AUCLA ... 1 adder, LDMCA ... State control circuit, LDMCB ... Overflow processing circuit, LDPRM ... I / O control circuit.
22 ... SDRAM, 30 ... mode register, 200A, 200B ... memory array, 201A, 201B ... row decoder, 202A, 202B ... sense amplifier and column selection circuit, 203A, 203B ... column decoder, 205 ... column address buffer, 206 ... row Address buffer, 207 ... column address counter, 208 ... refresh counter, 210 ... input buffer, 211 ... output buffer, 212 ... controller.

Claims (12)

A central processing unit;
A control circuit having an interface function of a synchronous dynamic RAM connected to the outside; a clock generation circuit capable of forming a plurality of clock signals including a first clock signal supplied to the central processing unit;
A first terminal for supplying a second clock signal to the clock terminal of the synchronous dynamic RAM;
A second terminal for outputting a clock enable signal for the synchronous dynamic RAM;
A third terminal for outputting a select signal to the synchronous dynamic RAM;
When the central processing unit accesses a predetermined address, a part of information of the predetermined address is output to the outside via an external address bus in order to set the mode of the synchronous dynamic RAM.
A row address signal, a column address signal, a write enable signal, and a select signal for outputting to the synchronous dynamic RAM to set the mode when a part of information of the predetermined address is output. Is enabled,
The control circuit outputs the clock enable signal to the synchronous dynamic RAM via the second terminal in synchronization with the second clock signal, and outputs the select signal via the third terminal. Output,
A semiconductor integrated circuit device formed on one semiconductor substrate. Access to the predetermined address by the central processing unit is write access,
The predetermined address is assigned to an internal address of the semiconductor integrated circuit device.
The semiconductor integrated circuit device according to claim 1.   The semiconductor integrated circuit device according to claim 2, wherein the clock generation circuit includes a PLL.   4. The semiconductor integrated circuit device according to claim 3, wherein the clock generation circuit is capable of inputting a clock from the outside in order to form the plurality of clock signals. Furthermore, it has a power supply terminal for PLL,
5. The semiconductor integrated circuit device according to claim 4, wherein power supplied via the PLL power supply terminal is supplied to the PLL.   6. The semiconductor integrated circuit device according to claim 1, wherein the select signal is a signal for designating a start of a command input cycle for the synchronous dynamic RAM. A central processing unit capable of accessing an externally connected synchronous dynamic RAM;
A control circuit for controlling the synchronous dynamic RAM connected to the outside;
A clock generation circuit capable of generating a system clock for supplying to the central processing unit and an operation clock of the synchronous dynamic RAM connected to the outside;
A first terminal for outputting a pre-SL operating clock,
A second terminal for outputting a clock enable signal indicating the validity of the operation clock ;
A third terminal for outputting a chip select signal indicating a selection state of the synchronous dynamic RAM ;
A fourth terminal capable of outputting a row address strobe signal of the synchronous dynamic RAM;
A fifth terminal capable of outputting a column address strobe signal of the synchronous dynamic RAM;
A data processing device formed on a single semiconductor substrate to have a,
When the central processing unit accesses a predetermined address assigned to the internal address of the data processing device in order to set the mode of the synchronous dynamic RAM, a part of information of the predetermined address is externally transmitted. Output,
When the mode of the synchronous dynamic RAM is set, signals output from the second terminal to the fifth terminal are enabled.
The control circuit outputs the operation clock via the first terminal, outputs the clock enable signal via the second terminal, and the chip select signal via the third terminal,
The clock enable signal is activated when the central processing unit performs a write access to the externally connected synchronous dynamic RAM.
Data processing device. The externally connected synchronous dynamic RAM can capture an address signal supplied from the data processing device in synchronization with an edge of the operation clock,
The data processing apparatus according to claim 7, wherein the clock generation circuit includes a PLL. Before SL control circuit outputs with the active state of the row address strobe signal through the fourth terminal, a row address to the outside,
9. The data processing apparatus according to claim 7, wherein the control circuit activates the column address strobe signal via the fifth terminal and outputs a column address to the outside. A central processing unit capable of accessing an externally connected synchronous dynamic RAM;
A control circuit capable of outputting a control signal to the synchronous dynamic RAM;
A pulse generator including a PLL and capable of forming a plurality of clock signals including a clock signal for supply to the central processing unit;
When said central processing unit makes access to Jo Tokoro address, a portion of the predetermined address via the control circuit can perform the synchronous mode setting of a dynamic RAM by being outputted to the outside And
The control circuit externally outputs a plurality of control signals including a clock enable signal for validating a clock signal supplied to the synchronous dynamic RAM and a chip select signal for selecting the synchronous dynamic RAM. Output to
The control circuit is a microcomputer formed on one semiconductor substrate that activates the clock enable signal and the chip select signal in synchronization with a clock signal supplied to the synchronous dynamic RAM. The microcomputer further has a power supply terminal for PLL,
The microcomputer according to claim 10, wherein power supplied via the PLL power supply terminal is supplied to the PLL. The access at the predetermined address is a write access,
12. The microcomputer according to claim 10, wherein the predetermined address is an address assigned for a built-in peripheral.