JP4447667B2 - Data transmission method, data recording apparatus and data reproducing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a data transmission method and a data recording apparatus applicable to copy prevention, unauthorized use prevention, or billing system.as well asThe present invention relates to a data reproducing apparatus.
[0002]
[Prior art]
In recent years, with the increase in capacity and spread of digital recording media such as optical disks, it has become important to prevent copying and prevent unauthorized use. That is, in the case of digital audio data and digital video data, it is possible to easily generate a copy without deterioration by copying or dubbing, and in the case of computer data, the same data as the original data can be easily copied. Therefore, the actual situation is that the harmful effects of illegal copying have already occurred.
[0003]
In order to avoid illegal copying of digital audio data and digital video data, for example, so-called SCMS (serial copy management system) and CGMS (copy generation management system) standards are known. Since a copy prohibition flag is set in a portion, there is a problem that data is extracted by a method such as so-called dump copy.
[0004]
In addition, file contents such as computer data are encrypted and licensed only to authorized users. As a form of information distribution, a digital recording medium in which information is encrypted and distributed is distributed, or an encrypted digital signal is easily available via a wired or wireless transmission path. It is linked to a system that obtains key information for the contents required by the user and obtains the key information and makes it possible to use it by decrypting the code. However, establishment of a simple and useful encryption method is desired. Yes.
[0005]
[Problems to be solved by the invention]
By the way, at the time of data encryption, if the data of the header part of the sector that is the data recording unit or transmission unit is synchronized (sink) or the address data is encrypted, the synchronization or address information is required unless the encryption is broken. Since it cannot be obtained, it may become an obstacle to high-speed access.
[0006]
  The present invention has been made in view of the above-described circumstances, and can be encrypted with a simple configuration, can easily control the degree of difficulty or depth of encryption, and can be harmful to deterioration in high-speed accessibility. Data transmission method and data recording apparatusas well asAn object is to provide a data reproducing apparatus.
[0007]
[Means for Solving the Problems]
  In order to solve the above-described problem, a data transmission method according to the present invention includes a data transmission unit.Located at the beginning of the data transmission unitData transmission method for transmitting error-correction coding processing to input digital data having a header portion and a user data portionBecauseThe number of pieces of data to be subjected to data conversion according to the encryption key information for data excluding at least the header part of the data handled in the error correction coding process It is characterized by changing.
[0008]
  Also, the data recording apparatus according to the present invention performs error correction coding processing on input digital data comprising a header portion and a user data portion whose data recording unit is arranged at the head position of the data transmission unit. A data recording device for recording on a recording medium, wherein at least one of the data handled in the error correction coding process according to the key information input from the input means and the key information from the input means And a means for performing data conversion on the data excluding the header portion and changing the number of data to be subjected to the data conversion.
[0009]
  Furthermore, in the data reproduction method according to the present invention, the data recording unit isLocated at the beginning of the data transmission unitData reproducing apparatus for reproducing a signal recorded on a recording medium by performing error correction coding processing on input digital data having a header portion and a user data portionBecause, Key information input means for inputting encryption key information indicating data conversion to be performed on data excluding at least the header portion of data handled in the error correction encoding process, and the error correction An error correction decoding process corresponding to the encoding process is performed, and data conversion for the data conversion is performed on the data corresponding to the encryption key information from the key information input unit, and the data conversion Error correction decoding means for changing the number of data to be subjected to according to the key information.
[0010]
By performing data conversion according to the encryption key information on the data excluding the header part of the data handled in the error correction coding process, the header part is not subjected to the decryption process of the encryption. Can play. The number of uncorrectable errors increases unless data conversion is performed for decryption according to the key information during reproduction. A desired encryption difficulty level can be realized by changing the number of data to be subjected to data conversion.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0012]
FIG. 1 is a block diagram schematically showing a data recording apparatus to which an embodiment of the present invention is applied.
In FIG. 1, the input terminal 11 is supplied with digital data such as data obtained by digitally converting an analog audio signal or video signal, or computer data, for example. This input digital data is sent to the sectoring circuit 13 via the interface circuit 12, and is sectored in units of a predetermined data amount, for example, 2048 bytes. The sectorized data is sent to the scramble processing circuit 14 and scrambled. The scramble process in this case is intended to randomize the input data so that the same byte pattern does not appear continuously, that is, to remove the same pattern, so that the signal can be read and written appropriately. It is a randomization process. The scrambled or randomized data is sent to the header addition circuit 15, header data arranged at the head of each sector is added, and then sent to the error correction coding circuit 16. The error correction encoding circuit 16 adds a parity by performing data delay and parity calculation. In the next modulation circuit 17, for example, 8-bit data is converted into 16-channel bit modulation data according to a predetermined modulation method, and sent to the synchronization adding circuit 18. The synchronization adding circuit 18 adds a synchronization signal of a so-called out-of-rule pattern that breaks the modulation rule of the predetermined modulation method in units of a predetermined data amount, and sends it to the recording head 20 via a drive circuit, that is, a driver 19. Yes. The recording head 20 performs, for example, optical or magneto-optical recording, and records the modulated recording signal on a disk-shaped recording medium 21. The disk-shaped recording medium 21 is rotationally driven by a spindle motor 22.
[0013]
The scramble processing circuit 14 may be inserted after the header addition circuit 15 to scramble the digital data to which the header is added and send it to the error correction coding circuit 16.
[0014]
Here, the error correction coding circuit 16 performs data conversion according to encryption key information on the data excluding the header portion of the data handled in the error correction coding processing. It has a configuration.
[0015]
Specific examples of the configuration of the error correction coding circuit 16 are shown in FIGS.
2 and 3, the data from the header addition circuit 15 in FIG. 1 is supplied to the input terminal 51 to the C1 encoder 52 as the first encoder. In this specific example, one frame of error correction coding is made up of 148 bytes or 148 symbols of data, and the digital data from the input terminal 51 is collected every 148 bytes and is sent by the first encoder. It is supplied to a certain C1 encoder 52. In the C1 encoder 52, 8-byte P parity is added and sent to the C2 encoder 54, which is the second encoder, via a delay circuit 53 for interleaving. In the C2 encoder 54, a 14-byte Q parity is added, and this Q parity is fed back to the C1 encoder 52 via the delay circuit 55. 170 bytes including the P and Q parities from the C1 encoder 52 are extracted and output via the delay circuit 56 and the rearrangement circuit 57 having the inverter unit 57a of FIG. 3, and are output to the modulation circuit 17 of FIG. Sent.
[0016]
In such an error correction coding circuit, as an encryption process in which data conversion is performed on data excluding the header portion of data handled internally according to encryption key information, for example, For example, each byte of the inverter unit 57a in the array circuit 57 may be selected to turn on or off the inverter according to encryption key information. In other words, in the reference configuration, the inversion by the inverter unit 57a of the rearrangement circuit 57 is performed on the 22-byte P and Q parity, and some of the inverters in these inverter units 57a are eliminated. In some cases, some inverters are inserted on the C1 data side and inverted to be output.
[0017]
When such data conversion is performed, the error-correction probability changes depending on the degree of difference from the reference configuration, and when the difference is small, the error occurrence probability in the final reproduction output is slightly higher, whereas the difference When there is a large number of errors, the error correction is not performed as a whole and almost no reproduction is possible. That is, for example, when looking at the C1 encoder, the so-called distance, which is an index indicating the error correction capability, is 9, so that error detection and correction can be performed up to 4 bytes, and if there is an erasure pointer, correction up to 8 bytes can be performed. Therefore, if there are five or more differences, the C1 code cannot always be corrected. If there are four differences, a subtle situation is indicated in which correction is not possible if an error occurs even with one byte. As the difference decreases to 3, 2, and 1 places, the probability of error correction increases. By using this, when providing audio and video software, etc., it is possible to actively create a playback state that can be played to some extent but is not perfect and sometimes disturbed, etc. Can be used for
[0018]
In this case, for example, a method of prescribing about two places where the inverter is changed in advance, a method of randomly selecting the changed place according to the key information, and limiting the minimum number to about two places, and the like are combined. And a method.
[0019]
Further, the position where the inverter is inserted or changed is not limited to the position of the rearrangement circuit 57 in FIG. 2, and other positions such as a front stage or a rear stage of the C1 encoder 52 or these positions may be combined. Different keys may be used for a plurality of positions. In addition to using an inverter, the above data conversion uses bit addition or various logical operations, transposes data according to encryption key information, or encrypts data key information. You may make it replace according to.
[0020]
Next, the header part of the data handled by the error correction coding circuit will be described.
[0021]
FIG. 4 shows a specific example of the sector format. One sector has a 2048-byte user data area 41, a 4-byte synchronization area 42, a 16-byte header area 43, and a 4-byte error detection code. (EDC) region 44 is added. The error detection code in the error detection code area 44 is composed of a 32-bit CRC code generated for the user data area 41 and the header area 43.
[0022]
In the header area 43, as shown in FIG. 4, a CRC 45 which is a so-called cyclic code, copy information 46 for copying permission / non-permission, copy generation management, etc., and a layer (layer) indicating which layer of the multilayer disk ) 47, address 48, and spare 49 are provided.
[0023]
Here, the header portion in the embodiment of the present invention includes synchronization, that is, sector sync and header information. In the example of FIG. 4, the 4-byte synchronization area 42 and the 16-byte header area 43 A total of 20 bytes of data is the header data. The remaining user data area 41 and error detection code (EDC) area 44 serve as a user data portion.
[0024]
FIG. 5 shows an error correction format when such a header part and user data part are subjected to cross-interleave type error correction coding.
[0025]
The example of FIG. 5 shows a state where the error correction encoding circuit of FIG. 2 and FIG. 3 performs the error correction encoding process on the sector format data of FIG. 4 and includes 20-byte header portions 71 and 2052. The byte user data section 72 constitutes a sector 73 of 2072 bytes. This sector is arranged in a two-dimensional array of 148 bytes in the R / W direction, which is the recording / reproducing direction, and 14 bytes in a direction orthogonal to this, and the C1 direction of error correction is taken in the R / W direction to make 8 bytes. A C1 parity 74 is generated and added, and the C2 direction of error correction is taken in an oblique direction, and a 14-byte C2 parity 75 is generated and added. The above-described data conversion is performed on a portion excluding the portion 76 in the same row as the header portion 71 of the first 20 bytes in the R / W direction of the error correction format of FIG. Note that the data conversion may be performed on a portion excluding the portion 77 in the same column as the header portion 71 in FIG. 5 or a combination thereof.
[0026]
Here, FIG. 6 shows, as another specific example of the error correction coding circuit 16, an exclusive OR (ExOR) as a data conversion means at a position after the inverter unit 57 a in the rearrangement circuit 57, that is, at the output side. An example is shown in which a circuit group 61 is inserted, and an ExOR circuit group 66 as data conversion means is also inserted in the previous stage of the C1 encoder 52, that is, the position on the input side.
[0027]
These ExOR circuit groups 61 and 66 as data conversion means perform data conversion on data excluding 20 bytes corresponding to the portion 76 in FIG. 5 of the error correction format. Specifically, the ExOR circuit group 61 has 170 bytes of data taken out from the C1 encoder 52 via the delay circuit 56 and the inverter 57a of the rearrangement circuit 57, that is, information data C1._{170n + 169}~ C1_{170n + 22} And parity data P1_{170n + 21}~ P1_{170n + 14}, Q1_{170n + 13}~ Q1_170nOf the first 20 bytes of data C1_{170n + 169}~ C1_{170n + 150}150 bytes of data C1 excluding_{170n + 149}~ Q1_170nIs converted to data using an exclusive OR (ExOR) circuit, and the ExOR circuit group 66 is 148 bytes of input data B._148n~ B_{148n + 147}Of which the first 20 bytes of data B_148n~ B_{148n + 19} 128 bytes of data B, excluding_{148n + 20}~ B_{148n + 147}Is converted using an exclusive OR (ExOR) circuit. The ExOR circuits used in these ExOR circuit groups 61 and 66 take the exclusive OR (ExOR) of 1-byte, that is, 8-bit input data and predetermined 8-bit data indicated by 1-bit control data, respectively. There are 150 such 8-bit ExOR circuits (corresponding to inverter circuits when the predetermined 8-bit data is all 1), 150 in the ExOR circuit group 61 and 128 in the ExOR circuit group 66. Used.
[0028]
In FIG. 6, 150-bit key information is supplied to the terminal 62, and is supplied to each of 150 ExOR circuits in the ExOR circuit group 61 via a so-called D latch circuit 63. In response to the 1-bit encryption control signal supplied to the enable terminal 64, the D latch circuit 63 sends the 150-bit key information from the terminal 62 to the ExOR circuit group 61 as it is, or all zero, that is, all 150 bits. Whether or not is set to “0” is controlled. Of the 150 ExOR circuits in the ExOR circuit group 61, the ExOR circuit to which “0” is sent from the D latch circuit 63 outputs the data from the inverter unit 57a in the rearrangement circuit 57 as it is, and D The ExOR circuit to which “1” is sent from the latch circuit 63 converts the data from the inverter unit 57a of the rearrangement circuit 57 and outputs it. When all zeros, the data from the inverter unit 57a of the rearrangement circuit 57 is output as it is. The ExOR circuit group 66 is the same as the ExOR circuit group 61 except that the ExOR circuit group 66 has 128 ExOR circuits and the key information is 128 bits. The key information is sent to each of 128 ExOR circuits in the ExOR circuit group 66 via the D latch circuit 68, and the D latch circuit 68 determines whether the 128-bit key information or all-zero is received by the encryption control signal of the enable terminal 69. Switching control is performed.
[0029]
In the example of FIG. 6, the ExOR circuit group 61 includes information data C1 as 170-byte data extracted from the C1 encoder 52 via the delay circuit 56 and the inverter unit 57a._{170n + 169}~ C1_{170n + 22} And parity data P1_{170n + 21}~ P1_{170n + 14}, Q1_{170n + 13}~ Q1_170nOf the first 20 bytes of data C1_{170n + 169}~ C1_{170n + 150}150 bytes of data C1 excluding_{170n + 149}~ Q1_170nIs converted using an exclusive OR (ExOR) circuit, but parity data is not converted and the remaining 128 bytes of information data C1_{170n + 149}~ C1_{170n + 22} On the other hand, data conversion corresponding to 128-bit key information may be performed.
[0030]
Of course, in the circuit of FIG. 6, the same operation and effect as those of FIGS. 2 and 3 can be obtained. It is also possible to use only one of the ExOR circuit groups 61 and 66, or to select either one or both as the encryption key.
[0031]
Note that AND, OR, NAND, NOR, an invert circuit group, etc. may be used instead of the ExOR circuit groups 61 and 66 as the data conversion means. In addition to performing a logical operation using 1-bit key information or key data in units of 8 bits, a logical operation may be performed on 8-bit information data using 8-bit key data. A combination of AND, OR, ExOR, NAND, NOR, and an invert circuit may be used for each of the 8 bits corresponding to one word. In this case, for example, 128 × 8 bit key data is used for 128 bytes, that is, 128 × 8 bit data, and AND, OR, ExOR, NAND, NOR, and an invert circuit are used in combination. In this case, the combination itself can also be used as a key. In addition to logical operations, transposition that changes the position of data, replacement that replaces data values, and the like can also be used as the data conversion.
[0032]
In the above-described embodiment, an example of a cross-interleave type error correction code has been described. However, the present invention can be similarly applied to a product code as shown in FIG.
[0033]
In the example of FIG. 7, eight sectors of a sector 83 comprising a header part 81 of 20 bytes and a user data part 82 of 2052 bytes have a two-dimensional matrix configuration of 148 bytes long and 112 bytes wide, and are read / written. The C1 parity 84 is generated and added to 148 bytes in the R / W direction, which is the direction, and the C2 parity 85 is generated and added to 112 bytes in the direction orthogonal thereto. In the portion 86 where the C1 and C2 parities intersect, C1 encoding and C2 encoding are doubly applied. In addition, data conversion corresponding to the key information is performed on the data excluding the hatched portion 87 in the same row as the 20-byte header portion 81.
[0034]
Also in the case of this product code, the data excluding the portion 88 in the same column as the header portion 81 may be subjected to data conversion in accordance with the key information. Only the portion excluding both the row portion 87 and the same column portion 88 may be subjected to data conversion according to the key information.
[0035]
Here, in the case of a product code, it is possible to remove only the header portion 81 without removing all of the hatched portion 87 in the same row as the header portion 81, and remove only this header portion 81. The data conversion may be performed on the remaining data. An LDC (Long Distance Code) without C1 parity may be used as an error correction code.
[0036]
As described above, with respect to intermediate data or the like handled at the time of error correction encoding, by performing data conversion on a part of data corresponding to the encryption key information by an inverter or the like, the probability of occurrence of an uncorrectable error is increased. The level of encryption, the depth, the difficulty of decryption, and the like change depending on the number of data to be converted. In other words, the encryption depth and difficulty required according to the application can be arbitrarily set according to the number of data to be converted, and if you want to provide an overview as a sample or want to make it impossible for non-authorized users to reproduce Various measures can be taken according to the case and the request of the security level.
[0037]
Further, since the data conversion is not performed on the header portion at the head of the sector, the sector sync and the sector address can be read quickly, and high-speed access is possible.
[0038]
Here, not only the error correction coding circuit 16 but also at least one of the sectorization circuit 13, the scramble processing circuit 14, the header addition circuit 15, the modulation circuit 17, and the synchronization addition circuit 18 of FIG. In this case, the input is subjected to encryption processing and output. Such encryption key information includes identification information written in an area different from the data recording area of the recording medium 21, such as medium-specific identification information, manufacturer identification information, seller identification information, or a recording device. The identification information unique to the encoder, the identification information unique to the medium manufacturing apparatus such as the cutting machine or the stamper, the identification information supplied from the outside, and the like are used at least in part. As described above, the identification information written outside the data recording area of the medium is, for example, information sent from the interface circuit 12 to the terminal 24 via the TOC (Table of contents) generation circuit 23, and from the interface circuit 12. Information sent directly to the terminal 25. The identification information from these terminals 24 and 25 is used as a part of the key information at the time of encryption. At least one of the circuits 13 to 18, preferably two or more, the input data using this key information is input. Encryption processing is performed.
[0039]
In this case, which circuit of the circuits 13 to 18 has been subjected to the encryption process is also an option, and is considered a key necessary for obtaining a normal reproduction signal during reproduction. That is, if encryption processing is performed in one circuit, it is necessary to select one of six options. If encryption processing is performed in two circuits, one of 30 options is selected. It is necessary to choose. If there is a possibility that encryption processing is performed in 1 to 6 of the 6 circuits 13 to 18, the options increase further, and it is difficult to find this combination by trial and error, It fully plays the role of cryptography.
[0040]
In addition, by switching the encryption key information at a predetermined timing, for example, at a sector period, the encryption level or the difficulty of decryption can be further increased.
[0041]
Next, FIG. 8 shows a disc-shaped recording medium 101 such as an optical disc as an example of the recording medium. The disc-shaped recording medium 101 has a center hole 102 in the center, and leads from the inner circumference to the outer circumference of the disc-shaped recording medium 101 as a TOC (table of contents) area that is a program management area. A (lead in) area 103, a program area 104 in which program data is recorded, and a program end area, a so-called lead out area 105, are formed. In an audio signal or video signal reproducing optical disc, audio and video data are recorded in the program area 104, and time information and the like of the audio and video data are managed in the lead-in area 103.
[0042]
As a part of the key information, it is possible to use identification information or the like written in an area other than the program area 104 which is a data recording area. Specifically, in the lead-in area 103 or the lead-out area 105 which is a TOC area, identification information such as identification information such as a serial number unique to the medium, manufacturer identification information, seller identification information, or a recording device or encoder The unique identification information of the medium and the unique identification information of the medium manufacturing apparatus such as a cutting machine or stamper are written, and at least one, preferably two of the above-described six circuits 13 to 18 are used as key information. The signal obtained by performing the encryption process as described above is recorded in the program area 104 which is a data recording area. At the time of reproduction, the identification information may be used as key information for decrypting the encryption. Also, identification information may be physically or chemically written inside the lead-in area 103, read at the time of reproduction, and used as key information for decrypting the encryption.
[0043]
As encryption, data conversion at the time of the above error correction encoding is always used, and it goes without saying that only data excluding the header part is subjected to data conversion according to encryption key information. is there.
[0044]
Next, a data reproducing apparatus to which the data reproducing method of the present invention is applied will be described with reference to FIG.
[0045]
In FIG. 9, a disc-shaped recording medium 101 as an example of a recording medium is rotationally driven by a spindle motor 108, and the content recorded on the medium is read by a reproducing head device 109 such as an optical pickup device.
[0046]
The digital signal read by the reproducing head device 109 is sent to the TOC decoder 111 and the amplifier 112. From the TOC decoder 111, the identification information recorded as part of the TOC information in the lead-in area 103 of the disc-shaped recording medium 101, for example, identification information such as a serial number unique to the medium, manufacturer identification information, seller identification information Alternatively, the identification information unique to the recording apparatus or encoder, the identification information unique to the medium manufacturing apparatus such as a cutting machine or a stamper is read, and this identification information is used as at least part of the key information for decrypting the encryption. It is done. In addition, the playback device-specific identification information or external identification information may be output from the CPU 122 inside the playback device, and this identification information may be used as at least part of the key information. The identification information from the outside includes identification information received via a communication line, a transmission line, etc., identification information obtained by reading a so-called IC card, ROM card, magnetic card, optical card, etc. It is done.
[0047]
The digital signal taken out from the reproducing head device 109 via the amplifier 112 and the PLL (phase lock loop) circuit 113 is sent to the sync separation circuit 114 and added by the sync adding circuit 18 shown in FIG. Signal separation is performed. The digital signal from the sync separation circuit 114 is sent to the demodulation circuit 115, and the process of demodulating the modulation of the modulation circuit 17 in FIG. 1 is performed. Specifically, the process is such that 16 channel bits are converted into 8-bit data. The digital data from the demodulation circuit 115 is sent to the error correction decoding circuit 116 and subjected to a decoding process as an inverse process of the encoding in the error correction encoding circuit 16 of FIG. Thereafter, the sector decomposition circuit 117 decomposes the data into sectors, and the header separation circuit 118 separates the header of the head portion of each sector. The sector decomposition circuit 117 and the header separation circuit 118 correspond to the sectorization circuit 13 and the header addition circuit 15 shown in FIG. Next, the descrambling processing circuit 119 performs descrambling processing as the reverse processing of the scrambling processing in the scrambling processing circuit 14 of FIG. 1, and the reproduction data is taken out from the output terminal 121 via the interface circuit 120.
[0048]
Here, as described above, during recording, the sectoring circuit 13, the scramble processing circuit 14, the header addition circuit 15, the error correction coding circuit 16, the modulation circuit 17, and the synchronization addition circuit 18 in FIG. Encryption processing is performed in at least one of the circuits including the error correction encoding circuit 16, and the encryption is decrypted by the reproduction side circuits 114 to 119 corresponding to the circuit subjected to the encryption processing. Processing is required. That is, when encryption processing is performed in the sectorization circuit 13 of FIG. 1, the sector decomposition circuit 117 requires encryption decryption processing using key information at the time of encryption. . Similarly, the encryption / decryption process in the descrambling circuit 119 corresponds to the encryption process in the scramble processing circuit 14 in FIG. 1, and the header corresponding to the encryption process in the header addition circuit 15 in FIG. Each of the encryption / decryption processes in the separation circuit 118 is required. The encryption processing in the error correction encoding circuit 16 of FIG. 1 is always performed, and the encryption / decryption processing in the error correction decoding circuit 116 is required corresponding to this. In addition, when encryption processing is performed in the modulation circuit 17 of FIG. 1, the encryption / decryption processing in the demodulation circuit 115 correspondingly corresponds to the encryption processing in the synchronization addition circuit 18 in FIG. Therefore, the encryption / decryption processing in the synchronization separation circuit 114 is required for each case.
[0049]
Here, in the error correction decoding circuit 116, for example, the reverse processing of the error correction coding processing of FIG. 2 and FIG. 3 is performed by the configuration of FIG. 10 and FIG.
[0050]
10 and FIG. 11, the rearrangement circuit 142 having the inverter unit 142a of FIG. 11 is input to the input terminal 141 as a group of 170 bytes or 170 symbols of data demodulated by the demodulation circuit 115. Via the delay circuit 143 to the C1 decoder 144 as the first decoder. Of the 170 bytes of data supplied to the C1 decoder 144, 22 bytes are P and Q parity, and the C1 decoder 144 performs error correction decoding using these parity data. 170-byte data is output from the C1 decoder 144 and sent to the C2 decoder 146, which is the second decoder, via the delay circuit 145, and error correction decoding using parity data is performed. Output data from the C2 decoder 146 is sent to the delay / C1 decode circuit 140 of FIG. This is similar to the delay circuit 143 and the C1 decoder 144, and performs error correction decoding by repeatedly performing the same processing as the delay circuit 143 and the C1 decoder 144. In the example of FIG. 11, a delay circuit 147 and a C3 decoder 148 as a third decoder are used. The final error correction decoding is performed by the delay circuit 147 and the C3 decoder 148 or the delay / C1 decoding circuit 140, and 148-byte data without parity is taken out via the output terminal 149. The 148-byte data corresponds to the 148-byte data input to the C1 encoder 52 shown in FIGS.
[0051]
Then, the inverter 57a of the rearrangement circuit 57 of the error correction coding circuit of FIGS. 2 and 3 performs the error correction of FIGS. 10 and 11 by encryption based on the presence or absence of the inverter, that is, data conversion according to the key information. It is necessary to perform corresponding encryption / decryption in the inverter unit 142a in the rearrangement circuit 142 of the decryption circuit. However, since the data conversion is performed only on the data excluding the header part, the decoding is performed only on the data excluding the header part. In addition, corresponding to the various encryption processes described with reference to FIGS. 2 and 3, it is needless to say that encryption / decryption, which is an inverse process for decrypting the encryption, is required.
[0052]
Next, FIG. 12 is a diagram showing a specific configuration of the error correction decoding circuit corresponding to the specific configuration of the error correction encoding circuit of FIG.
[0053]
In FIG. 12, corresponding to the ExOR circuit group 61 inserted on the output side of the rearrangement circuit 57 in FIG. 6, the positions of the inverter unit 142a of the rearrangement circuit 142 and the input side of the delay circuit 143 are positioned. The ExOR circuit group 151 is inserted, and the ExOR circuit group 156 is inserted on the output side of the C3 decoder 148 corresponding to the ExOR circuit group 66 inserted on the input side of the C1 encoder 52 of FIG.
[0054]
As described above, these ExOR circuit groups 151 and 156 perform data conversion for decoding data conversion on data excluding the header portion of the sector. The ExOR circuit group 151 includes 150 8-bit data. The ExOR circuit and the ExOR circuit group 156 are each composed of 128 8-bit ExOR circuits. If the ExOR circuit group 61 of the error correction encoding circuit in FIG. 6 on the recording side performs data conversion according to key information on 128-byte information data excluding parity data, the ExOR circuit Of course, the group 151 includes 128 8-bit ExOR circuits.
[0055]
The terminal 152 in FIG. 12 is supplied with 150-bit key information corresponding to the key information supplied to the terminal 62 in FIG. 6, and each of the 150 pieces in the ExOR circuit group 151 via the so-called D latch circuit 153. It is supplied to each ExOR circuit. In response to the 1-bit encryption control signal supplied to the enable terminal 154, the D latch circuit 153 sends the 150-bit key information from the terminal 152 to the ExOR circuit group 151 as it is, or is all zero, that is, all 150 bits. Whether or not is set to “0” is controlled. The ExOR circuit group 156 has 128 ExOR circuits, and the ExOR circuit group 151 has the same configuration as that of the ExOR circuit group 151 except that the key information is the same 128 bits as the key information supplied to the terminal 67 in FIG. The 128-bit key information supplied to the terminal 157 is sent to the 128 ExOR circuits in the ExOR circuit group 156 via the D latch circuit 158, and the D latch circuit 158 is connected to the enable terminal 159. Switching between 128-bit key information and all zeros is controlled by the encryption control signal.
[0056]
In this way, simple and large encryption can be realized by using the inverter of the error correction circuit as a key for encryption. Also, by controlling the number of inverters, it is possible to respond to security level requirements, such as encryption level data that cannot be absolutely reproduced or data that cannot be reproduced when an error state deteriorates. In other words, by controlling the number of inverters, ExOR circuits, etc., it is possible to control the playback so that it can be played back when the error condition is good, and cannot be played back when it becomes bad. Possible states can also be formed. Further, as the encryption key, the number of bits is as large as several hundreds of bits per place as in the example shown in the figure, and encryption with a large number of bits of the key can be performed, so that data security is improved. Moreover, by implementing such an error correction coding circuit and error correction decoding circuit in the hardware of so-called LSIs and IC chips, it is difficult for general users to access, and in this respect data security is also high. It has become a thing.
[0057]
In addition, since data conversion is not performed on the data in the header part of the sector, it is not necessary to perform data conversion for decryption of the sector sync (synchronization) and the sector address in the header part at the time of reproduction. Is possible.
[0058]
Note that the present invention is not limited to the above-described embodiments. For example, as data conversion, an example of an inverter or ExOR is shown. However, data conversion by bit addition, various logical operations, or the like is also possible. Of course, it is also possible to perform the above. In addition, various modifications can be made without departing from the scope of the present invention.
[0059]
【The invention's effect】
According to the present invention, since data conversion is performed in accordance with encryption key information for data excluding the header portion of the data handled in the error correction encoding process, Since the process of breaking the encryption is unnecessary and the data in the header portion can be obtained quickly, high-speed access is possible. Further, it is possible to perform encryption at an arbitrary level from a state where data can be restored to some extent by error correction processing to a state where data cannot be restored. As a result, it is possible to perform control so that playback can be performed when the error state is good, and playback cannot be performed when the error state is bad, and it is possible to cope with data according to the purpose of data provision or according to the security level.
[0060]
Furthermore, encryption with a large number of bits of the key is possible in the error correction process, and since encryption is realized in a huge black box such as error correction encoding or decoding IC or LSI, Decryption by general users can be made difficult, and data security can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a data recording apparatus to which an embodiment of the present invention can be applied.
FIG. 2 is a diagram illustrating a schematic configuration of an example of an error correction coding circuit.
FIG. 3 is a diagram illustrating a specific configuration of an example of an error correction coding circuit.
FIG. 4 is a diagram illustrating an example of a sector format.
FIG. 5 is a diagram illustrating an example of a cross interleave type error correction code.
FIG. 6 is a diagram showing another specific example of an error correction coding circuit.
FIG. 7 is a diagram illustrating an example of an error correction code in the case of a product code.
FIG. 8 is a diagram illustrating an example of a data recording medium.
FIG. 9 is a block diagram showing a schematic configuration of a data reproducing apparatus to which the embodiment of the present invention can be applied.
FIG. 10 is a diagram illustrating a schematic configuration of an example of an error correction decoding circuit.
FIG. 11 is a diagram illustrating a specific configuration of an example of an error correction decoding circuit.
FIG. 12 is a diagram illustrating another example of an error correction decoding circuit.
[Explanation of symbols]
13 Sectorization circuit
14 Scramble processing circuit
15 Header addition circuit
16 Error correction coding circuit
17 Modulation circuit
18 Synchronization additional circuit
52 C1 encoder
53, 55, 56, 143, 145, 147 delay circuit
54 C2 encoder
57, 142 rearrangement circuit
57a, 142a Inverter part
61, 66, 151, 156 ExOR circuit group
114 Sync separation circuit
115 Demodulation circuit
116 Error correction decoding circuit
117 Sector decomposition circuit
118 Header separation circuit
119 Descramble processing circuit

Claims (6)

A data transmission method for transmitting error correction coding processing to input digital data comprising a header portion and a user data portion arranged at the head position of the data transmission unit .
The data handled at the time of the error correction coding process is subjected to data conversion in accordance with the key information of encryption for data excluding at least the header part, and the number of data to be subjected to the data conversion is determined. A data transmission method characterized by changing.   2. The data transmission method according to claim 1, wherein the data conversion is performed by a logical operation between the data and encryption key information.   2. The data transmission method according to claim 1, wherein the encryption key information includes identification information at least in part.   2. The data transmission method according to claim 1, wherein the data to be subjected to the data conversion is data excluding data in the same row or the same column as the header portion in the error correction code matrix. A data recording apparatus for performing error correction coding processing on input digital data having a header unit and a user data unit arranged at the head position of a data transmission unit and recording the data on a recording medium. And
Means for inputting encryption key information;
In accordance with the key information from this input means, the data to be processed at the time of the error correction coding process is subjected to data conversion on data excluding at least the header part, and the number of data to be subjected to the data conversion And a data recording device. A signal recorded on a recording medium after error correction coding processing is applied to input digital data having a header portion and a user data portion whose data recording unit is arranged at the head position of the data transmission unit A data reproducing device for reproducing
Key information input means for inputting encryption key information indicating data conversion to be performed on data excluding at least the header part of data handled in the error correction encoding process;
Performing error correction decoding processing corresponding to the error correction encoding processing, performing data conversion for decryption with respect to the data conversion to data corresponding to the key information of encryption from the key information input means, An error correction decoding means for changing the number of data to be subjected to data conversion according to the key information.

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