JP4446792B2 - Calibration apparatus and calibration method in DA converter system - Google Patents

Description

  The present invention relates to a DA converter system and a calibration method for outputting a gain-controlled analog signal with a digital signal as an input, and in particular, an accurate calibration operation is performed during a calibration period and during a normal operation period (during a non-calibration period). The present invention relates to a DA converter system having a noise shaper and a calibration method capable of preventing the generation of a clicking sound when changing the gain.

  In a digital audio system such as a CD player or a DVD player, a digital signal extracted from a medium is converted into an analog signal by a DA converter, and a speaker or a headphone is sounded. There may be some offset due to manufacturing variations of circuit elements.

  For example, in the case of a system that operates with both positive and negative power supplies and a signal system that is centered on zero volts (ground potential), this offset is an input intended to output a ground potential with respect to zero volts (ground potential) as a preset voltage. This is the voltage difference of the DA converter output with respect to the code.

  In the case of a signal system centered on a predetermined operating point (analog ground potential) in a system operating between the positive power source and ground, the intention is to output the analog ground potential for the predetermined operating point (analog ground potential). Is the voltage difference of the DA converter output with respect to the input code.

  The offset as described above does not appear in the output signal when the DA converter is in the off state, but appears when it is in the on state.

  Therefore, when the DA converter is turned from the off state to the on state, or when the DA converter is turned from the on state to the off state, “step noise” corresponding to the offset voltage is generated in the output signal, which is audibly uncomfortable. Therefore, a DA converter that does not have such an offset is strongly desired.

  Therefore, as a representative means for eliminating the offset difference for eliminating the “step noise” noise, a means for blocking the DC signal component by inserting a capacitor in series between the DA converter and the analog volume circuit. And a means for providing a calibration period for calibrating the offset and performing an operation to eliminate the offset difference during the calibration period.

  In the case of the former means for blocking, a capacitor of about 0.1 uF to 10 uF is usually required, and it cannot be very integrated in a semiconductor integrated circuit.

  Adding a capacitor element to the outside of a semiconductor integrated circuit is a great advantage for portable audio devices that are constantly aiming for miniaturization.

Japanese Patent Publication No. 5-599102

  Therefore, it is most strongly desired that the latter calibration period is provided and a means for performing an operation for eliminating the offset difference during the calibration period is appropriately implemented in the semiconductor circuit. The following means are described as means for calibrating the offset difference.

  FIG. 16 shows an example of a conventional system configuration (see Patent Document 1) comprising means for calibrating the offset difference.

  The system 100 for calibrating the offset difference includes a digital addition block 101, a converter 102 (DAC), a gain control circuit 103, a calibration circuit 104, and an offset register 105.

  In this configuration, the calibration circuit 104 extracts a part of the analog output signal 120 output from the gain control circuit 103 (that is, the analog volume circuit) during the calibration period, and is included in the analog output signal 120. Detect the offset.

  The calibration circuit 104 performs a process of adding a digital signal 130 that cancels an offset difference between the digital input signal 110 and the analog output signal 120 to the digital input signal 110 in a normal operation state that is a non-calibration period.

  However, in such a calibration process, it is necessary to extend the operation bit width of the input of the DA converter 102 to the upper bit side by the digital signal 130 that cancels the added offset difference, and the circuit scale of the DA converter 102 itself increases. There is a problem that it ends up.

  Furthermore, in the system of Patent Document 1, the calibration operation of the DA converter 102 in the DA converter system having the noise shaper is not described in detail, and the importance to be overcome at the time of the calibration operation in the case of the DA converter 102 including the noise shaper. However, no countermeasures are taken against local signal peaks due to noise shaping.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a DA converter system including a noise shaper that is small without increasing the circuit scale of the DA converter and that does not generate an offset during a normal operation period (normal state). A DA converter system and a calibration method capable of performing an accurate calibration operation even for a local signal peak due to noise shaping without generating a step noise when switching from an ON state to an OFF state. It is to provide.

The present invention provides a DA converter system that sequentially inputs a digital input signal to a DA converter noise shaper and a DA converter circuit, converts the analog input signal into an analog output signal, and outputs the analog output signal when the DA converter is not operating. A calibration device that calibrates an offset difference between an offset of a signal and an offset of the analog output signal output during an operation period of the DA converter, wherein the DA converter performs the DA conversion of the DA converter during a non-operation period In the circuit, a reference signal input means for inputting a reference offset signal for predetermined offset adjustment in place of the digital signal output from the noise shaper, and a time point when the offset difference with respect to the reference offset signal becomes zero The operating point adjustment signal for offset adjustment Creating an operating point adjustment signal generating means for inputting the operating point adjustment signal to the DA converter circuit, and sequentially comparing the operating point adjustment signal with respect to the reference offset signal to obtain an offset difference between the signals; Offset difference detection means for detecting the value of the operating point adjustment signal when the offset difference becomes zero value, and offset calibration information corresponding to the operating point adjustment signal when the detected offset difference becomes zero value In the operation period of the DA converter in the operation period of the DA converter, the output is output from the DA converter in the operation period by adjusting the operation point of the DA converter based on the offset calibration information stored in the calibration period. Between the analog output signal and the analog control signal output from the DA converter during the non-operation period. Wherein the bets difference equipped with adjustment means to prevent the occurrence.

  Here, the digital input signal may be a digital signal weighted by a power of 2, or a digital signal having a plurality of unweighted bits having an equivalent weight.

The present invention provides a DA converter system that sequentially inputs a digital input signal to a digital interpolation filter, a noise shaper, and a DA converter circuit of a DA converter, converts the digital input signal into an analog output signal, and outputs the analog output signal. A calibration apparatus that calibrates an offset difference between the offset of the analog output signal output to the analog converter and the offset of the analog output signal output during the operation period of the DA converter, and Reference signal input means for inputting a predetermined offset adjustment reference offset signal to the DA converter circuit of the DA converter instead of the digital signal output from the noise shaper, and an offset difference with respect to the reference offset signal is zero To detect when An operating point adjustment signal for offset adjustment is sequentially created, and the operating point adjustment signal generating means for inputting the operating point adjustment signal to the DA converter circuit is sequentially compared with the reference offset signal. An offset difference detecting means for obtaining an offset difference between the signals and detecting the value of the operating point adjustment signal when the offset difference becomes zero, and an operation when the detected offset difference becomes zero By adjusting the operating point of the DA converter based on the offset calibration information stored in the calibration period in the operating period of the DA converter in the storage means for storing the offset calibration information corresponding to the point adjustment signal An analog output signal output from the DA converter during the operation period and an output signal from the DA converter during the non-operation period Is the is characterized in that comprises an adjustment means to allow the offset difference does not occur between the analog control signal.

The digital input signal is a digital signal weighted by a power of 2 or an unweighted digital signal having a plurality of bits having an equivalent weight, and the digital signal is interpolated by the digital interpolation filter The digital signal output from the noise shaper after noise shaping the interpolated digital signal is a weighted digital signal with a power of 2 having a bit number smaller than the bit number of the digital input signal, or equivalent It is a digital signal having a plurality of unweighted bits with weights.

The digital signal output from the noise shaper is a digital signal having a plurality of bits having an equivalent weight.

  The reference offset signal input to the DA converter circuit during the calibration period may be a code pattern made up of a single code.

  The reference offset signal input to the DA conversion circuit during the calibration period may be a code pattern in which at least two codes are repeated in a preset pattern.

  A randomizer for controlling the bit position of the digital input signal may be provided between the digital noise shaper and the DA converter circuit.

According to the present invention, when a digital input signal is sequentially input to a noise shaper of a DA converter and a DA converter circuit and converted into an analog output signal and output, the offset of the analog output signal output by the DA converter during a non-operation period. And a calibration method for calibrating an offset difference from the offset of the analog output signal output during an operation period of the DA converter, wherein the DA converter is connected to the DA converter circuit of the DA converter during a non-operation period. In place of the digital signal output from the noise shaper, a step of inputting a reference offset signal for predetermined offset adjustment, and an offset adjustment for detecting a time point when an offset difference with respect to the reference offset signal becomes zero value. The operating point adjustment signal is sequentially generated, and the operating point adjustment signal is The step of inputting to the conversion circuit and the operation point adjustment signal are sequentially compared with the reference offset signal to obtain an offset difference between the signals, and the operation point adjustment signal at the time when the offset difference becomes zero value. A step of detecting a value, a step of storing offset calibration information corresponding to an operating point adjustment signal at the time when the detected offset difference becomes zero, and a calibration period in the operation period of the DA converter. By adjusting the operating point of the DA converter based on the stored offset calibration information, an analog output signal output from the DA converter in the operating period and an analog output signal from the DA converter in the non-operating period And a step of preventing an offset difference from occurring between the control signal and the control signal.

According to the present invention, when a digital input signal is sequentially input to a digital interpolation filter, a noise shaper, and a DA converter circuit of a DA converter to be converted into an analog output signal and output, the DA converter outputs it during a non-operation period. A calibration method for calibrating an offset difference between an offset of the analog output signal and an offset of the analog output signal output during an operation period of the DA converter, wherein the DA converter is in a non-operation period of the DA converter. A step of inputting a reference offset signal for predetermined offset adjustment to the DA converter circuit instead of the digital signal output from the noise shaper, and a time point when the offset difference with respect to the reference offset signal becomes zero. Operating point adjustment signal for offset adjustment Sequentially generating and inputting the operating point adjustment signal to the DA converter circuit, and sequentially comparing the operating point adjustment signal with respect to the reference offset signal to obtain an offset difference between the signals, A step of detecting the value of the operating point adjustment signal at the time when the zero value is reached, a step of storing in the memory offset calibration information corresponding to the operating point adjustment signal at the time when the detected offset difference becomes the zero value, In the operation period of the DA converter, by adjusting the operating point of the DA converter based on the offset calibration information stored in the calibration period, the analog output signal output from the DA converter in the operation period and the Prevent an offset difference from the analog control signal output from the DA converter during a non-operation period And characterized in that it comprises a and extent.

  According to the present invention, in a DA converter system including a noise shaper, a predetermined offset adjustment reference offset signal is input to a DA conversion circuit during a calibration period, and an offset is applied to the DA converted reference offset signal. Compare the comparison signals, detect the value of the offset comparison signal when the offset difference becomes zero, store the detected offset comparison signal as offset calibration information, and store the offset stored in the calibration period during the operation period Since the operation point of the DA converter or the gain control circuit of the analog volume circuit is adjusted based on the calibration information, the analog output signal of the DA converter and the analog control signal of the analog volume circuit during the operation period are adjusted. Offset difference between them can be eliminated. Ri, compact without increasing the circuit scale of the DA converter and the analog volume circuit, and Noizushe - can be performed even accurate calibration operations to local signal peak by ping.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First example]
A first embodiment of the present invention will be described with reference to FIGS.
(Constitution)
FIG. 1 shows a configuration example of a DA converter system 1 according to the present invention.
The DA converter system 1 includes a DA converter 2 and a calibration circuit 4.

  The DA converter 2 includes a digital noise shaper 11 to which a digital input signal 20 is input, a DA converter circuit 12 to which a noise-shaped digital signal 21 is input, and a switch unit 14 that switches an input signal.

  The digital input signal 20 is a power signal that is weighted to a power of 2, or a digital signal that is not weighted and has an equivalent weight.

  In this example, a code pattern 50 composed of a single code is used as the reference offset signal.

FIG. 2 shows the internal configuration of the calibration circuit 4.
The calibration circuit 4 includes a CPU 30, a code pattern generation unit 13, an adjustment signal generation circuit 31, a detection circuit 32, and a storage circuit 33.

The calibration circuit 4 calibrates the offset difference between the analog output signal 22 output from the DA converter 2 during the non-operation period (calibration period) and the analog control signal 22 output from the DA converter 2 during the operation period. .
The code pattern generator 13 is a circuit that generates a reference offset signal to be input to the DA converter circuit 12 during the calibration period.

  Here, an example of a code pattern generation method and an input method to the DA conversion circuit 2 will be described.

  As a method of generating a code pattern, in the case of a fixed value code pattern, there are (1) a method generated by a hard wire logic, and (2) a method of outputting a code stored in a ROM or SRAM.

  As another generation method, when two codes are output alternately (or a plurality of codes in a predetermined periodic pattern), (1) Two codes made of hard wire are alternately displayed. There are a method for selective output, (2) a method for periodically reading and outputting a code from a plurality of ROMs and SRAMs, and (3) a method for obtaining a code output having periodicity by giving a clock to a counter circuit.

  As a simple input method to the DA conversion circuit 2, there is a method of inputting the generated code pattern to the DA conversion circuit 2 as a multi-bit parallel signal.

  As another input method, a method of serially transferring the analog signal to the DA conversion circuit 2 and assembling an analog signal bit by bit. After receiving all bits serially in the DA conversion circuit 2, a DA conversion process is performed in parallel. There is a method of converting to an analog signal.

The adjustment signal generation circuit 31 outputs an operating point adjustment signal 40 to the DA converter 2.
The CPU 30 includes a control circuit such as a DSP.
The detection circuit 32 includes a comparator and the like.

  The detection circuit 32 receives the analog output signal 22 output from the DA converter 2 during the calibration period, detects whether the offset comparison result is H or L, and sends the detection result to the CPU 30.

  The storage circuit 33 includes a storage element such as an SRAM circuit or a flip-flop, and stores the detection result as offset calibration information 60.

  The offset calibration information 60 may be stored in a storage device or the like provided outside the calibration circuit 4.

(Operation)
Hereinafter, the operation of the DA converter system 1 will be described.
In FIG. 1, when a digital input signal 20 consisting of a digital signal weighted by a power of 2 or a digital signal having an equivalent weight and a plurality of unweighted bits is input to the DA converter 2, The input signal is converted by the noise shaper 11 into a noise shaped digital signal 21.

  In this case, the digital input signal 20 and the digital signal 21 output from the digital noise shaper 11 have the same rate. Therefore, the digital input signal 20 input to the digital noise shaper 11 is output as a digital signal 21 having the same signal rate and is introduced into the DA conversion circuit 12.

  The DA conversion circuit 12 DA-converts the noise-shaped digital signal 21 to convert it into an analog output signal 22 and outputs it. The analog output signal 22 is also introduced into the calibration circuit 4 for offset calibration.

(Offset calibration process)
The offset calibration process of the calibration circuit 4 in FIG. 2 will be described.
The CPU 30 controls the adjustment signal generation circuit 31 so as to gradually change the value of the operating point adjustment signal 40 that is an analog signal, and when the detection result from the detection circuit 32 changes (that is, the offset difference becomes zero). At the time when the offset adjustment is completed), the control for changing the operating point adjustment signal 40 is terminated.

  Further, the CPU 30 writes the offset calibration information 60 corresponding to the operating point adjustment signal 40 at the time when the offset adjustment is completed in the storage circuit 33.

  Further, the CPU 30 outputs a calibration instruction signal 41 intended for the calibration period to the DA converter 2.

  Here, an input switching method of how to perform input switching with a digital signal in the DA converter 2 will be described.

  As the simplest input switching method, there is a method of switching between a digital signal and an offset generation pattern signal by providing an alternative switch in the path. In this case, the same number of switches as the number of bits are provided in the case of a parallel signal, and one switch is provided in the case of a serial signal. The switch path selection is controlled by a calibration instruction signal 41 (a signal for distinguishing between a calibration period and a normal operation period) output from the CPU 30.

  During the non-calibration period (normal operation period), the CPU 30 reads the offset calibration information 60 corresponding to the time point when the offset adjustment stored during the calibration period is completed from the storage circuit 33, and according to the offset calibration information 60. An operating point adjustment signal 40 for eliminating the offset difference is generated from the adjustment signal generation circuit 31 and sent to the DA conversion circuit 12 of the DA converter 2.

  FIG. 3 summarizes the procedure of offset calibration processing in this system as a flowchart.

  In step S1, it is determined whether it is during a calibration period or during a normal operation period. If it is during the calibration period, the process proceeds to step S2. On the other hand, during the normal operation period, the process jumps to step S5.

  In step S2, the calibration instruction signal 41 is output to the DA converter 2 to switch the input. By this input switching operation, a single code pattern 50 (reference offset signal) generated by the code pattern generation unit 13 is replaced with the DA conversion circuit 12 instead of the digital signal 21 output from the digital noise shaper 11 until then. Is input.

  At the same time, the calibration circuit 4 outputs an operating point adjustment signal 40 (offset comparison signal) for offset adjustment to detect an operating point at which the offset difference is zero.

  For example, calibration can be performed by adjusting the voltage applied to the non-inverting input terminal (+) of the operational amplifier 90 in the DA converter circuit 12 shown in FIG.

  In step S3, the DA conversion circuit 12 compares the operating point adjustment signal 40 with the analog-converted code pattern 50.

  This comparison result is sent to the detection circuit 32 of the calibration circuit 4 shown in FIG. In this determination, the value of the operating point adjustment signal 40 is detected when the magnitudes of both the signals 40 and 50 are the same, that is, when the offset difference becomes zero.

  In step S4, the offset calibration information 60 corresponding to the operating point adjustment signal 40 at the time when the detected offset difference becomes zero is stored in the storage circuit 33.

  In step S5, during the normal operation period, an operating point adjustment signal 40 is generated based on the offset calibration information 60 stored during the calibration period, and this operating point adjustment signal 40 is input to the DA converter 2 to enter the operating point. Adjust.

  Here, an example of a method of adjusting using the operating point adjustment signal 40 based on the offset calibration information 60 stored during the calibration period during the normal operation period will be described.

  The stored offset calibration information 60 refers to a signal (or code, information) that can instruct a circuit configuration for generating an analog operating point signal that can eliminate an offset difference upon completion of a calibration operation.

  That is, for example, the adjustment signal generation circuit 31 is configured by a DA converter, and an analog signal is output in correspondence with a digital code (a sufficient number of bits for obtaining a desired resolution). A digital code corresponding to an analog signal to be output by the DA converter is stored as offset calibration information 60.

  As a specific example of the adjustment means, during a normal operation period, the CUP 30 instructs the adjustment signal generation circuit 31 to output the offset calibration information 60 stored in the storage circuit 33, so that a constant analog value is output. A signal is output. The generation of the analog signal having a constant value is started simultaneously with the end of the calibration period or when an instruction to start the normal operation is given from the outside, and remains constant during the normal operation period. In this normal operation state, the input to the DA converter 2 is not a fixed pattern signal but a digital signal input.

  By such offset calibration processing, between the offset of the analog output signal 22 output from the DA converter 2 during the operation period and the offset of the analog output signal 22 output from the DA converter 2 during the non-operation period, Adjustment can be made so as not to cause an offset difference.

  As described above, the calibration process can be performed based on the analog output signal 22 obtained by DA-converting the code pattern 50 including a single code that does not include the shaping noise that is locally large noise. With this configuration, it is possible to perform an accurate calibration process, and it is possible to eliminate the occurrence of a clicking sound (offset step) during the operation period of the system.

[Second example]
A second embodiment of the present invention will be described with reference to FIGS. In addition, about the same part as the 1st example mentioned above, the description is abbreviate | omitted and the same code | symbol is attached | subjected.
(Constitution)
FIG. 4 shows the configuration of the DA converter system 1.
In the DA converter system 1 of this example, the DA converter 2 is configured by sequentially connecting a digital interpolation filter 70, a digital noise shaper 11, a DA converter circuit 12, and an analog low-pass filter 71. 20 is converted into an analog output signal 22 and output.

  The digital input signal 20 is a power signal that is weighted to a power of 2, or a digital signal that has an equal weight and has a bit number of at least 16 bits.

The digital noise shaper 11 converts a high-speed power-of-two-weighted digital signal having a smaller number of bits than the noise-shaped 16 bits, or a digital signal having a plurality of unweighted bits with equivalent weights. To do.
The reference offset signal generated by the code pattern generation unit 13 is a code pattern 51 including a pattern in which two codes are alternately repeated. The code pattern 51 is input to the DA conversion circuit 12 during the calibration period after input switching is performed based on the calibration instruction signal 41 output from the calibration circuit 4.
Other configurations are the same as those in FIG.

(Operation)
The operation of this system will be described below.
In the DA converter system 1, a digital input signal 20 having a large number of bits, such as 16 bits, is interpolated by a digital interpolation filter 70.

  The digital input signal 20 input to the digital interpolation filter 70 is output as a digital signal having a faster signal rate than the input signal rate, and the digital signal having the higher signal rate is input to the digital noise shaper 11.

  The digital noise shaper 11 noise-shapes the input digital signal having a high signal rate by the digital noise shaper 11 and outputs the digital signal as a digital signal having the same rate as the input high signal rate. To introduce.

  Therefore, the digital input signal 20 and the noise-shaped digital signal 21 output from the digital noise shaper 11 have different rates.

(Offset calibration process)
The offset calibration process of this system will be specifically described.
<Non-calibration period: Normal operation>
First, the operation in the normal state will be described.
In FIG. 5, the digital input signal 20 is, for example, a 16-bit 44.1 KHz audio digital signal represented by 2's complement, and a code in the no-signal state is represented by a midscale code (that is, an all-zero code).

  The digital interpolation filter 70 interpolates the digital input signal 20 at a rate of 8 times, and further, the same data 16 times at the rate of 16 times (that is, the rate of 128 times the input to the DA converter 2). Is output.

  The digital signal output from the digital interpolation filter 70 is a digital signal having a bit number of 16 bits or 16 bits or more in order to obtain the same resolution as the input.

  The digital noise shaper 11 is a third-order delta sigma modulator, for example, and outputs an output at the same rate as the signal rate input to this block (that is, a rate 128 times higher than the input to the DA converter 2).

  In this example, the output from the digital noise shaper 11 is an 8-bit equivalent unweighted 8-bit (ie, 8-level) signal, and is expressed by 8 levels from “code 0” to “code 7”. Is done.

  Further, the 3-bit (ie, 8-level) signal 80 is converted into an equivalent 8-bit signal 81 that is not weighted in the relationship as shown in FIG.

  The DA converter circuit 12 generates an analog signal 22 in accordance with the digital signal 21 output from the 8-bit digital noise shaper 11.

FIG. 6 shows the configuration of the DA converter circuit 12 composed of a switched capacitor circuit.
There are eight input elements, and charges corresponding to “1” or “0” of each signal output from the digital noise shaper 11 are input in synchronization with the clock.

  That is, when the clock is at the H level, the switch pointed to by P1 is turned on, and the switch pointed to by P2 is turned off. When the clock is at L level, the switch pointed to by P1 is turned off, and the switch pointed to by P2 is turned on.

  Assuming that the capacitance of each input element is C, when each bit of the digital signal 21 output from the digital noise shaper 11 is “1”, the charge amount ((+ VREF) − (VGND)) × C is “0”. In this case, the charge amount ((−VREF) − (VGND)) × C is input every clock cycle.

  This clock can be made equal to the rate of the digital signal 21 output from the digital noise shaper, (+ VREF) is a positive power supply voltage, (−VREF) is a negative power supply voltage or ground potential, and (VGND) is ( + VREF) and (−VREF) can be set to the midpoint voltage.

  The analog signal 22a is output from the output terminal 91 of the operational amplifier 90 connected to the output stage of the DA converter circuit 12 in FIG.

  The analog low-pass filter 71 shown in FIG. 4 is also realized by the feedback capacitor Cfb and the switched capacitor C2 of the DA converter circuit 12 shown in FIG. 6, but is configured as a smoothing filter having the operational amplifier 93 shown in FIG. It can also be output as an analog signal.

  In such a DA converter system 1, between the offset of the analog output signal 22 output from the DA converter 2 during the non-operation period and the offset of the analog output signal 22 output from the DA converter 2 during the operation period. If there is an offset difference, step noise (bottom noise) is generated when the off state is turned on and when the on state is turned off.

  Therefore, prior to the normal state, a calibration period as shown below is provided, and calibration is performed using the calibration circuit 4 to eliminate the offset difference.

<Calibration period>
Next, the operation during the non-operation period (calibration period) will be described.
In the calibration period, in this example, for example, the DA converter 2 as shown in FIGS. 4 and 7 outputs an offset voltage, and the offset of the analog output signal 22 output from the analog low-pass filter 71 is adjusted. Process to eliminate the difference.

  If the input of the DA converter 2 is a midscale code input that means no signal input, as shown in FIG. 8, the output level of the digital signal 21 output from the digital noise shaper 11 corresponding to the no signal state is “ Although it is “code 4”, since it includes shaping noise, “code 3” or “code 5” is mixed.

  Even if this digital signal 21 is converted into an analog signal via the DA conversion circuit 12 and the analog low-pass filter 71, it has a local peak as shown by a broken line 100 in FIG. Therefore, if the calibration operation is performed at the local peak portion, correct calibration is not performed.

  Therefore, in the present invention, in the calibration period, a signal input to the DA converter circuit 12 is, for example, a code pattern 51 (reference offset signal) made of a fixed code. In this example, it is assumed that the reference offset signal output from the code pattern generator 13 is a code pattern 51 including a pattern in which two codes are alternately repeated.

FIG. 9 shows a configuration example of the code pattern generating unit 13 that generates the code pattern 51.
During the calibration period of normal 8-bit input, the control signal (CAL) 101 output from the calibration circuit 4 changes, forcing 4 bits out of 8 bits to be an H level signal and the remaining 4 units to be an L level signal. Switch to output.

  Further, according to the code name of FIG. 5 described above, in the case of “code 4”, four “1” signals and four “0” signals are given to the DA converter circuit 12. Thus, the analog signal 22a output from the DA converter circuit 12 does not include shaping noise and is output as an offset voltage of the stationary DA converter 2.

FIG. 10 shows an example of the code pattern 51.
The analog output signal 22 output from the analog low-pass filter 71 does not have a local peak as indicated by the broken line 105.

Next, a method for adjusting the output of the DA converter 2 so that there is no offset will be described.
As an example of the adjustment method, the adjustment can be performed by using the analog low-pass filter 71 of FIG. 7 as a comparator. That is, the analog low-pass filter 71 compares the analog output signal 22a (a signal obtained by analog processing of the code pattern 51) output from the DA converter 2 with a ground potential as a preset voltage, and determines the magnitude of both input signals. Determine.

  The adjustment voltage (operating point adjustment signal 40) applied to the non-inverting input terminal (+) of the operational amplifier 93 shown in FIG. 7 is generated in the adjustment signal generation circuit 31 of the calibration circuit 4, and the adjustment voltage is gradually increased from a low voltage. The change in the output of the operational amplifier 93 is detected by the detection circuit 32 of the calibration circuit 4 by sequentially changing the voltage.

  In this detection circuit 32, when the voltage (ground potential) applied at the initial stage of adjustment is low, the output of the operational amplifier 93 is L level, and becomes H level when the offset difference disappears.

  The calibration circuit 4 includes a voltage applied to the non-inverting input terminal of the operational amplifier 95 at the moment when it becomes H level or a circuit configuration for supplying the voltage, an analog output signal 22 output from the DA converter 2 during a non-operation period, and a DA converter. 2 is stored in the storage circuit 33 such as an SRAM circuit or a flip-flop or an external storage device as offset calibration information 60 for eliminating the offset difference from the analog output signal 22 output during the operation period.

  As a result, the calibration operation is completed, and in the subsequent normal state, the voltage based on the offset calibration information 60 stored during the calibration period is adjusted so that the operational point of the analog low-pass filter 71 of the DA converter 2 is adjusted. Apply to the input terminal (+).

  In this example, adjustment of the offset difference between the offset of the analog output signal 22 output from the DA converter 2 during the non-operation period and the offset of the analog output signal 22 output from the DA converter 2 during the operation period is shown in FIG. 7 is performed by adjusting the voltage applied to the non-inverting input terminal (+) of the operational amplifier 93 of the analog low-pass filter 71 shown in FIG. 7 and adjusting the operating point of the DA converter 2. Calibration can be similarly performed by adjusting the voltage applied to the non-inverting input terminal (+) of the operational amplifier 90 of the DA converter circuit 12 shown in FIG.

  As described above, according to the configuration of the present system, in the case of a DA converter system that includes the digital interpolation filter 70 and the analog low-pass filter 71 that are provided in addition to the DA converter 2, Since the calibration operation is performed by the analog output signal 22 obtained by DA-converting the code pattern 51 (reference offset signal) that does not include the shaping noise that becomes a large noise, accurate calibration can be performed.

  In addition, in the present system, when the digital signal 11 output from the digital noise shaper 11 is a multi-bit signal having the same weight, a DA conversion is performed on the code pattern 51 that does not include shaping noise that is locally large noise. Since the calibration operation is performed by the analog output signal 22, accurate calibration can be performed.

  In addition, in the present system, when the predetermined code pattern 51 input to the DA converter circuit 12 during the calibration period is a single code, no signal output from the digital noise shaper 11 (that is, the operation center means) This is particularly effective when the code corresponding to the signal output) is uniquely determined. The code corresponding to the no-signal output is input to the DA converter circuit 12, and the calibration operation is performed by the analog output signal 22 stationary in the no-signal state. Therefore, accurate calibration can be performed.

[Third example]
A third embodiment of the present invention will be described with reference to FIGS. In addition, about the same part as each example mentioned above, the description is abbreviate | omitted and the same code | symbol is attached | subjected.
(Constitution)
FIG. 11 shows the configuration of the DA converter system 1.
In the DA converter system 1 of this example, a randomizer 73 is provided between the digital noise shaper 11 and the DA converter circuit 12.

  When the digital signal 21 output from the digital noise shaper 11 is a multi-bit output and is output as a plurality of unweighted bit signals, the randomizer 73 is an individual of a plurality of DA conversion elements of the DA conversion circuit 12. This is effective as a means for alleviating the occurrence of distortion due to the difference.

  Further, the output of the reference offset signal such as the code patterns 50 and 51 made of a fixed code is not limited to being generated in the DA converter 2 as shown in FIGS. 1 and 4 described above.

(Operation)
Hereinafter, the operation in the normal state is the same as that in the first and second examples described above, and therefore the description thereof is omitted. Only the operation of the randomizer 73 which is a different part will be described.

  The randomizer 73 receives an unweighted equivalent 8-bit digital signal 21 output from the digital noise shaper 11 and outputs an equivalent unweighted 8-bit digital signal 21a.

FIG. 12 is a timing chart of the digital signal 21 a output from the randomizer 73.
As the digital signal 21a, for example, the bit position is controlled so that the “1” signal circulates at each sampling time (T0, T1, T2,...).

  Even when the same “code 4” continues, since the position of “1” is circulated in the digital signal 21a, the DA conversion elements in all the DA conversion circuits 12 are uniformly used. It is possible to average the variation of the individual elements, and on average, the analog signal 22a having the correct offset can be generated.

This operation will be further described.
“1” exists in the order of bit numbers, and in each sampling period, “1” is arranged in the next period starting from the next bit that was the last “1” in the previous period. However, since bit 8 is always “0”, the circulation of “1” is performed in 7 bits from bit 1 to bit 7.

  In the case of this example, the calibration operation is a pattern in which the digital signal 12a output from the randomizer 73 in the calibration period is, for example, four patterns of “1” and “0” corresponding to the no-signal state. Performs a process of alternately repeating “1” and “0”.

FIG. 13 shows a generation circuit 74 that generates such a pattern of “1” and “0”.
The generation circuit 74 is inserted from the randomizer 73 into the signal path in the previous stage of the DA conversion circuit 12.

  By setting the signal CAL intended for the calibration period to the H level, a code of (11110000) and a code of (000011111) are alternately repeated at the CLK cycle.

  FIG. 14 shows a timing chart of the digital signal 21a output from the randomizer 73 via the circuit 74 at each sampling time (T0, T1, T2,...).

  As a result, the analog signal 22a output from the DA converter circuit 12 includes noise corresponding to the capacity difference between the two groups due to individual differences. However, the analog signal 22a is analog because of high-frequency noise having a cycle rate twice the clock cycle. The low-pass filter 71 is greatly attenuated. As a result, the D / A converter 2 outputs an analog output signal 22 having a substantially stationary offset voltage with no level fluctuation.

  As shown in FIG. 15, the analog output signal 22 output from the analog low-pass filter 71 with respect to the output level of the digital signal 21 output from the digital noise shaper 11 corresponding to the no-signal state is as indicated by a broken line 110. Has no local peak. Therefore, an accurate calibration operation is performed.

  In the system of this example, when a predetermined code pattern input to the DA converter circuit 12 during the calibration period is a pattern in which two codes are alternately repeated, no signal output from the digital noise shaper 11 ( That is, it is particularly effective when the code corresponding to the signal output (meaning the operation center) is in the middle of the two codes.

  The analog signal 22a generated by alternately inputting these two codes to the DA converter circuit 12 includes a high frequency component, but the analog output signal is stationary in a no-signal state from which the high frequency component has been removed by the analog low pass filter 71. Therefore, the calibration operation is performed by an almost stationary analog signal, and accurate calibration can be performed.

  In addition, the digital signal 21 output from the digital noise shaper 11 is a multi-bit signal having the same weight, and a code corresponding to a no-signal output (that is, a signal output meaning an operation center) is uniquely determined. ”And“ 0 ”are particularly effective.

  Two codes, a code with half “1” and half “0”, and a reverse code with all “1” and “0” interchanged, are alternately input to the DA converter circuit 12 and created. The analog signal 22a includes a high-frequency component due to individual differences of each input element of the DA converter circuit 12, but the analog low-pass filter 71 becomes the analog output signal 22 stationary in a no-signal state from which the high-frequency component has been removed. Calibration can be performed.

It is a block diagram which shows the structure of the DA converter system which is the 1st Embodiment of this invention. It is a block diagram which shows the structure of a calibration circuit. It is a flowchart which shows an offset calibration process. It is a block diagram which shows the structure of the DA converter system which is the 2nd Embodiment of this invention. It is explanatory drawing which shows the correspondence of the signal introduce | transduced into a DA converter circuit from a digital noise shaper. It is a circuit diagram of a DA converter circuit. It is a circuit diagram of an analog low pass filter. It is a time chart which shows each signal at the time of the conventional calibration as a comparative example. It is a circuit diagram which shows the structural example of the code pattern generation part which generates a fixed code. It is a time chart which shows each signal at the time of calibration of this invention. It is a block diagram which shows the structure of the DA converter system which is the 3rd Embodiment of this invention. It is explanatory drawing which shows operation | movement of a randomizer. It is a circuit diagram which shows the structural example of the signal control circuit which generates a pattern. It is explanatory drawing which shows operation | movement of a randomizer. It is a time chart which shows each signal at the time of calibration of this invention. It is a block diagram which shows the conventional system structure which consists of a means to calibrate an offset difference.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DA converter system 2 DA converter 4 Calibration circuit 11 Digital noise shaper 12 DA conversion circuit 13 Code pattern generation part 14 Switch part 20 Digital input signal 21, 21a Digital signal 22, 22a Analog output signal 30 CPU
31 adjustment signal generation circuit 32 detection circuit 33 storage circuit 40 operating point adjustment signal 41 calibration instruction signal 50, 51 reference offset signal 60 offset calibration information 70 digital interpolation filter 71 analog low pass filter 100 system 101 digital addition block 102 converter 103 gain Control circuit 104 Calibration circuit 105 Offset register 110 Digital input signal 120 Analog output signal 130 Digital signal

Claims (16)

In a DA converter system that sequentially inputs a digital input signal to a DA converter noise shaper, a DA converter circuit, converts the analog input signal to an analog output signal,
A calibration device for calibrating an offset difference between an offset of the analog output signal output during a non-operation period of the DA converter and an offset of the analog output signal output during an operation period of the DA converter,
In the non-operation period of the DA converter,
Reference signal input means for inputting a reference offset signal for predetermined offset adjustment to the DA converter circuit of the DA converter instead of the digital signal output from the noise shaper ;
Operating point adjustment signal generating means for sequentially generating an operating point adjustment signal for offset adjustment for detecting a time point when the offset difference with respect to the reference offset signal becomes zero, and inputting the operating point adjustment signal to the DA converter circuit When,
An offset difference detecting means for sequentially comparing the operating point adjustment signal with respect to the reference offset signal to obtain an offset difference between the signals and detecting a value of the operating point adjustment signal when the offset difference becomes zero. When,
Storage means for storing offset calibration information corresponding to the operating point adjustment signal at the time when the detected offset difference becomes zero;
In the operation period of the DA converter,
By adjusting the operating point of the DA converter based on the offset calibration information stored in the calibration period, the analog output signal output from the DA converter in the operating period and the DA converter in the non-operating period A calibration device comprising adjustment means for preventing an offset difference from occurring with an analog control signal to be output. The digital input signal is:
2. The calibration apparatus according to claim 1, wherein the digital signal is a weighted digital signal of power of 2, or a plurality of unweighted digital signals having equivalent weights. In a DA converter system that sequentially inputs a digital input signal to a digital interpolation filter, a noise shaper, a DA converter circuit of a DA converter, converts the digital input signal into an analog output signal, and outputs the analog output signal.
A calibration device for calibrating an offset difference between an offset of the analog output signal output during a non-operation period of the DA converter and an offset of the analog output signal output during an operation period of the DA converter,
In the non-operation period of the DA converter,
Reference signal input means for inputting a reference offset signal for predetermined offset adjustment to the DA converter circuit of the DA converter instead of the digital signal output from the noise shaper ;
Operating point adjustment signal generating means for sequentially generating an operating point adjustment signal for offset adjustment for detecting a time point when the offset difference with respect to the reference offset signal becomes zero, and inputting the operating point adjustment signal to the DA converter circuit When,
An offset difference detecting means for sequentially comparing the operating point adjustment signal with respect to the reference offset signal to obtain an offset difference between the signals and detecting a value of the operating point adjustment signal when the offset difference becomes zero. When,
Storage means for storing offset calibration information corresponding to the operating point adjustment signal at the time when the detected offset difference becomes zero;
In the operation period of the DA converter,
By adjusting the operating point of the DA converter based on the offset calibration information stored in the calibration period, the analog output signal output from the DA converter in the operating period and the DA converter in the non-operating period A calibration device comprising adjustment means for preventing an offset difference from occurring with an analog control signal to be output. The digital input signal is a power-of-two weighted digital signal or an unweighted digital signal with multiple weights with an equivalent weight;
Interpolating the digital signal with the digital interpolation filter;
The interpolated digital signal is subjected to noise shaping, and the digital signal output from the noise shaper has a weighted digital signal with a power of 2 having a bit number smaller than the bit number of the digital input signal, or an equivalent weight. 4. The calibration apparatus according to claim 3, wherein the calibration signal is a digital signal having a plurality of unweighted bits. The digital signal output from the noise shaper is
5. The calibration apparatus according to claim 1, wherein the calibration apparatus is a digital signal having a plurality of bits having an equivalent weight. The reference offset signal input to the DA converter circuit during the calibration period is
6. The calibration apparatus according to claim 1, wherein the calibration pattern is a single code pattern. The reference offset signal input to the DA converter circuit during the calibration period is
6. The calibration apparatus according to claim 1, wherein the calibration apparatus is a code pattern in which at least two codes are repeated in a preset pattern.   8. The calibration apparatus according to claim 1, wherein a randomizer that controls a bit position of the digital input signal is provided between the digital noise shaper and the DA converter circuit. When a digital input signal is sequentially input to a DA converter noise shaper and a DA converter circuit to be converted into an analog output signal and output,
A calibration method for calibrating an offset difference between an offset of the analog output signal output during a non-operation period of the DA converter and an offset of the analog output signal output during an operation period of the DA converter,
In the non-operation period of the DA converter,
A step of inputting a predetermined offset adjustment reference offset signal to the DA converter circuit of the DA converter instead of the digital signal output from the noise shaper ;
Sequentially creating an operating point adjustment signal for offset adjustment for detecting a time point when the offset difference with respect to the reference offset signal becomes zero, and inputting the operating point adjustment signal to the DA conversion circuit;
Sequentially comparing the operating point adjustment signal with respect to the reference offset signal to obtain an offset difference between the signals, and detecting a value of the operating point adjustment signal when the offset difference becomes zero;
Storing offset calibration information corresponding to the operating point adjustment signal at the time when the detected offset difference becomes zero value in a memory;
In the operation period of the DA converter,
By adjusting the operating point of the DA converter based on the offset calibration information stored in the calibration period, the analog output signal output from the DA converter in the operating period and the DA converter in the non-operating period And a step of preventing an offset difference from occurring with an analog control signal to be output. The digital input signal is:
10. The calibration method according to claim 9, wherein the digital signal is a weighted digital signal of power of 2, or an unweighted digital signal having a plurality of bits having an equivalent weight. When a digital input signal is sequentially input to a digital interpolation filter, a noise shaper, and a DA converter circuit of a DA converter, converted into an analog output signal, and then output.
A calibration method for calibrating an offset difference between an offset of the analog output signal output during a non-operation period of the DA converter and an offset of the analog output signal output during an operation period of the DA converter,
In the non-operation period of the DA converter,
A step of inputting a predetermined offset adjustment reference offset signal to the DA converter circuit of the DA converter instead of the digital signal output from the noise shaper ;
Sequentially creating an operating point adjustment signal for offset adjustment for detecting a time point when the offset difference with respect to the reference offset signal becomes zero, and inputting the operating point adjustment signal to the DA conversion circuit;
Sequentially comparing the operating point adjustment signal with respect to the reference offset signal to obtain an offset difference between the signals, and detecting a value of the operating point adjustment signal when the offset difference becomes zero;
Storing offset calibration information corresponding to the operating point adjustment signal at the time when the detected offset difference becomes zero value in a memory;
In the operation period of the DA converter,
By adjusting the operating point of the DA converter based on the offset calibration information stored in the calibration period, the analog output signal output from the DA converter in the operating period and the DA converter in the non-operating period And a step of preventing an offset difference from occurring with an analog control signal to be output. The digital input signal is a power-of-two weighted digital signal or an unweighted digital signal with multiple weights with an equivalent weight;
Interpolating the digital signal with the digital interpolation filter;
The interpolated digital signal is noise-shaped and the digital signal output from the noise shaper is a weighted digital signal with a power of 2 having a bit number smaller than the bit number of the digital input signal or an equivalent weight. 12. The calibration method according to claim 11, wherein the calibration signal is a digital signal having a plurality of unweighted bits. The digital signal output from the noise shaper is
The calibration method according to claim 9, wherein the calibration method is a digital signal of a plurality of bits having an equivalent weight. The reference offset signal input to the DA converter circuit during the calibration period is
The calibration method according to claim 9, wherein the calibration pattern is a single code. The reference offset signal input to the DA converter circuit during the calibration period is
The calibration method according to claim 9, wherein the calibration pattern is a code pattern in which at least two codes are repeated in a preset pattern.   16. The calibration method according to claim 9, wherein a bit position of the digital input signal is controlled by a randomizer connected between the digital noise shaper and the DA converter circuit.

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