JP4445486B2 - Data processing system - Google Patents

Description

  The present invention relates to the field of data processing. More particularly, the present invention relates to data processing systems that require operations to be performed on one or more data streams.

  It is known to provide a data processing system capable of performing operations on data, and such operations may involve bi-directional, ie input to output, or output to input data flow. In addition, each of the input data and the output data can have an associated data format. Examples of commonly required data stream operations for bidirectional data flow are data alignment, buffering, forward and rewind of the data stream, as well as reading variable length coded syntax elements on the stream, It includes data stream merging and connection functions. Similarly, in order to provide an output data stream with a different temporal sequence in many cases, ie to provide out-of-order access to the data stream, It is necessary to make changes to the sequence. An example of such a data processing system that requires operations to be performed is a system for processing a multimedia data stream containing audio data and / or video data encoded according to a known format; Formats are being defined by international “standards” (eg, MP3 or MPEG).

  However, these known data processing systems allow a programmer to explicitly manage a number of data processing tasks such as recording which parts of the input data stream have been received, manipulated and output. Alternatively, a software library having a plurality of functions for executing data processing is required to be provided and maintained, which places a serious burden on the programmer. The obvious management of data processing is also time consuming and providing and maintaining a software library is time consuming and inefficient. Accordingly, there is a need for a data processing system that removes at least some of the tasks associated with processing input and output data from the programmer in a more efficient manner.

  In a data processing device with a main processing unit, sometimes referred to as a loosely coupled coprocessor that can be used to process a specific data processing task on behalf of the main processing unit (it is external to the main processing unit) At the same time, it is known to provide a data engine that is loosely coupled in the sense that the synchronization between the data engine and the main processing unit is performed only on a process or task level. In this description, the term main processing unit (i.e. main processor) refers to whether it can be a central processing unit (CPU) or alternatively other simplified control elements in the data processing unit, e.g. It is defined that it can simply be a control element that controls activation and then delegates all other tasks to one or more data engines. Providing a data engine can result in various performance improvements with respect to a data processing device where all of the tasks are processed by the main processing device, such as increased execution speed, a specific set of tasks. One or more of a reduction in power consumption or a reduction in the total silicon area required to support the required functionality. However, data stream processing tasks are generally computationally intensive and, when assigned to a data engine, can consume a large portion of the data engine's computer processing power, thus impersonating the main processing unit. Reduce the utility value of performing data processing tasks.

  US patent application Ser. No. 11 / 121,185, filed May 4, 2005, is a first-in-first-out that can be used to provide a window to a locally stored data stream. A data processing apparatus including an Out (FIFO) memory will be described. The contents of US Patent Application No. 11 / 121,185 are hereby incorporated by reference.

  According to a first aspect, the present invention executes a main processing device operable to execute a plurality of data processing tasks, and executes some of the plurality of data processing tasks on behalf of the main processing device. A data engine having an operable data engine core, and a data stream processing device that provides a data communication path between the main processing device and the data engine core, the data stream processing device comprising: A control interface operable to receive at least one instruction from the engine core; and at least one input data stream for receiving at least one input data stream and generating at least one output data stream including a series of data elements; At least one operation on one input data stream A data stream controller operable to perform the data stream processing unit from the data engine core to control the data stream controller to perform the at least one operation. A data processing system is provided that is responsive to at least one instruction.

  Note that each of the input data stream and the output data stream can be provided from, for example, a data engine or external processing (such as direct memory access).

  The present invention recognizes that the processing of the data stream can be performed more efficiently by providing a data stream processing device that performs operations on the input data stream on behalf of the data engine. A subset of the processing tasks assigned to the data engine by the main processing unit can be delegated to the data stream processing unit via the control interface, thus improving its efficiency. This reduces the computational burden on the data engine since at least a subset of the data stream processing operations are performed by the data stream processing device on behalf of the data engine. Therefore, the capacity of the data engine for executing other data processing operations increases, and the data stream processing apparatus can execute processing tasks in parallel with the data engine, so that the overall calculation efficiency is improved. In addition, some simple processing operations can be combined into more complex operations that can be efficiently performed by the data stream processing device. The data stream processing unit, as well as determining and decoding syntax elements defined in the data stream, such as data alignment, buffering, rewind or forward, and data stream connection and merging in the data stream, Provides support for data stream operations. Thus, the data stream processing device is used to perform a subset of data processing tasks so as to reduce the burden on the main processing device and the data engine. Effectively, this can be viewed as a state machine in which the control interface of the data stream controller is able to perform the respective processing without further intervention from the main processing unit or from the data engine. Means that. In devices where the data stream controller comprises more than one interface, each interface will have an associated state machine and associated process, and a particular process is associated with the rest of the interface. Depending on the current state of the machine. Information regarding the state of each of the plurality of state machines may be exchanged via a data stream controller.

  The data stream processor responds to instructions (such as control signals) from the data engine core to control the data controller of the data stream processor to perform operations on the input data stream. The ability to send instructions from the data engine core to a data stream processing operation to perform one or more operations on the input data stream is defined by appropriately defining the instructions output by the data engine core. Several data processing tasks involved in the generation can be removed from the programmer. Furthermore, the ability to define instructions for control operations performed on the input data stream by the data stream processing device provides the programmer with expanded flexibility in the types of operations that can be performed.

  The main processing unit can take a variety of forms. For example, it can be a central processing unit (CPU) or alternatively other simplified control elements in the data processing unit, such as simply controlling activation and then one or more data engines Can be a control element that delegates all other tasks to

  In one embodiment, the data stream processing device is operable to store management information including at least one reference position in at least one input data stream. The data stream processing device executes at least one instruction based on the at least one reference position. This simplifies access to data elements in the input data stream, as the task of saving the reference point is performed by the data stream controller. This reduces the complexity of the instructions output to the data stream processing device by the data engine core.

  In one embodiment, some of the data processing tasks performed by the data engine core have a series of instructions including at least one instruction of an instruction set executable by the data engine core. The data engine core is operable to output at least one instruction to the control interface of the data stream processing device with respect to execution of the at least one instruction. This simplifies bi-directional information exchange (bi-directional communication) between the data stream processing device and the data engine core, since the processing tasks to be executed by the data engine core can be easily assigned to the instructions of the instruction set. .

  In one embodiment, the input data stream is a multimedia data stream structured according to a predetermined set of rules, and the instruction set is defined based on the predetermined set of rules. The set of rules will match, for example, an audio data standard such as the MP3 standard, or a video data standard such as the MPEG standard. The ability to define an instruction set so that it is specifically tailored to perform a set of processing operations typically performed when processing a particular multimedia data stream has the ability to process a special set of processing operations. Provides a lot of flexibility to fine tune performance.

  In one embodiment, the data stream processing device is operable to operate asynchronously according to at least one instruction with respect to receiving an input data stream by a data stream controller or with respect to transmitting an output data stream element. This provides flexibility to adapt to changes in the arrival or departure of the data stream when performing processing tasks on the input data stream or the output data stream.

  In one embodiment, the data stream controller is configurable by at least one of a data engine and a main processing device comprising configuration information. Since the data stream processing unit does not need to request this configuration information from either the main processing unit or the data engine during runtime, this data extends an extended level of independence from the main processing unit. Provided to a stream processing apparatus.

  In one embodiment, the data stream controller is operable to selectively buffer at least a portion of the at least one data stream within a connected buffering resource when performing at least one operation. is there. This provides an efficient way for the data engine to cause instruction reordering access to the data stream, since a portion of the data can be buffered for later output.

  In one embodiment, the data stream processing apparatus comprises a data output logic circuit having a multiplexer operable to selectively output data from buffering resources, and the data stream controller includes at least one output data stream. Is operable to control the output of the multiplexer. This simple circuit configuration is efficient and nevertheless effective for data flow because selected portions of data can be easily assigned to buffering in response to instructions from the data stream processor. Management is possible.

  In one embodiment, the connected buffering resource is a software FIFO. In some such embodiments, the memory area is defined by a partition pointer, while access to data is controlled by the state of at least one head pointer and at least one tail pointer. The use of a software FIFO allows for more rapid and efficient access to buffered data and allows the data stream processor to manage buffering resources by simply managing the head and tail pointers. To make it easier.

  In one embodiment, the data stream controller is operable to save a history of which portions of the at least one input data stream are currently stored in the connected buffering resource. Thus, the programmer need not have knowledge of where the requested data portion is stored, more precisely, the programmer can simply request a particular portion of the data stream and the data stream The processing unit can independently determine whether data needs to be read from the buffer.

  In one embodiment, the configuration information includes the size of buffering resources connected to the data stream controller. This allows the data stream processor to manage buffering operations more autonomously, and removes the need for the programmer or data engine to record the buffer occupancy level.

  In one embodiment, the data stream processing device comprises a processing interface that provides a data path to the processing module, and the processing module is responsive to execution of at least one instruction of an instruction set executable by the data processor core; It is operable to execute a processing task. This extends the functionality of the data stream processor as the processing interface provides additional data flow paths from the data stream processor to the input / output data elements. The processing resources made available by the accessibility of the processing module can be used to perform specialized data processing functions such as decryption, particularly in an efficient manner.

  In one embodiment, the configuration information provided to the data stream processing device by at least one of the data engine and the main processing device includes characteristics of at least one processing resource. This increases the autonomy of the data stream processing device after the initial configuration operation and what additional processing resources are available to it to follow the instructions to perform the data stream processing task from the data stream functional device. It does not need to reference the main processing unit to determine if it is.

  In one embodiment, the configuration information provided to the data stream processing device by at least one of the data engine and the main processing device includes a start point and an end point of a buffering resource connected to the data stream controller. Including. In addition, this increases the autonomy of the data stream processing device when performing data stream operations.

  In one embodiment, the at least one input data stream includes a plurality of data portions arranged in order in a temporary sequence of inputs, and the at least one output data stream has a different output than the temporary sequence of inputs. It includes a plurality of data portions of a temporary sequence of inputs arranged in order in the temporary sequence. This provides instruction reordering access to the input data stream, which is a trivial data manipulation operation for applications such as Constant Bit-Rate (CBR) audio coding algorithms.

  In one embodiment, at least one instruction of the instruction set executable by the data engine core is either an instruction with a conditional response or an instruction with an unconditional response. Classifying instructions in this way allows calculation processing deadlocks to be more easily avoided by providing that abnormal termination operations are associated with conditional response instructions.

  In one embodiment, the at least one instruction corresponds to a respective process to be performed by the data stream controller in response to the at least one instruction output by the data stream functional unit, and each process is a data It has an associated state machine maintained by the stream controller. By combining the processing of calculations performed by a data stream processing device having a given state, the performance of the control processing is eliminated and identified during the time that the data stream processing device is in a state associated with its processing task. It is possible to easily suppress specific control processing that jeopardizes completion of the processing task. Modeling a processing task as each state of the data stream controller is also an efficient way to allow the data stream processing device to record the data operations performed.

  In one embodiment, the instruction set executable by the data engine core includes buffering instructions operable to cause the data stream controller to selectively buffer data elements of at least one input data stream. Buffering is a task that is frequently performed with respect to instruction reordering access and data stream connection, and the provision of explicit buffering instructions allows efficient data manipulation.

  In one embodiment, the instruction set executable by the data engine core causes the data stream controller to read at least one data element of at least one input data stream from the buffering resource and at least one output data stream. Includes a data read instruction operable to cause at least one data element to be output. This is done without the need for the programmer to specify exactly where the buffered data elements are actually stored, and in the program code devised by the programmer to perform operations on the data stream. Facilitates programmer access to buffered data elements without the overhead of storing location information.

  In one embodiment, the management information is at least a current output position indicating data in one of the at least one input data stream to be subsequently supplied to the at least one output data stream by the data stream controller. including. This alleviates the burden on the programmer to record what data has already been output and simplifies the instructions that must be supplied to the data engine to access the data stream data.

  In one embodiment, the instruction set executable by the data engine core is such that the current output position corresponds to the data element at the previous point in the temporary sequence of inputs associated with the corresponding input data stream. Includes a back step command operable to change the output position. This facilitates instruction order change access to the input data stream.

  In one embodiment, the management information includes a history indicating which data elements of at least one input data stream are stored in the buffering resource, and which data elements of at least one input data stream are received by the data stream controller. At least one of the history indicating This means that one or more of the data management tasks described above can be managed independently by the data stream controller, and the complexity of these management tasks can be easily hidden from the programmer.

  In one embodiment, the instruction set executable by the data engine core includes data insertion instructions operable to cause a data stream controller to insert data from the data engine into at least one output data stream. This provides the flexibility to insert specified data from the data engine into the data stream.

  In one embodiment, the data processing system comprises a direct memory access interface operable to provide a data communication path directly to the memory access controller for supply of at least one input data stream to the data stream controller.

  In one such embodiment, the configuration information includes at least one characteristic of the direct memory access controller. This performs access to the data stream where the operation is to be performed more efficiently since access to the data can be obtained without reference to the main processing unit. In one such embodiment, the configuration information provided by the main processing device to the data stream processing device includes at least one characteristic of the DMA controller. This means that the data stream controller can more easily and independently manage access to the input data stream, which reduces the processing burden on the main processing unit and thereby increases efficiency.

  In one embodiment, the data stream processing device temporarily stores data elements of at least one input data stream before the data stream controller provides the stored data elements to the at least one output data stream. Data input register. Local buffering of input data elements provides some flexibility within the data stream processing device to respond to a series of rates of arrival of incoming data, and which data elements of the incoming data stream are already Facilitates data management operations such as recording what has been received.

  In one embodiment, the instruction set executable by the data engine core relates to the state of the data pointer at the moment the instruction associated with the set count instruction is transmitted from the data engine core to the data stream processing device. And a count setting instruction operable to instruct the data stream processing apparatus to set an upper limit of a data pointer state. After execution of the count setting instruction, the data stream processing device will continue to execute requests for data elements, or syntax elements. However, the data stream processing device will prevent the data stream pointer value from proceeding beyond the set upper limit so that the data pointer remains at this upper limit regardless of further requests for data. Any data element request signal that is output after the data pointer reaches the upper limit, or a data element request signal that would lead to the data pointer must exceed this upper limit, is a configurable error code or fixed Error code (i.e., zero) and the setting of bits in the status register corresponding to some of the management information maintained by the data stream processor. The data stream processing device (i) reissues the count setting instruction with a new value, (ii) outputs a reset instruction, or (iii) issues a count setting instruction with a special code (ie -1) Thus, the final state that has reached the upper limit can be released.

  Although the data stream processing device may be provided as a separate entity having a data communication path with data, in one embodiment, the data stream processing device is at least partially integrated into the data engine. In this way, selective portions of the data stream processing device can be moved to the data engine. For example, a barrel shifter that is part of a data access register of a data stream processor may be combined with a data engine arithmetic logic unit (ALU) barrel shifter.

  According to a second aspect, the present invention executes a main processing device operable to execute a plurality of data processing tasks, and executes some of the plurality of data processing tasks on behalf of the main processing device. And a data stream processing device for providing a data communication path to and from a data engine having a data engine core operable so that the data stream processing device receives at least one instruction from the data engine core. A control interface operable to receive and at least one input data stream to receive at least one input data stream and to generate at least one output data stream that includes a series of data elements. Data operable to perform one operation And a stream controller, said data stream processing device, for controlling said data stream controller to perform said at least one operation, responsive to said at least one instruction from the data engine core.

  According to a third aspect, the present invention uses the process of assigning a plurality of data processing tasks to a main processing device and a data engine having a data engine core, and uses the data processing on behalf of the main processing device. A process that performs some of the processing tasks, a process that uses a data stream processing device to provide a data communication path between the main processing device and the data engine core, and at least from the data engine core A process for receiving an instruction at the data stream processor, a process for receiving at least one input data stream at a data stream controller of the data stream processor, and at least one output comprising a series of data elements To generate the data stream, the at least one input data Performing at least one operation on the data stream, wherein the data stream processing unit from the data engine core to control the data stream controller to perform the at least one operation. A data processing method is provided that is responsive to at least one instruction.

  According to a fourth aspect, the present invention provides a main processing device operable to execute a plurality of data processing tasks, and executes some of the plurality of data processing tasks on behalf of the main processing device. A data engine having an operable data engine core, and a data stream processing device that provides a data communication path between the main processing device and the data engine core, the data stream processing device comprising: A control interface operable to receive at least one instruction from the engine core; a first interface for at least one data stream; and a second interface for at least one data element stream comprising a series of data elements. And having the first interface and the A data stream controller operable to perform at least one operation for managing data transfer between the two interfaces, wherein the data stream processing device performs the at least one operation A data processing system responsive to the at least one instruction from the data engine core to control the data stream controller.

  According to a fifth aspect, the present invention provides a data stream processing device for providing a data communication path between a main processing device and a data engine core, and the data stream processing device comprises the data engine. A control interface operable to receive at least one instruction from the core; a first interface for at least one data stream; and a second interface for at least one data element stream including a series of data elements. And a data stream controller operable to perform at least one operation for managing data transfer between the first interface and the second interface, the data stream processing device Performs the at least one operation To control the data stream controller to so that, responsive to said at least one instruction from the data engine core.

  It will be appreciated that embodiments of the data stream processing apparatus according to the present invention may include one or more of any of the related features described above with respect to the data processing system.

  According to a sixth aspect, the present invention uses the process of assigning a plurality of data processing tasks to a main processing device and a data engine having a data engine core, and uses the data processing on behalf of the main processing device. A process that performs some of the processing tasks, a process that uses a data stream processing device to provide a data communication path between the main processing device and the data engine core, and at least from the data engine core Data transfer between processing to receive one instruction at the data stream processing device, a first interface for at least one data stream, and a second interface for at least one data element stream of the data stream controller A process that performs at least one operation for managing A data processing method in which the data stream processing device is responsive to the at least one instruction from the data engine core to control the data stream controller to perform the at least one operation. provide.

  A data element stream is a stream of “values” that is meaningful in the scope of the instruction set structure of the data engine core to which the data stream processing device is connected, that is, operations related thereto are executed by using instructions and resources. It is an element to get A data element can be composed of one or more bits, and in one embodiment, a data element can include a syntax element defined by the standard. One such example of a syntax element would be a Huffman word.

  The syntax elements are IS0-IEC 11172-3 MPEG 1 audio, IS0-IEC 13818-3 MPEG 2 audio, IS0-IEC 13818-7 MPEG 2, AAC audio, IS0-IEC 14496-3 MPEG-4 MC twinVQ audio, , IS0-IEC 11172-2 MPEG 1 video, IS0-IEC 13818-2 MPEG 2 video, IS0-IEC 14496-2 MPEG-4 video, H.261, H.262, H.263, H.264 video and VCI Can be structured as defined according to any of a number of different international standards.

  The data stream is a “pattern” that is meaningful in the physical structure of the hardware device found in the subsystem layer surrounding the data engine (the data stream processing device is part of it), or in the scope of the structure surrounding the subsystem. It is a stream. For example, the patterns include data portions (ie units of quantities or atoms) that will be transferred across the bus or stored in memory, rather than syntax elements. A data stream consists of differently defined portions of data provided by a portion of data that includes a data element stream.

  The above objects and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments, which should be read in conjunction with the accompanying drawings.

  FIG. 1 schematically illustrates a data processing system. The system includes a main processing unit 110, a memory 120, a direct memory access (DMA) controller 130, a data engine 140 having a data engine core 142, a data stream processing unit 150, and a system bus 160.

  The data stream processing unit 150 is located between the data engine 140 and the system bus 160 and is operable to perform processing tasks that are under the control of the data engine core 142. The data engine core 142 of the data engine 140 is configured to perform a subset of processing tasks on behalf of the main processing unit 110 and may be considered a loosely coupled coprocessor. Data engine core 142 is in the sense that it is not integrated with main processor 110 and that synchronization between data engine core 142 and main processor 110 is performed only at the process or task level. Loosely coupled. In this device, the data engine core 142 has access to several resources shared by the main processing device 110. In particular, access to the DMA controller 130 and the memory 120 is shared.

  The data engine core 142 is operable to execute a set of instructions on behalf of the main processing unit 110 and at least instruct it to the data stream processing unit 150 with respect to execution of a subset of the set of program instructions. It is operable to generate a single instruction (eg, a control signal). In response to this instruction, the data stream processing device 150 is controlled to perform one or more data stream processing tasks. The data stream processing device 150 can be configured to receive one or more input data streams from the memory 120 via the bus 160 and under the control of the DMA controller.

  Data stream processor 150 is operable to perform operations on the input data stream to generate one or more output data streams. In order to perform these data stream operations, the data stream processor 150 has access to a buffer memory (not shown). Particularly in this device, the buffer memory forms part of the memory 120. In an alternative device, the buffer memory is provided locally in the data stream processing device 150. The operations performed by the data stream processing unit 150 may be part of at least two input data streams, for example to enable instruction reordering access to the input data streams or to generate a single output data stream. Enable connection. The data stream processing device 150 can be configured by the main processing device 110 having configuration information such as buffer size and position, start address and end address for the buffer memory, and characteristics of the DMA controller 130, for example.

  In FIG. 1, the combination of data stream processor 150 and data engine 140 provides data stream processing with improved performance and reduced complexity, both in terms of programming and integration. The data stream processing device 150 and the data engine 140 effectively function as a DMA slave device capable of processing a data stream without the need for further bidirectional information exchange from the host system. An application program interface (API) provided to execute a data stream processing task by the data engine core 142 is similar to stream buffering and rewinding functions for instruction order change access to a bitstream. Provides functionality for variable length bitstream access with automatic data alignment. Such instruction order change access is common in a constant bit-rate (CBR) audio encoding algorithm.

  FIG. 2 schematically illustrates the data engine 140 of FIG. 1 in further detail. In FIG. 1, the data stream processing device 150 is provided outside the data engine 140. However, in an alternative device, the data stream processing device 150 can be integrated as a component of the data engine 140. This is indicated in FIG. 2 by the dotted line of the data stream processing device 150. The data engine core includes a data engine controller 210, a data stream function device 220, and a plurality of other function devices 230. Data engine controller 210 is operable to receive program instructions for execution from main processing unit 110 (see FIG. 1) and to execute each instruction, data stream function unit 220 and It is configured to transmit to an appropriate one of the plurality of functional devices 230. Data engine controller 210 outputs control signals that result in the movement of data in data engine core 140 and the issue of program instructions for execution by data stream functional unit 220 or other functional unit 230. Execution of these instructions can use data or generate data.

  Data stream functional unit 220 and a plurality of other functional units 230 are each operable to execute at least one program instruction on behalf of main processing unit 110. Different ones of the functional devices 230 are dedicated to performing different processing tasks. Data stream functional unit 220 is a special type of functional unit configured to execute instructions for generating instructions to be transmitted to data stream processing unit 150. The instructions (in this case, control signals) supplied as input to the data stream processing unit 150 by the data stream functional unit 220 perform the tasks including access to the input data stream and manipulation of the input data stream. The processing device 150 is controlled. Examples of data streams to be processed include, but are not limited to, video data and audio data in a compressed and / or coded format.

  FIG. 3 schematically illustrates the logic circuitry in the data stream processing device and how the data stream processing device 150 interfaces with the data engine core 142. The data stream processing apparatus includes a configuration module 310, a data reception module 320, a buffer interface 330, a data stream controller 340, a control interface 350, and an accelerator interface 360 that provides access to the accelerator 362. The data receiving module 320 is configured to communicate with the DMA interface 370. The buffer interface 330 provides a data communication path with the external buffer 332.

  Similarly, the data stream processing device 150 includes a management module 380 that stores management data in a management record. The management record in this embodiment is a file stored locally by the management module 380, however, in an alternative device, the management record is a file stored in the external memory of the data stream processing device 150. The management record is accessible by the data stream controller 340 via the management module 380. The management data includes, but is not limited to, a pointer to data stored in the buffer and marker data indicating the beginning and end of the header portion. Note that in this specification, the terms module and logic will be used to refer to components that may include hardware elements, software elements, or combinations thereof. is required.

  The data receiving module 320 communicates with the DMA interface 370 via a handshake protocol and is operable to receive one or more input data streams via the DMA interface 370. The data receiving module 320 is described in further detail in FIG. The configuration module 310 includes the characteristics of the buffer 332, the characteristics of the DMA controller 130 (see FIG. 1) accessible via the DMA interface 370, and the accelerator processing module 362 accessible via the accelerator interface 360. Programmed by the main processor 110 having configuration information including characteristics.

  By programming the configuration module 310 of the data stream processing device 150 with such configuration information, the details of the buffering implementation performed by the data stream processing device 150 can be hidden from the programmer. This is because the data stream processing device 150 can manage the buffering process executed in response to the execution of the program instruction by the data stream function device 220 based on the configuration information stored in the configuration module 310. Thus, the requirement in program instructions executed by data stream functional unit 220 to explicitly specify the location of the buffer to store and read buffered data therefrom is eliminated.

  The control interface 350 can directly communicate with the data stream function device 220 and receives a control signal output by the data stream function device 220. Data engine core 142 receives a subset of program instructions from the main processing unit, and data engine core 142 is responsible for executing the processing tasks associated with those program instructions. The controller 210 executes program instructions to generate control signals. The controller 210 assigns processing tasks to the data stream functional device 220 and other functional devices 230. That would assign at least some processing tasks associated with the data stream that can be handled to the data stream functional unit 220. In particular, the controller 210 sends control signals to the data stream functional unit 220 to perform a subset of processing tasks. The data stream function device 220 sequentially transmits control signals to the control interface 350 of the data stream processing device 150.

  Data stream controller 340 controls operations performed on the input data stream based on instructions received from data stream functional unit 220 via control interface 350. Data stream controller 340 is operable to direct several data elements (eg, bits, bytes, or words) of the input data stream to buffer interface 330 for temporary storage in buffer 332. The data stream controller 340 includes a plurality of interfaces including a data receiving module 320, an accelerator interface 360, a buffer interface logic 330, and a control interface 350. The data stream controller 340 can perform operations on one or more input data streams to generate one or more output data element streams, or provide an output data stream. Bidirectional data flow is supported so that operations can be performed on one or more input data element streams. It should be remembered that the data element stream is a meaningful value stream with respect to the instruction set structure of the data engine core with which the data stream processor 150 is communicating, ie, the elements whose operations can be performed using instructions and resources. is there. Examples of data elements are syntax elements defined by international standards. Accelerator 362 is operable to process syntax elements of a data stream, such as a multimedia data stream.

  Programmers that provide program instructions for execution by the data stream functional unit 220 (along with a series of instructions that can be executed by the main processing unit 110) can be used for location, current capacity, or data supplied to the buffer. There is no need to have knowledge of the characteristics of the buffer, such as the storage address to be used, because the data stream processor 150 is self-supporting in this respect. The independence of data stream processor 150 is the fact that it stores configuration data in configuration module 310 that specifies details of the connected data processing resources such as buffer 332, accelerator 362, and DMA controller 130. At least in part.

  The configuration module 310 is accessible by the main processing unit 110 (see FIG. 1) and other processing units connected to the bus 160, but is not accessible by the data engine 140. Further, the data stream processing device 150 stores how many data elements of each input data stream are received by the data receiving module 340 via the management module 380, and which data elements of each input data stream are stored in the current buffer. Or a management record that records which data elements of each input data stream have already been output via the control interface 350 or the accelerator interface 360.

  The accelerator interface 360 provides an accelerator 362 for the input / output data communication path. The accelerator 362 is configured to perform a series of specialized processing tasks quickly and efficiently. In particular, in this apparatus, the accelerator is configured to perform Huffman encoding / decoding of the data stream. Accelerator 362 is operable to perform data stream encoding / decoding in response to instructions supplied by data stream functional unit 220 received via control interface 350. In response to this accelerator instruction (or sequence of instructions), the data stream processing device 150 reads the data elements to be manipulated by the accelerator 362 and performs the encoding / decoding of those data elements. Run both independently.

  As shown in FIG. 3, the data engine core 142 is operable to execute an instruction set that includes a plurality of instructions and to generate control signals for the control interface 350 in response to execution of each instruction. . The instruction set that can be executed by the data engine core 142 includes the following instructions.

(i) A “getbits ()” instruction to read the specified data element from the input data stream.
(ii) A “bufferbits ()” instruction to instruct the data stream controller 340 to buffer specified data elements of the input data stream.
(iii) After the next data element following it has already been supplied to the output data stream, by reading the data element of the pre-buffered data stream, “ backstep () ”command.
(iv) A “putbits ()” instruction operable to insert data from the data engine into a data stream processor for insertion into the data stream.
(v) A “setcount ()” instruction for setting a counter for recording data in the data stream processing device 150.
(vi) “rstcount ()” instruction to reset the counter.
(vii) “setbufferdepth ()” instruction for setting the depth of the buffer 332.
(viii) A “get Huffword ()” instruction for autonomous reading of syntax elements from the data stream. A syntax element may contain multiple data elements.
(ix) “unbufferbits ()” command to delete data from the buffer.
(x) A “peakbits ()” instruction that allows access to the stream itself or a limited number of bits from the data stream without advancing the bit pointer.

  For example, buffering for output may be accomplished by executing a “backstep ()” instruction followed by a “putbits ()” instruction followed by an “unbufferbits ()” instruction.

  In an alternative device, the data stream processing device takes one data stream (either input or output) and performs the basic function of converting it to another differently formatted data stream It is possible to operate. In this case, the only instructions that would be needed from the above list are the “getbits ()” instruction for the input stream and the “putbits ()” instruction for the output stream.

  All of the instructions executed by the data engine core 142 and resulting in instructions sent from the data stream function device 220 of the data engine to the data stream processing device 150 via the control interface 350 are: Either a response command with a response or (b) an unconditional response command. An unconditional response instruction (for example, a “getbits ()” instruction) is independent of the lock state of other processes, whether internal or external. These instructions are therefore guaranteed to return. On the other hand, condition response instructions can depend on the lock state, and thus a corresponding “abort ()” instruction is provided to these instructions to prevent deadlock. Note that the “getbits ()” instruction is an unconditional response instruction, but will stop if the required data is not available.

  The “setcount ()” and “resetcount ()” instructions are explicitly provided to make data stream access more secure. For example, in the “ISO.IEC 11172-3” and “ISO.IEC 13818-3” (MPEG1, 2 audio) standards, it is defined that a certain number of bits are read, but the amount of data read. There is no guarantee that will match the integer number of data elements (eg, syntax elements) or that it will match the full number of processing steps of the processing loop. In order to avoid the costly “break” instruction, the “setcount ()” instruction allows the data stream processing unit 150 to provide a specified number of bits and later generate zero and exit conditions. enable. This guarantees that the code will end at the end of the loop.

  The output data stream generated by the data stream processing device 150 is transmitted to the data engine 140 via the control interface 350. Data received from the data stream processing device 150 by the data engine 140 is stored in a register (not shown) in the data engine 140.

  The instruction signal generated by the execution of each program instruction described above is supplied to the data stream processing device 150 by the data engine core 142 via the control interface 350. Execution of each instruction by the data engine core 142 induces a processing task in the data stream processing device 150. The control interface 350 is a port through which a self-supporting process (for example, “bufferbytes ()” instruction, “getbits ()” instruction, etc.) starts and ends. Each self-supporting process has its own state machine.

  The DMA interface 370 and the data receiving module 320 or buffer interface logic 330 perform operations in response to receiving data from the input data stream, while the control interface 350 performs operations on the input data stream. In response to commands received from the data engine core 142 (generally asynchronously with respect to receiving the input data stream) to control the data stream processing device 150. Thus, for example, the DMA interface 370 is configured to respond to bus signals even if there is no corresponding command received via the control interface 350. Thus, the operation of the data stream processing device requires adjustment and this adjustment is performed using a state machine. If a “bufferbytes ()” operation is being performed by the data stream processing device 150 such that data is being transferred from the data receiving module 320 to the buffer interface logic 330, then buffering is in progress The “getbits ()” instruction received via the control interface 350 during this time cannot be processed simultaneously with buffering. Buffering will continue regardless of receipt of the “getbits ()” instruction. Interruption of buffering, including memory access, will result in wasted power consumption as well as functionally misbehavior due to inter-instruction dependencies. The state machine prevents the buffering operation from stopping upon receipt of the “getbits ()” instruction. A further example of the use of a state machine is the state machine associated with the “bufferbytes ()” operation. During the buffering operation, the buffer interface logic 330 generates a write enable signal for writing data to the connected buffer 332. However, if the buffering operation is stopped due to the use of the buffer 332 by another process, it takes precedence over the use of the buffer 332 by the data stream processor 150 and it indicates that the write enable signal for the buffer 332 is This is the case when it remains high during the period of outage. This will waste a significant amount of power. To prevent this, the state machine associated with the buffering process lowers the write enable signal during any outage period (low state) and writes when the buffer 332 becomes available again. It is operable to restore the enable signal.

  The control interface 350 enables the current state of the data stream processing device 150 and allows the processing performed thereon to be set, reset, saved and restored (Data Engine Core). Supports a set of instructions (executed by 142).

  FIG. 4 is a flow chart that schematically illustrates how a series of data stream processing tasks are performed by the data processing apparatus of FIG. The session is initialized at stage 410 and as a result the data processing device is activated. Next, in stage 420, the main processing device 110 that has determined the characteristics of the data processing resources that can be used at the time of activation, passes through any buffering resources that can be used via the buffer interface 330 and the accelerator interface 360. The configuration information is transmitted to the configuration module 310 (see FIG. 3) of the data stream processing device 150 that specifies the characteristics of all processing resources that can be used.

  Configuration information stored by the configuration module 310 is not accessible to the data engine 140. Once the configuration module is configured in stage 420, the data engine core 142 is started and can be used by the main processing unit 110 to execute a subset of processing tasks on its behalf. It becomes like this.

  At stage 430, the data engine core 142 receives program instructions and sends (at least some of) these instructions to the data stream functional unit 220 (see FIG. 2) for execution. In response to execution of certain program instructions, the data stream functional unit 220 sends at least one instruction to the data stream via the control interface 350 to perform data processing tasks on the data elements of one or more input data streams. Output to the controller 340. Data processing tasks that may be performed include data operations that require buffering of data elements. For example, instruction reordering stream access, or data stream connection (ie concatenation of parts of two or more input data streams to form an output data stream). After the task associated with execution of the predetermined instruction executed by the data stream functional unit 220 is completed, processing proceeds to stage 460.

  At stage 460, it is determined whether all data stream processing tasks received via the data engine core controller 210 have been completed. If further tasks must still be performed, then processing returns to stage 440. However, if all processing tasks have already been completed at stage 460, processing proceeds to stage 470, which results in the data engine core being stopped. It should be noted in the flowchart of FIG. 4 that for purposes of explanation, it is assumed that all program instructions received by the data engine controller 210 are to go to the data stream functional unit 220. is there. However, it will be appreciated that some instructions that do not involve data stream operations are actually directed to other functional units 230 to execute rather than the data stream functional unit 220.

  FIG. 5 is a diagram schematically illustrating the logic circuitry used in the data stream processing unit 150 to manage the input and output of the data elements of the data stream as they pass through. The logic circuit includes a set of data input registers 510 (which is part of the data receiving module 320 of FIG. 3) and a set of data access registers 520 and connected bit pointers 522 (both of the control interface 350 of FIG. 3). And a multiplexing module 530 (which forms part of the data stream controller 340 of FIG. 3) having a bidirectional data communication path that connects to a connected internal buffer 532. . 5 is external to the data stream arithmetic processing unit 150, whereas the buffer 332 in FIG. 3 is internal to the data stream arithmetic processing unit 150, the apparatus of FIG. Note that it is an alternative to.

  The data elements of the input data stream received by the DMA interface 370 (see FIG. 3) are temporarily stored in a first-in-first-out (FIFO) infrastructure in the data input register 510. . The FIFO nature of the data input register 510 allows the data stream to be accessed sequentially via the DMA interface 370. The management module 380 (see FIG. 3) records how many data elements have been received and which data elements are still in the data input register 510. The data element is output from the data input register 510 and supplied to the multiplexing module 530. Based on instructions received from the data stream functional unit 220 via the control interface 350 (see FIG. 3), the multiplexing module 530 may store some data elements from the data input register 510 for temporary storage. And direct other data elements from the data input register 510 directly to the data access register 520 of the control interface 350, which is accessible to the data engine core 142. The data stream processing device 150 stores management information including at least one reference point in the input data stream. This reference point corresponds to the state machine state associated with the data access register 520 in FIG. Similarly, the data input register 510 has an associated state machine that stores reference point information associated with the data input process. The fact that the data stream processing device 150 can store at least one reference point for the data stream effectively means that it can store state information. This allows execution of a “getbits ()” instruction that automatically reads bits from the data stream (as described above). Similarly, depending on the stored state information, the data stream processing device 150 acquires data from which port or writes data to which port (ie, an interface connected to the data input register 510, or a buffer 532). It is possible to automatically select the interface connected to the.

  Multiplex module 530 similarly buffered data in the input data stream for output to data access register 520 in response to an instruction generated in response to execution of a “getbits ()” instruction. The element is operable to read from the buffer 532. In addition, the management module 380 records which data elements are still in the buffer and where they are located, as well as which data elements are present in the data access register 520. The output data stream is generated by selectively outputting data elements from the data access register 520 onto the transmission stream using the “putbits ()” instruction.

  Bit pointer 522 points to the next data element to be supplied to the output data stream. In order to reset the bit pointer, a “resetbitpointer ()” instruction or a “reset ()” instruction is used. The data access register 520 of FIG. 5 automatically selects a reference point in the data stream that is used as a reference point by the data stream processing device 150 when operating on instructions from the data engine core. The data stream processing device 150 stores management information including this reference point. The management information also includes a record of which data elements are stored in the buffer 532 and which data elements are received at the data input register 510 via the DMA interface. As described above with reference to FIG. 3, DMA interface 370, accelerator interface 360, buffer interface 330, and control interface 350 all have an associated state machine. Thus, for example, the management information is stored in the state machine of each interface so that the state machine associated with the buffer interface 330 stores management information specifying which data elements are stored in the connected buffer 332. Can be distributed / assigned.

  FIG. 6 is a diagram schematically illustrating a logic circuit that controls the flow of data passing through the data stream processing apparatus. The logic circuit is operable to multiplex data elements from the buffer 532 (see FIG. 4) and data elements from the input data register. The device of FIG. 6 corresponds to the data path from the DMA interface 370 to the control interface 350 of FIG. Multiplexer 610 and multiplexer 612 are connected to the data path, while multiplexer 614, multiplexer 618, multiplexer 620, and multiplexer 622 are connected to the control path. Multiplexer 610 controls whether buffered data from buffer 332 or direct data from FIFO data input register 510 is supplied to data engine 140 via control interface 350. The multiplexer 612 controls whether the data from the FIFO input register 510 is supplied directly to the control interface 350 for output or alternatively to the buffer 332 for temporary storage. The data portion will be buffered and output in response to commands from the data stream functional unit 220 (see FIG. 2). Multiplexer 614 and multiplexer 618 are operable to receive an ACK signal (acknowledgment) from the data engine core (see FIG. 3) via control interface 350. Multiplexer 620 and multiplexer 622 are operable to output a request signal to data engine core 142 via control interface 350. If the data does not reach the FIFO 510, the FIFO outputs a hold signal that reaches the control interface 350 via the multiplexer 620 and the multiplexer 622. The hold signal stops the data engine controller 210 (see FIG. 3). On the other hand, if a data stream is being supplied to the FIFO 510, then an ACK signal (acknowledgment signal) is sent from the data engine core 142 to the FIFO 510 via the control interface 350, the multiplexer 614, and the multiplexer 618. It will be. The main data path connecting the FIFO 510 and the control interface 350 via the multiplexer 610 and the multiplexer 612 can be set as follows.

(i) Data is passed straight from the input FIFO 510 to the control interface 350 for use (consumption) by the data engine 140.
(ii) Read data from the buffer 332.
(iii) Buffer data from input FIFO 510 for storage in cache 332.

  Request / acknowledge multiplexer 614, multiplexer 618, multiplexer 620, and multiplexer 622 must follow the precedent. For example, in buffering mode, when data from the FIFO 510 is being fed into the cache 332, any request for data by the data engine 140 will result in an outage while buffering is in progress. To guarantee, a zero signal input will be placed on the request control path 620,622. For simplicity, the circuit shown in FIG. 6 does not show all of the circuit elements associated with data flow control. For example, additional circuit elements (not shown) are provided to provide the controller 340 with an ACK signal (acknowledgment signal) that recognizes the arrival of data at the data engine 140.

  FIG. 7 schematically illustrates a logic circuit that is operable to control the flow of data through the data stream processor and similarly store pending data being transferred when the data transfer is interrupted. It is a figure explaining. This device is an alternative to the device of FIG. The lower portion 710 of the circuit configuration is identical in both form and function to the circuit configuration of FIG. The upper portion 720 of the circuitry is operable to store pending data in the transfer. When the data engine core 142 transmits an instruction for interrupting the data transfer including the data stream supplied to the data receiving module 320 via the DMA interface to the data stream processing device 150 (see FIG. 3). The apparatus of FIG. 7 is useful. If the data engine core 142 outputs a command to terminate the data transfer when the data is still in a transfer state to the DMA interface 370 at that time, then the data engine core 142 does not currently require it, but the data It is desirable to buffer. Otherwise, when the data engine core 142 resumes processing, if the data already output by the DMA controller is simply discarded, the data stream is probably corrupted. The upper portion 720 of the circuit configuration of FIG. 7 consumes data being transferred or “overflow data” sent to the data stream processor 150 before the stop command from the engine core 142 is processed. Function. Overflow data is received by the input FIFO 510 and supplied to the buffer 742 for storage via the multiplexer 744. Regarding the resumption of processing by the data engine core 142, the data stored in the buffer 742 is processed below the circuit configuration 710 for processing via the interface 730 that connects the upper circuit portion 720 to the lower circuit portion 710. Supplied to the part. The circuit configuration of FIG. 7 allows the data stream to be interrupted without data loss. As mentioned above, the data stream processing device 150 has (at least) a state machine associated with each of its interfaces. If an abnormal data end occurs, it will be recognized that the state machine state at the time prior to the abnormal end operation is saved to allow the process to resume at a later time.

  FIG. 8 is a diagram schematically illustrating a state machine representation of the multiplexing operation performed by the logic circuit of FIG.

  With respect to the data multiplexing processing task depicted in FIG. 8, the data stream processing device 150 operates in one of three processing states including a default output state 810, a buffering state 820, and a buffer data read state 830. be able to.

  In state 810, data is read directly from the data input register 510 (see FIG. 4) and provided to a data access register 520 ready for transmission of the output data stream. State 820 is a buffering state in which data read from the data input register 510 is routed by the multiplexing module 530 to a buffer 532 for temporary storage until such time as requested from the output. The state transition from the state 810 to the state 820 is executed in response to an instruction from the data stream function device 220 (see FIG. 3) generated as a result of executing the “bufferbytes ()” instruction. When this state transition occurs (from state 810 to state 820), the counter maintained by management logic circuit 380 is reset, and thereafter this counter determines the number of consecutive data elements in the buffered data stream. Record and guarantee to enter the buffering state 820 with a predetermined count value. In state 820, once the requested number of data elements (eg, bits, bytes, or words) has been buffered, then a state transition is performed to return to the default output state.

  If the data stream function device 220 (see FIG. 3) executes a “backstep ()” instruction when the system is in the default output state 810, then a state transition to the buffer data read state 830 occurs. Will do. In the buffer data read state 830, the management module 380 of the data stream processing device determines the storage location of the stored data element corresponding to the previous point in the temporary sequence of the input data stream. In addition to being referenced by the device 340, the data stream controller 340 resets the bit pointer 522 (see FIG. 5) to prepare for output of the stored data to the output data stream. This is the way in which instruction reordering access to a given input data stream is achieved. Any request for data from the data engine core 142 when the data stream processor 150 is in either the buffering state 820 or the buffer data read state 830 will result in a stall. This outage is achieved by supplying zero to the multiplexer 620 of the apparatus of FIG.

  FIG. 9A is a diagram schematically illustrating a format of a part of an MP3 audio data stream. The data stream processing device 150 uses the FIFO data input register 510 (see FIG. 3) to sequentially access the input data stream via the DMA interface 370. However, the MP3 standard specifies that it is possible to return up to 512 bytes in the bitstream during processing of the input MP3 data stream to access the main data stored in the previous frame. MP3 audio corresponds to MPEG1 layer 3 audio and MPEG2 layer 3 audio, and is related to the following industry standards “IS0-IEC 11172-3” and “IS0-IEC 13818-3”.

  Note that 512 bytes exclude the header date, cyclic redundancy check (CRC) data, and side information. After such a “backstep” instruction, all header, CRC, and side information is skipped. Accordingly, it will be appreciated that up to 512 bytes of payload data may appear in the input data stream before the header and CRC information associated with the payload data is received. Thus, there will be a request to buffer this data for some time after the relevant header information is received.

  Referring to FIG. 9A, a typical MP3 bitstream portion includes a total of 66 data elements “DS [O: 65]”. The data stream includes a first header portion 910 that includes a data element “DS [O: 4]”, a first payload data portion 920 that includes a data element “DS [5:34]”, and a data element “DS [ 35:45] ”, a second payload data portion 930 containing a data element“ DS [46:50] ”and a second header portion 940 containing a data element“ DS [51:65] ”. 3 payload data portions 950.

  The first payload data portion 920 is combined with the first header portion 910, while both the second payload data portion 930 and the third payload data portion 950 are the second header portion 940 and Are combined. Since the second payload data portion 930 appears at a point in the temporary sequence of inputs prior to receipt of the associated header portion (second header portion 940), it was relevant when that payload data was processed. It is appropriate to buffer the second data portion 930 before output so that header information is available.

  FIG. 9B schematically illustrates a series of data operations (or processing tasks) performed by the data engine core 142 and the data stream processing device 150 (see FIG. 3) for the input data stream portion of FIG. 9A. .

  In step 1, the first header portion 910 is read by the data engine 140. This operation is performed in response to execution by the data stream functional unit 220 (see FIG. 3) of a “getbits ()” instruction having five input arguments representing five data elements. This results in the data element “DS [O: 4]” being read from the FIFO data input register 510 and supplied to the data access register 520 (see FIG. 5) ready for output.

  In step 2, the first payload data portion 920 is read from the input data register 510. This is accomplished by the data stream functional unit 220 executing the program instruction “getbits (30)”, so that the data element “DS [5:34]” is removed from the input data register 510 and ready for output. Stored in the data access register 520.

  In step 3, the second payload data portion 920 is read from the data input register 510 and provided to the multiplexing module 530 where it is routed to a buffer 532 for temporary storage. This operation is performed by the data stream processing device 150 in response to the execution of the command “bufferbits (11)” by the data stream function device 220. Eleven data elements corresponding to “DS [35:45]” are stored in the buffer. The management module 380 (see FIG. 3) saves which data elements are buffered and the location of the buffer where they are stored.

  In step 4, the second header portion 940 is read from the input data register 510 and stored in the data access register 520 ready for transmission of the output data stream. Since the data elements of the second payload data portion 930 were buffered in step 3, the second header portion will be output directly after the first payload data portion 920.

  In step 5, the data engine core 142 prepares to access the buffer 532. Therefore, the data stream functional unit 220 executes the instruction “backstep (11)” and, as a result, the bit pointer 522 that controls the current output position of the data to be supplied to the output data stream is “DS [35 ] ”, Ie, rewound to correspond to the start point 35 of the second payload data portion.

  In step 6, the second payload data portion 930 is read from a buffer ready for output from the data access register 520. Since the bit pointer 522 has been reset in step 5, this data can be added to the output data stream by execution of the instruction “getbits (11)” by the data stream functional unit 220.

  Finally, in step 7, the third payload data portion 950 combined with the second header portion (similar to the second payload data portion 930) is read from the input data register 510 and the output It is stored in the ready data access register 520. This is achieved by the execution of the instruction “getbits (15)” by the data stream functional unit 220, and in response, the data element “DS [51:65]” is output.

  FIG. 10 is a diagram schematically illustrating an apparatus in which the buffer of FIG. 3 is implemented as a software FIFO. FIG. 10 shows a subset of the components of the data stream processing device 150 and the data engine core 142, and their bidirectional information exchange (bidirectional communication) will be described by the software FIFO 1005. A software FIFO 1005 is connected to the data stream controller 340, and the data stream controller 340 is operable to selectively provide data elements of the input data stream to the software FIFO 1005 for buffering. Data stream controller 340 injects and ejects software FIFO 1005 in response to at least one of local head address 1010 and local tail address 1020 stored in a management record maintained by management module 380. Operate to manage. The memory area associated with the software FIFO is defined by the partition pointer.

  The local head address 1010 and the local tail address 1020 are physical addresses associated with memory areas allocated for use as the software FIFO 1005. Head pointer 1010 controls the memory location to be written when a new data element is received by software FIFO 1005 from data input register 510 (see FIG. 5). The tail pointer 1020 advances when data elements at or near the tail position are no longer needed, for example because they have already been sent to the output data stream.

  The management module 380 records which data elements stored in the buffer are no longer needed and manages the advancement of the head pointer 1010 and the tail pointer 1020. However, these two pointers 1010, And the pointer 1020 may be changed as well. An example of this was described above with reference to step 5 of FIG. 9B.

  The head pointer is moved based on the DMA data provided to the data stream processing device via the DMA interface 370 and the data receiving module 320 and the available space in the buffer (the head has not yet engaged the tail). The tail pointer is updated in response to a “getbit ()” type instruction output from the control interface 350. However, the tail pointer is not modified after the “forward ()” instruction (equivalent to the “bufferbytes ()” instruction).

  The software FIFO 1005 defines a circular buffer memory (ring) in which the head pointer and tail pointer define the beginning and end of stored data, respectively, and circulate at the end of the memory address space in a conventional manner for circular buffers. Buffer).

  In order to perform data processing operations in a system that does not include a data stream processor 150, a number of data processing operations need to be explicitly specified in software by the programmer. For example, a portion of program code (written in the C programming language) shown below performs a function corresponding to a “getbits ()” instruction according to the present technology, that is, a function for reading a data portion of a data stream.

  From the above program code, it can be seen that data processing operations such as bit alignment, masking, and concatenation are specified in software functions. According to the present technique, all of these data processing operations are removed from the programmer. To read a portion of data in accordance with the present technique, the data engine core 142 simply executes a “getbits ()” instruction, which results in a control signal sent to the control interface 350 (see FIG. 3), In response, the data stream processing device 150 performs reading of the data portion from the data stream.

  The above program code is for use in a system where the format of the read data is determined by the physical properties of the system, i.e. the bus width and port width.

  FIG. 11A is a diagram schematically illustrating “example 1” in the above-described program code in which the data portion is read from the data word 1100. In FIG. 11A, the bus width (equivalent to the word length) is N bits, and the portion of the data to be read corresponds to the data portion “bits2get”. In this case, the requested number of bits of data is sufficiently small that it is contained within one data word 1100. Portion 1110 corresponds to data that has already been consumed. Of the available data, only a subset corresponds to “bits2get”. To read this data, the available bits are least significant bit (LSB) aligned and unnecessary bits of the word are masked.

  FIG. 11B schematically illustrates “Case 2” in the above program code. In this example, the bit “bits2get” to be read spans two data words: a first data word 1200 and a second data word 1300. The data portion 1210 of the first data word 1200 corresponds to a bit that has already been consumed. The available bits “part1bits” of the first data word 1200 are not sufficient in number to satisfy the data request, so the data word 1300 must be read as well and to satisfy the request. The part of the second data word “part2bits” corresponding to the additional number of bits required is extracted from the second data word 1200. In this case, “part1bits” from the first data word 1200 and “part2bits” from the second data word are concatenated in an LSB alignment (LSB alignment) format to prepare for output.

  12A and 12B are diagrams schematically illustrating the use of the “setcount ()” instruction. The “setcount ()” and resetcount () instructions are explicitly provided to make data stream access more secure.

  In FIG. 12A, the argument of the “setcount ()” instruction is a default value that means there is no limit on the number of bits that can be read from the data stream. Thus, the data stream pointer can be incremented indefinitely. However, it should be noted that the pointer of the data stream has an associated state that includes at least the value of the pointer. An additional state variable corresponds to whether the data pointer is locked or released. Data output is prevented in the locked state.

  In FIG. 12B, the “setcount ()” instruction has an argument M. This is because the state of the bit pointer at the moment the instruction (ie, control signal) associated with the “setcount (M)” instruction is sent from the data engine core 142 to the data stream processing device 150 (see FIG. 3). Set an upper bound on the data pointer state associated with. In FIG. 12B, the state of the data stream pointer when the “setcount (M)” instruction is transmitted to the data stream processing device 150 corresponds to the value of “t”. At the next time corresponding to the state when the data stream pointer has a value of “(t + K)”, an instruction signal resulting from the execution of the data read instruction “getElements (P)” is transmitted by the data stream processing device 150. Received. The “getelements (P)” instruction requested reading P data elements from the data stream. However, as shown in FIG. 12B, the reading of the P data elements results in exceeding the “setcount (M)” threshold for the data stream pointer. The threshold is equal to “t + M”. Therefore, the output of the “getElements (P)” operation is declared invalid.

  In the above discussion of the embodiments of the present invention, it has been described that the main processor (ie, the main processing unit) is connected to a single data engine, while it is likewise a single processor comprising multiple data engines. Could be connected to a hierarchy. It is equally possible to arrange many data engines in a hierarchical manner. For example, the main processor may present itself as a data engine to a higher level hierarchy.

  For the interested reader, more general features of embodiments of the present invention are described in the following paragraphs.

"Overview"
“AudioDE” is an application class specific data engine that is tailored to digital signal processing built into portable audio applications. A combination of structural characteristics and a highly parallelizing compiler provides a solution that results in minimal power and area requirements for audio applications. The accompanying dedicated system functions and the general “ARM-AMBA” interface function (AIKO) support easy integration of “AudioDE”.

"Introduction"
The design goal for “AudioDE” focuses on maximizing the requirements of portable audio players, namely power and area performance (PPA). This results in a digital signal processing platform (DSP) that still requires a minimum “MHz” for its task, with a small core size, and a small memory footprint. For both integer and fractional data calculations, "AudioDE" can be used equally well for other DSP algorithms, despite the name, because the microstructure features a standard DSP instruction set.

  The “AudioDE” core strikes a balance between computational resources, register files, memory bandwidth, and address generation capabilities. This property, along with multiple instruction sets for variable length-long instruction word (VL-LIW) controllers, is common in applications of interest, thus minimizing "MHz" requirements. Enables the development of very fast and extremely parallel algorithms.

  “AudioDE” includes a single 24-bit integer arithmetic unit (ALU) and a single 24 × 24-bit multiply-accumulate unit (Multiplier and Accumulator unit: MAC) that accumulates 48 bits. It has a dual Harvard structure. These units operate in parallel with two data memory ports and an associated address generator. Efficient single cycle memory access is supported for all addressing modes such as bit inversion and modulo addressing.

  The ALU is extended with instructions to facilitate bitstream access that is typical for compressed media files. This feature allows “AudioDE” to directly process data from DMA-driven input streams and provides an automatic buffering facility for instruction reordering access in the stream, as is common to many standards. provide. As with other external interfaces such as memory ports, “AudioDE” automatically enters a low power mode when data is not available.

  The “OptimoDE” structure is equipped with a comprehensive set of development tools. These tools include both cores, structural means that allow for enhanced simulation means such as instruction set simulators, and "OptimoDE" advanced parallel processing compilers. The compiler achieves code efficiency as good as any handmade assembly library. Since these tools can be operated in an interactive environment, feedback is provided for optimization at the source level and for trade-offs between speed and object code size.

  The MP3 decoder is a good example of the efficiency of the “AudioDE” core and “OptimoDE” tool. The decoder can be programmed to require only 8 [MHz] cycles with a 22 [Kbyte] program and 22 [Kbyte] data memory, and 1.2 [V] for the 42 [Kgate] core. ] Results in a power consumption of 0.8 [mW] in a 0.13 [μm] CMOS.

“OptimoDE” technology
“AudioDE” is derived from the standard “OptimoDE” structure using the standard tools and IP framework provided as part of the structure. This means that although specific configurations are presented in this specification, it is easy to generate variations or extensions that better fit the application. There are three stages in the data engine development cycle: :

-Design stage: selection or creation of microstructures.
-Programming phase: compiling and profiling source code for a fixed structure for tasks that will run on the data engine;
-Implementation stage: Implementation of the microstructure in synthesizable "Verilog". This includes standard instantiations or resource instantiations defined by users.

  When the microstructure can be modified, the first two stages can be over-determined repeatedly. A configuration tool that is all part of one framework simplifies this process. In other cases, only the last two stages can be applied and only machine code for a fixed structure will be generated. FIG. 13 illustrates this process.

  The result of the design phase is the release of a microstructure with fixed characteristics by the “DesignDE” configuration tool. An ISS model is similarly generated.

  Part of this process involves the programming and profiling of related code fragments and is equivalent to the programming steps described below, unless there is a specific purpose to improve the microstructure.

  “DesignDE” has several components. The configuration tool captures a given microstructure and allows easy modification and expansion. In the latter case, the designer defines the interconnection between data path resources. A standard resource library with functional devices is provided.

  User-defined resource design maintains a library of such components and generates a “Verilog” from the source description of “C”, “C ++”, or “System C” Promoted by Librarian. This “Verilog” is functionally correct and can be synthesized.

  The result of the programming phase is the release of microcode by the “DEvelop” compiler corresponding to the given source code for the provided microstructure.

  The source code is compiled in an interactive manner. “DEvelop” provides detailed and static profiling results regarding detailed schedules and resource usage.

  Improved dynamic profiling can be performed based on an ISS model that complements the microstructure.

  The result of the implementation phase is a synthesizable “Verilog” of the microstructure exemplified by the “BuildDE” tool. Since code development requires only the results of the design phase, the implementation phase can be performed in parallel with it, thus reducing elapsed time.

"Application class specific design flow"
“AudioDE” is a unique result of a core constructed using the “OptimoDE” tool. Starting from one of the “OptimoDE” starting microstructures, this section shows the design process of “AudioDE”.

  FIG. 14 illustrates various steps in the design process. The purpose of the process is to find the balance between core cost and its efficiency while eliminating the risk of overdesign.

  Algorithm and application class analysis: As a starting point, many existing audio applications and general DSP applications were analyzed and outlined. In particular, the following observations seemed to be related to the audio algorithm. :

Noise requirements support a 24-bit data path that reduces intermediate scaling overhead.
-The audio encoding algorithm is based on MAC's centralized filter bank.
-Variable length data is read from the bitstream and inserted into the bitstream.

  These, and more elaborate observations, are used to define performance predictions for the microstructure to be solved either by instruction set specialization or data path parallelization.

  Application-specific resources and instruction set: One of the applications of this method for “AudioDE” resulted in an enhancement of the standard ALU for bitstream access. Algorithmic analysis shows that providing instructions specifically for this purpose results in significant savings.

  This specialization is particularly effective because it not only saves the “MHz” of the calculation period, but also reduces the structural complexity by providing a unified interface to streaming media.

  In general, "AudioDE" refers to extended instructions for fractional arithmetic for signal processing, integer arithmetic for standard "C" support, and zero-overhead address computation. Featuring a rich instruction set with equal attention.

  System structure tuning: This feature of the micro structure definition corresponds to the ability to perform continuous zero-overhead parallel MAC-style computation. The performance indicators are both traditional DSP benchmark algorithms and filter codes found in audio applications.

  This tuning stage defined a data path that supports high-throughput calculations while maintaining efficient state and power consumption. Therefore, the “AudioDE” system structure was chosen to include only a single MAC and ALU. Although this limits the parallelism of operation, the ALU and MAC are arranged so that the algorithm can be operated with 100% load on the unit, thus providing a high level of data movement parallelism.

"AudioDE hardware structure"
The overall hardware structure is illustrated in FIG.

  “AudioDE” features a low branch delay controller with multiple instruction sets and a variable length-long instruction word (VL-LIW). The “OptimoDE” compiler has sufficient visibility of the instruction and data pipeline in all programs, and the complexity of loop control is solved by development tools that reduce hardware complexity.

  All “AudioDE” functional devices are single cycle with no internal pipeline. Since the “OptimoDE” compiler is responsible for all data path operations, the device can be pipelined to achieve higher clock frequencies without any modification in the controller.

  The “AudioDE” data path is composed of a 24-bit ALU and a 24-bit MAC device. The MAC unit performs single-precision multiplication or single-cycle, double-precision accumulation. Fractional multiplication is supported by automatic output alignment. Since the saturator is an integral part of the device, all instructions can be saturated or desaturated. In addition, both ALU and MAC support absolute and explicit rounding instructions for multiplication, right shifting, and type conversion.

  The data path features a large high bandwidth register file. Its size is suitable for high speed radix-4 calculations of FFT and DCT, or similar algorithms.

  To reduce structural complexity in the “AudioDE” core and simplify compiler tasks, the arithmetic data path is relatively separated from the address generation data path described below.

  As with the high radix algorithm, two independent next to the third single-wide program memory port to maintain a simple single-cycle multiply-accumulate sequence A data memory port was provided.

  In order to minimize the memory requirements for cost-sensitive embedded applications, the X-memory and Y-memory are made asymmetric. Only the X-memory is 24 bits wide to meet typical audio processing requirements, while the Y-memory is optimized for 16 bits sufficient for integer and coefficient data. A large data path register file ensures that there are no adverse conditions associated with the fact that 24-bit data is limited only to X-memory.

  As discussed in the above section, the “AudioDE” memory is outside the data path to provide total freedom regarding cost optimization and system integration issues.

  Each data memory has its own address generator with a 15 bit address range. Note that this is the address range maintained for a single task, and the total address range can be extended by memory management functions in the subsystem.

  The address generator is capable of single cycle operation in all modes including automatic modulo addressing and programmable bit-reversed addressing. The latter is particularly important for the FFT algorithm.

  The number of available primary pointer and secondary pointer manipulation register fields is optimized to save power, space, and control complexity.

  The stream interface is a unique multimedia specific feature of “AudioDE” for improved performance and reduced complexity, both from a programming and integration perspective.

  This interface allows “AudioDE” to be connected as a DMA slave device and to process bitstreams without the need for further bidirectional information exchange (bidirectional communication) with the host system. .

  The data path API is a function related to variable length bit stream access having an automatic data alignment function, and an instruction reordering access to a bit stream which is common in a constant bit rate (CBR) audio encoding algorithm Provides a stream buffer and rewind function for

"Power reduction function"
A common "OptimoDE" approach for low power consumption is to reduce "MHz" requirements by taking advantage of all available parallelism. This results in a very dense code with very high resource activity, thus minimizing unnecessary on-off toggling of resources as well. Further, with respect to the loop body, such dense code is suitable for other optimizations related to memory management within the cache or system outside the core.

  Apart from their structural advantages, the “AudioDE” core has additional power saving technologies. In addition to that particular low power library, a library provided by ARM's physical IP department can be used during silicon-mapping.

  Clock gating: The "AudioDE" core description is fully compatible with industry standard clock gating.

  “AudioDE” is specifically designed for both streaming interfaces and use of external storage devices. If data is not available, the “AudioDE” core automatically enters a low-power stall mode.

  The “OptimoDE” compiler has full visibility of the complete instruction and data pipeline. Thus, when data must be available for input, or when it occurs, this property avoids unexpected pipeline outages and related additional logic.

"System integration"
“AudioDE” is related to the data engine, but it is also designed for clearly cost-effective system integration. For this reason, some components have been explicitly excluded from the core to provide the possibility to share these functions with blocks that already exist in the system, for example DMA controllers.

  With respect to cost-sensitive system memory features, the same freedom for optimization is provided to system designers. Two examples of system integration scenarios are described below. Both scenarios are supported by standard “OptimoDE” components, such as AMBA Integration Kit (AIKO) for “OptimoDE”.

  Minimal cost solution: This scenario corresponds to a power optimized and area optimized solution that appears at the expense of application flexibility. This would be compatible with audio player products based on, for example, low cost portable flash cards.

  In this case, “AudioDE” is integrated into a local dedicated memory. This configuration minimizes power consumption because the memory size and topology can be freely selected as a function of the best results. In addition, the streaming interface completely eliminates the need for any fast system interaction, thus allowing "AudioDE" to operate as a highly efficient high performance peripheral.

  The AIKO interface ensures that their memory is always visible to the system.

  Flexible shared memory structure: This scenario targets the highest flexibility for application development subject to the limitations of minimum memory power consumption. An example of such an application would be an audio player that supports many different codecs.

  As with any system resource such as the host bus or DMA controller, all “AudioDE” memory ports in this case are connected to a flexible single-level shared memory arbiter circuit. Connected. This configuration still allows for optimal memory size and layout for minimal power consumption, while providing lock-free and starvation-free operation of all system functions. Guarantee.

  In particular, the "AudioDE" subsystem also features a lightweight memory management function to enable dynamic configuration of memory and task address spaces.

"MP3 application example"
As a means to establish the point of performance certification, the MP3 decoder algorithm of IS0 / IEC specification was compiled for "AudioDE". This algorithm has two distinct features. First, the bitstream decoding and dequantize functions are later connected with stereo processing and a large two-stage synthesis filter bank.

  The first part of the code used the rich “AudioDE” bitstream access API. This resulted in a simple, compact and very efficient code. The second part of the algorithm was organized to take advantage of the high radix processing power of “AudioDE”. For both sections, C code was used as the source language.

  The resulting algorithm required 8 [MHz] periods for a stereo signal sampled at 48 [KHz] from a 320 [Kbit / s] bitstream. This code used 22 [Kbyte] program memory and 22 [Kbyte] data memory. Deploying power saving technology is described in the above section using 0.13 [μm] at 1.2 [V] using ARM's Physical IP low-power libraries. It has been described to yield a 42 [Kgate] core with a power consumption of 0.1 [mW / MHz] in CMOS. When decoding such an audio stream, the power consumption for the “AudioDE” core is just below 0.8 [mW], while with an optimal memory subsystem, the total power consumption is sufficiently 2 [mW ] Would be less.

"Conclusion"
“AudioDE” is a small, power efficient core that uses the configuration and development tools derived from the “OptimoDE” structure and supplied with standards. The result of this is a design that can run the MP3 benchmark algorithm with half the gate and resources, yet almost twice as fast as the alternative solution.

  While illustrative embodiments of the invention have been illustrated in detail herein with reference to the accompanying drawings, the invention is not limited to those precise embodiments and is intended to be the subject of the invention as defined by the appended claims. It should be understood that various changes and modifications thereto can be achieved by those skilled in the art without departing from the scope and spirit.

1 is a diagram schematically illustrating a data processing system. FIG. FIG. 2 schematically illustrates the data engine of FIG. 1 in more detail. FIG. 2 is a diagram schematically illustrating a logic circuit in the data stream processing apparatus of FIG. 1 and how the data stream processing apparatus interfaces with a data engine core. FIG. 2 is a flowchart schematically illustrating how a series of data stream processing tasks are performed by the data processing apparatus of FIG. FIG. 2 schematically illustrates a logic circuit used in a data stream processing unit 150 to manage the input and output of data elements of a data stream as they pass through. It is a figure which illustrates schematically the logic circuit which controls the flow of the data which passes a data stream processing apparatus. FIG. 6 schematically illustrates a logic circuit that controls the flow of data through a data stream processing device and is similarly operable to store pending data being transferred when the data transfer is interrupted. is there. FIG. 7 schematically illustrates a state machine representation of a multiplexing operation performed by the logic circuit of FIG. 6. It is a figure which illustrates roughly the format of the part of MP3 audio data stream. FIG. 9B is a diagram schematically illustrating a series of data operations (or processing tasks) executed by the data engine core and the data stream processing apparatus of FIG. 3 for the input data stream portion of FIG. 9A. FIG. 4 is a diagram schematically illustrating an apparatus in which the buffer of FIG. 3 is implemented as a software FIFO. It is a figure explaining reading of the data part from the data word which has a predetermined size. It is a figure explaining reading of the data part from the data word which has a predetermined size. It is a figure which illustrates roughly how a "setcount ()" command performs a data protection function. It is a figure which illustrates roughly how a "setcount ()" command performs a data protection function. It is a figure which illustrates roughly the general characteristic of the Example of this invention. It is a figure which illustrates roughly the general characteristic of the Example of this invention. It is a figure which illustrates roughly the general characteristic of the Example of this invention.

Explanation of symbols

110 Main Processing Unit 120 Memory 130 Direct Memory Access (DMA) Controller 140 Data Engine 142 Data Engine Core 150 Data Stream Processing Unit 160 System Bus 210 Data Engine Controller 220 Data Stream Functional Unit 230 Multiple Other Functional Units 310 Configuration Module 320 Data reception module 330 Buffer interface 332 Buffer 340 Data stream controller 350 Control interface 360 Accelerator interface 362 Accelerator 370 DMA interface 380 Management module 510 Data input register 520 Data access register 522 Bit pointer 530 Multiplex module 532 Internal buffer 810 Default output state 820 bag Aringu state 830 buffer data read state 1005 software FIFO
1010 Head address 1020 Tail address

Claims (58)

(i) a main processing unit operable to perform a plurality of data processing tasks;
(ii) a data engine having a data engine core operable to perform some of the plurality of data processing tasks on behalf of the main processing unit;
(iii) a data stream processing device that provides a data communication path between the main processing device and the data engine core;
The data stream processing device is
(a) a control interface operable to receive at least one instruction from the data engine core;
(b) receiving at least one input data stream and operative to perform at least one operation on the at least one input data stream to generate at least one output data stream including a series of data elements With a possible data stream controller,
The data stream processing device is responsive to the at least one instruction from the data engine core to control the data stream controller to perform the at least one operation ;
The data stream processing device is operable to store management information including at least one reference position in the at least one input data stream;
The data stream processing system, wherein the data stream processing device executes at least one command based on the at least one reference position . Some of the data processing tasks performed by the data engine core comprise a series of instructions including at least one instruction of an instruction set executable by the data engine core;
The data engine core is operable to output the at least one instruction to the control interface of the data stream processing device with respect to execution of the at least one instruction. Data stream processing system. The input data stream is a multimedia data stream structured according to a predetermined set of rules;
The data stream processing system of claim 2 , wherein the instruction set is defined based on the predetermined set of rules. The data stream processing device is operable to operate asynchronously according to the at least one instruction with respect to reception of the input data stream by the data stream controller or with respect to transmission of the output data stream element; The data stream processing system according to claim 1, wherein: The data stream processing system of claim 1, wherein the data stream controller is configurable by at least one of the data engine and the main processing device comprising configuration information. When the data stream controller is performing the at least one operation, the data stream controller is operable to selectively buffer at least a portion of the at least one input data stream within a connected buffering resource. The data stream processing system according to claim 1. The data stream processing apparatus comprises a data output logic circuit having a multiplexer operable to selectively output data from the buffering resource;
The data stream processing system of claim 6 , wherein the data stream controller is operable to control an output of the multiplexer to generate the at least one output data stream. The data stream processing system according to claim 6 , wherein the connected buffering resource is a software FIFO. Claim 6 wherein the data stream controller, characterized in that said operable such that at least one of which parts of the input data stream to store the history of whether the currently stored in the connected buffered resources The data stream processing system described in 1. The data stream controller is configurable by at least one of the data engine and the main processing unit comprising configuration information;
The data stream processing system according to claim 6 , wherein the configuration information includes a size of the buffering resource connected to the data stream controller. The data stream processing device comprises a processing interface for providing a data path to a processing module;
The processing module of claim 1, wherein the processing module is operable to perform a processing task in response to execution of at least one instruction of the instruction set executable by the data processor core. Data stream processing system. The data stream controller is configurable by at least one of the data engine and the main processing unit comprising configuration information;
Claim 11 wherein the data engine, and the configuration information supplied to the data stream processing unit by at least one of the main processing apparatus, characterized by comprising at least the property of one of the processing resources Data stream processing system. The data stream controller is configurable by at least one of the data engine and the main processing unit comprising configuration information;
The configuration information provided to the data stream processing device by at least one of the data engine and the main processing device is a start point and an end point of the buffering resource connected to the data stream controller. The data stream processing system according to claim 6 , comprising: The at least one input data stream includes a plurality of data portions arranged in order in a temporary sequence of inputs;
The at least one output data stream includes the plurality of data portions of the temporary sequence of inputs arranged in order in a temporary sequence of outputs different from the temporary sequence of inputs. The data stream processing system according to claim 1. Wherein said executable said instruction set by the data engine core at least one instruction, or an instruction having a response conditional, according to claim 2, characterized in that one of the instruction with an unconditional response Data stream processing system. The at least one instruction corresponds to a respective process to be performed by the data stream controller in response to the at least one instruction output by the data stream functional unit;
The data stream processing system of claim 2 , wherein the respective processing comprises an associated state machine maintained by the data stream controller. The instruction set executable by the data engine core includes a buffering instruction operable to cause the data stream controller to selectively buffer a data portion of the at least one input data stream. The data stream processing system according to claim 6 . The instruction set executable by the data engine core causes the data stream controller to read at least one data element of the at least one input data stream from the buffering resource and the at least one output data The data stream processing system of claim 1 , further comprising a data read instruction operable to cause the stream to output the at least one data element. The management information is at least a current output position indicating data in one of the at least one input data stream to be next supplied to the at least one output data stream by the data stream controller. The data stream processing system according to claim 1 , further comprising: The current output such that the instruction set executable by the data engine core corresponds to a data element at a previous point in a temporary sequence of inputs associated with a corresponding input data stream and a current output position. The data stream processing system of claim 1 , further comprising a back command operable to cause the position to change. The management information includes a history indicating which data elements of the at least one input data stream are stored in the buffering resource, and which data elements of the at least one input data stream are received by the data stream controller. The data stream processing system according to claim 6 , comprising at least one of histories indicating whether or not. The instruction set executable by the data engine core includes data insertion instructions operable to cause the data stream controller to insert data from the data engine into the at least one output data stream. The data stream processing system according to claim 1 . The direct memory access interface operable to provide a direct memory access controller with a data communication path for supply of the at least one input data stream to the data stream controller. The described data stream processing system. The data stream controller is configurable by at least one of the data engine and the main processing unit comprising configuration information;
The data stream processing system of claim 23 , wherein the configuration information includes at least one characteristic of the direct memory access controller. The data stream processing device for temporarily storing data elements of the at least one input data stream before the data stream controller supplies the stored data elements to the at least one output data stream; The data stream processing system according to claim 1, further comprising: a data input register. The instruction set executable by the data engine core is related to the state of the data pointer at a moment when an instruction associated with a count setting instruction is transmitted from the data engine core to the data stream processing device. The data stream processing system of claim 1 , further comprising a count setting instruction operable to instruct the processing device to set an upper limit of a data pointer state. The data stream processing system according to claim 1, wherein the data stream processing device is at least partially incorporated in the data engine. A data engine having a main processing device operable to execute a plurality of data processing tasks, and a data engine core operable to execute some of the plurality of data processing tasks on behalf of the main processing device A data stream processing device for providing a data communication path between
The data stream processing device is
(a) a control interface operable to receive at least one instruction from the data engine core;
(b) receiving at least one input data stream and operative to perform at least one operation on the at least one input data stream to generate at least one output data stream including a series of data elements With a possible data stream controller,
The data stream processing device is responsive to the at least one instruction from the data engine core to control the data stream controller to perform the at least one operation ;
The data stream processing device is operable to store management information including at least one reference position in the at least one input data stream;
The data stream processing apparatus, wherein the data stream processing apparatus executes at least one command based on the at least one reference position . (i) a process of assigning a plurality of data processing tasks to the main processing unit;
(ii) using a data engine having a data engine core to execute some of the plurality of data processing tasks on behalf of the main processing device;
(iii) using a data stream processing device to provide a data communication path between the main processing device and the data engine core;
(iv) a process of receiving at least one instruction from the data engine core in the data stream processing device;
(v) receiving at least one input data stream at a data stream controller of the data stream processing device;
(vi) performing at least one operation on the at least one input data stream to generate at least one output data stream including a series of data elements;
The data stream processing device is responsive to the at least one instruction from the data engine core to control the data stream controller to perform the at least one operation ;
The data stream processing device is operable to store management information including at least one reference position in the at least one input data stream;
The data stream processing method, wherein the data stream processing device executes at least one command based on the at least one reference position . (i) a main processing unit operable to perform a plurality of data processing tasks;
(ii) a data engine having a data engine core operable to perform some of the plurality of data processing tasks on behalf of the main processing unit;
(iii) a data stream processing device that provides a data communication path between the main processing device and the data engine core;
The data stream processing device is
(a) a control interface operable to receive at least one instruction from the data engine core;
(b) having a first interface for at least one data stream and a second interface for at least one data element stream including a series of data elements, and wherein the first interface and the second interface A data stream controller operable to perform at least one operation for managing data transfer between,
The data stream processing device is responsive to the at least one instruction from the data engine core to control the data stream controller to perform the at least one operation ;
The data stream processing device is operable to store management information including at least one reference position in the at least one data stream or the at least one data element stream;
The data stream processing system, wherein the data stream processing device executes at least one command based on the at least one reference position . Some of the data processing tasks performed by the data engine core comprise a series of instructions including at least one instruction of an instruction set executable by the data engine core;
32. The method of claim 30 , wherein the data engine core is operable to output the at least one instruction to the control interface of the data stream processing device with respect to execution of the at least one instruction. Data stream processing system. The at least one data stream is a multimedia data stream structured according to a predetermined set of rules;
32. The data stream processing system of claim 31 , wherein the instruction set is defined based on a predetermined set of rules. The data stream processing device operates asynchronously according to the at least one instruction with respect to reception or transmission of the at least one data stream of the first interface or the at least one data element stream of the second interface The data stream processing system of claim 30 , wherein the data stream processing system is operable to: 31. The data stream processing system of claim 30 , wherein the data stream controller is configurable by the main processing device comprising configuration information. When the data stream controller is performing the at least one operation, selectively the at least one data stream, or at least a portion of the at least one data element stream, in a connected buffering resource. The data stream processing system of claim 30 , wherein the data stream processing system is operable to buffer. The data stream processing apparatus comprises a data output logic circuit having a multiplexer operable to selectively output data elements from the buffering resources;
36. The data stream processing system of claim 35 , wherein the data stream controller is operable to control an output of the multiplexer to generate the at least one data element stream. 36. The data stream processing system of claim 35 , wherein the connected buffering resource is a software FIFO. The data stream controller is operable to store a history of the at least one data stream or which portion of the at least one data element stream is currently stored in the connected buffering resource. 36. A data stream processing system according to claim 35 . The data stream controller can be configured by the main processing unit with configuration information;
36. The data stream processing system according to claim 35 , wherein the configuration information includes a size of the buffering resource connected to the data stream controller. The data stream processing device comprises a processing interface for providing a data path to a processing module;
The processing module, wherein the response by the data processor core for execution of at least one instruction executable said instruction set, according to claim 30, characterized in that it is operable to perform processing tasks Data stream processing system. The data stream controller can be configured by the main processing unit with configuration information;
41. The data stream processing system according to claim 40 , wherein the configuration information supplied to the data stream processing device by the main processing device includes characteristics of at least one of the processing resources. The data stream controller can be configured by the main processing unit with configuration information;
Wherein the configuration information provided to the data stream processing unit by the main processing unit, the data stream controller and connected to the starting point of the buffering resources, and to claim 35, characterized in that it comprises an end point The described data stream processing system. The at least one data stream includes a plurality of data elements arranged in order in a first temporary sequence;
The at least one data element stream includes the plurality of data elements of the first temporary sequence arranged in order in a second temporary sequence different from the first temporary sequence; 31. A data stream processing system according to claim 30 , wherein: 32. The method of claim 31 , wherein the at least one instruction of the instruction set executable by the data engine core is either an instruction having a conditional response or an instruction having an unconditional response. Data stream processing system. The at least one instruction corresponds to a respective process to be performed by the data stream controller in response to the at least one instruction output by the data stream functional unit;
32. The data stream processing system of claim 31 , wherein each of the processes comprises an associated state machine maintained by the data stream controller. The instruction set executable by the data engine core is operable to cause the data stream controller to selectively buffer the data of the at least one data stream or the at least one data element stream. 36. The data stream processing system of claim 35 , comprising instructions. The instruction set executable by the data engine core causes the data stream controller to read at least one data item from the buffering resource and to the first interface or the second interface The data stream processing system of claim 30 , further comprising a data read command operable to cause the at least one data item to be output. Of the at least one data stream, or the at least one data element stream, the management information to be next supplied to the first interface or the second interface by the data stream controller 32. The data stream processing system of claim 30 , including at least a current output position indicating a data item in one. The instruction set executable by the data engine core is a data item at a previous point in a temporary sequence associated with one of the corresponding at least one data stream or at least one data element stream and the current 31. The data stream processing system of claim 30 , further comprising a back command operable to change the current output position so that the output position corresponds. The management information is a history indicating which data of the at least one data stream or the at least one data element stream is stored in the buffering resource, and the at least one data stream, or the at least one data 36. The data stream processing system of claim 35 , comprising at least one of a history indicating which data of an element stream was received by the data stream controller. The instruction set executable by the data engine core is operable to cause the data stream controller to insert data from the data engine into the at least one data stream or the at least one data element stream. The data stream processing system according to claim 30 , further comprising a data insertion instruction. Claim 30, characterized in that it comprises an operable direct memory access interface to provide a data communication path to the direct memory access controller for the supply of the at least one data stream for the data stream controller Data stream processing system. The data stream controller can be configured by the main processing unit with configuration information;
53. The data stream processing system of claim 52 , wherein the configuration information includes at least one characteristic of the direct memory access controller. The data stream processing device before the data stream controller outputs the stored data to the first interface or the second interface, the at least one data stream, or the at least one data element; The data stream processing system according to claim 30 , further comprising a data input register for temporarily storing data of the stream. The instruction set executable by the data engine core is related to the state of the data pointer at a moment when an instruction associated with a count setting instruction is transmitted from the data engine core to the data stream processing device. 31. The data stream processing system of claim 30 , including a count setting instruction operable to instruct the processing device to set an upper limit of a data pointer state. The data stream processing system according to claim 30 , wherein the data stream processing device is at least partially incorporated in the data engine. A data stream processing device for providing a data communication path between a main processing device and a data engine core,
The data stream processing device is
A control interface operable to receive at least one instruction from the data engine core;
Data between the first interface and the second interface having a first interface for at least one data stream and a second interface for at least one data element stream including a series of data elements A data stream controller operable to perform at least one operation for managing transfers,
The data stream processing device is responsive to the at least one instruction from the data engine core to control the data stream controller to perform the at least one operation ;
The data stream processing device is operable to store management information including at least one reference position in the at least one data stream or the at least one data element stream;
The data stream processing apparatus, wherein the data stream processing apparatus executes at least one command based on the at least one reference position . Assigning multiple data processing tasks to the main processing unit;
Using a data engine having a data engine core to perform some of the plurality of data processing tasks on behalf of the main processing unit;
Using a data stream processing device to provide a data communication path between the main processing device and the data engine core;
Receiving at least one instruction from the data engine core at the data stream processing device;
Processing to perform at least one operation for managing data transfer between a first interface for at least one data stream and a second interface for at least one data element stream of the data stream controller. ,
The data stream processing device is responsive to the at least one instruction from the data engine core to control the data stream controller to perform the at least one operation ;
The data stream processing device is operable to store management information including at least one data stream or at least one reference position in the at least one data element stream;
The data stream processing method, wherein the data stream processing device executes at least one command based on the at least one reference position .

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