JP4445395B2 - Booster circuit - Google Patents

Description

  The present invention relates to a semiconductor charge pump circuit that generates a voltage higher than an operating voltage or a negative voltage, and a semiconductor integrated circuit using the same.

と表すことができる。しかし、出力側に近づくにつれｎＭＯＳトランジスタのドレイン、ソース電圧が昇圧されソース基板間電圧Ｖｓｂの上昇により、基板効果によるＮＭＯＳトランジスタのしきい値電圧Ｖｔが式（２）で示されるように上昇する。

さらに式（２）からＶｔ＝Ｖｃｃとなる時のＶｓｂが昇圧電圧の最大電圧と言えるので、

式（３）により昇圧最大電圧Ｖｏｕｔ＿ｍａｘを算出できる。図４に電源電圧Ｖｃｃと昇圧電圧Ｖｏｕｔの算出値を示した。図４からわかるようにＤｉｃｓｏｎ型チャージポンプでは、電源電圧Ｖｃｃに依存して昇圧電圧Ｖｏｕｔ＿ｍａｘが決まっていることがわかる。
Ｄｉｃｓｏｎ型チャージポンプの改良版も検討されている。特開平１１−３０８８５６「チャージポンプ回路装置」では、ｎ型ＭＯＳを複数のグループに分離して基板電位を除々に高くすることにより基板効果によるｎ型ＭＯＳ Ｖｔの上昇を抑えている。
上記従来技術であるＤｉｃｓｏｎ型チャージポンプは、昇圧されるにつれｎ型ＭＯＳのソース基板間電圧Ｖｓｂが上昇することで、基板効果の影響によりｎ型ＭＯＳのしきい値電圧Ｖｔが上がり、昇圧電圧の最大値が決まってしまう。結果として、３Ｖ以下の低電源電圧においては、不揮発性メモリの消去、Ｗｒｉｔｅに必要な１２Ｖ程度の高電圧を生成することができない。
また、特開平１１−３０８８５６「チャージポンプ回路装置」にあるようなｎ型ＭＯＳを複数のグループに分離して基板電位を除々に高くすることにより基板効果の影響を抑えるようにしたとしても、複数のグループの中でＶｓｂ＝０Ｖとならないｎ型ＭＯＳがあり、全てのｎ型ＭＯＳの基板効果を無くすことはできない。
また、特開２００３−４５１９３「半導体チャージポンプ回路および不揮発性半導体記憶装置」では、前々段のチャージ電圧をｎ型ＭＯＳの基板電位とする方式で、各段毎に異なる電圧値がｎ型ＭＯＳの基板電位に設定されるが、Ｖｓｂは少なくとも１段分の電圧増幅値Ｖｇａ（＝Ｖｃｃ−Ｖｔ）となり、基板効果は発生することとなる。
本発明は、基板効果の影響を無くしたチャージポンプ回路を提供すると共に、効率がいい回路構成及びプラス又はマイナスの高圧電圧を発生することができるチャージポンプ回路を提供することを目的とする。At the time of erasing and writing of the nonvolatile memory of Flash and EEPROM, a high voltage of about 12 V is required because the tunnel effect or hot electrons and hot holes are used. A conventional charge pump type booster circuit for generating a high voltage is disclosed in the document IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 8, AUGUST 1997 “A Dynamic Analysis of the Dicson Charge Pump”, generally known as a Dicson charge pump with a diode-connected MOS transistor (hereinafter referred to as “transfer MOS”) that moves charge as analyzed. Since the circuit configuration is very simple, it is often used. FIG. 1 and FIG. 2 show a configuration diagram of a Dicson type charge pump. FIG. 1 is a conceptual block diagram described in the IEEE document, and FIG. 2 is an example in which the buffer of FIG. 1 is replaced with an n-type MOS. In FIG. 2, the drain and gate of the n-type MOS are short-circuited, and CLK is applied to the other side of the capacitor connected to the drain and source. CLK and CLKn have a complementary relationship as shown in FIG. When CLKn is “High” and CLK is “Low”, the drain potential of the first and third odd-numbered stages is higher than the source potential, so that the drain current flows through the odd-numbered n-type MOS and the odd capacity of C1 and C3. Charge is charged. On the other hand, when CLK is “High” and CLKn is “Low”, the drain potentials of the second and fourth even stages are higher than the source potential, the drain current flows through the n-type MOS of the even stages, and the odd capacitors C1, Even capacity C2, C4 charges move from C3.
When the threshold voltage of the n-type MOS transistor constituting this Dicson type charge pump is Vt, the output voltage Vout is

It can be expressed as. However, as the voltage approaches the output side, the drain and source voltages of the nMOS transistor are boosted and the source-substrate voltage Vsb rises, so that the threshold voltage Vt of the NMOS transistor due to the substrate effect rises as shown in equation (2).

Furthermore, since Vsb when Vt = Vcc is the maximum voltage of the boost voltage from Equation (2),

The boosted maximum voltage Vout_max can be calculated from the equation (3). FIG. 4 shows calculated values of the power supply voltage Vcc and the boosted voltage Vout. As can be seen from FIG. 4, in the Dicson type charge pump, the boost voltage Vout_max is determined depending on the power supply voltage Vcc.
An improved version of the Dicson charge pump is also being considered. In Japanese Patent Laid-Open No. 11-308856 “Charge Pump Circuit Device”, the n-type MOS is divided into a plurality of groups and the substrate potential is gradually increased to suppress the rise of the n-type MOS Vt due to the substrate effect.
In the conventional Dicson type charge pump, the source-substrate voltage Vsb of the n-type MOS increases as the voltage is boosted, so that the threshold voltage Vt of the n-type MOS increases due to the effect of the substrate, and the boost voltage The maximum value is determined. As a result, at a low power supply voltage of 3 V or less, a high voltage of about 12 V necessary for erasing and writing of the nonvolatile memory cannot be generated.
Even if an n-type MOS as in JP-A-11-308856 “Charge Pump Circuit Device” is divided into a plurality of groups to gradually increase the substrate potential, the influence of the substrate effect is suppressed. In this group, there is an n-type MOS that does not satisfy Vsb = 0V, and the substrate effect of all n-type MOSs cannot be eliminated.
Japanese Patent Laid-Open No. 2003-45193 “Semiconductor Charge Pump Circuit and Nonvolatile Semiconductor Memory Device” uses a method in which the charge voltage of the previous stage is set to the substrate potential of the n-type MOS, and the voltage value that differs for each stage is n-type MOS However, Vsb becomes a voltage amplification value Vga (= Vcc−Vt) for at least one stage, and the substrate effect occurs.
It is an object of the present invention to provide a charge pump circuit that eliminates the influence of the substrate effect, and to provide a charge pump circuit that can generate an efficient circuit configuration and a positive or negative high voltage.

In order to solve the above problem, by adding a MOS for controlling the substrate of the n-type MOS that transfers charges, the substrate potential is always set to the lower potential of the drain or source potential in the case of the n-type MOS. Thus, Vsb = 0V and the effect of the substrate effect is eliminated.
When Vsb = 0V, the second term of Equation (2) can be set to 0, but Vt0 of the first term remains. In order to set Vt0 of this n-type MOS to 0V, a voltage equal to or higher than (power supply voltage + Vt0) is applied to the gate of the n-type MOS through the capacitor Cg. The charge transfer efficiency is improved by controlling the type MOS gate potential.

FIG. 1 is a configuration diagram of a conventional Dicson type charge pump.
2 is a circuit diagram of a conventional Dicson type charge pump.
FIG. 3 is a diagram showing a clock waveform.
FIG. 4 is a graph showing calculated Dicson charge pump boost voltage.
FIG. 5 is an overall circuit diagram of a charge pump circuit according to a first embodiment of the present invention.
FIG. 6 is a partial circuit diagram of the charge pump circuit according to the first embodiment of the present invention.
7 is a circuit explanatory diagram of the charge pump circuit according to the first embodiment of the present invention in the CLK X1 period. FIG. 8 is a circuit explanatory diagram of the charge pump circuit of the first embodiment of the present invention during the CLK X2 period. FIG. 10 is a timing diagram of a charge pump circuit according to the first embodiment of the present invention. FIG. 10 is a circuit diagram of a charge pump circuit simulation according to the first embodiment of the present invention.
FIG. 11 is a graph showing a charge pump circuit simulation result of the present invention.
FIG. 12 is a double voltage CLK generation circuit. FIG. 13 is a minus high voltage generation charge pump circuit diagram according to a second embodiment of the present invention.
14 is a circuit explanatory diagram of the charge pump circuit according to the second embodiment of the present invention in the CLK X1 period. FIG. 15 is a circuit explanatory diagram of the charge pump circuit of the second embodiment of the present invention during the CLK X2 period. The plus high voltage generation charge pump circuit diagram showing the 3rd example of.
FIG. 17 is a minus high voltage generation charge pump circuit diagram showing a fourth embodiment of the present invention.
FIG. 18 is a plus / minus high voltage generation charge pump circuit diagram showing a fifth embodiment of the present invention.
FIG. 19 is a configuration diagram of a high voltage generation charge pump circuit representing a sixth embodiment of the present invention.
FIG. 20 shows a series charge pump circuit according to a seventh embodiment of the present invention.
FIG. 21 is a hardware configuration of an IC card equipped with the charge pump circuit of the present invention.

ここで、電圧増幅度Ｖｇａは、最大Ｖｃｃとなる。Ｖｏｕｔに負荷電流ＩＬが流れた場合は、

（５）式で表されたΔＶの電圧降下が起きるので、

Ｖｇａは（６）式のようになる。
ここで、負荷電流ＩＬが流れた場合の電位を図７、図８の各接続点で示すと、図７の各接続点は、ｎ１＝ｎ２＝ｎ５＝ｎ６＝〜（Ｖｃｃ−ΔＶ）、ｎ３＝２Ｖｃｃ、ｎ４＝３Ｖｃｃ−２ΔＶとなり、図８の各接続点は、ｎ１＝２Ｖｃｃ−ΔＶ、ｎ２＝ｎ３＝Ｖｃｃ、ｎ４＝ｎ５＝２Ｖｃｃ−２ΔＶ、ｎ６＝３Ｖｃｃ−ΔＶとなり、各段のチャージ容量とＴＭＯＳとの接続点ｎ１、ｎ４で（段数×ΔＶ）の電圧低下がある。
図１０に、本発明の基板制御型チャージポンプ回路のシミュレーション回路とＳｐｉｃｅシミュレーション結果を図１１に示した。チャージポンプ段数１３段、チャージポンプ容量７０Ｆ／段の回路構成において、負荷抵抗（ＲＬＯＡＤ）＝１００ＭΩ、負荷容量（ＣＬＯＡＤ）＝１００ｐＦの条件で、電源電圧Ｖｃｃ＝１．５Ｖで約１８．５Ｖ，電源電圧Ｖｃｃ＝１．３Ｖで約１５．５Ｖとなり、低電源電圧においても不揮発性メモリの消去、Ｗｒｉｔｅに必要な１２Ｖ程度以上の高電圧を生成することができる。このＳｐｉｃｅシミュレーション時の、トランスファーＮＭＯＳのＶｔ０は、約０．９Ｖであり、基板効果係数γは約０．８である。
ここで、図１０の回路図にも示してある２倍圧ＣＬＫ発生回路の動作を図１２で説明する。２倍圧ＣＬＫ発生回路は、図５〜図８で示したＣＬＫ、ＣＬＫｎから２ＶＣＬＫ、２ＶＣＬＫｎを発生する回路である。この２倍圧ＣＬＫ発生回路においてもチャージポンプ方式を使用し、トランスファーＭＯＳとしてｐＭＯＳを使用した。ＣＬＫ＝Ｖｃｃの時、トランスファーｐＭＯＳゲートは０Ｖになり容量Ｃに電荷がチャージされｎ２電位はＶｃｃになると同時に出力は０Ｖになる。次にＣＬＫ＝０Ｖになると、ｎ２電位が２×Ｖｃｃになり、トランスファーｐＭＯＳゲートはｎ２電位に設定されトランスファーｐＭＯＳはＯＦＦになる。また出力はｎ２電位が出力され２×Ｖｃｃとなる。このように２倍圧ＣＬＫ発生回路は、入力ＣＬＫに同期して０Ｖから２Ｖｃｃの電圧を発生している。
図５〜１２は、プラスの高電圧を発生させるチャージポンプであったが、本願発明の第２の実施例であるマイナスの高電圧を発生させる回路を図１３に示した。
回路構成としては、図５とほぼ同一であるが、ＣＬＫの位相及びゲート電圧設定ＭＯＳの位置が違う。図５のプラス昇圧の場合は、ゲート電圧設定ＭＯＳのドレインとソースは、ＴＭＯＳとチャージ容量Ｃとの接続点の逆側とＴＭＯＳゲートに接続されていたが、図１３のマイナス昇圧の場合は、ＴＭＯＳとチャージ容量Ｃの接続点とＴＭＯＳゲートに接続した。また、図５のプラス昇圧は、ＣＬＫと２ＶＣＬＫｎ、ＣＬＫｎと２ＶＣＬＫがペアになって各ポンプセルを制御していたが、図１３のマイナス昇圧は、ＣＬＫと２ＶＣＬＫ、ＣＬＫｎと２ＶＣＬＫｎがペアになって各ポンプセルを制御した。これにより、プラス昇圧の場合は、電荷を次段のチャージ容量に電荷を流すことによりプラス高電圧を得ていたが、マイナスの場合は、電荷の流れる向きがプラスと逆方向にすることにより、前段へ電荷を流しマイナスの高電圧を得るようにしたものである。
また、Ｎ段目のＴＭＯＳゲート電圧設定ＭＯＳのゲートは、（Ｎ−１）段目のＴＭＯＳゲートと接続しているが、１段目のＴＭＯＳゲート電圧設定ＭＯＳのゲートは、ＣＬＫｎと接続し制御した。各段のＴＭＯＳゲート電圧設定ＭＯＳの基板は、各段のトランスファーＭＯＳの基板電位と接続した。
図１４、図１５を使用して動作を説明する。図１４のＣＬＫ Ｘ１期間においては、ＣＬＫ＝０Ｖ、２ＶＣＬＫ＝０Ｖとなり、１段目のトランスファーＭＯＳのゲートｎ３電位は、ゲート電圧設定ＭＯＳのゲートがＣＬＫｎ＝Ｖｃｃに接続されているので、ゲート電圧設定ＭＯＳはＯＮし、ｎ３電位とｎ１電位が接続される。動作中においてはｎ１電位は、−Ｖｃｃ〜０Ｖになるので、Ｔ１はＯＦＦする。また、Ｔ１の基板電位ｎ２は、ｔ２がＯＦＦ、ｔ１がＯＮとなり、ｎ２電位とｎ１電位は接続される。
２段目は、ＣＬＫｎ＝Ｖｃｃ、２ＶＣＬＫｎ＝２Ｖｃｃとなり、Ｔ２のゲートｎ６電位は、２ＶＣＬＫにより約−２Ｖｃｃから０Ｖ程度になる。また、ｔ６のゲート電位であるｎ３は、約−Ｖｃｃでｔ６はＯＦＦするので、Ｔ２はＯＮし、ｎ４電位は、ｎ１電位と同じ−Ｖｃｃまでになる。また、ｎ５電位は、ＣＬＫがＶｃｃになった直後においてｎ４電位は、ｎ１電位より約Ｖｃｃ高いので、ｔ５がＯＮし、ｎ５電位はｎ１電位と同じになる。
図１５のＸ２期間では、ＣＬＫ＝Ｖｃｃ、２ＶＣＬＫ＝２Ｖｃｃとなり、ｎ３電位は２ＶＣＬＫにより−ＶｃｃからＶｃｃとなる。また、ｔ３はＣＬＫｎ＝０ＶによりＯＦＦするので、Ｔ１はＯＮし、ｎ１電位は０Ｖになる。また、ｎ２電位は、ＣＬＫがＶｃｃになった直後においてｎ１電位は、ｎ１電位より約Ｖｃｃ高いので、ｔ２がＯＮし、ｎ２電位は０Ｖとなる。
２段目は、ＣＬＫｎ＝０Ｖ、２ＶＣＬＫｎ＝０Ｖとなり、Ｔ２のゲートｎ６電位は、２ＶＣＬＫにより約０Ｖから−２Ｖｃｃ程度になる。また、ｎ４電位は、ＣＬＫｎにより−Ｖｃｃから−２Ｖｃｃとなり、ｔ６のゲート電位ｎ３＝Ｖｃｃなので、ｔ６はＯＮしｎ６電位とｎ４電位が接続され、Ｔ２はＯＦＦする。また、ｎ５電位はｔ４がＯＮすることにより、ｎ４電位と同じ−２Ｖｃｃとなる。
ここで、マイナス電圧昇圧の場合、１段当りの電圧増幅度をＶｇａとすると、このチャージポンプから出力される電圧Ｖｏｕｔは、（７）式で表すことができる。

電圧増幅度Ｖｇａは、最大Ｖｃｃとなる。
図５〜１５は、トランスファーＭＯＳ、基板制御ＭＯＳ及びゲート電圧設定ＭＯＳをｎＭＯＳで構成したチャージポンプ回路であったが、ｐＭＯＳで構成した本発明のチャージポンプ回路の第３の実施例を図１６に、第４の実施例を図１７に示した。
図１６は、プラスの昇圧チャージポンプ回路であり、ＴＭＯＳ、基板制御ＭＯＳ及びゲート電圧設定ＭＯＳにｐＭＯＳを使用した。また、ＣＬＫと２ＶＣＬＫ、ＣＬＫｎと２ＶＣＬＫｎの同相のクロックがペアになって各ポンプセルを制御することで、前段ポンプセルから当該ポンプセルへと電荷が転送され、後段へいくほどプラス昇圧される。また、ｎＭＯＳの時と違って、トランスファーＭＯＳの基板は、基板制御ＭＯＳにより、トランスファーのドレイン又はソース電位の高い方に設定されることになる。
図１７は、マイナスの昇圧チャージポンプ回路である。図１６のプラス昇圧の場合と違って、ゲート電圧設定ＭＯＳの位置がチャージ容量と反対側に位置しているのと、ＣＬＫと２ＶＣＬＫｎ、ＣＬＫｎと２ＶＣＬＫの逆相のクロックがペアになって各ポンプセルを制御している。これにより、当該ポンプセルから前段ポンプセルに電荷が転送され、後段へいくほどマイナス昇圧される。また、図１６のプラス昇圧と同じく、トランスファーＭＯＳの基板は、基板制御ＭＯＳにより、トランスファーのドレイン又はソース電位の高い方に設定されることになる。図１６、図１７からもわかるように回路構成はｎＭＯＳの場合と、同じである。図１６のｐＭＯＳを使用したプラス昇圧回路は、図１４、図１５のｎＭＯＳを使用したマイナス昇圧回路と回路構成は同じであり、図１７のｐＭＯＳを使用したマイナス昇圧回路は、図５〜図８のｎＭＯＳを使用したプラス昇圧回路と回路構成は同じであり、ｐＭＯＳ、ｎＭＯＳどちらを使用しても同じ回路構成で、プラス及びマイナスの昇圧電圧を得ることができる。
不揮発性メモリの制御において、例えば消去時にはマイナス高電圧、Ｗｒｉｔｅ時にはプラス高電圧が必要となることがある。この場合、別個にプラス及びマイナスのチャージポンプ回路を作るのはチップ面積が増大し、チップ価格が高くなってしまう。そこで、消去及びＷｒｉｔｅは、同時に発生しないことから１個のチャージポンプ回路で、プラス又はマイナスの高電圧を発生させる本発明の第５の実施例であるチャージポンプ回路を図１８に提案した。基本回路としては、図５と同じであり、基本動作も図７、８で説明したものと同じであるが、プラス高電圧発生時とマイナス高電圧発生時とで、入出力を逆にすることが選択回路及び選択信号により可能となっていることが特徴である。プラス高電圧発生時は、図５〜図８で説明した内容と同じであり、入力が図１８左側でＶｄｄとし、出力は図１８右側になる。マイナス高電圧発生時は、図１８右側が入力０Ｖとし、図１８左側が出力となる。プラス及びマイナス高電圧発生共に、電荷の移動は図１８の左から右となるので、マイナスの場合は、電荷は０Ｖに流れ込み、前段は除々にマイナスになっていき、マイナス高電圧が発生できる。
次に不揮発性メモリの制御においては、例えば１２Ｖ，６Ｖ等の２種類の高電圧が同時に必要となってくることがある。図５で示したチャージポンプ回路から出力される第１の高電圧と、この第１の高電圧を使用して第２の高電圧を発生させる回路構成である本発明の第６の実施例を図１９に示す。図１９内の基板制御型並列チャージポンプは、図５と同一である。本発明の第７の実施例である図１９の直列型チャージポンプを図２０に示した。直列型チャージポンプは、トランスファーｐＭＯＳを使用し、チャージ容量を第１の高電圧の電圧でＯＮ、ＯＦＦすることにより、第１の高電圧の２倍の電位が得られること及び直列型チャージポンプのＣＬＫ信号で、内部直列ブロック１と内部直列ブロック２を交互にＯＮ、ＯＦＦさせていることを特徴としている。
図２１に、本発明の昇圧回路を搭載したＩＣカードのハードウェア構成を示す。ＩＣカードハードウェア内のフラッシュメモリ及びＥＥＰＲＯＭで本発明の昇圧回路が搭載される。
また、フラッシュメモリ及びＥＥＰＲＯＭは、データの書き込み、消去時にプラス又はマイナス高電圧が必要となり、本発明の昇圧回路が使用されることとなるが、読み出し時に本発明の昇圧回路を使用して、書き込み及び消去されたメモリが期待したしきい値に達しているかを確認するために使用することもできる。
以下、上記実施例で説明したチャージポンプ回路は、電源電圧以外のプラス又はマイナス高電圧を必要とするＥＥＰＲＯＭ、フラッシュメモリー代表される不揮発性メモリ等を含むＬＳＩ回路、ＩＣカードチップ、ＩＣカード等に適用可能である。Embodiments of the present invention will be described below with reference to the drawings. Although not limited to the circuit element of the present invention, it is realized by a well-known Si semiconductor integrated circuit. In the drawings of the present application, the back gate having an inward arrow represents an n-type MOSFET. A back gate having an outer arrow and a circle on the gate represents a p-type MOSFET.
In the present specification, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is omitted and referred to as a MOS. The present invention is generally applicable to MISFETs.
FIG. 5 shows an entire circuit for generating a plus high voltage, which is a form of the first embodiment of the charge pump circuit invented this time, and FIG. 6 shows a part extracted from the charge pump stage. The charge pump circuit of the present application is formed by connecting a plurality of basic pump cells including four n-type MOSs and two capacitors in series. The basic pump cell includes a transfer MOS (TMOS) that transfers charges to the next stage, a substrate control MOS that serves as a connection circuit that connects a TMOS substrate (also referred to as a well) to the drain or source of the transfer MOS, and a transfer MOS A gate voltage setting MOS that functions as a connection circuit for connecting the gate potential to the drain, a charge capacitor (C) that charges the charge transferred from the TMOS, and a transfer gate capacitor (Cg) that transmits the potential of 2VCLK or 2VCLKn to the gate of the TMOS. ). The gate of the TMOS is connected to the gate of the gate voltage setting MOS of the next stage. However, the gate of the first stage gate voltage setting MOS is connected to the connection point between the TMOS and the charge capacitor. These transfer MOS, substrate control MOS and gate voltage setting MOS are all nMOS.
The two-phase clock signals CLK and CLKn have the operating voltage Vcc as the amplitude. When the clock signal CLK is at the operating voltage Vcc, the output timing of the clock signals CLK and CLKn is 0V, and when the clock signal CLK is 0V, the CLKn is the operating voltage Vcc, and are in opposite phase relation to each other. It is a clock signal.
The two-phase clock signals 2VCLK and 2VCLKn have an amplitude of 2Vcc, which is twice the operating voltage. Similar to CLK and CLKn, 2VCLK and 2VCLKn are clock signals having opposite phases to each other.
The operation will be described below with reference to FIGS.
In the CLK X1 period of FIG. 7, CLK = 0V and 2VCLKn = 2Vcc, so that the gate n3 potential which is a transfer MOS becomes 2Vcc or more, T1 is turned on, electric charge is supplied from Vcc to the charge capacitor C1, and finally n1 The potential becomes Vcc. . Accordingly, since the n1 potential is equal to or lower than Vcc while the charge capacitor C1 is charged, the nMOS gate is connected to the n1 potential, and t2 and t3 where the source or drain is equal to or higher than Vcc are turned OFF. In addition, the nMOS gate is connected to Vcc, t1 when the n1 potential which is the drain or source potential is Vcc or less is turned ON, the substrate potential n2 of the transfer MOS T1 becomes the n1 potential, and the drain or source of the TMOS is low. It will be connected to the potential. Here, Vt0 of the transfer nMOS is normally less than Vcc, and when the gate potential n3 of the transfer nMOS becomes 2 Vcc or more, the n1 potential rises to Vcc without loss of Vt0.
In the second stage, CLKn = Vcc and 2VCLK = 0V. Therefore, if the charge charged in the charge capacitor C2 is Q2, the potential n4 becomes (Q2 / C2) + Vcc. Here, if all the charge charges of C1 from the first stage are transferred, it can be said that Vcc + (Q1 / C1) = (Q2 / C2) = 2Vcc, so the n4 potential is 3Vcc, and n4 potential> n1 potential. Therefore, t5 where the nMOS gate is connected to the n4 potential is turned ON, and t4 where the nMOS gate is connected to the n1 potential is turned OFF. When t5 is turned on, the substrate potential n5 of the transfer nMOS T2 becomes n1 potential. Further, t6 where the nMOS gate is connected to the n3 potential is turned ON, and the n6 potential, which is the T2 gate potential, becomes the n5 potential and T2 is turned OFF.
In the odd (2N-1) th stage after the third stage (N is 1 or more), the TMOS is turned on as in the first stage, and the connection point between the charge capacitor C (2N-1) and the TMOS is Vcc × ( 2N-1). In the even 2N stage, the TMOS is turned off, and the connection point between the charge capacitor C (2N) and the TMOS is Vcc + Vcc × 2N.
In the CLK X2 period of FIG. 8, CLK = Vcc and 2VCLKn = 0V, so that the potential n1 becomes the potential Vcc + Vcc = 2Vcc that is charged and increased in the charge capacitor C1 in the X1 period. As a result, t2 and t3 when the nMOS gate is connected to the n1 potential are turned on, the gate potential n3 and the substrate potential n2 of the transfer nMOS are Vcc, and T1 is turned off.
In the second stage, CLKn = 0V, 2VCLK = 2Vcc and the n4 potential becomes 2Vcc or less, so that n1 potential ≧ n4 potential, t4 when the n1 potential is connected to the nMOS gate is turned ON, and the n4 potential is connected to the nMOS gate. T5 is turned OFF. As a result, the substrate potential n5 of the transfer MOS T2 becomes the n4 potential. Further, t6 when the n3 potential which is Vcc is connected to the nMOS gate is turned OFF, and the n6 potential is set to Vcc in the X1 period, 2VCLK = 2Vcc is added to 3Vcc, and T2 is turned ON. As a result, charges move from the charge capacitors C1 to C2, and the n4 potential finally becomes 2Vcc.
In the odd (2N-1) th stage after the third stage (N is 1 or more), the TMOS is turned off as in the first stage, and the connection point between the charge capacitor C (2N-1) and the TMOS is Vcc + Vcc × ( 2N-1). In the even 2N stage, the TMOS is turned on, and the connection point between the charge capacitor C (2N) and the TMOS is Vcc × 2N.
FIG. 9 shows a voltage state in the circuit in the CLK X1 and X2 periods. Here, the gate of the Nth stage TMOS gate voltage setting MOS is connected to the (N−1) th stage TMOS gate, but the charge pump capacitor C1 is connected to the gate of the first stage TMOS gate voltage setting MOS. Control was performed by connecting to the connected n1 potential.
In this charge pump, in the case of positive voltage boosting, assuming that the voltage amplification per stage is Vga, the voltage Vout output from this charge pump can be expressed by equation (4).

Here, the voltage amplification degree Vga is the maximum Vcc. When the load current IL flows through Vout,

Since the voltage drop of ΔV expressed by the equation (5) occurs,

Vga is expressed by equation (6).
Here, when the potential when the load current IL flows is shown by the connection points in FIGS. 7 and 8, the connection points in FIG. 7 are n1 = n2 = n5 = n6 = ˜ (Vcc−ΔV), n3. = 2Vcc, n4 = 3Vcc-2ΔV, and the connection points in FIG. 8 are n1 = 2Vcc−ΔV, n2 = n3 = Vcc, n4 = n5 = 2Vcc-2ΔV, n6 = 3Vcc−ΔV, and the charge capacity of each stage There is a voltage drop of (number of stages × ΔV) at connection points n1 and n4 between TMOS and TMOS.
FIG. 10 shows a simulation circuit and a Spice simulation result of the substrate control type charge pump circuit according to the present invention. In a circuit configuration with 13 charge pump stages and a charge pump capacity of 70 F / stage, power supply voltage Vcc = 1.5V and about 18.5 V under the conditions of load resistance (RLOAD) = 100 MΩ and load capacity (CLOAD) = 100 pF The voltage Vcc = 1.3V is about 15.5V, and even at a low power supply voltage, a high voltage of about 12V or more necessary for erasing and writing of the nonvolatile memory can be generated. In this Spice simulation, Vt0 of the transfer NMOS is about 0.9 V, and the substrate effect coefficient γ is about 0.8.
Here, the operation of the double voltage CLK generating circuit also shown in the circuit diagram of FIG. 10 will be described with reference to FIG. The double voltage CLK generating circuit is a circuit for generating 2VCLK and 2VCLKn from CLK and CLKn shown in FIGS. This double voltage CLK generating circuit also uses a charge pump system and uses a pMOS as a transfer MOS. When CLK = Vcc, the transfer pMOS gate becomes 0V, the capacitor C is charged, the n2 potential becomes Vcc, and the output becomes 0V at the same time. Next, when CLK = 0V, the n2 potential becomes 2 × Vcc, the transfer pMOS gate is set to the n2 potential, and the transfer pMOS is turned off. Further, the output is n2 potential and becomes 2 × Vcc. As described above, the double voltage CLK generation circuit generates a voltage of 0 V to 2 Vcc in synchronization with the input CLK.
5 to 12 are charge pumps for generating a positive high voltage. FIG. 13 shows a circuit for generating a negative high voltage according to the second embodiment of the present invention.
The circuit configuration is almost the same as in FIG. 5, but the phase of CLK and the position of the gate voltage setting MOS are different. In the case of the plus boost of FIG. 5, the drain and the source of the gate voltage setting MOS are connected to the opposite side of the connection point between the TMOS and the charge capacitor C and the TMOS gate, but in the case of the minus boost of FIG. The connection point between the TMOS and the charge capacitor C and the TMOS gate were connected. In addition, the positive boost of FIG. 5 controls each pump cell with a pair of CLK and 2VCLKn and CLKn and 2VCLK. However, the negative boost of FIG. 13 has a pair of CLK and 2VCLK and CLKn and 2VCLKn. The pump cell was controlled. As a result, in the case of plus boosting, a positive high voltage was obtained by flowing the charge to the charge capacitor of the next stage, but in the case of minus, the charge flow direction was reversed to the plus direction. Charge is passed to the previous stage to obtain a negative high voltage.
The gate of the Nth stage TMOS gate voltage setting MOS is connected to the (N-1) th stage TMOS gate, while the gate of the first stage TMOS gate voltage setting MOS is connected to CLKn and controlled. did. The substrate of the TMOS gate voltage setting MOS at each stage was connected to the substrate potential of the transfer MOS at each stage.
The operation will be described with reference to FIGS. In the CLK X1 period of FIG. 14, CLK = 0V, 2VCLK = 0V, and the gate n3 potential of the first-stage transfer MOS is set to the gate voltage setting because the gate of the gate voltage setting MOS is connected to CLKn = Vcc. The MOS is turned on, and the n3 potential and the n1 potential are connected. During operation, the n1 potential is -Vcc to 0 V, so T1 is turned OFF. The substrate potential n2 of T1 is t2 OFF and t1 ON, and the n2 potential and the n1 potential are connected.
In the second stage, CLKn = Vcc, 2VCLKn = 2Vcc, and the gate n6 potential of T2 is changed from about −2 Vcc to about 0 V by 2 VCLK. Further, since n3 which is the gate potential of t6 is about −Vcc and t6 is turned off, T2 is turned on and the n4 potential becomes −Vcc which is the same as the n1 potential. Further, immediately after the CLK becomes Vcc, the n4 potential is about Vcc higher than the n1 potential, so that the t5 is turned on and the n5 potential becomes the same as the n1 potential.
In the period X2 in FIG. 15, CLK = Vcc and 2VCLK = 2Vcc, and the n3 potential is changed from −Vcc to Vcc by 2VCLK. Further, since t3 is turned off by CLKn = 0V, T1 is turned on and the n1 potential becomes 0V. Further, the n2 potential immediately after CLK becomes Vcc, the n1 potential is approximately Vcc higher than the n1 potential, so that t2 is turned ON and the n2 potential becomes 0V.
In the second stage, CLKn = 0V, 2VCLKn = 0V, and the gate n6 potential of T2 is changed from about 0V to about −2Vcc by 2VCLK. The n4 potential is changed from −Vcc to −2 Vcc by CLKn, and the gate potential n3 = Vcc at t6. Therefore, t6 is turned on, the n6 potential and the n4 potential are connected, and T2 is turned off. The n5 potential becomes −2 Vcc, which is the same as the n4 potential, when t4 is turned ON.
Here, in the case of a negative voltage boost, assuming that the voltage amplification degree per stage is Vga, the voltage Vout output from this charge pump can be expressed by equation (7).

The voltage amplification degree Vga is the maximum Vcc.
FIGS. 5 to 15 show the charge pump circuit in which the transfer MOS, the substrate control MOS and the gate voltage setting MOS are composed of nMOS. FIG. 16 shows a third embodiment of the charge pump circuit of the present invention composed of pMOS. A fourth embodiment is shown in FIG.
FIG. 16 shows a positive boost charge pump circuit, in which a pMOS is used as a TMOS, a substrate control MOS, and a gate voltage setting MOS. Further, by controlling each pump cell with a pair of clocks having the same phase of CLK and 2VCLK and CLKn and 2VCLKn as a pair, charges are transferred from the preceding pump cell to the pump cell, and the voltage is boosted further toward the subsequent stage. Unlike the nMOS, the transfer MOS substrate is set to the higher transfer drain or source potential by the substrate control MOS.
FIG. 17 shows a negative boost charge pump circuit. Unlike the case of plus boosting in FIG. 16, the gate voltage setting MOS is positioned on the opposite side of the charge capacitor, and the clocks of opposite phases of CLK and 2VCLKn and CLKn and 2VCLK are paired to each pump cell. Is controlling. As a result, charges are transferred from the pump cell to the preceding pump cell, and the voltage is stepped down to the subsequent stage. Similarly to the plus boosting of FIG. 16, the substrate of the transfer MOS is set to the higher one of the transfer drain or source potential by the substrate control MOS. As can be seen from FIGS. 16 and 17, the circuit configuration is the same as that of the nMOS. The plus booster circuit using the pMOS in FIG. 16 has the same circuit configuration as the minus booster circuit using the nMOS in FIGS. 14 and 15, and the minus booster circuit using the pMOS in FIG. The circuit configuration is the same as that of the plus booster circuit using nMOS, and it is possible to obtain positive and negative boosted voltages with the same circuit configuration regardless of whether pMOS or nMOS is used.
In the control of the nonvolatile memory, for example, a minus high voltage may be required for erasing and a plus high voltage may be required for writing. In this case, separately making positive and negative charge pump circuits increases the chip area and increases the chip price. Therefore, since erase and write do not occur at the same time, a charge pump circuit according to a fifth embodiment of the present invention that generates a positive or negative high voltage with one charge pump circuit is proposed in FIG. The basic circuit is the same as in FIG. 5 and the basic operation is the same as that described in FIGS. 7 and 8, but the input and output are reversed when a plus high voltage is generated and when a minus high voltage is generated. Is characterized by the selection circuit and the selection signal. When a positive high voltage is generated, the contents are the same as those described with reference to FIGS. 5 to 8, and the input is Vdd on the left side of FIG. 18 and the output is on the right side of FIG. When a negative high voltage is generated, the input on the right side of FIG. 18 is 0 V, and the output on the left side of FIG. 18 is output. In both the positive and negative high voltage generations, the movement of the charge is from left to right in FIG. 18. In the negative case, the charge flows into 0V, and the preceding stage gradually becomes negative, and a negative high voltage can be generated.
Next, in the control of the nonvolatile memory, for example, two types of high voltages such as 12V and 6V may be required at the same time. A sixth embodiment of the present invention having a circuit configuration for generating a first high voltage output from the charge pump circuit shown in FIG. 5 and a second high voltage using the first high voltage. It shows in FIG. The substrate control type parallel charge pump in FIG. 19 is the same as FIG. FIG. 20 shows the series charge pump of FIG. 19 which is the seventh embodiment of the present invention. The series type charge pump uses a transfer pMOS, and by turning on and off the charge capacitor with the first high voltage, a potential twice as high as the first high voltage can be obtained. The internal serial block 1 and the internal serial block 2 are alternately turned on and off by the CLK signal.
FIG. 21 shows the hardware configuration of an IC card equipped with the booster circuit of the present invention. The booster circuit of the present invention is mounted on the flash memory and EEPROM in the IC card hardware.
In addition, the flash memory and the EEPROM require a positive or negative high voltage at the time of data writing and erasing, and the booster circuit of the present invention is used. And can be used to verify that the erased memory has reached the expected threshold.
Hereinafter, the charge pump circuit described in the above embodiment is applied to an LSI circuit, an IC card chip, an IC card, etc. including an EEPROM, a non-volatile memory typified by a flash memory, etc. that require a plus or minus high voltage other than the power supply voltage. Applicable.

  The present invention is used in a nonvolatile memory or an IC chip that requires a high voltage higher than a power supply voltage.

Claims (19)

A booster circuit for boosting by connecting N stages of basic pump cells,
The basic pump cell includes at least a first MISFET, a second MISFET, a third MISFET, a first capacitor, a fourth MISFET, and a second capacitor ,
A back gate of said first 1MISFET is connected to the first node, its Sosudore Lee down path is connected between the second node and a third node,
A back gate of said first 2MISFET is connected to said first node, its Sosudore Lee down path is connected between the first node and the second node,
A back gate of said first 3MISFET is connected to said first node, its Sosudore Lee down path is connected between said first node and said third node,
One end of the first capacitor is connected to the third node, and the other end receives a first clock having an amplitude of an operating voltage,
The third node is connected to the second node of the basic pump cell in the next stage;
One end of the second capacitor is connected to the gate of the first MISFET, and the other end has a voltage amplitude larger than the sum of the operating voltage and the threshold voltage of the first MISFET, and has a phase opposite to that of the first clock. A second clock is input,
The back gate of the fourth MISFET is connected to the first node, the source / drain path is connected between the second node and the gate of the first MISFET, and the gate forms the basic pump cell in the previous stage. A booster circuit connected to the one end of two capacitors . A booster circuit for boosting by connecting N stages of basic pump cells,
The basic pump cell includes at least a first MISFET, a second MISFET, a third MISFET, a first capacitor, a fourth MISFET, and a second capacitor,
The back gate of the first MISFET is connected to the first node, and the source / drain path is connected between the second node and the third node,
The back gate of the second MISFET is connected to the first node, and the source / drain path is connected between the first node and the second node,
A back gate of the third MISFET is connected to the first node, and a source / drain path is connected between the first node and the third node;
One end of the first capacitor is connected to the third node, and the other end receives a first clock having an amplitude of an operating voltage,
The third node is connected to the second node of the basic pump cell in the next stage;
One end of the second capacitor is connected to the gate of the first MISFET, the other end has a voltage amplitude larger than the sum of the operating voltage and the threshold voltage of the first MISFET, and is in phase with the first clock. The second clock is input,
The source / drain path of the fourth MISFET is connected between the third node and the gate of the first MISFET, and the gate is connected to the one end of the second capacitor constituting the basic pump cell in the previous stage. A booster circuit. The booster circuit according to claim 1, wherein
The first, second, third, and fourth MISFETs are n-type MISFETs,
A booster circuit which boosts a voltage to the positive side. The booster circuit according to claim 1, wherein
The first, second, third, and fourth MISFETs are p-type MISFETs,
A booster circuit that boosts a voltage to the negative side. The booster circuit according to claim 2, wherein
The first, second, third, and fourth MISFETs are n-type MISFETs,
A booster circuit that boosts a voltage to the negative side. The booster circuit according to claim 2, wherein
The first, second, third, and fourth MISFETs are p-type MISFETs,
A booster circuit which boosts a voltage to the positive side. The booster circuit according to claim 1 or 2,
A double voltage generation circuit for generating a clock having a voltage twice as high as the operating voltage;
The booster circuit, wherein the double voltage clock generation circuit generates the second clock. The booster circuit according to claim 1 or 2,
The first clock input to the odd-numbered stages of the basic pump cell and the first clock input to the even-numbered stages are in reverse phase,
2. The booster circuit according to claim 1, wherein the second clock input to the odd-numbered stages of the basic pump cells and the second clock input to the even-numbered stages are in opposite phases. A booster circuit for boosting by connecting N stages of basic pump cells,
The basic pump cell is
n-type transfer MISFET,
A first connection circuit for connecting the lower one of the drain or source of the transfer MISFET and the back gate of the transfer MISFET;
A circuit for applying a voltage having a voltage amplitude larger than the sum of the operating voltage and the threshold voltage of the transfer MISFET to the gate of the transfer MISFET via a capacitor;
A booster circuit comprising: a second connection circuit for connecting a gate of the transfer MISFET and a drain or a source when the transfer MISFET is in an OFF state. The booster circuit according to claim 9, wherein
The first connection circuit includes a first substrate control MISFET and a second substrate control MISFET,
One of said 1st, 2nd board | substrate control MISFET conduct | electrically_connects, and the lower one of the drain or the source | sauce of the said transfer MISFET and the back gate of the said transfer MISFET are connected. A booster circuit for boosting by connecting N stages of basic pump cells,
The basic pump cell is
p-type transfer MISFET,
A first connection circuit that connects the higher one of the drain or source of the transfer MISFET and the transfer MISFET and a back gate;
A circuit for applying a voltage having a voltage amplitude larger than the sum of the operating voltage and the threshold voltage of the transfer MISFET to the gate of the transfer MISFET via a capacitor;
A booster circuit comprising: a second connection circuit for connecting a gate of the transfer MISFET and a drain or a source when the transfer MISFET is in an OFF state. The booster circuit according to claim 11, wherein
The first connection circuit includes a first substrate control MISFET and a second substrate control MISFET,
One of said 1st, 2nd board | substrate control MISFET conduct | electrically_connects, The higher one of the drain or source | sauce of the said transfer MISFET and the back gate of the said transfer MISFET are connected, The booster circuit characterized by the above-mentioned. The booster circuit according to claim 1, wherein
A boosting circuit comprising a selection circuit that selects whether to boost to positive or negative. The booster circuit according to claim 13, wherein
The selection circuit includes:
A booster circuit, wherein the first node or the last stage of the basic pump cell is connected to the operating voltage, and the other third node is connected to a ground potential. The booster circuit according to claim 1, wherein
With a series charge pump,
The booster circuit, wherein the series charge pump outputs a second voltage from a first voltage output from the booster circuit. A non-volatile memory, wherein at least one of reading, writing, and erasing is performed by a voltage generated by the booster circuit according to claim 1. An IC card comprising the nonvolatile memory according to claim 16. The booster circuit according to claim 9, wherein
In the second connection circuit, a drain-source path is connected between the gate and drain or source of the transfer MISFET, and a gate voltage setting MISFET in which the gate voltage of the transfer MOS in the previous basic pump cell is applied to the gate value. A booster circuit characterized by the above. The booster circuit according to claim 11, wherein
The second connection circuit is a gate voltage setting MISFET whose drain source path is connected between the gate and drain or source of the transfer MISFET, and to which the gate voltage of the transfer MOS in the previous basic pump cell is applied. A step-up circuit characterized by being.

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