JP4442109B2

JP4442109B2 - Semiconductor integrated circuit device

Info

Publication number: JP4442109B2
Application number: JP2003099782A
Authority: JP
Inventors: 善弘重田; 元多田; 修広橋; 英登小林
Original assignee: Fuji Electric Systems Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2003-04-03
Filing date: 2003-04-03
Publication date: 2010-03-31
Anticipated expiration: 2023-04-03
Also published as: JP2004311536A

Description

【０００１】
【発明の属する技術分野】
本発明は、高電圧で入出力を行う端子を多数含む半導体集積回路装置に関する。
【０００２】
【従来の技術】
高電圧で入出力を行う端子（以下、本明細書中では単に高電圧端子という）を含む半導体集積回路装置の一例として、例えば、近年普及が著しいＰＤＰ（Plasma Display Panel）のドライバＩＣを挙げることができる。このＰＤＰ用ドライバＩＣは多出力・小型実装が要求され、例えば、挟ピッチ（０．５ｍｍピッチ）のＱＦＰ（Quad Flat Package）パッケージが一般的となっている。
【０００３】
図４は従来技術のＰＤＰ用ドライバＩＣのＱＦＰ端子配置図である。なお、この端子配置は、現状ではディファクトスタンダードとなっている。
このＰＤＰ用ドライバＩＣの端子として、ＶＤＨ１，ＶＤＨ２は高電圧電源端子（５０Ｖ〜１５０Ｖ）であり、ＶＤＬは制御用電源端子（３〜５Ｖ）であり、ＧＮＤは接地端子（０Ｖ）であり、ＤＯ０１〜ＤＯ６４は高電圧駆動端子（５０Ｖ〜１５０Ｖ）であり、ＣＬＲ，ＤＡ，ＯＣ１，ＯＣ２，ＬＥ，ＣＬＫ，ＤＢ，Ａ／Ｂ（３Ｖ〜５Ｖ）は制御用入力端子であり、ＮＣは未接続端子である。このＰＤＰ用ドライバＩＣにおける高電圧端子は、高電圧電源端子および高電圧駆動端子が該当する。
【０００４】
また、他のＰＤＰ用ドライバＩＣのＱＦＰの端子配置が、例えば非特許文献１などにより開示されている
【０００５】
【非特許文献１】
“ＳＴＶ７６１７，ＳＴＶ７６１７Ｄ，ＳＴＶ７６１７Ｕ／ＰＬＡＳＭＡＤＩＳＰＬＡＹＰＡＮＥＬＳＣＡＮＤＲＩＶＥＲ”、（第３頁，第４頁，第５頁）、［ＯＮＬＩＮＥ］、ＳＴマイクロエレクトロニクス株式会社、［平成１５年３月１１日検索］、インターネット＜ＵＲＬ：http：//www.st-japan.co.jp/data/adv/20000406_prod1_pdp/pdf/stv7617.pdf＞
【０００６】
【発明が解決しようとする課題】
従来技術のＰＤＰ用ドライバＩＣにおいて、ＱＦＰ実装時に半田ブリッジ（半田が隣接する２本の端子にまたがる）が発生したり、または、半田ブリッジが発生しなくともその後に金属性異物など何らかの導電性異物が付着することにより２個の端子間が短絡される場合がある。特に高電圧端子と他の端子が短絡するような場合には問題がある。
【０００７】
例えば、図４で示す従来技術のＰＤＰ用ドライバＩＣについて、高電圧電源端子の配置に着目すると以下のような配置となっている。
図４の矢印Ａは高電圧電源端子ＶＤＨ１を指し、高電圧駆動端子ＤＯ１および未接続端子ＮＣと隣接する端子配置となっている。
図４の矢印Ｂは高電圧電源端子ＶＤＨ１を指し、高電圧駆動端子ＤＯ３１および未接続端子ＮＣと隣接する端子配置となっている。
図４の矢印Ｃは高電圧電源端子ＶＤＨ２を指し、２個の未接続端子ＮＣと隣接する端子配置となっている。
図４の矢印Ｄは高電圧電源端子ＶＤＨ２を指し、高電圧駆動端子ＤＯ３５および未接続端子ＮＣと隣接する端子配置となっている。
【０００８】
例えば、図４で示した従来技術のＰＤＰ用ドライバＩＣにおいて、高電圧電源端子ＶＤＨ１，ＶＤＨ２と、隣接する高電圧駆動端子ＤＯｎと、が短絡され、このような状態で高電圧駆動端子ＤＯｎの電位が０Ｖになったとき、５０〜１５０Ｖでの電源短絡状態となり、ＰＤＰ用ドライバＩＣに過大な電流が流れて破壊に至るおそれがあるという問題点があった。
同様に、ＰＤＰ用ドライバＩＣの高電圧端子（高電圧電源端子または高電圧駆動端子）と、隣接する端子（接地端子，制御用入力端子など）と、が短絡するような場合にも、破壊に至るような問題が発生するおそれがある。
【０００９】
そこで、本発明はこのような問題を解決するためになされたものであり、その目的は、高電圧電源端子または高電圧駆動端子と、他の端子と、の間が導電性異物等により短絡されたとしても、破壊を防止するような半導体集積回路装置を提供することにある。
【００１０】
【課題を解決するための手段】
上記課題を解決するため、本発明の請求項１に係る発明の半導体集積回路装置は、
四角形の樹脂封止パッケージの二辺のそれぞれの辺から所定ピッチで並んで複数の端子が突出するとともに残る二辺では端子を不配置とした空間部が形成されるＳＯＰ型、または、四角形の樹脂封止パッケージの四辺のそれぞれの辺から所定ピッチで並んで複数の端子が突出するとともに四隅に端子を不配置とした空間部が形成されるＱＦＰ型であり、これらの複数の端子の一部に制御用電源端子およびこの制御用電源端子よりも高電圧で入力を行う高電圧電源端子を含むようになされ、かつ、一の高電圧電源端子、または、二以上の高電圧電源端子を並べて配置した高電圧電源端子群を複数箇所で備える半導体集積回路装置であって、
全ての前記高電圧電源端子または前記高電圧電源端子群の両側が所定ピッチ隔てて隣接する未接続端子または所定ピッチ隔てて隣接する未接続端子と前記空間部とで挟まれることを特徴とする。
【００１１】
また、本発明の請求項２に係る発明の半導体集積回路装置は、
四角形の樹脂封止パッケージの二辺のそれぞれの辺から所定ピッチで並んで複数の端子が突出するとともに残る二辺では端子を不配置とした空間部が形成されるＳＯＰ型、または、四角形の樹脂封止パッケージの四辺のそれぞれの辺から所定ピッチで並んで複数の端子が突出するとともに四隅に端子を不配置とした空間部が形成されるＱＦＰ型であり、これらの複数の端子の一部に制御用電源端子およびこの制御用電源端子よりも高電圧で入力を行う高電圧電源端子を含むようになされ、かつ、一の高電圧電源端子、および、二以上の高電圧電源端子を並べて配置した高電圧電源端子群を有し、少なくとも何れか一方を複数箇所で備える半導体集積回路装置であって、
全ての前記高電圧電源端子または前記高電圧電源端子群の両側が所定ピッチ隔てて隣接する未接続端子または所定ピッチ隔てて隣接する未接続端子と前記空間部とで挟まれることを特徴とする。
【００１２】
また、本発明の請求項３に係る発明の半導体集積回路装置は、
請求項１または請求項２に記載の半導体集積回路装置において、
前記端子の一部として制御用入力端子およびこの制御用入力端子より高電圧で入出力を行う高電圧駆動端子を含み、
前記未接続端子の一部は、その反対側では高電圧駆動端子と所定ピッチ隔てて隣接することを特徴とする。
【００１３】
また、本発明の請求項４に係る発明の半導体集積回路装置は、
請求項１〜請求項３の何れか一項に記載の半導体集積回路装置において、
前記端子の一部としてグランド端子を含み、
前記未接続端子の一部は、その反対側ではグランド端子と所定ピッチ隔てて隣接することを特徴とする。
【００１４】
また、本発明の請求項５に係る発明の半導体集積回路装置は、
四角形の樹脂封止パッケージの四辺のそれぞれの辺から所定ピッチで並んで複数の端子が突出するとともに四隅に端子を不配置とした空間部が形成されるＱＦＰ型であり、これらの複数の端子の一部に制御用電源端子およびこの制御用電源端子よりも高電圧で入力を行う高電圧電源端子を含むようになされ、かつ、二以上の高電圧電源端子を並べて配置した高電圧電源端子群を複数箇所で備える半導体集積回路装置であって、
全ての高電圧電源端子群の両側が所定ピッチ隔てて隣接する未接続端子により挟まれることを特徴とする。
【００１５】
また、本発明の請求項６に係る発明の半導体集積回路装置は、
請求項５に記載の半導体集積回路装置において、
前記端子の一部として制御用入力端子およびこの制御用入力端子より高電圧で入出力を行う高電圧駆動端子を含み、
前記高電圧電源端子群に所定ピッチ隔てて隣接する未接続端子のうち一方の未接続端子は、その反対側では高電圧駆動端子と所定ピッチ隔てて隣接することを特徴とする。
【００１６】
また、本発明の請求項７に係る発明の半導体集積回路装置は、
請求項６に記載の半導体集積回路装置において、
前記高電圧駆動端子は、樹脂封止パッケージの一辺の全部およびこの一辺の両側の空間部を挟んで隣接する二辺の一部まで連続して複数個が配置され、
前記高電圧電源端子群と所定ピッチ隔てて隣接する未接続端子は、その反対側では、連続する高電圧駆動端子の両側の端部に所定ピッチ隔てて隣接して配置されることを特徴とする。
【００１７】
また、本発明の請求項８に係る発明の半導体集積回路装置は、
請求項７に記載の半導体集積回路装置において、
前記複数の高電圧駆動端子は、樹脂封止パッケージの対向する二辺の全部および空間部を挟んで隣接する、残る二辺のそれぞれ両端の一部まで連続して複数個が配置されることを特徴とする。
【００１８】
また、本発明の請求項９に係る発明の半導体集積回路装置は、
請求項６〜請求項８の何れか一項に記載の半導体集積回路装置において、
前記端子の一部としてグランド端子を含み、
前記高電圧電源端子群に所定ピッチ隔てて隣接する未接続端子のうち残る未接続端子は、その反対側ではグランド端子と所定ピッチ隔てて隣接して配置されることを特徴とする。
【００１９】
【発明の実施の形態】
続いて、本発明の実施形態に係る半導体集積回路装置について、図を参照しつつ以下に説明する。図１，図２は本実施形態の半導体集積回路装置の一部の構成図である。
【００２０】
本実施形態の半導体集積回路装置は、図１（ａ）で示すように、高電圧で入出力を行う２個の高電圧電源端子ＶＤＨ１が隣接する端子群を備え、この端子群の両側に隣接して２個の未接続端子ＮＣが配置される。
半田ブリッジや金属製異物などの導電性異物による隣接間短絡（２端子短絡）は経験的に発生が確認されており、例えば、高電圧電源端子ＶＤＨ１と未接続端子ＮＣとの隣接間短絡、または、２個の高電圧電源端子ＶＤＨ１の隣接間短絡は発生するおそれがある。
【００２１】
しかしながら、高電圧電源端子ＶＤＨ１と未接続端子ＮＣとが短絡しても電気的な回路が構成されないためＰＤＰ用ドライバＩＣに影響を与えるような電流等は流れない。
また、２個の高電圧電源端子ＶＤＨ１同士が短絡しても、同電位なためＰＤＰ用ドライバＩＣに影響を与えるような電流等は流れない。
さらに、隣接する３個の端子にまたがる短絡（３端子短絡）が発生する確率は極めて低い。
【００２２】
このように本実施形態の半導体集積回路装置では、２個の高電圧電源端子ＶＤＨ１が隣接する端子群を備え、この端子群の両側に隣接して２個の未接続端子ＮＣで挟む配置としたため、半田ブリッジや金属製異物などの導電性異物により高電圧電源端子と隣接する端子が短絡したしても、破壊を防ぐことが可能となる。
【００２３】
また、このような端子の配置は各種の変形が可能である。例えば、図１（ｂ）で示す半導体集積回路装置では、高電圧で入出力を行う２個の高電圧電源端子ＶＤＨ１が隣接する端子群は、その一方を四隅の空間部で、また、他方を未接続端子ＮＣで挟む配置としている。
このような端子の配置とすることによっても、半田ブリッジや金属製異物などの導電性異物により高電圧電源端子と隣接する端子とが短絡（２端子短絡）しても破壊を防ぐことが可能となる。
【００２４】
なお、半導体集積回路装置では、端子群は原則的に全てが図１（ａ）で示すように２個の未接続端子ＮＣで挟まれて配置される。
しかしながら、ある端子群は例外的に図１（ｂ）で示すように一方が四隅の空間部で、また、他方が未接続端子ＮＣで挟まれて配置され、残りの端子群は図１（ａ）で示すように２個の未接続端子ＮＣで挟まれて配置されるような形態としても良い。
【００２５】
また、他の変形形態として、例えば、図２（ａ）で示す半導体集積回路装置では、高電圧で入出力を行う１個の高電圧電源端子ＶＤＨ１の両隣に２個の未接続端子ＮＣで挟む配置としている。
このような端子の配置とすることによっても、半田ブリッジや金属製異物などの導電性異物により高電圧電源端子と隣接する端子とが短絡（２端子短絡）したとしても、破壊を防ぐことが可能となる。
【００２６】
また、例えば、図２（ｂ）で示す半導体集積回路装置では、高電圧で入出力を行う１個の高電圧電源端子ＶＤＨ１の一方を四隅の空間部で、また、他方を未接続端子ＮＣで挟む配置としている。
このような端子の配置とすることによっても、半田ブリッジや金属製異物などの導電性異物により高電圧電源端子と隣接する端子とが短絡（２端子短絡）したとしても、破壊を防ぐことが可能となる。
【００２７】
なお、半導体集積回路装置では、端子は原則的に全てが図２（ａ）で示すように２個の未接続端子ＮＣで挟まれて配置される。
しかしながら、一部の端子が例外的に図２（ｂ）で示すように一方が四隅の空間部で、また、他方が未接続端子ＮＣで挟まれて配置され、残りの端子が図２（ａ）で示すように２個の未接続端子ＮＣで挟まれて配置されるような形態としても良い。
【００２８】
さらにまた、半導体集積回路装置では、図１（ａ），図１（ｂ），図２（ａ），図２（ｂ）で示すような端子および端子群による配置を全て含み、つまり、ある端子または端子群の両側は未接続端子で挟む配置とし、残りの端子または端子群の両側の一方を空間部で、他方を未接続端子で挟む配置であっても良い。
【００２９】
続いて、本実施形態の半導体集積回路装置の一具体例として、ＰＤＰ用ドライバＩＣを例に挙げて説明する。図３は本実施形態の一具体例であるＰＤＰ用ドライバＩＣのＱＦＰの端子配置図である。
図４で示した従来技術例のＰＤＰ用ドライバＩＣと、図３で示すＰＤＰ用ドライバＩＣとの相違点は、高電圧出力端子Ｄ０１〜ＤＯ３２，ＤＯ３３〜ＤＯ６４を左右に均等に分割し、接地端子ＧＮＤの一部を端子Ｎｏ３５〜Ｎｏ４１にまとめることにより全ての高電圧電源端子ＶＤＨ１，ＶＤＨ２が、未接続端子ＮＣと隣接するようにした点である。なお、図４で示す従来技術例のＰＤＰ用ドライバの端子配置と比較し、高電圧駆動出力端子ＶＤＨ１，ＶＤＨ２の数を８本、接地端子ＧＮＤの数を１１本とし、数が一致するようにした。
【００３０】
さらに、図３の矢印ａと矢印ｂとの間では、高電圧電源端子ＶＤＨ１の両隣にそれぞれ未接続端子ＮＣが隣接する端子配置となっている。
図３の矢印ｃと矢印ｄとの間は、高電圧電源端子ＶＤＨ１の両隣にそれぞれ未接続端子ＮＣが隣接する端子配置となっている。
図３の矢印ｅと矢印ｆとの間は、高電圧電源端子ＶＤＨ２の両隣にそれぞれ未接続端子ＮＣが隣接する端子配置となっている。
図３の矢印ｇと矢印ｈとの間は、高電圧電源端子ＶＤＨ２の両隣にそれぞれ未接続端子ＮＣが隣接する端子配置となっている。
【００３１】
また、図３の矢印ａと矢印ｉとの間では、高電圧駆動端子ＤＯ１の隣に未接続端子ＮＣが、また、高電圧駆動端子ＤＯ２の隣に四隅の空間部が隣接する端子配置ともなっている。
また、図３の矢印ｃと矢印ｊとの間では、高電圧駆動端子ＤＯ３２の隣に未接続端子ＮＣが、また、高電圧駆動端子ＤＯ２８の隣に四隅の空間部が隣接する端子配置ともなっている。
また、図３の矢印ｆと矢印ｋとの間では、高電圧駆動端子ＤＯ６４の隣に未接続端子ＮＣが、また、高電圧駆動端子ＤＯ６３の隣に四隅の空間部が隣接する端子配置ともなっている。
また、図３の矢印ｈと矢印ｌとの間では、高電圧駆動端子ＤＯ３３の隣に未接続端子ＮＣが、また、高電圧駆動端子ＤＯ３７の隣に四隅の空間部が隣接する端子配置ともなっている。
【００３２】
このように図３で示すＰＤＰ用ドライバＩＣでは、高電圧電源端子による端子群または高電圧駆動端子による端子群を備える半導体集積回路装置であるが、高電圧電源端子による端子群の両側は未接続端子で挟む配置とし、残りの高電圧駆動端子による端子群の両側の一方を空間部で、他方を未接続端子で挟む配置としている。
【００３３】
このような端子配置構造を採用することにより、半田ブリッジや金属製異物などの導電性異物により高電圧電源端子または高圧駆動端子と隣接する端子が短絡する隣接間短絡（２端子短絡）が発生しても直ちに破壊される事態の発生を防ぐ。また、半田ブリッジや金属製異物などの導電性異物による３端子短絡が発生する確率は極めて低い。このように本発明のような半導体集積回路装置では短絡による破壊が発生するおそれを極めて低くすることが可能となる。
【００３４】
以上本発明の半導体集積回路装置について説明した。
本実施形態では多数の端子を有する樹脂封止パッケージであるＱＦＰ（Quad Flat Package）パッケージを例に挙げて説明した。ＱＦＰパッケージではＩＣの４辺から外側に向かって，細かい間隔で接続用の端子が出ているパッケージであり、広く用いられているが、本実施形態ではＱＦＰに限定する趣旨ではなく、例えば、ＳＯＰ（Small Outline Package）パッケージに適用しても良い。
【００３５】
ＳＯＰパッケージでは平行な２辺から外向きの端子を有するが、このようなＳＯＰパッケージでも、全ての高電圧端子または高電圧端子による端子群が、２個の未接続端子ＮＣで挟まれて配置される構造、または一方を四隅の空間部で、また、他方を未接続端子で挟まれて配置される構造を採用するようにしても良い。
【００３６】
また、本発明は現状では高電圧電源端子を有するＰＤＰ用ドライバＩＣ等での採用が特に効果的である。
しかしながら、高電圧端子を有する半導体集積回路装置であれば、本発明の適用は可能である。今後登場する未知の装置のドライバ用ＩＣなど、各種適用が可能である。
【００３７】
【発明の効果】
以上の通り、本発明によれば、高電圧電源端子または高電圧駆動端子と、他の端子と、の間が導電性異物等により短絡されたとしても、破壊を防止するような半導体集積回路装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の実施形態の半導体集積回路装置の一部の構成図である。
【図２】本発明の実施形態の半導体集積回路装置の一部の構成図である。
【図３】本発明の実施形態の一具体例であるＰＤＰ用ドライバＩＣのＱＦＰの端子配置図である。
【図４】従来技術のＰＤＰ用ドライバＩＣのＱＦＰの端子配置図である。
【符号の説明】
ＶＤＨ１，ＶＤＨ２：高電圧電源端子
ＶＤＬ：制御用電源端子
ＧＮＤ：接地端子
ＮＣ：未接続端子
ＤＯ１〜ＤＯ６４：高電圧駆動端子
ＣＬＲ：制御入力端子
ＤＡ：制御入力端子
ＯＣ１：制御入力端子
ＯＣ２：制御入力端子
ＬＥ：制御入力端子
ＣＬＫ：制御入力端子
ＤＢ：制御入力端子
Ａ／Ｂ：制御入力端子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device including a large number of terminals that perform input / output at a high voltage.
[0002]
[Prior art]
As an example of a semiconductor integrated circuit device including a terminal for inputting / outputting at a high voltage (hereinafter, simply referred to as a high voltage terminal in this specification), for example, a driver IC of a PDP (Plasma Display Panel) which has been widely used in recent years Can do. The driver IC for PDP is required to have multiple outputs and small packaging, for example, a QFP (Quad Flat Package) package with a narrow pitch (0.5 mm pitch) is generally used.
[0003]
FIG. 4 is a QFP terminal layout diagram of a conventional PDP driver IC. This terminal arrangement is the de facto standard at present.
As terminals of this PDP driver IC, VDH1 and VDH2 are high voltage power supply terminals (50V to 150V), VDL is a control power supply terminal (3 to 5V), GND is a ground terminal (0V), DO01 ˜DO64 is a high voltage drive terminal (50 V to 150 V), CLR, DA, OC1, OC2, LE, CLK, DB, A / B (3 V to 5 V) are control input terminals, and NC is an unconnected terminal It is. The high voltage terminal in this PDP driver IC corresponds to a high voltage power supply terminal and a high voltage drive terminal.
[0004]
Further, the QFP terminal arrangement of another PDP driver IC is disclosed in, for example, Non-Patent Document 1.
[Non-Patent Document 1]
“STV7617, STV7617D, STV7617U / PLASMA DISPLAY PANEL SCAN DRIVER” (3rd page, 4th page, 5th page), [ONLINE], ST Microelectronics, Inc., [March 11, 2003 search], Internet <URL: http://www.st-japan.co.jp/data/adv/20000406_prod1_pdp/pdf/stv7617.pdf>
[0006]
[Problems to be solved by the invention]
In a conventional PDP driver IC, a solder bridge (sold over two adjacent terminals) occurs when QFP is mounted, or some conductive foreign matter such as a metallic foreign matter does not occur even if no solder bridge occurs. May cause a short circuit between the two terminals. There is a problem especially when the high voltage terminal and other terminals are short-circuited.
[0007]
For example, the conventional PDP driver IC shown in FIG. 4 has the following arrangement when attention is paid to the arrangement of the high voltage power supply terminals.
An arrow A in FIG. 4 indicates the high voltage power supply terminal VDH1, which is a terminal arrangement adjacent to the high voltage drive terminal DO1 and the unconnected terminal NC.
An arrow B in FIG. 4 indicates the high voltage power supply terminal VDH1, which is a terminal arrangement adjacent to the high voltage drive terminal DO31 and the unconnected terminal NC.
An arrow C in FIG. 4 indicates the high-voltage power supply terminal VDH2, and has a terminal arrangement adjacent to the two unconnected terminals NC.
An arrow D in FIG. 4 indicates the high voltage power supply terminal VDH2, which is a terminal arrangement adjacent to the high voltage drive terminal DO35 and the unconnected terminal NC.
[0008]
For example, in the conventional PDP driver IC shown in FIG. 4, the high voltage power supply terminals VDH1 and VDH2 and the adjacent high voltage drive terminal DOn are short-circuited, and in this state, the potential of the high voltage drive terminal DOn. When the voltage becomes 0 V, the power supply is short-circuited at 50 to 150 V, and there is a problem that an excessive current may flow to the PDP driver IC and cause destruction.
Similarly, even if the high voltage terminal (high voltage power supply terminal or high voltage drive terminal) of the driver IC for PDP and an adjacent terminal (grounding terminal, control input terminal, etc.) are short-circuited, it will be destroyed. Problems may occur.
[0009]
Therefore, the present invention has been made to solve such a problem, and its purpose is to short-circuit between the high-voltage power supply terminal or the high-voltage drive terminal and other terminals by a conductive foreign substance or the like. Even if it exists, it is providing the semiconductor integrated circuit device which prevents destruction.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit device according to a first aspect of the present invention provides:
A SOP type or rectangular resin in which a plurality of terminals protrude from each side of the two sides of the rectangular resin-sealed package at a predetermined pitch and a space is formed in which the terminals are not arranged on the remaining two sides. It is a QFP type in which a plurality of terminals protrude from each side of the four sides of the sealed package at a predetermined pitch and spaces are formed in the four corners with no terminals arranged. A control power supply terminal and a high voltage power supply terminal that inputs at a higher voltage than the control power supply terminal are included, and one high voltage power supply terminal or two or more high voltage power supply terminals are arranged side by side. A semiconductor integrated circuit device comprising a plurality of high voltage power supply terminal groups,
All the high voltage power supply terminals or both sides of the high voltage power supply terminal group are sandwiched between the unconnected terminals adjacent to each other with a predetermined pitch or the unconnected terminals adjacent to each other with a predetermined pitch and the space portion.
[0011]
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
A SOP type or rectangular resin in which a plurality of terminals protrude from each side of the two sides of the rectangular resin-sealed package at a predetermined pitch and a space is formed in which the terminals are not arranged on the remaining two sides. It is a QFP type in which a plurality of terminals protrude from each side of the four sides of the sealed package at a predetermined pitch and spaces are formed in the four corners with no terminals arranged. A control power supply terminal and a high voltage power supply terminal that inputs at a higher voltage than the control power supply terminal are included, and one high voltage power supply terminal and two or more high voltage power supply terminals are arranged side by side. A semiconductor integrated circuit device having a high voltage power supply terminal group and comprising at least one of them at a plurality of locations,
All the high voltage power supply terminals or both sides of the high voltage power supply terminal group are sandwiched between the unconnected terminals adjacent to each other with a predetermined pitch or the unconnected terminals adjacent to each other with a predetermined pitch and the space portion.
[0012]
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
The semiconductor integrated circuit device according to claim 1 or 2,
As a part of the terminal, including a control input terminal and a high voltage drive terminal for performing input / output at a higher voltage than the control input terminal,
Some of the unconnected terminals, at its opposite side, characterized in that the adjacent separating high-voltage terminal and a predetermined pitch.
[0013]
According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
In the semiconductor integrated circuit device according to any one of claims 1 to 3,
Including a ground terminal as part of the terminal;
Some of the unconnected terminals, at its opposite side, characterized in that the adjacent separating ground terminal and a predetermined pitch.
[0014]
According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
It is a QFP type in which a plurality of terminals protrude from each side of the four sides of a rectangular resin-sealed package at a predetermined pitch and spaces are formed in the four corners with no terminals arranged. A high-voltage power supply terminal group that includes a control power supply terminal and a high-voltage power supply terminal that inputs at a higher voltage than the control power supply terminal, and in which two or more high-voltage power supply terminals are arranged side by side. A semiconductor integrated circuit device provided at a plurality of locations,
Both sides of all of the high voltage power supply terminals and said Rukoto flanked by unconnected pin adjacent spaced a predetermined pitch.
[0015]
According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
The semiconductor integrated circuit device according to claim 5,
As a part of the terminal, including a control input terminal and a high voltage drive terminal for performing input / output at a higher voltage than the control input terminal,
One of the unconnected terminals adjacent to the high voltage power supply terminal group with a predetermined pitch is adjacent to the high voltage drive terminal with a predetermined pitch on the opposite side .
[0016]
According to a seventh aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
The semiconductor integrated circuit device according to claim 6.
A plurality of the high-voltage drive terminals are continuously arranged up to all of one side of the resin-sealed package and a part of two sides adjacent to each other across the space portion on both sides of the one side,
The unconnected terminals adjacent to the high voltage power supply terminal group with a predetermined pitch are disposed on the opposite side adjacent to the end portions on both sides of the continuous high voltage drive terminal with a predetermined pitch. .
[0017]
A semiconductor integrated circuit device according to an eighth aspect of the present invention includes:
The semiconductor integrated circuit device according to claim 7,
The plurality of high-voltage drive terminals are arranged in succession to all of the two opposite sides of the resin-sealed package and a part of each of the remaining two sides adjacent to each other across the space. Features.
[0018]
According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
The semiconductor integrated circuit device according to any one of claims 6 to 8,
Including a ground terminal as part of the terminal;
Unconnected terminals remain among the unconnected pin adjacent spaced a predetermined pitch in the high voltage power supply terminal group, at its opposite side characterized Rukoto disposed adjacent apart ground terminals and a predetermined pitch.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Subsequently, a semiconductor integrated circuit device according to an embodiment of the present invention will be described below with reference to the drawings. 1 and 2 are partial configuration diagrams of the semiconductor integrated circuit device of this embodiment.
[0020]
As shown in FIG. 1A, the semiconductor integrated circuit device according to the present embodiment includes a terminal group in which two high-voltage power supply terminals VDH1 that perform input / output at a high voltage are adjacent to each other, and are adjacent to both sides of this terminal group. Thus, two unconnected terminals NC are arranged.
It has been confirmed empirically that an adjacent short-circuit (two-terminal short-circuit) due to a conductive foreign material such as a solder bridge or a metal foreign material has occurred, for example, a short-circuit between adjacent high-voltage power supply terminal VDH1 and unconnected terminal NC, or There is a possibility that a short circuit between adjacent two high voltage power supply terminals VDH1 occurs.
[0021]
However, even if the high-voltage power supply terminal VDH1 and the unconnected terminal NC are short-circuited, an electric circuit that does not affect the PDP driver IC does not flow because an electrical circuit is not configured.
Even if the two high-voltage power supply terminals VDH1 are short-circuited, a current that affects the PDP driver IC does not flow because of the same potential.
Furthermore, the probability of occurrence of a short circuit (three-terminal short circuit) over three adjacent terminals is extremely low.
[0022]
As described above, in the semiconductor integrated circuit device according to the present embodiment, the two high voltage power supply terminals VDH1 are provided with adjacent terminal groups, and are arranged so as to be sandwiched between the two unconnected terminals NC adjacent to both sides of the terminal group. Even if a terminal adjacent to the high-voltage power supply terminal is short-circuited by a conductive foreign matter such as a solder bridge or a metallic foreign matter, the breakage can be prevented.
[0023]
In addition, the terminal arrangement can be variously modified. For example, in the semiconductor integrated circuit device shown in FIG. 1B, a terminal group adjacent to two high-voltage power supply terminals VDH1 that perform input / output at a high voltage is one of the four corner spaces and the other. It is arranged to be sandwiched between unconnected terminals NC.
Even with this arrangement of terminals, it is possible to prevent destruction even if the high-voltage power supply terminal and the adjacent terminal are short-circuited (two-terminal short-circuit) due to conductive foreign matters such as solder bridges and metal foreign matters. Become.
[0024]
In the semiconductor integrated circuit device, in principle, all the terminal groups are arranged between two unconnected terminals NC as shown in FIG.
However, as shown in FIG. 1 (b), one terminal group is exceptionally arranged such that one is a space portion at the four corners and the other is sandwiched between unconnected terminals NC, and the remaining terminal groups are shown in FIG. As shown by (), a configuration may be adopted in which the two non-connected terminals NC are arranged.
[0025]
As another modification, for example, in the semiconductor integrated circuit device shown in FIG. 2A, two unconnected terminals NC are sandwiched on both sides of one high voltage power supply terminal VDH1 that inputs and outputs at a high voltage. It is arranged.
Even with this arrangement of terminals, even if the high-voltage power supply terminal and the adjacent terminal are short-circuited (two-terminal short-circuit) due to conductive foreign matter such as a solder bridge or metal foreign matter, destruction can be prevented. It becomes.
[0026]
Further, for example, in the semiconductor integrated circuit device shown in FIG. 2B, one high-voltage power supply terminal VDH1 that performs input / output at a high voltage is one of the four corner spaces, and the other is the unconnected terminal NC. The arrangement is sandwiched.
Even with this arrangement of terminals, even if the high-voltage power supply terminal and the adjacent terminal are short-circuited (two-terminal short-circuit) due to conductive foreign matter such as a solder bridge or metal foreign matter, destruction can be prevented. It becomes.
[0027]
In the semiconductor integrated circuit device, in principle, all terminals are sandwiched between two unconnected terminals NC as shown in FIG.
However, as shown in FIG. 2B, some of the terminals are exceptionally arranged such that one is a space at the four corners and the other is sandwiched between unconnected terminals NC, and the remaining terminals are shown in FIG. As shown by (), a configuration may be adopted in which the two non-connected terminals NC are arranged.
[0028]
Furthermore, the semiconductor integrated circuit device includes all the arrangements of terminals and terminal groups as shown in FIG. 1A, FIG. 1B, FIG. 2A, and FIG. Alternatively, both sides of the terminal group may be sandwiched by unconnected terminals, and one of the remaining terminals or both sides of the terminal group may be sandwiched by a space portion and the other may be sandwiched by unconnected terminals.
[0029]
Subsequently, as a specific example of the semiconductor integrated circuit device of the present embodiment, a PDP driver IC will be described as an example. FIG. 3 is a QFP terminal layout diagram of a PDP driver IC which is a specific example of the present embodiment.
The difference between the PDP driver IC of the prior art example shown in FIG. 4 and the PDP driver IC shown in FIG. 3 is that the high voltage output terminals D01 to DO32 and DO33 to DO64 are equally divided into left and right, and ground terminals. All the high voltage power supply terminals VDH1 and VDH2 are adjacent to the unconnected terminal NC by combining a part of GND into terminals No35 to No41. Compared with the terminal arrangement of the PDP driver of the prior art example shown in FIG. 4, the number of high voltage drive output terminals VDH1 and VDH2 is 8, and the number of ground terminals GND is 11, so that the numbers match. did.
[0030]
Further, between the arrow a and the arrow b in FIG. 3, a terminal arrangement in which unconnected terminals NC are adjacent to both sides of the high voltage power supply terminal VDH1 is provided.
Between the arrow c and the arrow d in FIG. 3, there is a terminal arrangement in which unconnected terminals NC are adjacent to both sides of the high voltage power supply terminal VDH1.
Between the arrow e and the arrow f in FIG. 3, there is a terminal arrangement in which unconnected terminals NC are adjacent to both sides of the high-voltage power supply terminal VDH2.
Between the arrow g and the arrow h in FIG. 3, there is a terminal arrangement in which unconnected terminals NC are adjacent to both sides of the high-voltage power supply terminal VDH2.
[0031]
Further, between the arrow a and the arrow i in FIG. 3, there is a terminal arrangement in which the unconnected terminal NC is adjacent to the high voltage drive terminal DO1 and the four corner spaces are adjacent to the high voltage drive terminal DO2. Yes.
Also, between the arrow c and the arrow j in FIG. 3, the terminal arrangement is such that the unconnected terminal NC is adjacent to the high voltage drive terminal DO32 and the four corner spaces are adjacent to the high voltage drive terminal DO28. Yes.
In addition, between the arrow f and the arrow k in FIG. 3, the non-connected terminal NC is adjacent to the high voltage driving terminal DO64, and the four corner spaces are adjacent to the high voltage driving terminal DO63. Yes.
Further, between the arrow h and the arrow l in FIG. 3, there is a terminal arrangement in which the unconnected terminal NC is adjacent to the high voltage drive terminal DO33 and the space portions at the four corners are adjacent to the high voltage drive terminal DO37. Yes.
[0032]
As described above, the PDP driver IC shown in FIG. 3 is a semiconductor integrated circuit device having a terminal group by a high voltage power supply terminal or a terminal group by a high voltage drive terminal, but both sides of the terminal group by a high voltage power supply terminal are not connected. The arrangement is such that one of the two sides of the terminal group of the remaining high voltage drive terminals is sandwiched between the space portions and the other is sandwiched between the unconnected terminals.
[0033]
By adopting such a terminal arrangement structure, an adjacent short-circuit (two-terminal short-circuit) in which a high-voltage power supply terminal or a terminal adjacent to a high-voltage drive terminal is short-circuited by conductive foreign matter such as a solder bridge or metal foreign matter occurs. However, it will prevent the occurrence of immediate destruction. In addition, the probability of occurrence of a three-terminal short circuit due to conductive foreign matters such as solder bridges and metallic foreign matters is extremely low. As described above, in the semiconductor integrated circuit device according to the present invention, it is possible to extremely reduce the possibility of breakdown due to a short circuit.
[0034]
The semiconductor integrated circuit device of the present invention has been described above.
In the present embodiment, a QFP (Quad Flat Package) package, which is a resin-sealed package having a large number of terminals, has been described as an example. The QFP package is a package in which connection terminals come out at a fine interval from the four sides of the IC toward the outside, and is widely used. However, the present embodiment is not limited to the QFP. (Small Outline Package) It may be applied to a package.
[0035]
The SOP package has terminals facing outward from two parallel sides, but even in such an SOP package, all high-voltage terminals or a terminal group of high-voltage terminals are sandwiched between two unconnected terminals NC. Alternatively, a structure may be adopted in which one is disposed between four corner spaces and the other is sandwiched between unconnected terminals.
[0036]
In addition, the present invention is particularly effective when used in a PDP driver IC having a high voltage power supply terminal.
However, the present invention can be applied to any semiconductor integrated circuit device having a high voltage terminal. Various applications such as driver ICs for unknown devices that will appear in the future are possible.
[0037]
【The invention's effect】
As described above, according to the present invention, a semiconductor integrated circuit device that prevents destruction even when a high-voltage power supply terminal or high-voltage drive terminal and another terminal are short-circuited by a conductive foreign material or the like. Can be provided.
[Brief description of the drawings]
FIG. 1 is a partial configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 2 is a partial configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 3 is a QFP terminal layout diagram of a PDP driver IC which is a specific example of an embodiment of the present invention;
FIG. 4 is a QFP terminal layout diagram of a conventional PDP driver IC;
[Explanation of symbols]
VDH1, VDH2: High voltage power supply terminal VDL: Control power supply terminal GND: Ground terminal NC: Unconnected terminals DO1 to DO64: High voltage drive terminal CLR: Control input terminal DA: Control input terminal OC1: Control input terminal OC2: Control input Terminal LE: Control input terminal CLK: Control input terminal DB: Control input terminal A / B: Control input terminal

Claims

A SOP type or rectangular resin in which a plurality of terminals protrude from each side of the two sides of the rectangular resin-sealed package at a predetermined pitch and a space is formed in which the terminals are not arranged on the remaining two sides. It is a QFP type in which a plurality of terminals protrude from each side of the four sides of the sealed package at a predetermined pitch and spaces are formed in the four corners with no terminals arranged. A control power supply terminal and a high voltage power supply terminal that inputs at a higher voltage than the control power supply terminal are included, and one high voltage power supply terminal or two or more high voltage power supply terminals are arranged side by side. A semiconductor integrated circuit device comprising a plurality of high voltage power supply terminal groups,
All the high-voltage power supply terminals or both sides of the high-voltage power supply terminal group are sandwiched between unconnected terminals adjacent to each other with a predetermined pitch or unconnected terminals adjacent to each other with a predetermined pitch and the space portion Integrated circuit device.

A SOP type or rectangular resin in which a plurality of terminals protrude from each side of the two sides of the rectangular resin-sealed package at a predetermined pitch and a space is formed in which the terminals are not arranged on the remaining two sides. It is a QFP type in which a plurality of terminals protrude from each side of the four sides of the sealed package at a predetermined pitch and spaces are formed in the four corners with no terminals arranged. A control power supply terminal and a high voltage power supply terminal that inputs at a higher voltage than the control power supply terminal are included, and one high voltage power supply terminal and two or more high voltage power supply terminals are arranged side by side. A semiconductor integrated circuit device having a high voltage power supply terminal group and comprising at least one of them at a plurality of locations,
All the high-voltage power supply terminals or both sides of the high-voltage power supply terminal group are sandwiched between unconnected terminals adjacent to each other with a predetermined pitch or unconnected terminals adjacent to each other with a predetermined pitch and the space portion Integrated circuit device.

The semiconductor integrated circuit device according to claim 1 or 2,
As a part of the terminal, including a control input terminal and a high voltage drive terminal for performing input / output at a higher voltage than the control input terminal,
The portion of the unconnected terminals, the semiconductor integrated circuit device, characterized in that at the opposite side of the adjacent separating high-voltage terminal and a predetermined pitch.

In the semiconductor integrated circuit device according to any one of claims 1 to 3,
Including a ground terminal as part of the terminal;
The portion of the unconnected terminals, the semiconductor integrated circuit device, characterized in that the adjacent separating ground terminal and a predetermined pitch in the opposite side.

It is a QFP type in which a plurality of terminals protrude from each side of the four sides of a rectangular resin-sealed package at a predetermined pitch and spaces are formed in the four corners with no terminals arranged. A high-voltage power supply terminal group that includes a control power supply terminal and a high-voltage power supply terminal that inputs at a higher voltage than the control power supply terminal, and in which two or more high-voltage power supply terminals are arranged side by side. A semiconductor integrated circuit device provided at a plurality of locations,
The semiconductor integrated circuit device in which both sides of all of the high voltage power supply terminals and said Rukoto flanked by unconnected pin adjacent spaced a predetermined pitch.

The semiconductor integrated circuit device according to claim 5,
As a part of the terminal, including a control input terminal and a high voltage drive terminal for performing input / output at a higher voltage than the control input terminal,
One unconnected terminal among the unconnected terminals adjacent to the high voltage power supply terminal group with a predetermined pitch is adjacent to the high voltage drive terminal with a predetermined pitch on the opposite side .

The semiconductor integrated circuit device according to claim 6.
A plurality of the high-voltage drive terminals are continuously arranged up to all of one side of the resin-sealed package and a part of two sides adjacent to each other across the space portion on both sides of the one side,
The unconnected terminals adjacent to the high voltage power supply terminal group with a predetermined pitch are disposed on the opposite side adjacent to the end portions on both sides of the continuous high voltage drive terminal with a predetermined pitch. Semiconductor integrated circuit device.

The semiconductor integrated circuit device according to claim 7,
The plurality of high-voltage drive terminals are arranged in succession to all of the two opposite sides of the resin-sealed package and a part of each of the remaining two sides adjacent to each other across the space. A semiconductor integrated circuit device.

The semiconductor integrated circuit device according to any one of claims 6 to 8,
Including a ground terminal as part of the terminal;
Unconnected terminals remain among the unconnected pin adjacent spaced a predetermined pitch in the high voltage power supply terminals, the semiconductor integrated circuit device in the opposite side, characterized in Rukoto disposed adjacent apart ground terminals with a predetermined pitch .