JP4439341B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device having thin and thick portions in an interlayer insulating film of a layer sandwiched between multilayer wirings.

  In general, semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and wirings are formed on the surface of a semiconductor substrate such as a silicon substrate. After these semiconductor elements are formed, an interlayer insulating film made of a silicon oxide film or the like is formed so as to cover the semiconductor substrate surface and the formed semiconductor elements. Then, a first layer wiring is formed on the interlayer insulating film, and an interlayer insulating film is further formed on the first layer wiring. In this way, a further upper layer wiring and an interlayer insulating film corresponding to the number of layers of the upper layer wiring are formed in multiple layers.

  The prior art document information related to the invention of this application includes the following.

JP-A-4-82263 JP 2000-58638 A JP 2000-223492 A JP 2002-313908 A R. Scheuerlein et al., `` A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell '' ISSCC 2000 / SESSION 7 / TD: EMERGING MEMORY & DEVICE TECHNOLOGIES / PAPER TA 7.2, pp. 128-129 P.K.Naji et al., `` A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM '' ISSCC 2001 / SESSION 7 / TECHNOLOGY DIRECTIONS: ADVANCED TECHNOLOGIES / 7.6, pp.122-123

  In order to form each thin and thick portion in an interlayer insulating film of a certain layer sandwiched between multilayer wirings on a semiconductor substrate, for example, the following method has been performed.

  First, by using a CVD (Chemical Vapor Deposition) technique, an interlayer insulating film having a uniform thickness is formed in a lower structure (an n-th layer wiring (n = 0, 1) covered with an interlayer insulating film to be formed from a semiconductor substrate). , 2, 3..., But when n = 0, it indicates the structure up to (wiring formed on the surface of the semiconductor substrate). Thereafter, using a photolithography technique and an etching technique, a portion of the surface of the interlayer insulating film that is desired to be thin is selectively etched. In this way, the etched portion becomes the thin film portion, the unetched portion becomes the thick film portion, and the interlayer insulating film in the same layer can be formed to have the thin portions.

  However, according to the above method, an additional step of partial removal of the formed film is required after the formation of the interlayer insulating film, which is a complicated manufacturing method.

  Another possible method is to use the difference in the number of layers to be overlapped, such as forming a portion to be thinned as a single interlayer insulating film and forming a portion to be thickened as a double interlayer insulating film. However, also in this case, an additional step of forming a new interlayer insulating film is required, which is a complicated manufacturing method.

  The present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor device that can easily manufacture a semiconductor device in which an interlayer insulating film of a certain layer sandwiched between multilayer wirings has thick and thin portions. Objective.

In a first aspect of the present invention, a method of manufacturing a semiconductor device includes a step of preparing a semiconductor substrate having a first region and a second region, and a plurality of MTJs (Magneto-Tunneling Junction) above the semiconductor substrate in the first region. ) forming an element, covering the plurality of MTJ elements, and a step of forming an insulating film having an upper surface, penetrate the insulating film, a plurality of contact holes reaching each one of a plurality of MTJ elements relatively tightly forming, a step of forming a conductive film in said contact hole and the insulating film, by generating erosion and facilities a CMP (Chemical Mechanical Polishing) to the conductive layer, the contact of the conductive layer is buried in the hole, a step to make the upper surface of the insulating layer of the first region than the upper surface of the insulating film on the second region is lower, the Conta Forming a wiring electrically connected to the conductive film embedded in the cut hole above the insulating film.
According to a second aspect of the present invention, in a method for manufacturing a semiconductor device, a step of preparing a semiconductor substrate having a first region and a second region, and a plurality of MTJs (Magneto- forming a Tunneling Junction) element, covering the plurality of MTJ elements, forming a first insulating film having an upper surface, penetrates the first insulating film, a plurality of contacts to reach each of the plurality of MTJ elements a step of relatively densely forming a hole, and forming a conductive film in said contact hole and said first insulating film, thereby generating an erosion by facilities a CMP (Chemical Mechanical Polishing) on the conductive layer As a result, the conductive film is embedded in the contact hole, and the upper surface of the first insulating film on the first region is lower than the upper surface of the first insulating film on the second region. A step of forming a second insulating film on the first insulating film, a step of forming a third insulating film on the second insulating film, and a second insulating film after the CMP step. using film as an etching stopper film, after etching the third insulating film, by etching the second insulating film, forming a pattern reaching said conductive layer, buried in the contact hole in the pattern during and a step of forming the conductive film electrically connected to wiring lines.

According to the present invention, the interlayer insulating film can be formed thin in the first region, and the interlayer insulating film can be formed thick in the second region. As a result, a semiconductor device in which a certain level of interlayer insulating film sandwiched between multilayer wirings has thick and thin portions can be easily manufactured.

<Embodiment 1>
In this embodiment, contact holes are formed relatively densely in one region of the interlayer insulating film, and contact holes are formed relatively sparsely in the other region, and CMP (Chemical Mechanical Polishing) is formed on the surface of the interlayer insulating film. ) To generate erosion in a relatively dense contact hole formation portion. Thereby, the interlayer insulating film can be formed thin in the first region and the interlayer insulating film can be formed thick in the second region by a single CMP process, and the interlayer insulating film of a certain layer sandwiched between the multilayer wirings can be made thin and thin. A semiconductor device having a portion can be easily manufactured.

  FIG. 1 is a top view of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present embodiment. 2, 3 and 4 are cross-sectional views taken along cutting lines II-II, III-III and IV-IV in FIG. 1, respectively.

  As shown in FIGS. 1 to 4, in this semiconductor device, an n-th layer wiring (n = 0, 1, 2, 3...: N = 0) is formed on a lower structure 1 including a semiconductor substrate such as a silicon substrate. In this case, wirings L4 to L8 formed on the surface of the semiconductor substrate and an interlayer insulating film 2 such as a silicon oxide film are formed. Here, the lower structure 1 refers to a structure from the semiconductor substrate to the n-th layer wirings L4 to L8 covered with the interlayer insulating film 2 to be formed.

  In the first region AR1 of the interlayer insulating film 2, contact plugs PG5 and contact plugs PG2 connected to the nth layer wirings L5 and L6 and dummy plugs DP1 and DP2 not connected to the nth layer wirings are formed relatively densely. Has been. The contact plugs PG2 and PG5 and the dummy plugs DP1 and DP2 are all connected to a thick and thick wiring L3 formed on the surface of the interlayer insulating film 2. Note that the thickness B of the wiring L3 is, for example, 400 nm.

  On the other hand, in the second region AR2 of the interlayer insulating film 2, the contact plug PG1 connected to the contact plug PG4, the nth layer wiring L4, and the contact plug PG3 connected to the nth layer wiring L8 are formed relatively sparsely. ing. The contact plugs PG1 and PG4 are connected to the thin and thin wiring L1 formed on the surface of the interlayer insulating film 2, and the contact plugs PG3 and PG4 are connected to the thin and thin wiring L2 formed on the surface of the interlayer insulating film 2. Has been. Note that the thickness A of the wirings L1 and L2 is, for example, 300 nm.

  Note that the wirings L1 to L3 function as the (n + 1) th layer wiring.

  5 to 11 are views for explaining a manufacturing process of the semiconductor device shown in FIGS. 1 to 4 taking the cross-sectional structure of FIG. 4 as an example.

  First, an insulating film 2a such as a silicon oxide film constituting the interlayer insulating film 2 is formed on the lower structure 1 by a CVD (Chemical Vapor Deposition) method or the like, and the insulating film 2a is formed on the insulating film 2a by using a photolithography technique and an etching technique. The n-layer wirings L4 to L8 are patterned. Thereafter, a conductive film (not shown) such as copper is formed so as to embed the patterning portion, and CMP is performed on the conductive film to form n-th layer wirings L4 to L8 (FIG. 5).

  Next, an insulating film 2b such as a silicon oxide film constituting the interlayer insulating film 2 is formed by a CVD method or the like so as to cover the n-th layer wirings L4 to L8 and the insulating film 2a (FIG. 6).

  Subsequently, contact holes for forming contact plugs PG2 and PG5 and dummy plugs DP1 and DP2 are formed relatively densely in the first region AR1 of the insulating film 2b by using a photolithography technique and an etching technique. In the second region AR2 of the insulating film 2b, contact holes for forming the contact plugs PG1, PG3, PG4 are formed relatively sparsely (FIG. 7).

  In FIG. 7, the dummy hole DH1 for forming the dummy plug DP1 and the contact hole VH1 for forming the contact plug PG3 are shown. Of course, other contact plugs PG1, PG2, PG4, PG5, not shown, and Similar contact holes and dummy holes are also formed in the formation region of the dummy plug DP2.

  Next, a conductive film MT1 such as copper, which is a material for forming the contact plugs PG1 to PG5 and the dummy plugs DP1 and DP2, is formed by sputtering or the like in the dummy hole DH1 and the contact hole VH1, and other contact holes and dummy holes. Embed (FIG. 8).

  Subsequently, CMP is performed from the surface of the conductive film MT1, and the upper conductive film MT1 is removed from the surface of the insulating film 2b to form contact plugs PG1 to PG5 and dummy plugs DP1 and DP2.

  At this time, immediately after the conductive film MT1 on the insulating film 2b is removed by CMP, CMP is also performed on the surface of the insulating film 2b constituting the interlayer insulating film in both the first and second regions AR1 and AR2. Will be given. By performing CMP also on the surface of the insulating film 2b, erosion ER occurs in the portion of the first region AR1 where the contact holes are formed relatively densely (FIG. 9).

  Here, erosion refers to a phenomenon in which the interlayer insulating film is removed by CMP in a dense region of wiring and plug patterns as shown in FIG. 7 of Patent Document 3, for example. In the present invention, by utilizing this erosion phenomenon, the interlayer insulating film is thinned in the first region AR1 (see the thickness D in FIG. 2) and the interlayer insulating film is formed in the second region AR2 by a single CMP process. It is formed thick (see thickness C in FIG. 2).

  Next, an insulating film 2c such as a silicon oxide film is formed on the insulating film 2b by a CVD method or the like (FIG. 10), and a part of the surface of the insulating film 2b is exposed in each of the first and second regions AR1 and AR2. As described above, patterning PT1 to PT3 for forming the wirings L1 to L3 is performed on the insulating film 2c by the photolithography technique and the etching technique. Then, a conductive film MT2 such as copper is formed by sputtering or the like so as to cover part of the surfaces of the insulating film 2c and the exposed insulating film 2b (FIG. 11). Thereafter, CMP is performed on the conductive film MT2. Thereby, the wirings L1 to L3 are formed on the surface of the insulating film 2b in the first and second regions AR1 and AR2, respectively.

  According to the method of manufacturing a semiconductor device according to the present embodiment, contact holes (for example, dummy holes DH1 for forming dummy plug DP1) are formed relatively densely in first region AR1 of insulating film 2b constituting the interlayer insulating film. In the second region AR2, contact holes (for example, contact holes VH1 for forming contact plugs PG3) are formed relatively sparsely, and the surface of the insulating film 2b is subjected to CMP, whereby the first region AR1 is formed. Erosion ER is generated in the contact hole forming portion.

  Therefore, the insulating film 2b constituting the interlayer insulating film can be formed thin in the first region AR1 and the insulating film 2b formed thick in the second region AR2 by a single CMP process. As a result, a semiconductor device in which a certain level of interlayer insulating film sandwiched between multilayer wirings has thick and thin portions can be easily manufactured.

  Further, according to the method of manufacturing a semiconductor device according to the present embodiment, the wirings L1 to L3 are formed in the insulating film 2c so that the surfaces of the insulating film 2b are partially exposed in the first and second regions AR1 and AR2, respectively. Wiring L1 to L3 is formed by performing patterning and performing CMP on the conductive film MT2 covering a part of the surface of the insulating film 2c and the exposed insulating film 2b. Therefore, the thick wiring L3 can be formed in the first region AR1 having a thin interlayer insulating film, and the thin wirings L1 and L2 can be formed in the second region AR2 having a thick interlayer insulating film. As a result, the low resistance wiring L3 can be formed in the first region AR1.

  As shown in FIG. 12 instead of the sectional view of FIG. 4, an n-th layer wiring L9 is provided below the dummy plug DP1, and the wiring L3 and the n-th layer wiring L9 are connected by the dummy plug DP1. Also good.

<Embodiment 2>
The present embodiment is a modification of the method for manufacturing the semiconductor device according to the first embodiment. In at least a part of the first region AR1 in the first embodiment, the insulation functions as an etching stopper film when forming a contact hole. A film is formed.

  FIG. 13 is a top view of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present embodiment. 14 and 15 are cross-sectional views taken along section lines XIV-XIV and XV-XV in FIG. 13, respectively.

  As shown in FIGS. 13 to 15, in this semiconductor device, as in the case of the first embodiment, n-layer wirings L5 to L8 and silicon oxide are formed on lower structure 1 including a semiconductor substrate such as a silicon substrate. An interlayer insulating film 2 such as a film is formed.

  In the first region AR1 of the interlayer insulating film 2, the contact plug PG9, the contact plug PG6 connected to the nth layer wirings L5 and L6, and the dummy plug DP3 not connected to the nth layer wirings L5 and L6 are relatively dense. Is formed. The contact plugs PG6 and PG9 and the dummy plug DP3 are all connected to a thick and thick wiring L3 formed on the surface of the interlayer insulating film 2.

  On the other hand, in the second region AR2 of the interlayer insulating film 2, contact plugs PG7 connected to the nth layer wiring L8 and contact plugs PG8 connected to the nth layer wiring L7 are formed relatively sparsely. The contact plug PG7 is connected to a thin and thin wiring L2 formed on the surface of the interlayer insulating film 2, and the contact plug PG8 is connected to a thin and thin wiring L1 formed on the surface of the interlayer insulating film 2. Note that the wirings L1 to L3 function as the (n + 1) th layer wiring.

  16 to 28 are views for explaining the manufacturing process of the semiconductor device shown in FIGS. 13 to 15 by taking the cross-sectional structure of FIG. 15 as an example.

  First, an insulating film 2a such as a silicon oxide film constituting the interlayer insulating film 2 is formed on the lower structure 1 by a CVD method or the like. L8 patterning is performed. Thereafter, a conductive film (not shown) such as copper is formed so as to embed the patterning portion, and CMP is performed on the conductive film to form n-th layer wirings L5 to L8 (FIG. 16).

  Next, an insulating film 2b such as a silicon oxide film constituting the interlayer insulating film 2 is formed by a CVD method or the like so as to cover the nth layer wirings L5 to L8 and the insulating film 2a (FIG. 17).

  Next, an insulating film 30a such as a silicon nitride film that functions as an etching stopper film when the contact hole is formed is formed on the insulating film 2b by a CVD method or the like (FIG. 18). Then, the insulating film 30a is patterned by the photolithography technique and the etching technique, and the insulating film 30 is formed only in the dummy plug DP3 formation region in the first region AR1 (FIG. 19).

  Subsequently, an insulating film 2c such as a silicon oxide film is formed on the insulating films 2b and 30 (FIG. 20). The insulating films 2b and 2c constitute the interlayer insulating film 2.

  Then, a dummy hole DH2 for forming the dummy plug DP3 in the insulating film 2c in the first region AR1 is formed using the insulating film 30 as an etching stopper film by the photolithography technique and the etching technique (FIG. 21). At this time, due to the presence of the insulating film 30, the etching of the dummy hole DH2 does not reach the insulating film 2b.

  Next, a conductive film MT3 such as copper, which is a material for forming the dummy plug DP3, is buried in the dummy hole DH2 by sputtering or the like (FIG. 22).

  Subsequently, CMP is performed from the surface of the conductive film MT3, and the upper conductive film MT3 is removed from the surface of the insulating film 2c to form a dummy plug DP3.

  At this time, immediately after the conductive film MT3 on the insulating film 2c is removed by CMP, CMP is also applied to the surface of the insulating film 2c constituting the interlayer insulating film in both the first and second regions AR1 and AR2. Will be given. By performing CMP also on the surface of the insulating film 2c, erosion ER occurs in the portion of the first region AR1 where the contact holes are formed relatively densely (FIG. 23).

  Next, an insulating film 2d such as a silicon nitride film that functions as an etching stopper film at the time of forming the wiring pattern is formed on the insulating film 2c and the dummy plug DP3 by a CVD method or the like (FIG. 24), and silicon is formed on the insulating film 2d. An insulating film 2e such as an oxide film is formed by a CVD method or the like (FIG. 25).

  Subsequently, contact holes for forming the contact plugs PG6 and PG9 are formed relatively densely in the first region AR1 of the insulating films 2b to 2e by using a photolithography technique and an etching technique, while the insulating film 2b In the second region AR2 of ˜2e, contact holes for forming the contact plugs PG7 and PG8 are formed relatively sparsely (FIG. 26).

  In FIG. 26, only the contact hole VH2 for forming the contact plug PG8 is shown. Of course, similar contact holes are also formed in regions where other contact plugs PG6, PG7, and PG9 (not shown) are formed. .

  Next, wiring is performed on the insulating film 2e while using the insulating film 2d as an etching stopper film by a photolithography technique and an etching technique so that a part of the surface of the insulating film 2c is exposed in each of the first and second regions AR1, AR2. Patterning PT1 to PT3 for forming L1 to L3 is performed (FIG. 27). Then, a conductive film MT4 such as copper is formed by sputtering or the like so as to cover part of the surfaces of the insulating film 2e and the exposed insulating film 2c (FIG. 28). Thereafter, CMP is performed on the conductive film MT4. Thereby, in the first and second regions AR1 and AR2, wirings L1 to L3 are formed on the surface of the insulating film 2c, respectively.

  According to the method of manufacturing a semiconductor device according to the present embodiment, contact holes such as dummy holes DH2 are formed in the insulating film 2c while using the insulating film 30 as an etching stopper film in at least a part of the first region AR1. To do. Therefore, when these contact holes are formed, the insulating film 30 becomes the bottom of the contact hole, and the contact hole does not reach below the insulating film 30. As a result, a portion below the insulating film 30 can be freely used as a region for forming the wirings L5 and L6 insulated from the contact holes.

  As shown in FIG. 29 in place of the top view of FIG. 13, not only the formation region of the dummy plug DP3 but also the formation region of the contact plugs PG6 and PG9, the insulating film 31 as an etching stopper film of the contact hole May be formed.

  In this case, as shown in FIG. 30 (a cross-sectional view taken along the cutting line XXX-XXX in FIG. 29), for the contact plugs PG6 and PG9 that need to be conducted to the lower part of the insulating film 31, the insulating film 31 is formed. It is formed through. In order to form in this way, it is only necessary not to provide etch selectivity between the insulating film 31 and the other insulating films 2b to 2e in the process from FIG. 25 to FIG. Note that the cross-sectional view taken along the cutting line XV-XV in FIG. 29 is the same as FIG.

<Embodiment 3>
The present embodiment is a modification of the method for manufacturing a semiconductor device according to the second embodiment, and the insulating film 30 that also functions as a polishing stopper film is exposed in the CMP for generating erosion in the second embodiment. This is what you do until you do.

  FIG. 31 is a top view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment. 32 is a cross-sectional view taken along a cutting line XXXII-XXXII in FIG. Note that a cross-sectional view taken along section line XIV-XIV in FIG. 31 is the same as FIG.

  As shown in FIGS. 31 and 32, in this semiconductor device, as in the case of the second embodiment, n-layer wirings L5 to L8 and silicon oxide are formed on lower structure 1 including a semiconductor substrate such as a silicon substrate. An interlayer insulating film 2 such as a film is formed.

  In the first region AR1 of the interlayer insulating film 2, the contact plug PG9 and the contact plug PG6 connected to the n-th layer wirings L5 and L6 are formed. Unlike the second embodiment, the dummy plug DP3 Is not formed. This is due to the disappearance of the dummy holes, as will be described later.

  The wiring L3 is formed in contact with the insulating film 30. The other structures are the same as those in the second embodiment, and thus description thereof is omitted.

  FIGS. 33 and 34 are diagrams illustrating a manufacturing process of the semiconductor device shown in FIGS. 31 and 32 by taking the cross-sectional structure of FIG. 32 as an example.

  First, similarly to the second embodiment, the steps of FIGS. 16 to 21 are performed. Then, CMP is performed on the surface of the insulating film 2c while using the insulating film 30 as a polishing stopper film without embedding the conductive film in the formation portion of the dummy hole DH2. By subjecting the surface of the insulating film 2c to CMP, erosion ER occurs in the portion of the first region AR1 where the contact holes are formed relatively densely (FIG. 33). At this time, CMP is performed until the insulating film 30 is exposed, and the dummy hole DH2 is eliminated.

  Next, on the insulating film 2c and the exposed insulating film 30, an insulating film 2d such as a silicon nitride film that functions as an etching stopper film when forming a wiring pattern is formed by a CVD method or the like (FIG. 34). Thereafter, the semiconductor device shown in FIGS. 31 and 32 can be manufactured by performing the same steps as those in FIGS.

  According to the method for manufacturing a semiconductor device according to the present embodiment, CMP for generating erosion is performed until the insulating film 30 that also functions as a polishing stopper film is exposed. Therefore, instead of the dummy holes DH2 disappearing on the insulating film 30, the insulating film 30 can prevent excessive polishing. Thereby, the thickness of the wiring L3 is equal to the depth to the insulating film 30 in each part of the first region AR1, and the resistance characteristics of the wiring L3 in the first region AR1 can be made uniform.

<Embodiment 4>
The present embodiment is a modification of the semiconductor device manufacturing method according to the first embodiment, and the semiconductor device manufacturing method according to the first embodiment is applied to the formation of an MRAM (Magnetic Random Access Memory). It is.

  The MRAM is an MTJ (Magneto-Tunneling Junction) element including two magnetic layers (free layer and pinned layer) and a tunnel insulating layer sandwiched between both magnetic layers as described in Non-Patent Documents 1 and 2. Refers to a storage device having a storage element as a storage element. In the MRAM, a bit line is provided above the MTJ element, and a digit line is provided below the MTJ element, and the magnetic field generated by the bit line and the digit line changes the magnetic characteristics of the MTJ element. The bit lines and digit lines are arranged orthogonally.

  FIG. 35 is a cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment.

  As shown in FIG. 35, in this semiconductor device, on the lower structure 10 including a semiconductor substrate such as a silicon substrate, the digit line DL1, the insulating film 20a such as a silicon nitride film, the insulating film 20b such as a silicon oxide film, silicon An insulating film 20c such as a nitride film and an insulating film 20d such as a silicon oxide film are formed. Here, the lower structure 10 refers to a structure from the semiconductor substrate to the lower part of the digit line DL1. The insulating films 20a to 20d constitute an interlayer insulating film.

  In the first region ARa of the insulating film 20b, the MTJ element T1 is formed on the insulating film 20a. The MTJ element T1 includes a free layer FR, a tunnel insulating layer TN, and a pinned layer PN. Further, a strap layer SP serving as an extraction electrode is provided under the pinned layer PN, and the hard mask HM used when forming the MTJ element T1 remains on the free layer FR. The digit line DL1, the MTJ element T1, and the strap layer SP are insulated by the insulating film 20a.

  An insulating film 20b is formed so as to cover the MTJ element T1 and the insulating film 20a, and a contact plug PG11 connected to the MTJ element T1 via the hard mask HM is relatively formed in the first region ARa of the insulating film 20b. It is densely formed. Each contact plug PG11 is individually connected to a corresponding thick bit line BL1 formed on the surface of the insulating film 20b. The bit line BL1 extends in a direction perpendicular to the paper surface, and its thickness F is, for example, 400 nm.

  On the other hand, in the second region ARb of the insulating film 20b, contact plugs PG10 penetrating the insulating film 20a and connected to the digit line DL1 are formed relatively sparsely. The contact plug PG10 is connected to a thin wiring L10 formed on the surface of the insulating film 20b. The wiring L10 extends in a direction perpendicular to the paper surface, and the thickness E thereof is, for example, 300 nm.

  The structure of FIG. 35 is also manufactured by the same process as in the first embodiment. That is, the digit line DL1, the insulating film 20a, the strap layer SP, the MTJ element T1, the hard mask HM, and the like are formed on the lower structure 10 by using a film forming technique such as a CVD method or a sputtering method, a photolithography technique, and an etching technique. Then, the insulating film 20b is formed.

  Subsequently, a contact hole for forming the contact plug PG11 is formed relatively densely in the first region ARa of the insulating film 20b by using a photolithography technique and an etching technique, and copper is formed in the contact hole by sputtering or the like. A conductive film such as is embedded. Then, the conductive film on the insulating film 20b is removed by CMP, and the surface of the insulating film 20b is also subjected to CMP to generate erosion. Thus, the interlayer insulating film is formed thin in the first region ARa (see thickness D in FIG. 35), and the interlayer insulating film is formed thick in the second region ARb (see thickness C in FIG. 35).

  Next, the contact plug PG10 is formed also in the second region AR2, and the insulating film 20c and the insulating film 20d are formed on the insulating film 20b. Subsequently, patterning for forming the wiring L10 and the bit line BL1 is performed on both insulating films by a photolithography technique and an etching technique. Then, a conductive film such as copper is formed by sputtering or the like so as to cover part of the surfaces of the insulating film 20d and the exposed insulating film 20b, and CMP is performed on the conductive film. Thereby, the wiring L10 and the bit line BL1 are formed on the surface of the insulating film 20b in the first and second regions ARa and ARb, respectively.

  As shown in FIG. 36, a structure in which the contact plug PG11 is eliminated and the bit line BL1 is directly connected to the MTJ element T1 via the hard mask HM may be employed. In this case, CMP may be performed without embedding the conductive film after the contact hole is formed, and erosion may be caused until the contact hole disappears.

  In addition, as a material for forming the wiring L10 and the bit line BL1, a material that can be easily patterned by etching, such as aluminum, may be employed. In this case, since the patterning can be performed not by the CMP method but by the photolithography technique and the etching technique, the structure shown in FIG. 37 is obtained. If erosion is caused until the contact hole disappears, the structure without the contact plug PG11 is obtained as shown in FIG.

  Also, the structure of FIG. 39 is provided with a polishing stopper film when erosion occurs. In the structure of FIG. 39, in addition to the structure of FIG. 35, an insulating film 20e that functions as a polishing stopper film at the time of CMP is formed so as to cover the insulating film 20a and the MTJ element T1.

  40 to 53 are views for explaining a manufacturing process of the semiconductor device shown in FIG.

  First, an insulating film (not shown) such as a silicon oxide film (not shown) is formed on the lower structure 10 by a CVD method or the like, and the digit wiring DL1 is patterned on the interlayer insulating film by using a photolithography technique and an etching technique. I do. Thereafter, a conductive film (not shown) such as copper is formed so as to fill the patterning portion, and the digit line DL1 is formed by performing CMP on the conductive film. Then, an insulating film 20a is formed by CVD or the like so as to cover the digit line DL1 and the insulating film (FIG. 40).

  Next, after forming a conductive film such as tantalum, for example, a strap layer SP is formed using a photolithography technique and an etching technique (FIG. 41). Then, film formation is performed in the order of pin layer material (for example, cobalt or nickel alloy), tunnel insulating layer material (for example, silicon oxide film), free layer material (for example, cobalt or nickel alloy), and hard mask material (for example, tantalum film). And patterning the hard mask material using a photolithography technique and an etching technique to form a hard mask HM.

  Etching is then performed using the hard mask HM as a mask, and the pinned layer PN, tunnel insulating layer TN, and free layer FR are patterned to form the MTJ element T1 (FIG. 42).

  Next, an insulating film 20e such as a silicon nitride film that functions as a CMP stopper film when the contact hole is formed is formed on the insulating film 2a and the MTJ element T1 by a CVD method or the like (FIG. 43). Then, an insulating film 20b is formed on the insulating film 20e by a CVD method or the like (FIG. 44).

  Then, by the photolithography technique and the etching technique, in the first region ARa, the contact hole VH3 for forming the contact plug PG11 is relatively densely formed in the insulating film 20b and the insulating film 20e via the hard mask HM. It forms so that it may connect with T1 (FIG. 45).

  Next, a conductive film MT5 such as tantalum used as a material for forming the contact plug PG11 is buried in the contact hole VH3 by sputtering or the like (FIG. 46).

  Subsequently, CMP is performed from the surface of the conductive film MT5 to remove the upper conductive film MT5 from the surface of the insulating film 20b, thereby forming a contact plug PG11.

  At this time, immediately after the conductive film MT5 on the insulating film 20b is removed by CMP, CMP is also performed on the surface of the insulating film 20b constituting the interlayer insulating film in both the first and second regions ARa and ARb. Will be given. By performing CMP on the surface of the insulating film 20b as well, erosion ER occurs in the portion of the first region ARa where the contact holes are formed relatively densely (FIG. 47).

  Since the insulating film 20e functioning as a polishing stopper film at the time of CMP is formed on the insulating film 20a and the MTJ element, the MTJ element T1 is polished even when the insulating film 20b is excessively polished. Can be prevented.

  Next, an insulating film 20c such as a silicon nitride film that functions as an etching stopper film when the wiring pattern is formed is formed on the insulating film 20b and the contact plug PG11 by a CVD method or the like (FIG. 48), and silicon is formed on the insulating film 20c. An insulating film 20d such as an oxide film is formed by a CVD method or the like (FIG. 49).

  Subsequently, contact holes VH4a for forming the contact plugs PG10 are formed relatively sparsely in the second regions ARb of the insulating films 20b to 20d using a photolithography technique and an etching technique (FIG. 50).

  In FIG. 50, only a contact hole VH4a for forming contact plug PG11 is shown because only one cross section is shown. Of course, similar contact holes are also formed in other contact plug formation regions (not shown). Is done.

  Next, in the first and second regions ARa and ARb, patterning PT5a and PT4a for forming the wiring L10 and the bit line BL1 on the insulating film 20d while using the insulating film 20c as an etching stopper film by photolithography technique and etching technique, respectively. (FIG. 51). Further, with the opposite etch selectivity between the insulating film 20d and the insulating film 20c, the insulating film 20c is subjected to the same patterning PT5b and PT4b as the patterning PT5a and PT4a by the etching technique (FIG. 52). Thereby, part of the surface of the insulating film 20b is exposed in each of the first and second regions ARa and ARb.

  At this time, the insulating films 20e and 20a, which are silicon nitride films, are also etched, and the bottom of the contact hole VH4a in the second region ARb is connected to the digit line DL1 to form the contact hole VH4b.

  Then, a conductive film MT6 such as copper is formed by sputtering or the like so as to cover part of the surfaces of the insulating film 20d and the exposed insulating film 20b (FIG. 53). Thereafter, CMP is performed on the conductive film MT6. Thus, the bit line BL1 and the wiring L10 are formed on the surface of the insulating film 20b in the first and second regions ARa and ARb, respectively.

  According to the method of manufacturing a semiconductor device according to the present embodiment, digit line DL1, MTJ element T1, and bit line BL1 are formed. Therefore, the MRAM can be formed in the first region ARa. Since the interlayer insulating film is thin in the first region ARa, the MTJ element T1 can be formed close to both the digit line DL1 and the bit line BL1. As a result, it is possible to easily manufacture an MRAM capable of generating a high-strength magnetic field even when the amount of current flowing through the digit line DL1 and the bit line BL1 is small. In addition, since the interlayer insulating film is thick in the second region ARb, a logic circuit or the like for controlling the MRAM can be formed. As a result, a system LSI (Large Scale Integration) in which a memory circuit and a logic circuit are mixed can be easily manufactured.

  In addition, the insulating films 20d and 20c are patterned so that the surfaces of the insulating films 20b are partially exposed in the first and second regions ARa and ARb, respectively, so as to cover the insulating films 20d and a part of the exposed surfaces of the insulating films 20b. By applying CMP to the conductive film MT6, the bit line BL1 and the wiring L10 are formed. Therefore, a thick wiring can be formed in the first region ARa with a thin interlayer insulating film, and a thin wiring can be formed in the second region ARb with a thick interlayer insulating film. As a result, a low resistance wiring can be formed in the first region ARa. Since the wiring in the first region functions as the bit line BL1, it is possible to reduce power consumption in the bit line BL1.

<Embodiment 5>
The present embodiment is a modification of the method for manufacturing a semiconductor device according to the fourth embodiment, and the insulating film 20e that functions as a polishing stopper film is exposed by CMP for generating erosion in the fourth embodiment. It is something to be done.

  FIG. 54 is a cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment.

  As shown in FIG. 54, in this semiconductor device, as in the case of the fourth embodiment, digit line DL1, insulating film 20a, strap layer SP, MTJ are formed on lower structure 10 including a semiconductor substrate such as a silicon substrate. The element T1, the hard mask HM, the insulating films 20e and 20b to 20d, the contact plugs PG10 and PG11, the wiring L10, and the bit line BL1 are formed.

  However, unlike the case of the fourth embodiment, on the MTJ element T1, the bit line BL1 is formed in contact with the insulating film 20e without the insulating film 20b interposed therebetween. As described later, this is due to the disappearance of the contact hole on the insulating film 20e.

  55 to 57 are views for explaining a manufacturing process of the semiconductor device shown in FIG.

  First, as in the case of the fourth embodiment, the steps of FIGS. 40 to 45 are performed. Then, CMP is performed on the surface of the insulating film 20b while using the insulating film 20e as a polishing stopper film without embedding the conductive film in the formation portion of the contact hole VH3. By subjecting the surface of the insulating film 20b to CMP, erosion ER occurs in the portion of the first region ARa where the contact holes are formed relatively densely (FIG. 55). At this time, CMP is performed until the insulating film 20e is exposed, and the contact hole VH3 on the insulating film 20e is eliminated.

  Then, a conductive film (not shown) such as tantalum is formed on the insulating film 20b and the exposed insulating film 20e by a sputtering method or the like, and contact holes left in the insulating film 20e are formed by performing CMP on the conductive film. A contact plug PG11 is formed in VH3 (FIG. 56).

  Next, on the insulating film 20b and the exposed insulating film 20e, an insulating film 20c such as a silicon nitride film that functions as an etching stopper film when forming a wiring pattern is formed by a CVD method or the like (FIG. 57). Thereafter, the semiconductor device shown in FIG. 54 can be manufactured by performing the same steps as those in FIGS.

  According to the method of manufacturing a semiconductor device according to the present embodiment, CMP for generating erosion is performed until the insulating film 20e functioning as a polishing stopper film is exposed. Therefore, instead of the contact hole VH3 disappearing on the insulating film 20e, excessive polishing can be prevented by the insulating film 20e. Thereby, the thickness of the bit line BL1 is equal to the depth to the insulating film 20e in each part of the first region ARa, and the resistance characteristics of the bit line BL1 in the first region ARa can be made uniform.

<Modification>
In the fourth and fifth embodiments, it is assumed that the shape of the contact plug PG11 that connects the bit line BL1 and the MTJ element T1 is cylindrical as in the first to third embodiments. FIG. 58 is an enlarged view showing the structure around the contact plug PG11 in the fourth embodiment together with numerical examples of specific dimensions.

  Here, sputter etching is employed in the step of forming the contact hole VH3 in FIG. 45, and for example, the sputter angle can be shifted from the vertical direction of the surface of the semiconductor substrate. In this way, the side wall of the contact hole VH3 can be tapered, and the shape of the contact plug PG11a as shown in FIG. 59 can be realized by embedding the conductive film in the contact hole VH3. FIG. 59 also shows numerical examples of specific dimensions of the structure around the contact plug PG11a.

  Furthermore, if the sputtering angle to the insulating film 20e and the sputtering angle to the insulating film 20b are made different, it is possible to realize the shape of the contact plug PG11b having a two-step taper as shown in FIG. If sputter etching is performed with the sputter angle shifted only on the insulating film 20e, the shape of the contact plug PG11c having a taper only at the lower stage as shown in FIG. 61 can be realized.

  In addition to this, if isotropic etching such as wet etching is employed in the step of forming the contact hole VH3 in FIG. 45, the top edge of the contact hole VH3 can be rounded. If the conductive film is embedded, the shape of the contact plug PG11d as shown in FIG. 62 can also be realized.

  Further, by adjusting the etch selectivity of the isotropic etching between the insulating films 20b and 20e, the etching only to the insulating film 20b is increased, and the diameter of the insulating film 20b as shown in FIG. 63 is increased. A shape of the contact plug PG11e wider than the diameter of the insulating film 20e can also be realized.

  In addition, isotropic etching of the insulating film 20e is also caused to some extent so that the lower portion of the side wall of the contact hole VH3 has a taper and the top periphery of the contact hole VH3 is rounded, as shown in FIG. The shape of the contact plug PG11f can also be realized.

  Further, FIG. 65 (a cross-sectional view in the extending direction of the bit line BL1 in FIG. 39) and FIG. 66 (an enlarged view of the structure around the contact plug PG11g in FIG. 65 together with numerical examples of specific dimensions) As shown in FIG. 5B, by adjusting the etching time for the insulating film 20b, the contact plugs PG11g to the MTJ elements T1 arranged in the direction of the bit line BL1 can be connected to each other at the connection portion CN. . Then, by adjusting the etching time to the insulating film 20b, the etching time to the insulating film 20e, and the etching selectivity between the insulating films 20b and 20e, each of FIGS. 67, 68, and 69 is shown. It is possible to realize various modified shapes of FIG. 66 such as the contact plugs PG11h, PG11i, and PG11j shown in FIG.

  The above also applies to the step of forming the contact hole VH3 in the fifth embodiment, and the structure in FIG. 70 showing the structure around the contact plug PG11 in the fifth embodiment together with numerical examples of specific dimensions is also expanded. It can be deformed into various shapes as shown in FIGS.

  Further, the same deformation can be performed on the shape of the contact plug PG11 in FIGS. 35 and 37 that does not have the insulating film 20e.

  As described above, if the contact hole VH3 is formed while the side wall of the contact hole VH3 is tapered and / or the top periphery of the contact hole VH3 is rounded, and the conductive film is embedded in the contact hole VH3, It is difficult for the conductive film to be embedded in the contact hole VH3, and variation in the resistance value of the contact plug PG11 of the MTJ element T1 is reduced.

4 is a top view of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment. FIG. It is sectional drawing in the cutting line II-II in FIG. It is sectional drawing in the cutting line III-III in FIG. FIG. 4 is a cross-sectional view taken along a cutting line IV-IV in FIG. 1. 6 is a diagram showing a step of the method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a step of the method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a step of the method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a step of the method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a step of the method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a step of the method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a step of the method of manufacturing a semiconductor device according to the first embodiment. FIG. FIG. 4 is another cross-sectional view taken along the cutting line IV-IV in FIG. 1. FIG. 6 is a top view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a second embodiment. It is sectional drawing in the cutting line XIV-XIV in FIG. It is sectional drawing in the cutting line XV-XV in FIG. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a diagram showing a step of the method of manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a top view of another semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment. FIG. 30 is a cross-sectional view taken along a cutting line XXX-XXX in FIG. 29. FIG. 10 is a top view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a third embodiment. FIG. 32 is a cross-sectional view taken along section line XXXII-XXXII in FIG. 31. FIG. 10 is a diagram showing a step of a method of manufacturing a semiconductor device according to a third embodiment. FIG. 10 is a diagram showing a step of a method of manufacturing a semiconductor device according to a third embodiment. FIG. 10 is a cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the fourth embodiment. It is sectional drawing of the other semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on Embodiment 4. FIG. It is sectional drawing of the other semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on Embodiment 4. FIG. It is sectional drawing of the other semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on Embodiment 4. FIG. It is sectional drawing of the other semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on Embodiment 4. FIG. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to a fourth embodiment. FIG. 10 is a cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a step of a method of manufacturing a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a step of a method of manufacturing a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a step of a method of manufacturing a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram showing a peripheral structure of a contact plug in a semiconductor device according to a fourth embodiment. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 4. FIG. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 4. FIG. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 4. FIG. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 4. FIG. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 4. FIG. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 4. FIG. FIG. 40 is a cross-sectional view of the bit line in FIG. 39 in the extending direction. FIG. 66 is an enlarged view of a structure around a contact plug in FIG. 65. FIG. 67 is a diagram showing a modification of the structure of FIG. 66. FIG. 67 is a diagram showing another modification of the structure in FIG. 66. FIG. 67 is a diagram showing another modification of the structure in FIG. 66. FIG. 10 is a diagram showing a peripheral structure of a contact plug in a semiconductor device according to a fifth embodiment. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 5. FIG. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 5. FIG. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 5. FIG. It is a figure which shows the other shape of the contact plug in the semiconductor device which concerns on Embodiment 5. FIG.

Explanation of symbols

1,10 substructure, 2,20a-20e interlayer insulation film, PG1-PG11 contact plug, DP1-DP3 dummy plug, VH1-VH3, VH4b contact hole, DH1-DH2 dummy hole, L1-L10 wiring, DL1 digit line, BL1 bit line, T1 MTJ element.

Claims (5)

Preparing a semiconductor substrate having a first region and a second region;
Forming a plurality of MTJ (Magneto-Tunneling Junction) elements above the semiconductor substrate in the first region;
Forming an insulating film covering the plurality of MTJ elements and having an upper surface;
The insulating film penetrate and a step of relatively densely formed a plurality of contact holes reaching each one of a plurality of MTJ elements,
Forming a conductive film in the contact hole and on the insulating film;
By generating erosion and facilities a CMP (Chemical Mechanical Polishing) to the conductive layer, with embedding the conductive film in the contact hole, the first region than the upper surface of the insulating film on the second region A step of lowering the upper surface of the upper insulating film;
Forming a wiring electrically connected to the conductive film embedded in the contact hole above the insulating film;
A method for manufacturing a semiconductor device comprising: Preparing a semiconductor substrate having a first region and a second region;
Forming a plurality of MTJ (Magneto-Tunneling Junction) elements above the semiconductor substrate in the first region;
Forming a first insulating film covering the plurality of MTJ elements and having an upper surface;
It penetrates the first insulating film, a step of relatively densely formed a plurality of contact holes reaching each one of a plurality of MTJ elements,
Forming a conductive film in the contact hole and on the first insulating film;
By generating erosion and facilities a CMP (Chemical Mechanical Polishing) to the conductive layer, with embedding the conductive film in the contact hole, the second from the upper surface of the first insulating film on the second region A step of lowering an upper surface of the first insulating film on one region;
Forming a second insulating film on the first insulating film after the CMP step;
Forming a third insulating film on the second insulating film;
Using said second insulating film as an etching stopper film, after etching the third insulating film, a step of etching the second insulating film, forming a pattern reaching said conductive layer,
Forming a wiring electrically connected to the conductive film embedded in the contact hole in the pattern;
A method for manufacturing a semiconductor device comprising: The method of manufacturing a semiconductor device according to claim 1, wherein the wiring in the first region is a bit line. 4. The method of manufacturing a semiconductor device according to claim 3, wherein when viewed in a cross-sectional view, the bit line is thicker than the wiring in the second region . The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a digit line below the MTJ before forming the MTJ.

Images