JP4432902B2 - Decoding apparatus and method, program, recording / reproducing apparatus and method, and reproducing apparatus and method - Google Patents

Description

The present invention is a decoding apparatus and method, a program, a recording and reproducing apparatus and method, and relates to reproducing apparatus and method, in particular, suitable for use when decoding the encoded data encoded by the ring R onto linear code, decoding The present invention relates to an apparatus and method , a program, a recording / reproducing apparatus and method, and a reproducing apparatus and method.

  In recent years, for example, the field of communication such as mobile communication and deep space communication and the field of broadcasting such as terrestrial or satellite digital broadcasting have been remarkably advanced. Research on coding theory is also actively conducted.

  As the theoretical limit of code performance, the Shannon limit given by the so-called Shannon (C. E. Shannon) channel coding theorem is known. Research on code theory is being conducted with the goal of developing codes that exhibit performance close to the Shannon limit. In recent years, as a coding method showing performance close to the Shannon limit, for example, so-called turbo codes such as parallel concatenated convolutional codes (PCCC (Parallel Concatenated Convolutional Codes)) and tandem concatenated convolutional codes (SCCC) A technique called Turbo coding has been developed. While these turbo codes are being developed, low density parity check codes (hereinafter referred to as LDPC codes), which is an encoding method that has been known for a long time, are attracting attention.

  The LDPC code was first proposed in "RG Gallager," Low Density Parity Check Codes ", Cambridge, Massachusetts: MIT Press, 1963 by RG Gallager, and then" DJC MacKay, "Good error correcting codes based on very sparse matrices ", Submitted to IEEE Trans. Inf. Theory, IT-45, pp. 399-431, 1999" and "MG Luby, M. Mitzenmacher, MA Shokrollahi and DA Spielman," Analysis of low density codes and improved designs using irregular graphs ", in Proceedings of ACM Symposium on Theory of Computing, pp. 249-258, 1998".

  Recent studies have shown that LDPC codes can achieve performance close to the Shannon limit as the code length is increased, similar to turbo codes and the like. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed. An advantage is that it hardly occurs.

  Hereinafter, such an LDPC code will be specifically described. Note that the LDPC code is a linear code and does not necessarily need to be binary, but will be described here as being binary.

The LDPC code is characterized by the fact that the parity check matrix that defines the LDPC code is sparse. Here, the sparse matrix is configured so that the number of "1" of the matrix components is very small. If the sparse check matrix is represented by H, as such a check matrix, for example, As shown in H _LDPC shown in FIG. 1, the Hamming weight (number of “1” s) of each row is “2” and the Hamming weight of each column is “4”.

  Thus, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is constant is referred to as a regular LDPC code. On the other hand, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is not constant is referred to as an irregular LDPC code.

Such an LDPC code encoding is realized by generating a generator matrix G based on the check matrix H and generating a codeword by multiplying the binary information message by the generator matrix G. . Specifically, the encoding device which performs encoding by LDPC codes, first, between the transposed matrix H ^T of the parity check matrix H, calculates a generator matrix G which formula GH ^T = 0 is established. Here, when the generator matrix G is a k × n matrix, the encoding device multiplies the generator matrix G by an information message (vector u) consisting of k bits, and a codeword c consisting of n bits. (= UG) is generated. The code word generated by this encoding device is mapped and transmitted such that the sign bit with the value “0” is “+1” and the sign bit with the value “1” is “1”. Is received on the receiving side via the communication path.

  On the other hand, decoding of an LDPC code is an algorithm proposed by Gallager called probabilistic decoding (Probabilistic Decoding), which is a variable node (also called a message node) and a check node (check node). ) And a message passing algorithm based on belief propagation on a so-called Tanner graph. Here, hereinafter, the variable node and the check node are also simply referred to as nodes as appropriate.

For example, the parity check matrix H _LDPC shown in FIG. 1 is represented by a Tanner graph as shown in FIG. In the Tanner graph of FIG. 2, each column of the parity check matrix H _LDPC of FIG. 1 is a variable node, each row is a check node, and an element of i rows and j columns with a parity check matrix H _LDPC value of “1” is The jth variable node and the ith check node are connected as edges.

However, in probabilistic decoding, since the message passed between each node is a real value, in order to solve it analytically, it is necessary to track the probability distribution itself of messages that take consecutive values. It will require analysis with difficulty. Therefore, Gallager has proposed algorithm A or algorithm B as a decoding algorithm for LDPC codes .

The decoding of the LDPC code is generally performed according to a procedure as shown in FIG. Here, the received value (received code sequence) is U ₀ (u _0i ), the message output from the check node is u _j, and the message output from the variable node is v _i . Further, here, the message is a real value expressing the value of “0” as a so-called log likelihood ratio.

First, in decoding of an LDPC code, as shown in FIG. 3, in step S1, a received value U ₀ (u _0i ) is received, a message u _j is initialized to “0”, and a counter for repetition processing is performed. The variable k taking an integer is initialized to “0”, and the process proceeds to step S2. In step S2, based on the received value U ₀ (u _0i ), the message v _i is obtained by performing the calculation shown in Expression (1) (variable node calculation). Further, based on this message v _i , The message u _j is obtained by performing the calculation (check node calculation) shown in Expression (2).

Here, d _v and d _c in Equation (1) and Equation (2) can be arbitrarily selected to indicate the number of “1” s in the vertical direction (column) and horizontal direction (row) of the parity check matrix H, respectively. For example, in the case of a (3, 6) code, d _v = 3 and d _c = 6.

It should be noted that in the calculation of the expression (1) or (2), a message input from an edge (a line connecting a variable node and a check node) to which a message is to be output is converted into a sum or product operation, respectively. Since it is not used as a parameter, the range of the sum or product operation is 1 to d _v −1 or 1 to d _c −1. In addition, the calculation shown in equation (2) actually creates a table of function R (v ₁ , v ₂ ) shown in equation (3) defined by one output for two inputs v ₁ and v ₂ in advance. This is done by using it continuously (recursively) as shown in equation (4).

  In step S2, the variable k is further incremented by “1”, and the process proceeds to step S3. In step S3, it is determined whether or not the variable k is larger than a predetermined iterative decoding count N. If it is determined in step S3 that the variable k is not greater than N, the process returns to step S2, and the same processing is repeated thereafter.

On the other hand, if it is determined in step S3 that the variable k is larger than N, the process proceeds to step S4, and a message v _i as a decoding result to be finally output is obtained by performing the calculation shown in the equation (5). And the LDPC code decoding process ends.

  Here, unlike the operation of equation (1), the operation of equation (5) is performed using input messages from all branches connected to the variable node.

For example, in the case of a (3, 6) code, such an LDPC code is decoded as shown in FIG. In FIG. 4, the node indicated by “=” (variable node) performs the calculation shown in Expression (1), and the node indicated by “+” (check node) performs the calculation shown in Expression (2). Done. In particular, in algorithm A, the message is binarized, and the exclusive OR operation of d _c −1 input messages is performed at the node indicated by “+”, and the received value is obtained at the node indicated by “=”. For R, if d _v −1 input messages all have different bit values, the sign is inverted and output.

  On the other hand, in recent years, research on an implementation method for decoding an LDPC code is also being conducted. Before describing the mounting method, first, decoding of an LDPC code will be schematically described.

  FIG. 5 is an example of a parity check matrix of a (3, 6) LDPC code (coding rate 1/2, code length 12). The parity check matrix of the LDPC code can be written using a Tanner graph as shown in FIG. Here, in FIG. 6, “+” represents a check node, and “=” represents a variable node. Check nodes and variable nodes correspond to the rows and columns of the parity check matrix, respectively. The connection between the check node and the variable node is an edge and corresponds to “1” of the parity check matrix. That is, when the component in the j-th row and the i-th column of the parity check matrix is 1, the i-th variable node ("=" node) from the top and the j-th check node ("from the top) in FIG. + "Node") are connected by a branch. The branch indicates that the sign bit corresponding to the variable node has a constraint condition corresponding to the check node. FIG. 6 is a Tanner graph of the parity check matrix of FIG.

  As a decoding method of the LDPC code, there is a Sum Product Algorithm (for example, “Masawa Wadayama,“ About Low Density Parity Check Code and Sum-Product Algorithm ”, [online], June 22, 2001). Japan, Okayama Prefectural University, [May 19, 2003 search], Internet, <URL: http: //vega.c.oka-pu.ac.jp/~wadayama/pdf/LDPC.pdf> ") .

  In the thumb product algorithm, the variable node calculation and the check node calculation are repeatedly performed.

In the variable node, as shown in FIG. 7, the calculation of Expression (1) (variable node calculation) is performed. That is, in FIG. 7, the message v _i corresponding to the branch to be calculated is calculated using the messages u ₁ and u ₂ from the remaining branches connected to the variable node and the reception information u _0i . Messages corresponding to other branches are similarly calculated.

  Next, before describing the operation of the check node, the expression (2) is changed into the expression a × b = exp {ln (| a |) + ln (| b |)} × sign (a) × sign (b) Using the relationship, the expression is rewritten as Equation (6). However, sign (x) is 1 when x ≧ 0, and −1 when x <0.

Furthermore, when x ≧ 0 and φ (x) = ln (tanh (x / 2)) is defined, φ ⁻¹ (x) = 2 tanh ⁻¹ (e ^−x ), so equation (6) is It can be written as equation (7).

In the check node, as shown in FIG. 8, the calculation of Expression (7) (check node calculation) is performed. That is, in FIG. 8, the message u _j corresponding to the branch to be calculated is calculated using the messages v ₁ , v ₂ , v ₃ , v ₄ , v ₅ from the remaining branches connected to the check node. The Messages corresponding to other branches are similarly calculated.

The function φ (x) can also be expressed as φ (x) = ln ((e ^x +1) / (e ^x −1)). When x> 0, φ (x) = φ ⁻¹ ( x). When the functions φ (x) and φ ⁻¹ (x) are mounted on hardware, they may be mounted using a LUT (Look Up Table), but both are the same LUT.

  When the thumb product algorithm is implemented in hardware, it is necessary to repeatedly perform the variable node calculation represented by Expression (1) and the check node calculation represented by Expression (7) with an appropriate circuit scale and operating frequency. It is.

  In addition, a calculation method of the calculation cost of an LDPC code using such a sum product algorithm is also widely known (for example, “Matthew C. Davey, David JC MacKay“ Low Density Parity Check Codes over GF (q) ””). reference).

  As described above, in order to obtain good decoding performance by applying the sum product algorithm (SPA), the parity check matrix needs to be low density.

  In addition, a parity check matrix H such as another general linear code, for example, a Reed Solomon code, is represented as shown in FIG. As shown in FIG. 9, the parity check matrix H of the linear code is generally not low density. Such a non-low-density Reed-Solomon code is subjected to decoding (hereinafter referred to as normal decoding) using an Euclid algorithm or the like.

  FIG. 10 is a block diagram illustrating a configuration example of an error correction system that performs error correction using a Reed-Solomon code. The error correction system shown in FIG. 10 is a system used in a digital communication system such as a digital television.

  In the error correction system of FIG. 10, digital information transmitted from the encoding device 10 on the transmission side is supplied to the decoding device 30 on the reception side via a communication path 21 typified by the Internet, for example.

  The encoding apparatus 10 includes a Reed-Solomon encoding unit 11 that encodes digital information for transmission supplied from the outside using a Reed-Solomon code, an interleaver 12 that rearranges the encoded digital information, and a convolutional code. A convolutional encoding unit 13 that performs conversion, and a communication processing unit 14 that communicates with the decoding device 30 via the communication path 21.

  In addition, the decoding device 30 includes a communication processing unit 31 that acquires a transmission word supplied via the communication path 21, a convolutional decoding unit 32 that performs convolution decoding on the acquired transmission word, and the rearranged information in the original order. It includes a deinterleaver 33 to be returned and a Reed-Solomon decoding unit 34 that performs Reed-Solomon decoding (normal decoding).

  Digital information for transmission supplied from the outside of the encoding device 10 is Reed-Solomon encoded by the Reed-Solomon encoding unit 11 of the encoding device 10 and then supplied to the interleaver 12. The interleaver 12 performs information rearrangement (interleaving) in order to spread burst errors mainly occurring in the communication path 21. Since the Reed-Solomon code performs error correction with a plurality of bits as one symbol, the interleaver 12 performs symbol interleaving for spreading burst errors in symbol units.

  The digital information for transmission subjected to the rearrangement is further subjected to a convolutional code in which a code sequence is sequentially determined based on a plurality of information blocks in the convolutional coding unit 13. For example, when the digital information is supplied from the interleaver 12 for each k-bit information block, the convolutional encoding unit 13 having the constraint length K includes not only the information block supplied this time but also the information block supplied in the past. Based on the K information blocks, encoding is performed into an n-bit code block.

  The convolutionally encoded digital information is converted into a transmittable data format in the communication processing unit 14 and supplied to the decoding device 30 via the communication path 21.

  In the decoding device 30, the communication processing unit 31 acquires a transmission word supplied via the wired or wireless communication path 21. The acquired transmission word is subjected to convolution decoding by the convolution decoding unit 32. When the deinterleaver 33 acquires the convolutionally decoded information, the deinterleaver 33 rearranges the information by a method corresponding to the interleaving performed in the interleaver 12 of the encoding device 10, and returns the rearranged information to the original order. Processing (deinterleaving) is performed. The Reed-Solomon decoding unit 34 performs Reed-Solomon decoding processing by normal decoding on the digital information returned to the original order, reproduces the digital information before encoding, and outputs the information to the outside of the decoding device 30. To do.

  As described above, the error correction system of FIG. 10 corrects an error that has occurred during communication so that more accurate communication can be performed.

  FIG. 11 is a block diagram illustrating a configuration example of a recording / reproducing apparatus to which an error correction system that performs error correction using a Reed-Solomon code is applied. The recording / reproducing apparatus shown in FIG. 11 is a digital recording medium recording / reproducing apparatus such as a DVD (Digital Versatile Disc) record player.

  The recording / reproducing apparatus 50 in FIG. 11 encodes digital information supplied from the outside in the encoding processing unit 60 and records it in the recording medium 72 in the recording / reproducing processing unit 70. Further, the recording / reproducing apparatus 50 reproduces the digital information recorded on the recording medium 72 by the recording / reproducing processing unit 70, performs decoding processing by the decoding processing unit 80 to obtain the original digital information, and obtains the information. Output to the outside.

  The encoding processing unit 60 includes a first Reed-Solomon encoding unit 61-1 to an n-th Reed-Solomon encoding unit 61-n that perform Reed-Solomon codes related to different dimensions on digital information.

  The recording / playback processing unit 70 is a recording unit 71 that records information supplied from the encoding processing unit 60 on a recording medium 72, for example, a recording medium 72 such as an optical disk, and a playback unit that plays back information recorded on the recording medium 72. 73.

  The decoding processing unit 80 is a decoder corresponding to the encoding processing unit 60, and performs first Reed-Solomon decoding unit 81-1 to n-th Reed that performs Reed-Solomon decoding (normal decoding) on different dimensions of digital information. It consists of a Solomon decoding unit 81-n.

  The digital information supplied from the outside of the encoding processing unit 60 is subjected to Reed-Solomon encoding for the first dimension in the first Reed-Solomon encoding unit 61-1. Subsequently, Reed-Solomon codes relating to the second to n-th dimensions are performed on the digital information in each of the second Reed-Solomon encoding unit 61-2 to the n-th Reed-Solomon encoding unit 61-n. Is called. When the encoding by the n-th Reed-Solomon encoding unit 61-n is completed, the encoding processing unit 60 supplies the encoded digital information to the recording / reproducing processing unit 70. The recording unit 71 of the recording / playback processing unit 70 records the digital information supplied from the encoding processing unit 60 on the recording medium 72.

  The reproduction unit 73 of the recording / reproduction processing unit 70 reproduces digital information (encoded digital information) recorded on the recording medium 72 and supplies the digital information to the decoding processing unit 80.

  In each of the first Reed-Solomon decoding unit 81-1 to the n-th Reed-Solomon decoding unit 81-n, the decoding processing unit 80 converts Reed-Solomon decoding (normal decoding) for each dimension into the digital information supplied from the reproduction unit 73. ) To restore the original digital information. In contrast to the case of the encoding processing unit 60, the decoding processing unit 80 first performs Reed-Solomon decoding on the n-th dimension in the n-th Reed-Solomon decoding unit 81-n, and performs the (n-1) -th order, n-th order. Reed-Solomon decoding is performed so as to decrease the number of dimensions in order from the second dimension, and finally, Reed-Solomon decoding is performed on the first dimension. The decoding processing unit 80 outputs the restored original digital information to the outside of the recording / reproducing apparatus 50.

  As described above, the recording / reproducing apparatus 50 shown in FIG. 11 corrects information errors that occur during recording or reproduction of information.

  Normal decoding for the Reed-Solomon code, BCH (Bose-Chaudhuri-Hocquenghem) code, and the like as described above is a decoding method that is performed on a hard-decision received word that estimates a received value by only “0” or “1”. is there.

  However, when a soft-decision received word is obtained, the decoding performance using the hard-decision received word is generally inferior to the decoding performance using the soft-decision received word. However, when the Reed-Solomon code is normally decoded as described above, the decoding performance is not improved.

  Therefore, a decoding method using the sum product algorithm as described above is conceivable. However, since a parity check matrix of a general linear code is usually not low density, there is a problem that decoding performance is not improved. In addition, even if the given parity check matrix is low density, the sum product algorithm on a large finite field is very complicated, and there is a problem in that its calculation cost increases.

  The present invention has been made in view of such a situation, and makes it possible to easily perform a high-performance decoding process when a sum product algorithm is applied as a decoding method for a general linear code. It is.

The decoding apparatus of the present invention includes: a linear combination calculation unit that calculates a linear combination of each row of a check matrix of a linear code on the ring R; and a set of vectors obtained by the linear combination calculated by the linear combination calculation unit, By extracting a lower-weight vector subset that spans the code complement space and creating a new parity check matrix with all vectors in the vector subset as row components, the density of elements with a value of 1 is reduced. And a decoding means for decoding a linear code by a sum product algorithm using the new parity check matrix created by the parity check matrix creation means .

  The ring may be a finite field based on a power of a prime number.

  The linear code may include a BCH code or a Reed-Solomon code over a finite field.

The check matrix on the finite field, further comprising a deployment means for deploying at a predetermined dimension on the part of the finite linear combination calculation means calculates a linear combination of rows of the check matrix which is expanded by expansion means be able to.

Soft decision decoding means for soft decision decoding the convolutionally encoded linear code is further provided, and the linear combination calculation means calculates a linear combination of each row of the check matrix of the linear code soft decision decoded by the soft decision decoding means. Can do.

The soft decision decoding by the soft decision decoding means, the calculation by the linear combination calculation means, the creation of a new check matrix by the check matrix creation means, and the decoding by the decoding means can be repeatedly executed.

The decoding method of the present invention includes a linear combination calculation step for calculating a linear combination of each row of a check matrix of a linear code on the ring R, and a set of vectors obtained by the linear combination calculated by the processing of the linear combination calculation step. From this, the vector subset with a lower weight that extends the code complement space is extracted, and a new check matrix having all the vectors in the vector subset as row components is created, thereby reducing the density of elements having a value of 1. It includes a parity check matrix creating step for densification and a decoding step for decoding a linear code by a sum product algorithm using a new parity check matrix created by the processing of the parity check matrix creating step .

A first program of the present invention includes a linear combination calculation step for calculating a linear combination of each row of a check matrix of linear codes on the ring R, and a set of vectors obtained by the linear combination calculated by the processing of the linear combination calculation step. The density of elements having a value of 1 is extracted by extracting a lower-weight vector subset spanning the code complement space and creating a new check matrix having all vectors in the vector subset as row components Characterized in that a computer performs a parity check matrix creation step for reducing the density and a decoding step for decoding a linear code by a sum product algorithm using a new parity check matrix created by the processing of the parity check matrix creation step. To do.

The recording / reproducing apparatus of the present invention includes a recording means for recording a linear code on the ring R on a recording medium, a reproducing means for reproducing the linear code recorded by the recording means, and a check matrix of the linear code reproduced by the reproducing means. From the linear combination calculation means for calculating the linear combination of each row of and the vector set obtained by the linear combination calculated by the linear combination calculation means, a vector subset having a lower weight that extends the code complement space is extracted. , By creating a new parity check matrix having all vectors in the vector subset as row components, a parity check matrix creating means for reducing the density of elements having a value of 1, and a new matrix created by the parity check matrix creating means And a decoding means for decoding a linear code by a sum product algorithm using a simple check matrix.

The recording / reproducing method of the present invention includes a recording control step for controlling recording of a linear code on the ring R onto a recording medium, and a reproduction control for controlling reproduction of the linear code whose recording is controlled by the processing of the recording control step. A linear combination calculation step for calculating a linear combination of each row of the check matrix of the linear code whose reproduction is controlled by the processing of the reproduction control step, and a vector obtained by the linear combination calculated by the processing of the linear combination calculation step. From the set, a vector subset having a lower weight that extends the code complement space is extracted, and a new check matrix having all the vectors of the vector subset as row components is created. using a check matrix creation step of low density the density, a new check matrix created by the process of the check matrix creation step, Samupuroda a linear code Characterized in that it comprises a decoding step of decoding by preparative algorithm.

The second program of the present invention is a recording control step for controlling the recording of the linear code on the ring R onto the recording medium, and the reproduction of the linear code whose recording is controlled by the processing of the recording control step. A reproduction control step for controlling, a linear combination calculation step for calculating a linear combination of each row of the check matrix of the linear code whose reproduction is controlled by the processing of the reproduction control step, and a linearity calculated by the processing of the linear combination calculation step By extracting a lower-weight vector subset that extends the code complement space from the set of vectors obtained by combining, and creating a new check matrix with all vectors in the vector subset as row components, the value used but the check matrix creation step of low density the density of the elements that are 1, a new check matrix created by the process of the check matrix creation step , Characterized in that to execute a decoding step of decoding the linear code by sum product algorithm on a computer.

The reproducing apparatus of the present invention reproduces the linear code on the ring R recorded by the recording means, and linear combination calculating means for calculating the linear combination of each row of the check matrix of the linear code reproduced by the reproducing means. Then, from the vector set obtained by the linear combination calculated by the linear combination calculation means, a vector subset having a lower weight that extends the code complement space is extracted, and all vectors of the vector subset are used as row components. By creating a new parity check matrix by creating a new parity check matrix and reducing the density of elements with a value of 1, and using the new parity check matrix created by the parity check matrix creation means , the linear code is summed. And decoding means for decoding by an algorithm.

The reproduction method of the present invention includes a reproduction control step for controlling the reproduction of a linear code on the ring R recorded on a recording medium, and the linearity of each row of the check matrix of the linear code whose reproduction is controlled by the processing of the reproduction control step. From the linear combination calculation step for calculating the combination and the vector set obtained by the linear combination calculated by the processing of the linear combination calculation step, a vector subset having a lower weight that extends the code complement space is extracted, and the vector is extracted. By creating a new parity check matrix using all the vectors of the subset as row components, a new parity matrix created by the processing of the parity check matrix creation step for reducing the density of elements having a value of 1 and the parity check matrix creation step And a decoding step of decoding a linear code by a sum product algorithm using a simple check matrix.

A third program of the present invention includes a reproduction control step for controlling reproduction of a linear code on the ring R recorded on a recording medium, and each row of a check matrix for a linear code whose reproduction is controlled by processing of the reproduction control step. From the linear combination calculation step that calculates the linear combination of, and the vector set obtained by the linear combination calculated by the processing of the linear combination calculation step, a lower-weight vector subset that extends the code complement space is extracted. , By creating a new parity check matrix with all the vectors in the vector subset as row components, thereby creating a parity check matrix creation step for reducing the density of elements whose value is 1, and a parity check matrix creation step. new check matrix using, that to execute the linear codes and a decoding step of decoding the sum product algorithm on a computer especially a To.

In the decoding apparatus and method and the program according to the present invention , a linear combination of each row of the check matrix of the linear code on the ring R is calculated, and the code complement space is selected from the set of vectors obtained by the calculated linear combination. The lower-weight vector subset is extracted, and a new parity check matrix having all the vectors in the vector subset as row components is created, thereby reducing the density of elements having a value of 1, The new check matrix thus created is used, and the linear code is decoded by the sum product algorithm.

In the recording / reproducing apparatus, method, and program of the present invention , the linear code on the ring R is recorded on the recording medium, the recorded linear code is reproduced, and each row of the parity check matrix of the reproduced linear code is reproduced. A linear combination is calculated, and from the set of vectors obtained by the calculated linear combination, a lower-weight vector subset that extends the code complement space is extracted, and all vectors of the vector subset are used as row components. By creating a new parity check matrix, the density of elements having a value of 1 is reduced, and the new parity check matrix created in this way is used to decode the linear code by the sum product algorithm. .
Further, in the reproducing apparatus and method and the program of the present invention, the linear code on the ring R recorded on the recording medium is reproduced, and the linear combination of each row of the check matrix of the reproduced linear code is calculated. From the set of vectors obtained by the calculated linear combination, a lower-weight vector subset that extends the code complement space is extracted, and a new check matrix is created with all the vectors in the vector subset as row components. Thus, the density of elements having a value of 1 is reduced, and the new check matrix created in this way is used to decode the linear code by the sum product algorithm.

  According to the present invention, a general linear code decoding process can be performed. In particular, when the sum product algorithm is applied as a decoding method for a general linear code, it is possible to easily perform a decoding process with good performance.

  Hereinafter, embodiments of the present invention will be described. First, examples of techniques to which the present invention is applied will be described.

  FIG. 12 is a block diagram illustrating a configuration example of a decoding device to which the present invention is applied.

  In FIG. 12, a decoding device 100 is a decoding device corresponding to, for example, a BCH code, and a density reduction process for converting a parity check matrix of a received word on ring R (or on a finite field) into a sufficiently low density matrix. It consists of unit 110 and LDPC decoding unit 121 that decodes a received word using a reduced parity check matrix.

  The density reduction processing unit 110 includes a linear combination calculation unit 111 that calculates a linear combination of rows of the parity check matrix, a parity check matrix generation unit 112 that generates a sufficiently sparse parity check matrix using the linearly combined rows, The determination processing unit 113 determines whether the rank of the created parity check matrix is the same as the rank of the original parity check matrix.

The linear combination calculator 111 calculates the linear combination of each row of the parity check matrix included in the acquired received word for all combinations. That is, the linear combination calculation unit 111 calculates a linear combination with 2 ⁿ combinations for n rows of parity check matrices. The linear combination calculation unit 111 supplies the calculation result and the received word to the parity check matrix creation unit 112.

  The parity check matrix creation unit 112 extracts a row according to a predetermined condition from the calculation result supplied from the linear combination calculation unit 111, that is, the linearly combined row, and a parity check configured by the extracted row Create a matrix. The parity check matrix creation unit 112 sparsely creates a density of the created parity check matrix, for example, by extracting rows in which the number of elements having a value “1” is equal to or less than a predetermined number from the linearly coupled rows. A condition is set so as to satisfy, and a row corresponding to the condition is extracted. The parity check matrix creation unit 112 supplies the created parity check matrix and received word to the determination processing unit 113. As will be described later, when the determination processing unit 113 determines that the rank of the created parity check matrix is different from the rank of the original parity check matrix, the parity check matrix creation unit 112 again extracts rows. To create a new parity check matrix. At this time, the parity check matrix creation unit 112 changes the conditions for the previous row extraction, and creates a parity check matrix including different rows from the previously created parity check matrix.

  The determination processing unit 113 determines whether the rank (rank) of the parity check matrix created by the parity check matrix creation unit 112 matches the rank of the original parity check matrix. If it is determined that the ranks match, the determination processing unit 113 supplies the received word and the created parity check matrix to the LDPC decoding unit 121. If it is determined that the ranks do not match, the determination processing unit 113 returns the processing to the parity check matrix creation unit 112 to create a new parity check matrix.

  As described above, the density reduction processing unit 110 reduces the density of the parity check matrix of the BCH code included in the received word, and sends the reduced parity check matrix to the LDPC decoding unit 121 together with the received word. Supply.

LDPC decoding section 121 decodes the received word using the sum product algorithm using the acquired low-density parity check matrix, and outputs the decoded received word to the outside of decoding apparatus 100.

  As described above, when the density reduction processing unit 110 reduces the parity check matrix of the received word, the LDPC decoding unit 121 uses the low-density parity check matrix to perform decoding using the sum product algorithm. Processing can be performed, and decoding processing with high performance can be performed. In addition, since the density reduction processing unit 110 reduces the parity check matrix of the received word using linear combination, the LDPC decoding unit 121 can perform decoding on a partial field, thereby reducing the calculation cost. You can also. That is, before performing the decoding process using the sum product algorithm, the decoding apparatus 100 can easily perform a high-performance decoding process by reducing the density of the parity check matrix by linear combination. .

  Next, the decoding process by the above decoding apparatus is demonstrated with reference to the flowchart of FIG.

  First, in step S21, the density reduction processing unit 110 of the decoding apparatus 100 executes a parity check matrix density reduction process to make the density of the parity check matrix included in the acquired received word sparse. Details of the parity check matrix lowering process will be described later with reference to the flowchart of FIG.

  In step S22, the LDPC decoding unit 121 performs a decoding process using the sum product algorithm (SPA) using the parity check matrix reduced in density by the process in step S21. When the process of step S22 ends, the LDPC decoding unit 121 ends the decoding process for the received word. Note that the decoding device 100 executes the above-described decoding process for each received word (for each block).

  Next, details of the parity check matrix density reduction processing executed in step S21 of FIG. 13 will be described with reference to the flowchart of FIG.

  First, in step S41, the linear combination calculation unit 111 of the density reduction processing unit 110 performs linear combination in all combinations using each row of the parity check matrix included in the acquired received word, and calculates a combination result. To do.

  In step S42, the linear combination calculation unit 111 that has calculated the linear combination sets the value of the variable n serving as a row extraction condition to an initial value such as “1”, as will be described later. Then, the linear combination calculation unit 111 supplies the received word, the calculation result of the linear combination, and the variable n to the parity check matrix creation unit 112, and the process proceeds to step S43.

  In step S43, the parity check matrix creation unit 112 calculates the number of elements having a value “1” for each of the acquired linear combination results, and the element having the value “1” from all the linear combination results. In which the number weight is less than or equal to the variable n is extracted, and a new low-density parity check matrix having them as rows is created.

  That is, the parity check matrix creation unit 112 extracts a vector subset having a lower weight that extends the code complement space from the set of vectors obtained by the linear combination calculated by the linear combination calculation unit 111, and the vector portion A new parity check matrix having all the vectors of the set as row components is created.

  The parity check matrix creation unit 112 that created the new parity check matrix proceeds to step S44, adds “1” to the value of the variable n, and determines the received word, the created parity check matrix, and the variable n. This is supplied to the processing unit 113.

  In step S45, the determination processing unit 113 supplied with the received word, the created parity check matrix, and the variable n determines the rank of the original parity check matrix based on the information about the original parity check matrix included in the received word. It is determined whether or not (the rank) matches the rank (the rank) of the low-density parity check matrix.

  For example, if it is determined that the rank of the low-density parity check matrix is low and does not match the original parity check matrix, the determination processing unit 113 returns the process to step S43 and repeats the subsequent processes. That is, the determination processing unit 113 supplies the determination result to the parity check matrix creation unit 112, and causes the parity check matrix creation unit 112 to create a low-density parity check matrix again. At that time, since the value of the variable n, which is a condition to be extracted from the linear combination result, is different from that in the previous process, the parity check matrix creation unit 112 has a low density (having different elements from the previous one). A parity check matrix can be created.

  In step S45, when it is determined that the rank (rank) of the original parity check matrix matches the rank (rank) of the low-density parity check matrix, the determination processing unit 113 proceeds to step S46, and receives the received word. The generated low-density parity check matrix is output to the LDPC decoding unit 121, and the process returns to step S22 of FIG.

  As described above, by performing the decoding process and the parity check matrix lowering process, the decoding apparatus 100 reduces the density of the parity check matrix by linear combination before performing the decoding process using the sum product algorithm. Since the density is increased, a high-performance decoding process can be easily performed.

  Next, a specific example of density reduction using the above decoding apparatus 100 will be described.

In the following, a finite field is assumed to be a finite field GF (2 ⁴ ) (fourth-order extension of GF (2)) based on a power of a prime number, a linear code C as a code length 15 and an information length 7 (15, 7) A case where a -BCH code is decoded will be described.

  Assume that the parity check matrix H of the linear code C is given as shown in FIG. The parity check matrix H shown in FIG. 15 is an 8 × 15 matrix, and a Tanner graph corresponding to the parity check matrix H is expressed as shown in FIG. The Tanner graph of FIG. 16 is a graph in which each column of the parity check matrix H shown in FIG. 15 is represented by a variable node indicated by “=” and each row is indicated by a check node indicated by “+”. And the density of edges connecting check nodes is high, indicating that the parity check matrix H in FIG. 15 is not a low-density matrix.

As described above, the density reduction processing unit 110 in FIG. 12 performs linear combination using these eight rows, and generates 2 ⁸ = 256 row vectors with a low density of “1”. Then, the density reduction processing unit 110 extracts 15 row vectors whose number of “1” is 4 or less, and creates a new matrix H _sp4 as shown in FIG. To do. A Tanner graph corresponding to the matrix H _sp4 shown in FIG. 17 is as shown in FIG. Since both the number of rows and the number of columns of the matrix H _sp4 shown in FIG. 17 are 15, the number of variable nodes and check nodes in the Tanner graph shown in FIG. 18 is both 15. Compared with the case of FIG. Thus, the density of edges connecting variable nodes and check nodes is low.

The density reduction processing unit 110 uses the matrix H _sp4 as a parity check matrix and supplies the parity check matrix to the LDPC decoding unit 121. The LDPC decoding unit 121 uses the low-density parity check matrix _Hsp4 shown in FIG. 17 to perform decoding using the sum product algorithm on the received word.

FIG. 19 shows a case where a BCH code having such a parity check matrix is _subjected to maximum likelihood decoding by Viterbi decoding, and decoding by a sum product algorithm using a low density parity check matrix H _sp4 as shown in FIG. It is a graph which shows the comparison of the decoding performance at the time of performing.

  In FIG. 19, a curve 131 indicates a bit error rate (BER) of a decoding result by the sum product algorithm (SPA) ((2) bch 15 7 (wgt4) SPA BER), and a curve 132 is by Viterbi decoding. The bit error rate (BER) of the decoding result is indicated ((1) bch 15 7 ML BER). The data plotted by the point 133 indicates the frame error rate (FER) of the decoding result by the sum product algorithm ((2) bch 15 7 (wgt4) SPA FER), and the data plotted by the point 134 is The frame error rate (FER) of the decoding result by Viterbi decoding is shown ((1) bch 15 7 ML FER).

  The maximum likelihood decoding (curve 132 in FIG. 19) is a performance limit when stochastic decoding such as the sum product algorithm is used, but the curve 131 using the present invention as shown in FIG. The performance is approaching the limit.

  As described above, the decoding apparatus 100 reduces the density of the parity check matrix by linear combination before performing the decoding process using the sum product algorithm on the BCH code. Decoding processing can be performed.

  Although the decoding process for the BCH code has been described above, the present invention is not limited to this, and any coding method may be used as long as it is a general linear code such as a Reed-Solomon code. Hereinafter, a case where decoding is performed by applying the sum product algorithm to the Reed-Solomon code will be described.

  FIG. 20 is a block diagram showing another configuration example of the decoding device to which the present invention is applied.

  In FIG. 20, a decoding device 150 is a decoding device corresponding to, for example, a Reed-Solomon code. The expansion processing unit 161 expands a parity check matrix of a received word, and converts the expanded parity check matrix into a sufficiently low-density matrix. It comprises a density reduction processing section 170 and an LDPC decoding section 181 that decodes a received word using a density reduction parity check matrix.

  The expansion processing unit 161 expands each element of the parity check matrix included in the acquired received word to a predetermined order according to the dimension of the finite field of the matrix as preprocessing of the parity check matrix density reduction processing. To do. That is, the expansion processing unit 161 expands a parity check matrix on a finite field based on a power of a prime number on a partial field of the finite field in a predetermined dimension. The expansion processing unit 161 supplies the expanded parity check matrix and received word to the density reduction processing unit 170.

  The density reduction processing unit 170 includes a linear combination calculation unit 171 that calculates a linear combination of rows of the parity check matrix, a parity check matrix generation unit 172 that generates a sufficiently sparse parity check matrix using the linearly combined rows, and The determination processing unit 173 determines whether the rank of the created parity check matrix is the same as the rank of the original parity check matrix. Since the configuration and operation of each of these units are the same as those of the density reduction processing unit 110 of the decoding device 100 shown in FIG. That is, the linear combination calculation unit 171 through the determination processing unit 173 that constitute the density reduction processing unit 170 correspond to the linear combination calculation unit 111 through the determination processing unit 113 shown in FIG. However, the density reduction processing unit 170 performs density reduction processing on the expanded parity check matrix supplied from the expansion processing unit 161.

  Densification processing section 170 reduces the density of the Reed-Solomon code parity check matrix expanded by expansion processing section 161, and supplies the reduced parity check matrix together with the received word to LDPC decoding section 181. To do.

  LDPC decoding section 181 decodes the received word using the sum product algorithm using the acquired low-density parity check matrix, and outputs the decoded received word to the outside of decoding apparatus 150.

As described above, the decompression processing unit 161 expands the parity check matrix before the density reduction processing unit 170 reduces the density of the parity check matrix, so that the LDPC decoding unit 181 reduces the density of the parity check matrix. The calculation cost of the decoding process by the sum product algorithm using the check matrix H _sp24 is performed by the decoding process by the sum product algorithm using the parity check matrix H included in the received word as shown in the following equation (8). Compared with the case, it is reduced to about one quarter.

  Therefore, the decoding device 150 can easily perform a decoding process with good performance.

  Next, the decoding process by the decoding device 150 as described above will be described with reference to the flowchart of FIG.

  First, in step S61, the expansion processing unit 161 of the decoding device 150 expands the parity check matrix included in the acquired received word in accordance with the dimension of the finite field. Then, the expansion processing unit 161 supplies the expanded parity check matrix and received word to the density reduction processing unit 170, and the process proceeds to step S62.

  In step S <b> 62, the density reduction processing unit 170 executes a parity check matrix density reduction process to reduce the density of the developed parity check matrix. The details of the parity check matrix lowering process are the same as those described with reference to the flowchart of FIG. However, in the parity check matrix lowering processing in this case, the lowering processing unit 170 performs processing to lower the density of the parity check matrix expanded by the expansion processing unit 161 as described above.

  In step S63, the LDPC decoding unit 181 performs a decoding process using the sum product algorithm (SPA) using the parity check matrix reduced in density by the process in step S62. When the process of step S63 ends, the LDPC decoding unit 121 ends the decoding process for the received word. Note that the decoding device 150 executes the above-described decoding process for each received word (for each block).

  As described above, by performing the decoding process, the decoding apparatus 150 expands each element of the parity check matrix before performing the density reduction process, so that it is possible to easily perform the decoding process with good performance. it can.

  Next, a specific example of expansion using the above decoding apparatus 150 will be described.

In the following, a case where a finite field is GF (2 ⁴ ) and a (15,11) -Reed-Solomon code having a code length of 15 and an information length of 11 is decoded as a linear code C will be described. Note that a primitive root of GF (2 ⁴ ) is α, a primitive polynomial composed of the primitive root α is Equation (9), and a code generation polynomial is Equation (10).

The parity check matrix of the linear code C at this time is given as shown in FIG. The parity check matrix H shown in FIG. 22 is a 4 × 15 matrix. By the way, since the finite field GF (2 ⁴ ) is a fourth-order extension field of GF (2), all elements and matrices on the finite field GF (2 ⁴ ) can be expanded in four dimensions. The expansion processing unit 161 of the decoding device 150 expands the parity check matrix H shown in FIG. 22 and converts it into a parity check matrix H _exp of 16 rows and 60 columns as shown in FIG. In this case, the expansion processing unit 161 generates the parity check matrix H _exp shown in FIG. 23 by expanding each element of the parity check matrix H shown in FIG. 22 into a 4 × 4 element group.

The density reduction processing unit 170 of the decoding device 150 performs density reduction processing on the expanded parity check matrix H _exp , and the LDPC decoding unit 181 uses the parity check matrix H _exp reduced in density. The decryption process is performed by the sum product algorithm.

FIG. 24 shows a case where a Reed-Solomon code having such a parity check matrix is normally decoded and a sum product algorithm using a parity check matrix H _{sp24 obtained} by _{reducing the} density of the developed parity check matrix H _exp in FIG. It is a graph which shows the comparison of the decoding performance at the time of performing decoding.

In FIG. 24, a curve 191 indicates a bit error rate (BER) of a decoding result when decoding by the sum product algorithm (SPA) is performed using the parity check matrix H _sp24 having a reduced density ((4 ) RS wgt24 SPA BER), a curve 192 indicates the bit error rate (BER) of the decoding result by the normal decoding ((3) RS ORD BER). The data plotted by the point 193 indicates the frame error rate (FER) of the decoding result when decoding by the sum product algorithm is performed using the _reduced parity check matrix _Hsp24 ((4) RS wgt24 SPA FER), the data plotted by point 194 indicates the frame error rate (FER) of the decoding result by normal decoding ((3) RS ORD FER).

  As shown in FIG. 24, the curve 191 (point 193) that is the decoding result of the decoding using the present invention has better performance than the curve 192 (point 194) that is the decoding result in the case of normal decoding. Is obtained.

  As described above, since the decoding apparatus 150 reduces the density of the parity check matrix by linear combination before performing the decoding process using the sum product algorithm on the Reed-Solomon code, the performance can be easily improved. Good decoding processing can be performed. In addition, since the decoding apparatus 150 expands each element and matrix of the parity check matrix before reducing the density of the parity check matrix, the calculation cost can be reduced.

  FIG. 25 is a block diagram showing a configuration example of an error correction system using a Reed-Solomon code to which the present invention is applied. The error correction system shown in FIG. 25 is a system used for a digital communication system such as a digital television.

  In the error correction system of FIG. 25, digital information transmitted from the encoding device 210 on the transmission side is supplied to the decoding device 230 on the reception side via a communication path 221 represented by the Internet, for example.

  The encoding device 210 includes a Reed-Solomon encoding unit 211 that encodes digital information for transmission supplied from outside using a Reed-Solomon code, an interleaver 212 that rearranges the encoded digital information, and a convolutional code. A convolutional encoding unit 213 that performs conversion, and a communication processing unit 214 that performs communication with the decoding device 230 via the communication path 221.

  The Reed-Solomon encoding unit 211 performs an encoding process using Reed-Solomon code on the digital information supplied from the outside of the encoding device 210, and supplies the encoded digital information to the interleaver 212. The interleaver 212 performs rearrangement (interleaving) of the encoded digital information in order to spread burst errors that mainly occur in the communication path 221. Since the Reed-Solomon code performs error correction with a plurality of bits as one symbol, the interleaver 212 performs symbol interleaving for spreading burst errors in symbol units. The interleaver 212 that has finished rearranging the information supplies the rearranged digital information to the convolutional coding unit 213.

  The convolutional coding unit 213 performs convolutional code in which a code sequence is sequentially determined based on a plurality of information blocks with reference to information encoded in the past with respect to the rearranged digital information. For example, when digital information is supplied for each k-bit information block from the interleaver 212, the convolutional encoding unit 213 having a constraint length K includes not only the information block supplied this time but also the information block supplied in the past. Based on the K information blocks, encoding is performed into an n-bit code block. When the convolutional coding is completed, the convolutional coding unit 213 supplies the digital information subjected to the convolutional coding to the communication processing unit 214.

  The communication processing unit 214 performs communication control processing, and transmits the supplied digital information as a transmission word to the decoding device 230 via the communication path 221 based on a predetermined protocol.

  The digital information output from the encoding device 210 is supplied to the decoding device 230 via the communication path 221.

  The decoding device 230 receives the digital information supplied via the communication path 221 as a received word, and a convolutional decoding unit 232 that performs a convolutional decoding process on the received word acquired by the communication processing unit 231. The deinterleaver 233 which rearranges the received convolutionally decoded received words in the original order, and the digital information before the Reed-Solomon encoding is performed on the digital information returned to the original order by performing a decoding process using the sum product algorithm The Reed-Solomon SPA decoding unit 234 restores.

  The communication processing unit 231 communicates with the communication processing unit 214 of the encoding device 210 via the communication path 221 and acquires digital information supplied from the communication processing unit 214 as a received word based on a predetermined protocol. The communication processing unit 231 supplies the acquired received word to the convolution decoding unit 232.

  The convolutional decoding unit 232 decodes the received word supplied from the transmission processing unit 231 by a method corresponding to the encoding method by the convolutional encoding unit 213 of the encoding device 210. That is, the convolutional decoding unit 232 performs, for example, a BCJR (Bahl, Cocke, Jelinek, and Raviv) algorithm or SOVA (Maximum posteriori probability decoding) on a received word. Soft decision decoding is performed using a soft output Viterbi algorithm) or the like. Then, the convolutional decoding unit 232 supplies the received word subjected to the soft decision decoding to the deinterleaver 233.

  The deinterleaver 233 rearranges information on the supplied received word by a method corresponding to the interleaving performed in the interleaver 212 of the encoding device 210, and returns the rearranged information to the original order. Processing (deinterleaving) is performed, and the received words rearranged in the original order are supplied to the Reed-Solomon SPA decoding unit 234.

  The Reed-Solomon SPA decoding unit 234 has basically the same configuration as that of the decoding device 150 shown in FIG. 20, and basically performs the same operation. As in the case of the decoding device 150, the block diagram of FIG. Since the flowchart shown in FIG. 21 can be applied, detailed description thereof is omitted.

  The Reed-Solomon SPA decoding unit 234 expands the parity check matrix and lowers the density of the Reed-Solomon-encoded received word, performs a decoding process using the sum product algorithm using the parity check matrix, The original digital information before being converted is restored. The Reed-Solomon SPA decoding unit 234 outputs the decoded digital information to the outside of the decoding device 230.

  As described above, the error correction system of FIG. 25 can easily perform a decoding process with good performance, and can perform more accurate communication. In addition, since the decoding apparatus 230 expands each element and matrix of the parity check matrix before reducing the density of the parity check matrix, the calculation cost of the decoding process can be kept low.

  In the above description, the error correction system is described to decode the Reed-Solomon code. However, the present invention is not limited to this. For example, a BCH code may be decoded.

  FIG. 26 is a block diagram showing another configuration example of the error correction system using the Reed-Solomon code to which the present invention is applied. The error correction system shown in FIG. 26 is a system used for a digital communication system such as a digital television. The same parts as those shown in FIG. 25 are denoted by the same reference numerals, and the description thereof is omitted.

  In the error correction system of FIG. 26, the digital information encoded by the encoding device 210 on the transmission side is supplied to the decoding device 240 on the reception side via, for example, a communication path 221 represented by the Internet. .

  The decoding device 240 receives the digital information supplied via the communication path 221 as a received word, and a convolutional decoding unit 242 that performs a convolutional decoding process on the received word acquired by the communication processing unit 241. Deinterleaver 243 that rearranges the received convolutionally decoded received words in the original order, performs decoding processing on the digital information that has been restored to the original order, and restores the digital information before Reed-Solomon encoding The Reed-Solomon SPA decoding unit 244 and the interleaver 245 that rearranges the digital information, like the interleaver 212 of the encoding device 210.

  As in the case of the communication processing unit 231 in FIG. 25, the communication processing unit 241 communicates with the communication processing unit 214 of the encoding device 210 via the communication path 221, and based on a predetermined protocol, the communication processing unit 214. The supplied digital information is acquired as a received word. The communication processing unit 241 supplies the acquired received word to the convolution decoding unit 242.

  As in the case of the convolutional decoding unit 232 in FIG. 25, the convolutional decoding unit 242 converts the received word supplied from the transmission processing unit 241 by a method corresponding to the encoding method by the convolutional encoding unit 213 of the encoding device 210. Decrypt. That is, the convolutional decoding unit 242 performs soft decision decoding on the received word using, for example, the BCJR algorithm, SOVA, or the like. Then, the convolution decoding unit 242 supplies the received word subjected to the soft decision decoding to the deinterleaver 243. The convolution decoding unit 242 is supplied with the received words that have been decoded by the sum product algorithm from the interleaver 245 again. The convolutional decoding unit 242 performs soft decision decoding on the received word as well as the received word supplied from the communication processing unit 241 using, for example, BCJR algorithm, SOVA, and the like, and deinterleaver 243. To supply.

  As in the case of the deinterleaver 233 in FIG. 25, the deinterleaver 243 performs information on the received word supplied from the convolutional decoding unit 242 by a method corresponding to the interleaving performed in the interleaver 212 of the encoding device 210. Are rearranged, processing for returning the rearranged information to the original order (deinterleaving) is performed, and the received words rearranged in the original order are supplied to the Reed-Solomon SPA decoding unit 244. As described above, the received word supplied from the convolutional decoding unit 242 includes the received word supplied from the communication processing unit 241 via the convolutional decoding unit 242 and the interleaver 245 via the convolutional decoding unit 242. Received words are also included.

  Similar to the Reed-Solomon SPA decoding unit 244 in FIG. 25, the Reed-Solomon SPA decoding unit 244 has basically the same configuration as the decoding device 150 shown in FIG. As in the case of the decoding device 150, the block diagram of FIG. 20 and the flowchart shown in FIG. 21 can be applied.

  The Reed-Solomon SPA decoding unit 244 expands the parity check matrix included in the received word and lowers the density of the received word acquired from the deinterleaver 243, and uses the parity check matrix to perform decoding processing by the sum product algorithm To restore the original digital information before encoding. The Reed-Solomon SPA decoding unit 244 outputs the decoded digital information to the outside of the decoding device 240. The Reed-Solomon SPA decoding unit 244 supplies the decoded digital information to the interleaver 245.

  The interleaver 245 rearranges the acquired digital information in a predetermined order, like the interleaver 212 of the encoding device 210. The rearrangement pattern by the interleaver 245 is the same as that of the interleaver 212. The digital information rearranged in this way is supplied to the convolutional decoding unit 242.

  As described above, the decoding device 240 performs soft decision decoding by the convolution decoding unit 242 and Reed-Solomon SPA decoding unit 244 on the received word acquired by the communication processing unit 241 via the deinterleaver 243 and the interleaver 245. The decoding using the sum product algorithm is repeated to reduce the decoding error probability in the decoding process. Note that the number of repetitions of this decoding may be determined in advance, and for example, it is determined whether or not to stop the repetition based on a predetermined condition such as the number of locations where error correction is performed. May be.

  In this way, the decoding device 240 can easily perform a decoding process with good performance, and the error correction system of FIG. 26 can perform more accurate communication. In addition, since the decoding apparatus 240 expands each element and matrix of the parity check matrix before reducing the density of the parity check matrix, the calculation cost of the decoding process can be kept low.

  In the above description, the Reed-Solomon SPA decoding unit 244 has been described to output the decoded digital information to the outside of the decoding device 240 and supply it to the interleaver 245. However, the present invention is not limited to this, and for example, decoding is repeated. In the meantime, the decoded digital information is supplied only to the interleaver 245, and when the decoding is repeated, the output destination of the digital information is switched from the interleaver 245 to the outside of the decoding device 240, and the decoded digital information is output. You may make it do.

  In the above description, the error correction system is described to decode the Reed-Solomon code. However, the present invention is not limited to this. For example, a BCH code may be decoded.

  FIG. 27 is a block diagram illustrating a configuration example of a recording / reproducing apparatus to which an error correction system that performs error correction using a Reed-Solomon code, to which the present invention is applied, is applied. The recording / reproducing apparatus shown in FIG. 27 is a digital recording medium recording / reproducing apparatus such as a DVD record player, for example.

  27, the digital information supplied from the outside is encoded by the encoding processing unit 260, and is recorded on the recording medium 272 by the recording / reproducing processing unit 270. Further, the recording / reproducing apparatus 250 reproduces the digital information recorded on the recording medium 272 by the recording / reproducing processing unit 270, performs the decoding process by the decoding processing unit 280, acquires the original digital information, and obtains the information. Output to the outside.

  The encoding processing unit 260 includes a first Reed-Solomon encoding unit 261-1 to an n-th Reed-Solomon encoding unit 261-n that perform Reed-Solomon codes related to different dimensions on digital information.

  The digital information supplied from the outside of the encoding processing unit 260 is subjected to Reed-Solomon encoding for the first dimension in the first Reed-Solomon encoding unit 261-1. Subsequently, Reed-Solomon codes relating to each dimension from the second dimension to the n-th dimension are sequentially assigned to the digital information in each of the second Reed-Solomon encoding unit 261-2 to the n-th Reed-Solomon encoding unit 261-n. Done. When the encoding by the n-th Reed-Solomon encoding unit 261-n is completed, the encoding processing unit 260 supplies the encoded digital information to the recording / reproducing processing unit 270.

  The recording / playback processing unit 270 records the information supplied from the encoding processing unit 260 on the recording medium 272, for example, a recording medium 272 such as an optical disk, and a playback unit that plays back information recorded on the recording medium 272. 273.

  The recording unit 271 of the recording / reproducing processing unit 270 records the digital information supplied from the encoding processing unit 260 on the recording medium 272 by performing NRZI (Non Return to Zero Invert) conversion (NRZI encoding) or the like. The playback unit 273 of the recording / playback processing unit 270 plays back the digital information (reed-solomon encoded digital information) recorded on the recording medium 272, and restores the NRZI conversion performed on the digital information. (Decode) and supply the digital information to the decoding processing unit 280.

  The decoding processing unit 280 is a decoder corresponding to the encoding processing unit 260, and performs the first Reed-Solomon SPA decoding unit 281-1 through n-th Reed-Solomon that perform decoding processing by the sum product algorithm with respect to different dimensions of the digital information. It consists of a SPA decoding unit 281-n.

  The first Reed-Solomon SPA decoding unit 281-1 to the n-th Reed-Solomon SPA decoding unit 281-n are respectively the first Reed-Solomon encoding unit 261-1 to the n-th Reed-Solomon encoding unit 261 of the encoding processing unit 260. Corresponding to -n, the Reed-Solomon code for each dimension is decoded by the sum product algorithm. Each of the first Reed-Solomon SPA decoding unit 281-1 to the n-th Reed-Solomon SPA decoding unit 281-n has basically the same configuration as the decoding device 150 shown in FIG. Do. Accordingly, the first Reed-Solomon SPA decoding unit 281-1 to the n-th Reed-Solomon SPA decoding unit 281-n are similar to the case of the decoding device 150, respectively, in the block diagram of FIG. 20 and the flowchart shown in FIG. Can be applied.

  The decoding processing unit 280 performs each element of the parity check matrix on the digital information supplied from the reproduction unit 273 in each of the first Reed-Solomon SPA decoding unit 281-1 to the n-th Reed-Solomon SPA decoding unit 281-n. The matrix is expanded, the parity check matrix is reduced in density, and the decoding process by the sum product algorithm for each dimension is performed. At that time, as shown in FIG. 27, the decoding processing unit 280 first performs the sum product algorithm for the n-th dimension in the n-th Reed-Solomon SPA decoding unit 281-n, contrary to the case of the encoding processing unit 260. The decoding process is performed, and then, in each Reed-Solomon SPA decoding unit connected in series, the decoding process by the sum product algorithm is performed so as to decrease the number of dimensions in order of the (n-1) th dimension and the (n-2) th dimension, respectively. Finally, the first Reed-Solomon SPA decoding unit 281-1 performs a decoding process using the sum product algorithm for the first dimension. The decoding processing unit 280 outputs the original digital information restored in this way to the outside of the recording / reproducing apparatus 250.

  In this way, the decoding processing unit 280 can easily perform a decoding process with good performance, and the recording / reproducing apparatus 250 can record and reproduce digital information more accurately. In addition, since the decoding processing unit 280 expands each element and matrix of the parity check matrix before reducing the density of the parity check matrix, the calculation cost of the decoding process can be kept low.

  In the above description, the recording / reproducing apparatus 250 is described to decode the Reed-Solomon code. However, the present invention is not limited to this. For example, a BCH code may be decoded.

  In the above, an example of a recording / reproducing apparatus that records and reproduces digital information has been described. However, the recording / reproducing apparatus 250 has a recording function for recording digital information on a recording medium, and digital information recorded on the recording medium. May be configured as a separate unit.

  FIG. 28 is a block diagram showing a configuration example of a recording apparatus having the same recording function as the recording / reproducing apparatus 250 of FIG. In addition, the same code | symbol is attached | subjected about the part similar to the case shown by FIG. 27, The description is abbreviate | omitted.

The recording apparatus 300 in FIG. 28 includes an encoding processing unit 260 including a first Reed-Solomon encoding unit 261-1 to an n-th Reed-Solomon encoding unit 261-n, and a recording process including a recording unit 271 and a recording medium 272. Part 310. The digital information supplied from the outside of the encoding processing unit 260 of the recording apparatus 300 is first subjected to Reed-Solomon encoding for the first dimension in the first Reed-Solomon encoding unit 261-1. Subsequently, the digital information encoded with respect to the first dimension is sequentially supplied to each unit of the second Reed-Solomon encoding unit 261-2 to the n-th Reed-Solomon encoding unit 261-n. A Reed-Solomon code for each dimension up to the nth dimension is performed. When the encoding by the n-th Reed-Solomon encoding unit 261-n is completed, the encoding processing unit 260 supplies the encoded digital information to the recording processing unit 310.

  The recording processing unit 310 includes a recording unit 271 that records the information supplied from the encoding processing unit 260 on the recording medium 272 and a recording medium 272 such as an optical disc. The recording unit 271 of the recording processing unit 310 records the digital information supplied from the encoding processing unit 260 on the recording medium 272 by performing NRZI conversion (NRZI encoding) or the like.

  That is, in the recording apparatus 300, as with the recording / reproducing apparatus 250 in FIG. 27, the digital information is Reed-Solomon encoded by the encoding processing unit 260, and the Reed-Solomon encoding is performed under the control of the recording unit 271 of the recording processing unit 310. The recorded digital information is recorded on the recording medium 272.

  A reproducing apparatus corresponding to such a recording apparatus 300 is shown in FIG. In addition, the same code | symbol is attached | subjected about the part similar to the case shown by FIG. 27, The description is abbreviate | omitted.

A playback device 350 in FIG. 29 is a playback device corresponding to the recording device 300 shown in FIG. 28, and includes a first Reed-Solomon SPA decoding unit 281-1 to an n-th Reed-Solomon SPA decoding unit 281-n. 280, and a reproduction processing unit 360 including a recording medium 272 and a reproduction unit 273. The reproduction unit 273 of the reproduction processing unit 360 reproduces digital information (Reed-Solomon encoded digital information) recorded on the recording medium 272, and returns (decodes) the NRZI conversion applied to the digital information. ), And supplies the digital information to the decoding processing unit 280.

  The decoding processing unit 280 performs each element of the parity check matrix on the digital information supplied from the reproduction unit 273 in each of the first Reed-Solomon SPA decoding unit 281-1 to the n-th Reed-Solomon SPA decoding unit 281-n. The matrix is expanded, the parity check matrix is reduced in density, and the decoding process by the sum product algorithm for each dimension is performed. At that time, as shown in FIG. 29, the decoding processing unit 280 first performs the sum product algorithm for the n-th dimension in the n-th Reed-Solomon SPA decoding unit 281-n, contrary to the case of the encoding processing unit 260. The decoding process is performed, and then, in each Reed-Solomon SPA decoding unit connected in series, the decoding process by the sum product algorithm is performed so as to decrease the number of dimensions in order of the (n-1) th dimension and the (n-2) th dimension, respectively. Finally, the first Reed-Solomon SPA decoding unit 281-1 performs a decoding process using the sum product algorithm for the first dimension. The decoding processing unit 280 outputs the original digital information restored in this way to the outside of the playback device 350.

  In this way, the decoding processing unit 280 can easily perform a decoding process with good performance, and the reproducing apparatus 350 can reproduce digital information more accurately. In addition, since the decoding processing unit 280 expands each element and matrix of the parity check matrix before reducing the density of the parity check matrix, the calculation cost of the decoding process can be suppressed.

In the above description, the recording apparatus 300 is described to decode the Reed-Solomon code. However, the present invention is not limited to this. For example, the BCH code may be decoded.

  FIG. 30 is a block diagram illustrating a configuration example of a recording / reproducing apparatus to which an error correction system that performs error correction using a Reed-Solomon code, to which the present invention is applied, is applied. A recording / reproducing apparatus 400 shown in FIG. 30 is, for example, a digital recording medium recording / reproducing apparatus such as a DVD record player. In addition, the same code | symbol is attached | subjected about the part similar to the case shown by FIG. 27, The description is abbreviate | omitted.

  In the recording / reproducing apparatus 400 of FIG. 30, digital information supplied from the outside is encoded by the encoding processing unit 260 and recorded on the recording medium 272 by the recording / reproducing processing unit 270. Further, the recording / reproducing apparatus 400 reproduces the digital information recorded on the recording medium 272 by the recording / reproducing processing unit 270, performs the decoding process by the decoding processing unit 410, acquires the original digital information, and obtains the information. Output to the outside.

  The decoding processing unit 410 is a decoder corresponding to the encoding processing unit 260, and each has the same configuration as the decoding processing unit 280 shown in FIG. 27, and performs the same decoding processing and is connected in series. The first decoding unit 420-1 to the m-th decoding unit 420-m are m decoding units.

  The first decoding unit 420-1 corresponds to the first Reed-Solomon encoding unit 261-1 to the n-th Reed-Solomon encoding unit 261-n of the encoding processing unit 260, similarly to the decoding processing unit 280 of FIG. The first Reed-Solomon SPA decoding unit 421-1-1 to the n-th Reed-Solomon SPA decoding, which are n decoding units connected in series, that perform decoding by the sum product algorithm for the Reed-Solomon codes relating to each dimension. It is comprised by the part 421-1-n. The first Reed-Solomon SPA decoding unit 421-1-1 to the n-th Reed-Solomon SPA decoding unit 421-1-n have basically the same configuration as the decoding device 150 shown in FIG. The same operation is performed. Accordingly, the first Reed-Solomon SPA decoding unit 421-1-1 to the n-th Reed-Solomon SPA decoding unit 421-1-n are respectively similar to the case of the decoding device 150, and the block diagram of FIG. The flowchart shown in FIG. 21 can be applied.

  Each of the second decoding unit 420-2 to the m-th decoding unit 420-m has the same configuration as the first decoding unit 420-1, and performs the same operation as the first decoding unit 420-1. For example, the second decoding unit 420-2 includes first Reed-Solomon SPA decoding units 421-2-1 to 421-2-n, which are n decoding units connected in series. The m-th decoding unit 420-m is also composed of first Reed-Solomon SPA decoding unit 421-m-1 to n-th Reed-Solomon SPA decoding unit 421-mn that are n decoding units connected in series. The Note that all of the first Reed-Solomon SPA decoding unit to the n-th Reed-Solomon SPA decoding unit constituting the second decoding unit 420-2 to the m-th decoding unit 420-m are respectively decoding devices 150 shown in FIG. Since the configuration is basically the same and basically the same operation is performed, the block diagram of FIG. 20 and the flowchart shown in FIG. 21 can be applied as in the case of the decoding device 150. .

  First, the decoding processing unit 410 applies the first Reed-Solomon SPA decoding unit 421-1-1 to the n-th Reed-Solomon SPA decoding unit 421 of the first decoding unit 420-1 to the digital information supplied from the reproduction unit 273. In each part of -1-n, each element and matrix of the parity check matrix are expanded, the parity check matrix is reduced in density, and decoding processing is performed by the sum product algorithm for each dimension.

  In that case, contrary to the case of the encoding processing unit 260, the first decoding unit 420-1 firstly performs decoding from the decoding process by the sum product algorithm for the nth dimension in the nth Reed-Solomon SPA decoding unit 421-1-n. Subsequently, each Reed-Solomon SPA decoding unit connected in series performs a decoding process by the sum product algorithm so as to decrease the number of dimensions in order of the (n-1) th dimension and the (n-2) th dimension, respectively. The first Reed-Solomon SPA decoding unit 421-1-1 performs a decoding process using the sum product algorithm for the first dimension.

  When the decoding process ends, the first decoding unit 420-1 supplies the decoded digital information to the second decoding unit 420-2. Similar to the first decoding unit 420-1, the second decoding unit 420-2 uses the first Reed-Solomon SPA decoding unit 421-2-1 to the n-th Reed-Solomon SPA decoding unit 421-2-n. Thus, the decoding process by the sum product algorithm is performed in the order of decreasing the number of dimensions one by one, and the decoded digital information is supplied to the next decoding unit. In this way, the decoding process is sequentially continued up to the m-th decoding unit 420-m. When the decoding process in the m-th decoding unit 420-m is completed, the decoding processing unit 410 outputs the decoded digital information to the outside of the recording / reproducing apparatus 400.

  In this way, the decoding processing unit 410 can easily perform a decoding process with good performance, and the recording / reproducing apparatus 400 can record and reproduce digital information more accurately. Moreover, since the decoding processing unit 410 expands each element and matrix of the parity check matrix before reducing the density of the parity check matrix, the calculation cost of the decoding process can be kept low.

  In the above description, the recording / reproducing apparatus 400 is described to decode the Reed-Solomon code. However, the present invention is not limited to this, and for example, a BCH code may be decoded.

  In the above, an example of a recording / reproducing apparatus that records and reproduces digital information has been described. However, the recording / reproducing apparatus 400 has a recording function for recording digital information on a recording medium, and the information is recorded on the recording medium. A reproduction function for reproducing digital information may be configured separately. In this case, the recording apparatus having the same recording function as the recording / reproducing apparatus 400 of FIG. 30 has the same configuration as the recording apparatus 300 shown in FIG. 28 and performs the same operation, so the block diagram of FIG. 28 is applied. The description thereof is omitted.

  FIG. 31 shows a reproducing apparatus corresponding to the recording apparatus 300 which is a recording apparatus having the same recording function as the recording / reproducing apparatus 400 of FIG. 30 that are the same as those shown in FIG. 30 are given the same reference numerals, and descriptions thereof are omitted.

  31 is a playback device corresponding to the recording device 300 shown in FIG. 28, and includes a decoding processing unit 410 including a first decoding unit 420-1 to an m-th decoding unit 420-m, and a recording medium. A reproduction processing unit 460 including a reproduction unit 272 and a reproduction unit 273. The playback unit 273 of the playback device 450 plays back digital information (Reed-Solomon encoded digital information) recorded on the recording medium 272, and restores (decodes) the NRZI conversion applied to the digital information. The digital information is supplied to the decoding processing unit 410.

  First, the decoding processing unit 410 expands each element and matrix of the parity check matrix in the first decoding unit 420-1 for the digital information supplied from the reproduction unit 273, and lowers the density of the parity check matrix. Thus, the decoding process by the sum product algorithm is performed for each dimension. Subsequently, the decoding processing unit 410 sequentially supplies the digital information to the second decoding units 420-2 to 420-m connected in series, and performs decoding processing by the sum product algorithm in each unit. When the decoding process in the m-th decoding unit 420-m is completed, the decoding processing unit 410 outputs the decoded digital information to the outside of the recording / reproducing apparatus 400.

  In this way, the decoding processing unit 410 can easily perform a decoding process with good performance, and the reproducing apparatus 450 can reproduce digital information more accurately. In addition, since the decoding processing unit 410 expands each element and matrix of the parity check matrix before reducing the density of the parity check matrix, the calculation cost of the decoding process can be suppressed.

  In the above description, the case where the present invention is applied to the decoding of the BCH code or the Reed-Solomon code has been described. However, the present invention is not limited to this, and the present invention is applicable to any code as long as it is a general linear code. You may make it apply this invention to.

  In the above description, the playback apparatus 450 has been described as decoding Reed-Solomon codes. However, the present invention is not limited to this, and for example, BCH codes may be decoded.

  Furthermore, in the above, for example, the decoding device 100 shown in FIG. 12, the decoding device 150 shown in FIG. 20, the Reed-Solomon SPA decoding unit 234 shown in FIG. 25, the Reed-Solomon SPA decoding unit 244 shown in FIG. The first Reed-Solomon SPA decoding unit 281-1 through n-th Reed-Solomon SPA decoding unit 281-n shown in FIG. 27 and the first decoding unit 420-1 through m-th decoding unit 420-m shown in FIG. Such a decoding apparatus or decoding unit to which the present invention is applied is described as a decoding method for a general linear code, in which the parity check matrix is reduced in density and the linear code is decoded using the reduced density check matrix. However, the present invention is not limited to this. For example, the density of the check matrix may be reduced in advance in another device or another processing unit. In that case, the decoding apparatus (or decoding unit) decodes the linear code supplied from the encoding apparatus or the like using the check matrix whose density is reduced in advance. That is, for example, the decoding device 230 shown in FIG. 25, the decoding device 240 shown in FIG. 26, the recording / reproducing device 250 shown in FIG. 27, the reproducing device 350 shown in FIG. 29, and the recording / reproducing device 400 shown in FIG. 31. Alternatively, the parity check matrix is reduced in advance outside the reproduction apparatus 450 shown in FIG. 31, and each apparatus uses the previously reduced check matrix to decode a supplied linear code. May be performed.

  The series of processes described above can be executed by hardware or can be executed by software. When executed by software, the above-described image processing apparatus is configured by a personal computer as shown in FIG.

  In FIG. 32, a CPU (Central Processing Unit) 501 of the personal computer 500 performs various processes according to a program stored in a ROM (Read Only Memory) 502 or a program loaded from a storage unit 513 to a RAM (Random Access Memory) 503. Execute the process. The RAM 503 also appropriately stores data necessary for the CPU 501 to execute various processes.

  The CPU 501, ROM 502, and RAM 503 are connected to each other via a bus 504. An input / output interface 510 is also connected to the bus 504.

  The input / output interface 510 includes an input unit 511 including a keyboard and a mouse, a display including a CRT (Cathode Ray Tube) and an LCD (Liquid Crystal display), an output unit 512 including a speaker, and a hard disk. A communication unit 514 including a storage unit 513 and a modem is connected. The communication unit 514 performs communication processing via a network including the Internet.

  A drive 515 is connected to the input / output interface 510 as necessary, and a removable medium 921 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is appropriately mounted, and a computer program read from them is loaded. It is installed in the storage unit 513 as necessary.

  When a series of processing is executed by software, a program constituting the software is installed from a network or a recording medium.

  As shown in FIG. 32, this recording medium is distributed to provide a program to the user separately from the apparatus main body, and includes a magnetic disk (including a floppy disk) on which the program is recorded, an optical disk (CD- It is not only composed of a removable medium 521 composed of ROM (compact disk-read only memory), DVD (digital versatile disk), magneto-optical disk (including MD (mini-disk)), or semiconductor memory. The program is provided with a ROM 502 on which a program is recorded and a hard disk included in the storage unit 513, which is provided to the user in a state of being pre-installed in the apparatus main body.

  In the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but is not necessarily performed in chronological order. It also includes processes that are executed individually.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

It is a figure which shows the example of a low density parity check matrix. It is a figure explaining the Tanner graph corresponding to the parity check matrix of FIG. It is a flowchart explaining the decoding procedure of an LDPC code. It is a figure explaining the flow of a message. It is a figure which shows the example of the check matrix of a LDPC code. It is a figure which shows the Tanner graph of a check matrix. It is a figure which shows a variable node. It is a figure which shows a check node. It is a figure which shows the example of the check matrix of a Reed-Solomon code. It is a figure which closes the structural example of the conventional error correction system. It is a figure which shows the structural example of the conventional recording / reproducing apparatus. It is a figure which shows the structural example of the decoding apparatus to which this invention is applied. It is a flowchart explaining the decoding process by the decoding apparatus of FIG. It is a flowchart explaining the parity check matrix low density process performed in step S21 of FIG. It is a figure which shows the example of the parity check matrix of a BCH code. FIG. 16 is a diagram illustrating a Tanner graph corresponding to the parity check matrix of FIG. 15. It is a figure which shows the example of the expanded parity check matrix. FIG. 18 is a diagram illustrating a Tanner graph corresponding to the parity check matrix of FIG. 17. It is a graph for comparing decoding performance. It is a figure which shows the other structural example of the decoding apparatus to which this invention is applied. It is a flowchart explaining the decoding process by the decoding apparatus of FIG. It is a figure which shows the example of the parity check matrix in a Reed-Solomon code. It is a figure which shows the example of the expanded parity check matrix. It is a graph for comparing decoding performance. It is a block diagram which shows the structural example of the error correction system to which this invention is applied. It is a block diagram which shows the other structural example of the error correction system to which this invention is applied. It is a block diagram which shows the structural example of the recording / reproducing apparatus to which this invention is applied. It is a block diagram which shows the structural example of a recording device. It is a block diagram which shows the structural example of the reproducing | regenerating apparatus to which this invention is applied. FIG. 10 is a block diagram illustrating another configuration example of a recording / reproducing apparatus to which the present invention is applied. FIG. 20 is a block diagram illustrating another configuration example of a playback device to which the present invention has been applied. It is a block diagram which shows the structural example of one Embodiment of the computer to which this invention is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 Decoding apparatus, 110 Densification process part, 111 Linear combination calculation part, 112 Parity check matrix preparation part, 113 Judgment processing part, 121 LDPC decoding part, 161 Decompression processing part, 210 Coding apparatus, 230 Decoding apparatus, 231 Communication Processing unit, 232 convolutional decoding unit, 233 deinterleaver, 234 Reed-Solomon SPA decoding unit, 240 decoding device, 244 Reed-Solomon SPA decoding unit, 245 interleaver, 250 recording / reproducing device, 260 encoding processing unit, 270 recording / reproducing processing unit, 280 decoding processing unit, 281-1 first Reed-Solomon SPA decoding unit, 300 recording device, 310 recording processing unit, 350 playback device, 360 playback processing unit, 400 recording / playback device, 410 decoding processing unit, 420-1 first decoding Part, 420-1- The first Reed-Solomon SPA decoding unit, 450 playback apparatus 460 and reproduction processing unit

Claims (14)

A linear code decoding device on ring R, comprising:
Linear combination calculation means for calculating a linear combination of each row of the check matrix of the linear code ;
From the set of vectors obtained by the linear combination calculated by the linear combination calculation means, a vector subset having a lower weight that extends the code complement space is extracted, and all the vectors of the vector subset are set as row components. A check matrix creating means for reducing the density of elements having a value of 1 by creating a new check matrix
A decoding device comprising: decoding means for decoding the linear code by a sum product algorithm using a new check matrix created by the check matrix creation means . The decoding apparatus according to claim 1, wherein the ring is a finite field based on a power of a prime number. The decoding apparatus according to claim 2, wherein the linear code includes a BCH code or a Reed-Solomon code on the finite field. The check matrix on the finite field, further comprising a deployment means for deploying at a predetermined dimension on the part of the finite field,
The decoding apparatus according to claim 2 , wherein the linear combination calculation unit calculates a linear combination of each row of the parity check matrix expanded by the expansion unit. A soft decision decoding means for soft decision decoding the convolutionally encoded linear code;
The decoding apparatus according to claim 1, wherein the linear combination calculation unit calculates a linear combination of each row of the parity code check matrix soft-decided by the soft-decision decoding unit. The soft decision decoding by the soft decision decoding means, the calculation by the linear combination calculation means, the creation of a new check matrix by the check matrix creation means, and the decoding by the decoding means are repeatedly executed. Item 6. The decoding device according to Item 5 . A method for decoding a linear code on ring R, comprising:
A linear combination calculation step of calculating a linear combination of each row of the check matrix of the linear code ;
From the vector set obtained by the linear combination calculated in the processing of the linear combination calculation, a vector subset having a lower weight that extends the code complement space is extracted, and all vectors of the vector subset are processed. A parity check matrix creating step for reducing the density of elements having a value of 1 by creating a new parity check matrix as a component;
And a decoding step of decoding the linear code by a sum product algorithm using a new parity check matrix created by the processing of the parity check matrix creation step . In a program for causing a computer to decode a linear code on the ring R,
A linear combination calculation step of calculating a linear combination of each row of the check matrix of the linear code ;
From the vector set obtained by the linear combination calculated in the processing of the linear combination calculation, a vector subset having a lower weight that extends the code complement space is extracted, and all vectors of the vector subset are processed. A parity check matrix creating step for reducing the density of elements having a value of 1 by creating a new parity check matrix as a component;
A program that causes a computer to execute processing including: a decoding step of decoding the linear code by a sum product algorithm using a new parity check matrix created by the processing of the parity check matrix creation step . A recording / reproducing apparatus for recording information on a recording medium and reproducing the information recorded on the recording medium,
Recording means for recording a linear code on the ring R on the recording medium;
Reproducing means for reproducing the linear code recorded by the recording means;
Linear combination calculation means for calculating a linear combination of each row of the check matrix of the linear code reproduced by the reproduction means ;
From the set of vectors obtained by the linear combination calculated by the linear combination calculation means, a vector subset having a lower weight that extends the code complement space is extracted, and all the vectors of the vector subset are set as row components. A check matrix creating means for reducing the density of elements having a value of 1 by creating a new check matrix
A recording / reproducing apparatus comprising: decoding means for decoding the linear code by a sum product algorithm using a new parity check matrix created by the parity check matrix creation means . A recording / reproducing method of a recording / reproducing apparatus for recording information on a recording medium and reproducing the information recorded on the recording medium,
A recording control step for controlling recording of the linear code on the ring R onto the recording medium;
A reproduction control step for controlling reproduction of the linear code whose recording is controlled by the processing of the recording control step;
A linear combination calculation step of calculating a linear combination of each row of the check matrix of the linear code whose reproduction is controlled by the processing of the reproduction control step;
From the vector set obtained by the linear combination calculated in the processing of the linear combination calculation, a vector subset having a lower weight that extends the code complement space is extracted, and all vectors of the vector subset are processed. A parity check matrix creating step for reducing the density of elements having a value of 1 by creating a new parity check matrix as a component;
And a decoding step of decoding the linear code by a sum product algorithm using the new parity check matrix created by the processing of the parity check matrix creation step . In a program for recording information on a recording medium and causing a computer to perform processing for reproducing the information recorded on the recording medium,
A recording control step for controlling recording of the linear code on the ring R onto the recording medium;
A reproduction control step for controlling reproduction of the linear code whose recording is controlled by the processing of the recording control step;
A linear combination calculation step of calculating a linear combination of each row of the check matrix of the linear code whose reproduction is controlled by the processing of the reproduction control step;
From the vector set obtained by the linear combination calculated in the processing of the linear combination calculation, a vector subset having a lower weight that extends the code complement space is extracted, and all vectors of the vector subset are processed. A parity check matrix creating step for reducing the density of elements having a value of 1 by creating a new parity check matrix as a component;
A program that causes a computer to execute processing including: a decoding step of decoding the linear code by a sum product algorithm using a new parity check matrix created by the processing of the parity check matrix creation step . A playback device for playing back information recorded on a recording medium,
Reproducing means for reproducing the linear code on the ring R recorded on the recording medium;
Linear combination calculation means for calculating a linear combination of each row of the check matrix of the linear code reproduced by the reproduction means ;
From the set of vectors obtained by the linear combination calculated by the linear combination calculation means, a vector subset having a lower weight that extends the code complement space is extracted, and all the vectors of the vector subset are set as row components. A check matrix creating means for reducing the density of elements having a value of 1 by creating a new check matrix
A playback apparatus comprising: decoding means for decoding the linear code by a sum product algorithm using a new check matrix created by the check matrix creation means . A playback method of a playback device for playing back information recorded on a recording medium,
A reproduction control step for controlling reproduction of a linear code recorded on the recording medium on the ring R;
A linear combination calculation step of calculating a linear combination of each row of the check matrix of the linear code whose reproduction is controlled by the processing of the reproduction control step;
From the vector set obtained by the linear combination calculated in the processing of the linear combination calculation, a vector subset having a lower weight that extends the code complement space is extracted, and all vectors of the vector subset are processed. A parity check matrix creating step for reducing the density of elements having a value of 1 by creating a new parity check matrix as a component;
And a decoding step of decoding the linear code by a sum product algorithm using a new parity check matrix created by the processing of the parity check matrix creation step . In a program for causing a computer to perform processing for reproducing information recorded on a recording medium,
A reproduction control step for controlling reproduction of a linear code recorded on the recording medium on the ring R;
A linear combination calculation step of calculating a linear combination of each row of the check matrix of the linear code whose reproduction is controlled by the processing of the reproduction control step;
From the vector set obtained by the linear combination calculated in the processing of the linear combination calculation, a vector subset having a lower weight that extends the code complement space is extracted, and all vectors of the vector subset are processed. A parity check matrix creating step for reducing the density of elements having a value of 1 by creating a new parity check matrix as a component;
A program that causes a computer to execute processing including: a decoding step of decoding the linear code by a sum product algorithm using a new parity check matrix created by the processing of the parity check matrix creation step .

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