JP4429415B2 - Semiconductor test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor test apparatus in which a logical comparator receives a strobe signal generated by a timing generator and performs timing determination. In particular, the present invention relates to a semiconductor test apparatus that improves the function of generating a high-accuracy strobe signal generated from a timing generator that performs timing determination.
[0002]
[Prior art]
The prior art will be described below with reference to FIGS. 4, 5, 6, 7, 8, and 9. Since the semiconductor test apparatus is known and well known in the art, a description of the overall system configuration is omitted except for the main part according to the present application.
[0003]
First, the configuration related to the strobe signal supplied to the DC of the conventional semiconductor test apparatus will be described. As shown in FIG. 4, the main components are a pattern generator PG, a timing generator TG, a timing controller TGC, a waveform shaper FC, and a logic comparator DC.
The PG supplies logical data (test pattern) to be applied to the device under test (DUT) to the FC, and supplies an expected value pattern EXP for determining pass / fail to the DC.
The FC receives logical data from the PG, receives a timing clock from the TG, converts it into a waveform of a predetermined timing, and applies a waveform that has been amplitude-converted to high / low predetermined voltages VIH and VIL by the driver to the DUT.
[0004]
The TG according to the present application supplies a predetermined timing clock to the FC and supplies a large number of strobe signals to the DC. Here, there are two types of strobe signals: an edge strobe signal and a multi-window strobe signal. The number and types of strobe signals that can be used per comparator channel differ depending on the system configuration. Here, as a representative value, as shown in FIG. 5, a case where there are a total of four edge strobe signals and two multi-window strobe signals per comparator channel will be described below.
[0005]
The DC according to the present application includes M comparator channels. The number of channels M varies depending on the system configuration, but it has several hundred channels or more. For each comparator unit of one channel, the response signal output from the DUT is converted into a logic signal by the analog comparator with predetermined threshold level voltages VOH and VOL. The DC receives the two converted logic signals DHi and DLow, selectively uses two types of strobe signals, latches the logic signals at a predetermined timing, and outputs a result of comparison with an expected value pattern.
[0006]
The two types of strobe signals include an edge strobe type and a window strobe type. As is well known, one edge strobe type latches the signal of the instantaneous timing of the edge, and the other window strobe type detects and latches the window period and is used for comparison with the expected value EXP.
Here, signals that do not require high accuracy, such as ranking, or those that require high accuracy for only one of the leading and trailing edges are called multi-window strobe signals, and both the leading and trailing edges require high accuracy. This will be described as a window strobe signal.
[0007]
As an example of using one window strobe signal, as shown in FIG. 8, a window period (see FIG. 8A) in which the timing of the leading edge and the trailing edge is defined with high accuracy is continuously detected. Then, for example, an instantaneous glitch (see FIG. 8B) is also detected and latched (see FIG. 8C), and used for subsequent comparison determination.
[0008]
As an application example of the other multi-window strobe signal, as shown in FIG. 9, it is used for ranking the setup time etc. output by the DUT using two multi-window strobe signals (see FIGS. 9A and 9B). For example, memory devices have different access time rankings. At this time, the timing accuracy of the leading and trailing edges that determine the window period may be slightly coarser than the window strobe signal.
9A, when the response signal output from the DUT is received at the timing of FIG. 9C, the fail signal FL1 is detected (see FIG. 9D) in the first window (see FIG. 9A), and the other The fail signal FL2 is not detected in the two windows (see FIG. 9B). As a result, it can be determined at a time that the DUT is a DUT having an access time later than that of the first window and earlier than that of the second window.
Similarly, in FIG. 9B, when the response signal output from the DUT is received at the timing shown in FIG. 9E, both fail signals FL1 and FL2 are detected (see FIGS. 9F and G). As a result, it can be determined at a time that the DUT has a later access time than the second window. As described above, when ranking the access time of the memory device or the like, it is possible to rank at least two ranks at a time. This means that when two or more multi-window strobe signals are provided, a plurality of ranks corresponding to the number of multi-window strobe signals can be implemented at one time. For example, three ranks can be divided into three ranks, and four ranks can be divided into four ranks at a time.
[0009]
The TGC according to the present application supplies a control signal for switching the operation mode related to the strobe of the TG to the TG and the DC. Usually, setting control is performed via a tester bus.
[0010]
Next, the connection configuration of the strobe signal system will be further described with reference to FIG.
FIG. 5 is a connection configuration diagram of one channel unit related to a strobe signal between TG and DC. Here again, a specific example assuming two edge strobe pulses and two window strobe pulses will be described below.
[0011]
The components in units of one channel include pulse generation circuits 101 and 102 and window waveform generation circuits 111 and 112 in TG, and pulse selection units 60 and 70 and fail determination unit 80 in DC. .
The pulse generation circuit 101 and the pulse generation circuit 102 are the same element. One pulse generation circuit 101 includes variable delay means inside, generates an edge pulse at a predetermined timing by a control signal from the TGC, and supplies this as a first edge strobe signal 101s to the DC via coaxial cable wiring. . As is well known, the variable delay means is a delay circuit that can be varied by setting digital data, and a predetermined timing accuracy is maintained by calibration. The other pulse generation circuit 102 is similar to the above, and generates the second edge strobe signal 102s and supplies it to the DC.
[0012]
The window waveform generation circuit 111 and the window waveform generation circuit 112 are the same element. As shown in FIG. 6A, the internal principle diagram of one window waveform generation circuit 111 is composed of pulse generation circuits 152 and 154 and a window pulse converting unit 156.
The pulse generation circuits 152 and 154 are equivalent to the above-described pulse generation circuit and need not be explained, but the timing accuracy may be slightly rough. The window pulse generation unit 156 generates a pulse having the edge pulse output from one pulse generation circuit 152 as a leading edge and the edge pulse output from the other pulse generation circuit 154 as a trailing edge, and this is generated as a first multi-window strobe. The signal 111s is supplied to the DC via coaxial cable wiring. The other window waveform generation circuit 112 is similar to the above, and generates the second multi-window strobe signal 112s and supplies it to the DC.
In the conventional configuration described above, the number of pulse generation circuits required for each comparator channel needs to be six. Accordingly, since the number of comparator channels M is several hundreds in the entire TG, the circuit scale becomes enormous.
[0013]
The pulse selection units 60 and 70 and the fail determination unit 80 will be described with reference to the internal principle configuration diagram of the timing determination unit in FIG.
The pulse selector 60 and the pulse selector 70 are the same element. One pulse selector 60 includes a flip-flop 62 and multiplexers 64 and 66. The flip-flop 62 generates a window pulse signal 62s defining the leading edge of the window with the first edge strobe signal 101s from the TG and defining the trailing edge of the window with the second edge strobe signal 102s, and supplies the window pulse signal 62s to the multiplexer 66. .
The multiplexer 64 is a 2-input 1-output type selector, receives the first edge strobe signal 101s and the first multi-window strobe signal 111s from the TG, selects one of them according to the control signal, and uses it as a first pulse signal 60s1. This is supplied to the first timing determination unit 81 of the fail determination unit 80.
The multiplexer 66 is a three-input one-output type selector that receives the window pulse signal 62 s, the second edge strobe signal 102 s from the TG, and the second multi-window strobe signal 112 s, and selects one by a control signal. The second pulse signal 60s2 is supplied to the second timing determination unit 82 of the fail determination unit 80.
[0014]
In the same manner as described above, the other pulse selection unit 70 supplies the selected third pulse signal 70s1 to the third timing determination unit 83 of the fail determination unit 80, and uses the fourth pulse signal 70s2 as the fourth timing determination of the fail determination unit 80. To the unit 84.
[0015]
The fail determination unit 80 includes a high side determination unit, a low side determination unit, a fail output unit 88, and a rank information storage unit 90. The high-side determination unit and the low-side determination unit are the same element although there is a difference in input signals.
An example of the internal configuration of one high-side determination unit includes a first timing determination unit 81, a second timing determination unit 82, and a multiplexer 85, and latches the high-side logic signal DHi at the timing of the strobe signal. The high-side fail signal FLH, which is compared with the value EXPH, is output from the multiplexer 85.
The first timing determination unit 81 receives the high-side logic signal DHi and determines the timing based on the first pulse signal 60s1. If the first pulse signal 60s1 is an edge pulse, the logic signal DHi at that time is latched and held at that edge, and the first fail signal 81f obtained by matching with the expected value EXPH is output. If the first pulse signal 60s1 is a multi-window signal, the target window period is detected and latched and compared with the expected value EXPH.
The same applies to the second timing determination unit 82, and a second fail signal 82f whose timing is determined by the second pulse signal 60s2 is output.
The multiplexer 85 receives both the fail signals 81f and 82f, and outputs a high-side fail signal FLH selected according to one of the control signals.
[0016]
The internal configuration of the low-side determination unit is the same as that of the above-described high-side determination unit. In the same manner as described above, the low-side logic signal DLow is latched at the timing of the strobe signal, and the low-side fail signal FLL that is compared with the expected value EXPL is output from the multiplexer 86.
[0017]
The fail output unit 88 receives the high-side fail signal FLH and the low-side fail signal FLL and determines whether the high-side fail signal FLH, the low-side fail signal FLL, or the logical sum of the two fail signals depends on the control signal. Is output as a fail signal FL of the comparator channel.
[0018]
The rank information storage unit 90 is a dedicated element for accumulating and storing determination information for performing device ranking separately from the above-described pass / fail determination of the device. In general, ranking is performed based on the determination results obtained many times when a device test for ranking is performed on non-defective devices.
As an example of this internal configuration, as shown in FIG. 6B, it is composed of OR gates 91 and 92 and flip-flops 93 and 94. One flip-flop 93 receives a fail signal obtained by logically summing the first fail signal 81f and the third fail signal 83f, and latches and holds it when detected once. The same applies to the other flip-flop 94. When the fail signal obtained by ORing the second fail signal 82f and the fourth fail signal 84f is detected even once, the latch is held. The CPU reads the two pieces of retained data 90s output from both flip-flops, and for example, ranks of access times of memory devices can be obtained. After reading, both flip-flops are reset to a standby state.
[0019]
[Problems to be solved by the invention]
As shown in the configuration example of FIG. 5, in the conventional technology, four edge strobe signals 101 s and 102 s and multi-window strobe signals 111 s and 112 s are individually supplied to the DC by coaxial cable wiring. By the way, there are almost no test conditions using both the edge strobe signal and the multi-window strobe signal at the same time. That is, in reality, two of the four strobe signals supplied to the DC are practically used at the same time. Accordingly, several hundreds of strobe signal lines are in the dormant state in all the comparator channels, and further, the pulse generation circuits extending over several hundred channels in the corresponding TG are also in the dormant state. This means that the strobe signal generation circuit and the strobe line are not used effectively.
On the other hand, if a plurality of ranks can be simultaneously performed in a single test, the number of times that the device test is performed a plurality of times by changing the timing of the multi-window strobe signal can be reduced, and the throughput of the device test can be greatly improved. For this reason, it is desired to increase the number of multi-window strobe signals for ranking.
Therefore, the problem to be solved by the present invention is a semiconductor that can reduce the number of strobe signals between TG and DC by integrating and supplying the edge strobe signal and the multi-window strobe signal on the TG side. It is to provide a test device.
[0020]
[Means for Solving the Problems]
First, in order to solve the above problem, in the configuration of the present invention, the response signal output from the device under test is converted into two high / low logic signals DHi and DLow, and the two converted logic signals A signal is supplied to a logical comparator (DC), and a timing generator (TG) generates both an edge strobe signal and a multi-window strobe signal and supplies the signal to DC, and one edge strobe signal is an instantaneous timing of the edge. The input logic signals DHi and DLow are latched and used for comparison judgment at the subsequent stage, and the other multi-window strobe signal is used for the window period in which the leading edge and the trailing edge are defined. In a semiconductor test apparatus having a configuration that is applied to detection and latching and subsequent comparison and determination,
Each strobe signal supplied from the TG side to the DC side is provided with first pulse generation means and second pulse generation means (for example, pulse generation circuits 101 and 102) that define two edges in the TG. First, when the control signal for selecting the form is received from the timing control unit (TGC) and output as the edge strobe signal, the edge pulse of the first pulse generating means is output from the TG as the dual strobe signal. When outputting as a multi-window strobe signal, the leading edge is defined by the edge pulse of the first pulse generating means, and the window pulse defining the trailing edge by the edge pulse of the second pulse generating means is output from the TG as a dual strobe signal. The semiconductor test apparatus includes an edge / window generation unit 120.
According to the above invention, it is possible to realize a semiconductor test apparatus capable of reducing the number of strobe signals between TG and DC by integrating and supplying the edge strobe signal and the multi-window strobe signal on the TG side.
[0021]
FIG. 3 shows the solution means according to the present invention.
Second, in order to solve the above problem, in the configuration of the present invention, the DC receives the dual strobe signal for each unit of two channels in which TG is generated, and one of the dual timing strobe signals directly corresponds to one timing determination unit. 81 and 83, when the control signal for first selecting the generation form in the other dual-use strobe signal is to generate the edge strobe signal, it passes as it is and the other timing determination unit 82 and 84 corresponding thereto. When the second window strobe signal is to be generated, a window strobe signal defining the leading edge and the trailing edge is generated at the edges of both the dual strobe signals, and the corresponding timing determination unit 82, The semiconductor test apparatus described above is characterized in that the edge / window generation unit 120 to be supplied to 84 is provided in the DC.
[0022]
FIG. 10 shows a solution means according to the present invention.
Thirdly, in order to solve the above-mentioned problem, in the configuration of the present invention, in the dual strobe signal for every two channels generated and generated inside the TG,
The output of one generation channel is supplied as it is to the DC as the dual-use strobe signal 302s, and when the control signal for selecting the generation mode is to be the generation of the edge strobe signal in the output of the other generation channel, it passes as it is. When the window strobe signal is to be generated and the second is to generate the window strobe signal, the edge / window generation that generates the window strobe signal that defines the leading edge and the trailing edge at the edge output from both generation channels and supplies it to the DC There is the above-described semiconductor test apparatus characterized in that the unit 120 is provided inside the TG.
[0023]
FIG. 11 shows the solving means according to the present invention.
Also, there is the above-described semiconductor test apparatus characterized by comprising a configuration for supplying at least two or more dual-use strobe signals for each channel unit of DC from TG.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings together with examples.
[0025]
The present invention will be described below with reference to FIG. 1, a principle connection configuration diagram in the case of supplying two window strobe pulses, FIG. 2 and FIG. In addition, the element corresponding to a conventional structure attaches | subjects the same code | symbol. Further, the number of strobe signals required on the DC side is assumed to be two edge strobe signals and two multi-window strobe signals as in the conventional case.
[0026]
First, the configuration related to the strobe signal supplied to the DC of the present invention will be described.
As shown in FIG. 1, the components per comparator channel in the TG are composed of dual strobe generators 301 and 302. This is achieved by incorporating a 4-channel pulse generation circuit in both. Conventionally, a pulse generation circuit for 6 channels is required from FIG. 5 and FIG. Therefore, in the present invention, the configuration is reduced by two channels.
The dual strobe generator 301 and the dual strobe generator 302 are the same element. One dual strobe generator 301 generates a first dual strobe signal 301s. This internal configuration includes pulse generation circuits 101 and 102 and an edge / window generator 120. Here, the pulse generation circuits 101 and 102 are the same as those in the prior art, and need not be described.
[0027]
The edge / window generator 120 generates an edge strobe signal or a multi-window strobe signal. An example of this internal configuration can be realized by a flip-flop 62 and a multiplexer 64 as shown in FIG.
The flip-flop 62 outputs a window pulse signal 62s defining the leading edge of the window with the first edge strobe signal 101s and defining the trailing edge of the window with the second edge strobe signal 102s.
The multiplexer 64 is a two-input one-output selector, receives the second edge strobe signal 102s and the window pulse signal 62s, selects one of them according to the control signal, and uses the DC-side timing as the first dual strobe signal 301s. Supply to the determination unit.
[0028]
The other dual strobe generation unit 302 is similar to the above, and includes pulse generation circuits 103 and 104 and an edge / window generation unit 120 to generate a second dual strobe signal 302s and supply it to the timing determination unit.
[0029]
Next, a timing determination unit per one comparator channel on the DC side will be described with reference to FIG. An example of the internal configuration of the timing determination unit includes an edge / window generation unit 120 and a fail determination unit 80 as shown in FIG. Here, the fail determination unit 80 is the same as the conventional one.
The edge / window generation unit 120 generates and outputs a high-precision window strobe signal using two high-precision edges in order to maintain compatibility with the conventional one. This can be realized by the internal configuration of FIG. Normally, the second dual-purpose strobe signal 302s is output as it is, but when a control signal using a high-precision window strobe signal is given, it is generated from the first dual-purpose strobe signal 301s by the flip-flop 62 shown in FIG. The window pulse signal 62s defining the leading edge of the window with the high-precision edge strobe signal and the trailing edge of the window defined with the high-precision edge strobe signal generated from the second dual-purpose strobe signal 302s And supplies this to the fail determination unit 80 shown in FIG.
On the TG side, if the pulse generation circuits 103 and 104 are configured such that the multi-window strobe signal generated by the second dual strobe signal 302s generates the leading edge and the trailing edge with high accuracy, The window generation unit 120 can be deleted.
[0030]
According to the above-described configuration of the present invention, the edge strobe signal and the multi-window strobe signal are integrated into one on the TG side, so that a conventional 6-channel pulse generating circuit is required per comparator channel on the TG side. This can be realized with a 4-channel pulse generation circuit. As a result, an advantage that the pulse generation circuits for 2 channels can be reduced is obtained. Therefore, since the number of comparator channels M is several hundreds in the entire DC, a great advantage can be obtained that a large number of 2 × M pulse generation circuits can be reduced.
Furthermore, since the number of coaxial cables for strobe signals connecting between TG and DC can be reduced from four to two, a great advantage can be obtained in that many 2 × M coaxial cables can be reduced. It becomes. On the other hand, when the same number of coaxial cable wirings are used, the advantage that two lines of multi-window strobe signals can be added is obtained.
[0031]
The constituent means of the present invention is not limited to the above-described embodiment. For example, as shown in FIG. 10, an edge / window generation unit 120 provided on the DC side may be provided on the TG side.
In addition, as shown in FIG. 11, the number of the dual strobe signals supplied to the timing determination unit for one channel may be a desired N number of two or more. For example, as shown in the internal configuration example in the case of four dual-use strobe signals 301 s to 304 s in FIG. 12, four high-side timing determination units and low-side timing determination units corresponding to the number N = 4 of dual-use strobe signals. By providing the corresponding multiplexers 85 and 86 and the rank information storage unit 90, it can be realized in the same manner as described above. In the case of four, there is an advantage that the rank can be divided into four ranks at a time.
[0032]
【The invention's effect】
The present invention has the following effects from the above description.
As described above, according to the present invention, the configuration means for integrating the edge strobe signal and the multi-window strobe signal on one side on the TG side is realized, thereby reducing the number of pulse generation circuits for two channels per comparator channel. The advantage is that all comparator channels have the advantage of reducing hundreds of channels of pulse generation circuits. Furthermore, there is an advantage that the number of coaxial cables for strobe signals connecting between TG and DC can be reduced by two per one comparator channel, and a great advantage that several hundred or more can be reduced in all comparator channels.
Accordingly, the circuit scale of the TG can be greatly reduced, and the test apparatus can be realized at a lower cost. Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.
[Brief description of the drawings]
FIG. 1 is a principle connection configuration diagram in the case of supplying two edge strobe pulses and two window strobe pulses per comparator channel according to the present invention.
2 shows an example of the internal configuration of the edge / window generator of FIG. 1 according to the present invention.
FIG. 3 is a principle configuration diagram of one DC channel according to the present invention.
FIG. 4 is a conceptual configuration diagram relating to generation of a strobe signal in a semiconductor test apparatus.
FIG. 5 is a principle connection configuration diagram in the case where two edge strobe pulses and two window strobe pulses are supplied per channel between TG and DC.
FIG. 6 is an internal principle diagram of a window waveform generation circuit and an internal principle diagram of a rank information storage unit.
FIG. 7 is a principle configuration diagram per DC channel.
FIG. 8 is a timing diagram illustrating the principle of window strobe detection.
FIG. 9 is a timing chart for explaining determination of IC ranking using two window strobes.
FIG. 10 is a principle connection configuration diagram in the case of supplying two dual-use strobe signals per channel between TG and DC according to the present invention.
FIG. 11 is a principle connection configuration diagram in the case of supplying N dual-purpose strobe signals per channel between TG and DC according to the present invention.
FIG. 12 is a diagram showing an internal principle configuration on the DC side when four dual-purpose strobe signals are supplied per DC channel according to the present invention.
[Explanation of symbols]
60, 70 Pulse selector
62, 93, 94 Flip flop
64, 66, 85, 86 Multiplexer
80 Fail judgment part
81, 82, 83, 84 Timing determination unit
88 Fail output section
90 rank information storage
91,92 OR gate
101, 102, 103, 104, 152, 154 Pulse generation circuit
111, 112 window waveform generation circuit
120 edge / window generator
156 Window pulse generator
Strobe generator for 301,302
DC logic comparator
DUT Device under test
FC waveform shaper
PG pattern generator
TG timing generator
TGC timing controller

Claims (5)

The response signal output from the device under test (DUT) is converted into two high / low logic signals, the two converted logic signals are supplied to the logic comparator (DC), and the timing generator (TG) Generates both an edge strobe signal and a multi-window strobe signal and supplies them to the DC, and one edge strobe signal latches the input logic signal at the instant timing of the edge and uses it for the subsequent comparison judgment, In the semiconductor test apparatus having a configuration in which the multi-window strobe signal is applied to detection and latching of an input logic signal for a window period in which a leading edge and a trailing edge are defined, and applied to comparison and determination at a subsequent stage.
For each strobe signal supplied from the TG side to the DC side, first pulse generating means and second pulse generating means for defining two edges in the TG, and first, when outputting as an edge strobe signal The edge pulse of the first pulse generating means is output from the TG as a dual strobe signal. Second, when outputting as a multi-window strobe signal, the leading edge is defined by the edge pulse of the first pulse generating means, and the second pulse is generated. A first edge / window generator for outputting a window pulse defining a trailing edge by means of an edge pulse of the means from the TG as a dual strobe signal;
A second edge / window generator that further defines a leading edge and a trailing edge of the window for the signal output as the multi-window strobe signal;
Equipped with,
A semiconductor test apparatus, wherein the second edge / window generator controls the accuracy of window edges . The DC receives the dual strobe signal for every two channel units in which TG is generated,
One dual-use strobe signal is supplied to the corresponding one timing judgment unit as it is,
In the other dual-use strobe signal, when the control signal for selecting the generation form is to be the generation of the edge strobe signal, it passes as it is and is supplied to the corresponding other timing determination unit, and secondly the window strobe signal. In the DC, a configuration is provided in which a window strobe signal defining a leading edge and a trailing edge at the edges of both dual strobe signals is generated and supplied to the corresponding other timing determination unit. The semiconductor test apparatus according to claim 1. In the dual-channel strobe signal for each two-channel unit generated and generated inside the TG,
The output of one of the generation channels is supplied as it is to the DC as a dual strobe signal,
In the output of the other generation channel, when the control signal for selecting the generation form is first to generate the edge strobe signal, it passes through and is output, and secondly to generate the window strobe signal. 2. The semiconductor test apparatus according to claim 1, further comprising a configuration in which a window strobe signal defining a leading edge and a trailing edge at edges output from both generation channels is generated and supplied to a DC.   4. The semiconductor test apparatus according to claim 1, further comprising a configuration for supplying at least two or more dual-use strobe signals for each channel unit of DC from TG.   The response signal output from the device under test (DUT) is converted into two high / low logic signals, the two converted logic signals are supplied to the logic comparator (DC), and the timing generator (TG) Generates both an edge strobe signal and a multi-window strobe signal and supplies them to the DC, and one edge strobe signal latches the input logic signal at the instant timing of the edge and uses it for the subsequent comparison judgment, The multi-window strobe signal is a semiconductor test apparatus having a configuration in which an input logic signal is detected and latched with respect to a window period in which a leading edge and a trailing edge are defined, and applied to comparison and determination at a subsequent stage.
  For each strobe signal supplied from the TG side to the DC side, first pulse generating means and second pulse generating means for defining two edges in the TG, and first, when outputting as an edge strobe signal The edge pulse of the first pulse generating means is output from the TG as a dual strobe signal. Second, when outputting as a multi-window strobe signal, the leading edge is defined by the edge pulse of the first pulse generating means, and the second pulse is generated. An edge / window generator for outputting a window pulse defining a trailing edge with an edge pulse of the means from the TG as a dual strobe signal;
A second edge / window generator that further defines a leading edge and a trailing edge of the window for the signal output as the multi-window strobe signal;
A determination unit for determining two or more different high-side timings and two or more low-side timings;
With
At least two or more window strobe signals having different window periods are generated for each channel unit from TG to DC, and the DUT is ranked into two or more ranks based on the test result using each window strobe signal. A semiconductor test apparatus.

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