JP4421734B2 - Encoded data conversion method and data recording medium - Google Patents

Description

【０１２８】
また、上記第１，第２の模擬符号化処理により得られる符号化単位当たりのビット数（第１，第２の模擬符号化ビット数）Ｒａ，Ｒｂの差分ΔＲabは、以下の式４により表される。ただしここでは、第２の模擬符号化処理における量子化ステップＱｂは、第１の模擬符号化処理における量子化ステップＱａより大きいため、第２の模擬符号化ビット数Ｒｂは、第１の模擬符号化ビット数Ｒａより小さい。
ΔＲab＝Ｒａ−Ｒｂ （式４）
【０１２９】
そこで、上記再符号化誤差増加率（ビットレートの単位変動量当りの模擬符号化ビット数の変動分）λ１は、以下の式５により表される。

【０１３０】
一般に、符号化処理における量子化ステップが大きくなると、符号化ストリームにおける、単位ビット数当りの符号化誤差の変動分が大きくなる。
このため、各符号化単位毎に最適量子化ステップＱｄとして、第１の模擬符号化処理における量子化ステップＱａ及び第２の模擬符号化処理における量子化ステップＱｂの一方を選択する量子化ステップ導出器Ｕ７４では、上記再符号化誤差増加率λ1が１フレームにおける各符号化単位の間でできるだけ同じ値となるようにするための誤差最小化の条件は、上記再符号化誤差増加率λ1が小さい符号化単位に対しては最適量子化ステップＱｄとして、大きい方の量子化ステップＱｂを用い、上記再符号化誤差増加率λ1が大きい符号化単位に対しては最適量子化ステップＱｄとして、小さい方の量子化ステップＱａを用いるというものとなる。
【０１３１】
図１３は、上記実施の形態４の再符号化システム４０を構成する量子化ステップ導出器Ｕ７４の具体的構成を示すブロック図である。
上記量子化ステップ導出器Ｕ７４は、上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂからの第１，第２の模擬符号化処理により発生する、各符号化単位に対応する第１，第２の模擬符号化ビット数Ｒａ，Ｒｂを受け、これらの模擬符号化ビット数の差分を模擬符号化ビット数増加量ΔＲabとして算出するビット数減算器Ｕ８ｂと、上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂからの、各符号化単位に対応する模擬符号化誤差（再符号化増加誤差）Ｄａ，Ｄｂを受け、これらの再符号化増加誤差の差分を模擬符号化誤差増加量Ｄabとして算出する誤差減算器Ｕ９ｂとを有している。
【０１３２】
また、上記量子化ステップ導出器Ｕ７４は、模擬符号化誤差増加量ΔＤabを模擬符号化ビット数増加量ΔＲabにより除算して、各符号化単位に対応する再符号化誤差増加率λ1を導出する除算器Ｕ１０ｂと、上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂからの、各符号化単位に対応する量子化ステップＱａ，Ｑｂの一方を、制御信号Ｑse１に基づいて選択して、処理対象となっている符号化単位に対応する最適量子化ステップＱｄとして出力する選択スイッチＵ１４と、各符号化単位の間で再符号化誤差増加率λ1の大きさを比較し、フレームビット数（１フレーム分の再符号化ストリームにおけるビット数）がフレーム目標ビット数Ｒｄとなるよう、制御信号Ｑse１により上記選択スイッチ１４を制御する最小誤差選択器Ｕ２０とを有している。
【０１３３】
次に動作について説明する。
この再符号化システム４０に入力ストリームＶinが供給されると、復号化器Ｕ１では、符号化ストリームである入力ストリームＶinに対して、逆量子化処理を含む復号化処理が施され、復号化ストリーム（復号画像データ）Ｖdec及び上記逆量子化処理における量子化ステップＱinが各符号化単位毎に出力される。
すると、第１の模擬符号化器Ｕ２ａでは、第１の模擬メモリＵ３ａに格納されている参照画像データＶａあるいは主メモリＵ３ｄに格納されている参照画像データＶrefaを参照して、処理対象となっている対象画面の復号化ストリームＶdecに対して、量子化ステップＱａによる量子化処理及び局所復号化処理を含む第１の模擬符号化処理が符号化単位毎に施される。なお、上記量子化ステップＱａは上記逆量子化処理で用いられた量子化ステップＱinより小さくならいよう設定される。これにより上記第１の模擬符号化器Ｕ２ａからは、局所復号化画像データＶstraが出力されるとともに、上記量子化ステップＱａ，模擬符号化ビット数Ｒａ，及び模擬符号化誤差Ｄａが出力される。
【０１３４】
同様に、第２の模擬符号化器Ｕ２ｂでは、第２の模擬メモリＵ３ｂに格納されている参照画像データＶｂあるいは主メモリＵ３ｄに格納されている参照画像データＶrefbを参照して、処理対象となっている対象画面の復号化ストリームＶdecに対して、量子化ステップＱｂによる量子化処理及び局所復号化処理を含む第２の模擬符号化処理が施される。なお、上記量子化ステップＱｂは、上記第１の模擬符号化処理に含まれる逆量子化処理における量子化ステップＱinより小さくならず、かつ上記量子化ステップＱａより大きな値になるよう設定される。これにより上記第２の模擬符号化器Ｕ２ｂからは、局所復号化画像データＶstrbが出力されるとともに、上記量子化ステップＱｂ，模擬符号化ビット数Ｒｂ，及び模擬符号化誤差Ｄｂが出力される。
【０１３５】
このとき、上記第１，第２の模擬メモリＵ３ａ，Ｕ３ｂには上記局所復号化画像データＶstra、Ｖstrbが、符号化処理済みの画面（フレーム）に対応する画像データとして格納される。このように第１，第２の模擬メモリＵ３ａ，Ｕ３ｂに格納された画像データは、未処理画面に対応する復号化データの符号化処理の際に、上記参照画像データＶａ，Ｖｂとして用いられる。
【０１３６】
そして、上記量子化ステップ導出部Ｕ７４では、上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂからの量子化ステップＱａ，Ｑｂ、模擬符号化ビット数Ｒａ，Ｒｂ、及び模擬符号化誤差Ｄａ，Ｄｂに基づいて、処理対象となっている対象画面に対応する符号化ビット数がフレーム目標ビット数Ｒｄを超えないよう、各符号化単位に対応する最適量子化ステップＱｄを導出する処理が行われる。
【０１３７】
この最適量子化ステップＱｄは主符号化器Ｕ２ｄに供給され、該主符号化器Ｕ２ｄでは、上記復号画像データＶdecに対して、量子化ステップＱｄによる量子化処理及び局所復号化処理を含む再符号化処理が、主メモリＵ３ｄに格納されている参照画像データＶrefdを参照して施される。これにより、主符号化器Ｕ２ｄからは再符号化ストリームＶoutが出力されるとともに、局所復号化画像データＶstrdが出力される。
【０１３８】
このとき、上記主メモリＵ３ｄには上記局所復号化画像データＶstrdが、符号化処理済みの画面（フレーム）に対応する画像データとして格納される。このように主メモリＵ３ｄに格納された画像データは、未処理画面に対応する画像データの再符号化処理の際に上記参照画面データＶrefdとして用いられ、また、未処理画面に対応する画像データの第１，第２の模擬符号化処理の際にも、上記参照画面データＶrefa，Ｖrefbとして用いられる。
【０１３９】
なお、上記主メモリＵ３ｄには、実際に出力されている再符号化ストリームＶoutに対応する局所復号化画像データが格納されているため、上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂでは、主メモリＵ３ｄに格納されている各符号化済み画面の画像データのうち、第１，第２の模擬メモリＵ３ａ，Ｕ３ｂに格納されている符号化済み画面の画像データと同一の画面に対応する画像データについては、第１，第２の模擬メモリＵ３ａ，Ｕ３ｂに格納されている符号化済み画面の画像データ（参照画像データ）Ｖａ，Ｖｂに代えて、主メモリＵ３ｄに格納されている各符号化済み画面の画像データが参照画像データＶrefa，Ｖrefとして用いられる。
【０１４０】
また、上記再符号化ストリームＶoutはフレーム目標ビット数計算器Ｕ６に供給され、該計算器Ｕ６では、再符号化ストリームＶoutのビットレートと外部から供給される目標ビットレートＲａｔｅとに基づいて、処理済み画面につづく処理対象画面に対応するフレーム目標ビット数Ｒｄが計算され、上記量子化ステップ導出器Ｕ７４に出力される。
【０１４１】
以下、上記量子化ステップ導出器Ｕ７４の具体的な動作について説明する。
まず、ビット数減算器Ｕ８ｂでは、第１の模擬符号化ビット数Ｒａから第２の模擬符号化ビット数Ｒｂを引き算する減算処理が行われて、これらの模擬符号化ビット数の差分（模擬符号化ビット数変動量）ΔＲabが算出される。また、誤差減算器Ｕ９ｂでは、上記第２の模擬符号化器Ｕ２ｂからの模擬符号化誤差Ｄｂから上記第１の模擬符号化器Ｕ２ａからの模擬符号化誤差Ｄａを引き算する減算処理が行われて、これらの模擬符号化誤差の差分（模擬符号化誤差変動量）ΔＤabが算出される。さらに、除算器Ｕ１０ｂでは、模擬符号化誤差変動量ΔＤabを模擬符号化ビット数変動量ΔＲabにより除算する演算処理が行われて、上記再符号化誤差増加率λ１が導出される。
【０１４２】
そして、最小誤差選択器Ｕ２０では、各符号化単位の間で再符号化誤差増加率λ1の大きさを比較する処理が行われ、フレームビット数（１フレーム分の再符号化ストリームにおけるビット数）がフレーム目標ビット数Ｒｄを超えないよう、上記比較処理結果に応じて、各符号化単位毎に上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂからの量子化ステップＱａ，Ｑｂの一方を選択するための制御信号Ｑse１が選択スイッチＵ１４に出力される。
該選択スイッチＵ１４では、上記制御信号Ｑse１に基づいて、上記量子化ステップＱａ，Ｑｂの一方が各符号化単位毎に選択され、選択された量子化ステップが最適量子化ステップＱｄとして出力される。
【０１４３】
次に、上記最小誤差選択器Ｕ２０の具体的な動作について説明する。
図１４は、上記最小誤差選択器Ｕ２０により各符号化単位の最適量子化ステップを導出する処理を説明するための図である。図１４(a)は、該量子化ステップ導出処理のフローを示し、図１４(b)は、１画面（１フレーム）における符号化単位の配列を示している。また、図１４(c)は、１フレームにおける各符号化単位に対応する最適量子化ステップＱｄが、上記第１，第２の模擬符号化処理における量子化ステップＱａ，Ｑｂのいずれかに設定された状態を模式的に示している。
【０１４４】
ここで、符号化単位は、１画面（フレーム）における１６×１６画素からなる表示領域（マクロブロック）とし、１フレームにおけるマクロブロックの数をｎ個とする。また、１フレームにおけるｉ（ｉ＝１，２，…，ｎ）番目のマクロブロックＢ［ｉ］に対応する量子化ステップを示す変数をＱ［ｉ］とし、ｉ番目のマクロブロックＢ［ｉ］に対応する復号画像データに対して、量子化ステップＱａ，Ｑｂによる量子化処理を含む模擬符号化処理を施して得られる模擬符号化ビット数をそれぞれ、Ｒａ［ｉ］，Ｒｂ［ｉ］とする。なお、以下、図４に関する説明ではマクロブロックを単にブロックという。
【０１４５】
上記最小誤差選択器Ｕ２０にて、処理対象となっている対象画面（被処理フレーム）における各ブロックの最適量子化ステップを決定する処理では、まず、各ブロックＢ［ｉ］の復号画像データに対して量子化ステップＱａ，Ｑｂによる量子化処理を含む第１，第２の模擬符号化処理を施した場合の第１，第２の模擬符号化ビット数Ｒａ［ｉ］，Ｒｂ［ｉ］が求められ、さらに被処理フレームにおける全ブロックの第１の模擬符号化ビット数Ｒａ［ｉ］の和Ｒ（＝ΣＲａ［ｉ］）が算出される（ステップＳ１）。
【０１４６】
次に、被処理フレームにおける全ブロックについて、対応する量子化ステップを示す変数Ｑ［ｉ］が上記量子化ステップＱａにより初期化される（ステップＳ２）。つまり、この時点で、被処理フレームにおける各ブロックＢ［ｉ］に対応する量子化ステップＱ［ｉ］が一旦すべてＱ［ｉ］＝Ｑａとなる。この結果、被処理フレームにおける全ブロックの模擬符号化ビット数Ｒａ［ｉ］の和Ｒは、Ｒ＝ΣＲａ［ｉ］となる。
その後、その量子化ステップＱ［ｉ］がＱａであり、かつ再符号化誤差増加率λ1（＝（Ｄｂ−Ｄａ）／（Ｒａ−Ｒｂ））が最小となるブロックＢ［ｋ］を検索する処理が行われる（ステップＳ３）。
【０１４７】
続いて、該検索処理により見つけられたブロックＢ［ｋ］の量子化ステップＱ［ｋ］が、量子化ステップＱａからこれより大きい量子化ステップＱｂに変更され、被処理フレームにおける全ブロックの模擬符号化ビット数の和Ｒが、Ｒ＋Ｒｂ［ｋ］−Ｒａ［ｋ］に更新される（ステップＳ４）。
【０１４８】
そして、上記被処理フレームにおける全ブロックの模擬符号化ビット数の和Ｒがフレーム目標ビット数Ｒｄより大きいか否かの判定が行われる（ステップＳ５）。この判定の結果、模擬符号化ビット数の和Ｒがフレーム目標ビット数Ｒｄより大きければ、再度上記ステップＳ３〜ステップＳ５の処理が繰り返し行われる。一方、上記ステップＳ５での判定の結果、模擬符号化ビット数の和Ｒがフレーム目標ビット数Ｒｄ以下であれば、この時点での被処理フレームにおける各ブロックの量子化ステップＱ［ｉ］の値（ＱａあるいはＱｂ）（図１４(c)参照）が、各ブロックに対応する最適量子化ステップＱｄとして出力される（ステップＳ６）。
【０１４９】
このように本実施の形態４の再符号化システム４０では、入力ストリームを復号化して得られる被処理フレームに対応する復号画像データ（復号化ストリーム）Ｖdecに対して、予め量子化ステップＱａ，Ｑｂによる量子化処理を含む第１，第２の模擬符号化処理を符号化単位毎に施す第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂを備え、該各模擬符号化処理の結果から各符号化単位に対応する再符号化誤差増加率λ１を求め、被処理フレームにおけるすべての符号化単位の符号化ビット数の総和が目標フレームビット数Ｒｄを越えないよう、被処理フレームにおける再符号化誤差増加率λ１が小さい符号化単位から順に上記両量子化ステップのうちの大きい方Ｑｂを割り当て、被処理フレームにおける残りの符号化単位にその小さい方Ｑａを割り当てる処理を行うので、被処理フレームにおける各符号化単位に対応する再符号化誤差増加率が一定値に近づくこととなる。これにより入力ストリームＶinに含まれる符号化誤差がわからない再符号化処理においても再符号化誤差を小さくすることができ、再符号化ストリームＶoutから再生される画像の画質の劣化を小さく抑えることができる。
【０１５０】
なお、上記実施の形態４では、符号化処理の単位をマクロブロック（１フレームにおける１６×１６画素からなる領域）としているが、符号化処理の単位は上記のようなＭＰＥＧにおけるマクロブロックに限るものではない。例えば、上記符号化処理の単位は、上記マクロブロックを構成する８×８画素からなるサブブロック、あるいは上記マクロブロック数個から構成されるスライスなどであってもよい。
【０１５１】
また、上記実施の形態４では、再符号化システムとして、第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂでは主符号化器Ｕ２ｄでの再符号化処理の対象となるフレームに対してのみ、量子化処理を含む模擬符号化処理を行うものを示しているが、上記再符号化システムの構成はこれに限るものではない。
例えば、再符号化システムは、ＭＰＥＧにおける画面間予測符号化処理を行う場合には、第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂでは、主符号化器Ｕ２ｄでの再符号化処理の対象となる被処理フレームに対してだけでなく、再符号化処理の際にこの被処理フレームを参照フレームとして用いるその他のフレームに対しても模擬符号化処理を施す構成であってもよい。
【０１５２】
つまりこのような構成の再符号化システムでは、具体的には、主符号化器Ｕ２ｄにて、図２４に示す表示時刻Ｔ３が設定されているＰフレームＦ（３）に対する再符号化処理を行う場合、上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂにて、該ＰフレームＦ（３）に対してだけでなく、表示時刻Ｔ２，Ｔ４が設定されているＢフレームＦ（２），Ｔ（４）及び表示時刻Ｔ５が設定されているＰフレームＦ（５）に対しての模擬符号化処理が施される。また、各フレームＦ（２）〜Ｆ（５）におけるすべての符号化単位毎に、対応する模擬符号化増加誤差Ｄａ，Ｄｂ、模擬符号化ビット数Ｒａ，Ｒｂが計算され、再符号化誤差増加率λ１が求められる。そしてさらに、上記フレームＦ（３）における各符号化単位には、各フレームＦ（２）〜Ｆ（５）におけるすべての符号化単位毎に対応する再符号化誤差増加率λ１に基づいて、最適量子化ステップとして、上記量子化ステップＱａ，Ｑｂの一方が設定される。
【０１５３】
この場合、フレームＦ（３）における各符号化単位に対応する最適量子化ステップは、フレームＦ（３），Ｆ（２），Ｆ（４），Ｆ（５）に対応する符号化誤差が最小化するよう設定される。
なお、ここで、ＰフレームＦ（３）は、その画像データがＢフレームＦ（２），Ｔ（４），及びＰフレームＦ（５）に対する画面間符号化処理の際に参照されるフレームであることは言うまでもない。
【０１５４】
（実施の形態５）
図１５は本発明の実施の形態５による再符号化システムを説明するためのブロック図である。
本実施の形態５の再符号化システム５０は、上記実施の形態４の再符号化システム４０における第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂに加えて、上記復号化器Ｕ１からの画像復号データ（復号化ストリーム）Ｖdecに対して、参照画面の画像データを参照して、上記量子化ステップＱｂより大きい量子化ステップＱｃによる量子化処理及び局所復号化処理を含む第３の模擬符号化処理を符号化単位毎に施す第３の模擬符号化器Ｕ２ｃを有している。この第３の模擬符号化器Ｕ２ｃは、上記第３の模擬符号化処理に含まれる局所復号化処理により得られる局所復号画像データＶstrcを出力するとともに、該模擬符号化処理に含まれる量子化処理にて用いた量子化ステップＱｃ，該模擬符号化処理により生じた符号化誤差（模擬符号化増加誤差）Ｄｃ，及び該模擬符号化処理により発生した模擬符号化ビット数Ｒｃを、各符号化単位毎に出力するよう構成されている。
【０１５５】
また、この再符号化システム５０は、上記実施の形態４の再符号化システム４０における第１，第２の模擬メモリＵ３ａ，Ｕ３ｂに加えて、上記第３の模擬符号化器Ｕ２ｃから出力される局所復号画像データＶstrcを格納する第３の模擬メモリＵ３ｃを有している。また、この第３の模擬メモリＵ３ｃは、上記第３の模擬符号化器Ｕ２ｃからの局所復号画像データＶstrcを格納し、該格納した画像データを、上記被処理画面に続く未処理画面の模擬符号化処理の際に参照画面の画像データＶｃとして第３の模擬符号化器Ｕ２ｃに出力する構成となっている。
【０１５６】
さらに、この再符号化システム５０では、上記主メモリＵ３ｄは、上記格納された局所復号画像データＶstrdを、被処理画面に続く未処理画面に対する再符号化処理の際に参照画面の画像データ（参照画像データ）Ｖrefdとして上記主符号化器Ｕ２ｄに出力するとともに、被処理画面に続く未処理画面に対する第１，第２，第３の模擬符号化処理の際に参照画面の画像データ（参照画像データ）Ｖrefa，Ｖrefb，Ｖrefcとして、上記第１，第２，第３の模擬符号化器Ｕ２ａ，Ｕ２ｂ，Ｕ２ｃに出力する構成となっている。
【０１５７】
このように、主メモリＵ３ｄには、実際に出力されている再符号化ストリームに対応する局所復号化画像データが格納されているため、上記第１，第２，第３の模擬符号化器Ｕ２ａ，Ｕ２ｂ，Ｕ２ｃは、主メモリＵ３ｄに格納されている各符号化済み画面の画像データのうち、第１，第２，第３の模擬メモリＵ３ａ，Ｕ３ｂ，Ｕ３ｂに格納されている符号化済み画面の画像データと同一の画面に対応する画像データについては、第１，第２，第３の模擬メモリＵ３ａ，Ｕ３ｂ，Ｕ３ｃに格納されている符号化済み画面の画像データＶａ，Ｖｂ，Ｖｃに代えて、主メモリＵ３ｄに格納されている各符号化済み画面の画像データＶrefa，Ｖrefb，Ｖrefcを参照するようになっている。
【０１５８】
また、この再符号化システム５０は、上記実施の形態４の再符号化システム４０におけるフレーム目標ビット数計算器Ｕ６に代えて、主符号化器Ｕ２ｄからの再符号化ストリームＶoutに基づいて、再符号化ストリームＶoutのビットレート（現在のビットレート）を外部からの目標ビットレートＲａｔｅと比較し、この比較結果に応じて、被処理フレームに対応する再符号化誤差増加率λをフレーム毎に計算するレート歪計算器Ｕ５を有している。
【０１５９】
ここで、このレート歪計算器Ｕ５では、各フレームに対応する再符号化ストリームＶoutに基づいて、符号化処理中のフレーム（被処理フレーム）の平均的なビットレートが目標ビットレートより大きくなりそうであれば、符号化処理の対象となっている符号化単位に対応する再符号化誤差増加率λとして大きな値を出力し、符号化処理中のフレーム（被処理フレーム）の平均的なビットレートが目標ビットレートより少なくなりそうであれば、符号化処理の対象となっている符号化単位に対応する再符号化誤差増加率λとして小さな値を出力する構成となっている。これは、この実施の形態５の再符号化システム５０では、再符号化誤差増加率λが大きければ、最適量子化ステップＱｄが大きくなって再符号化ストリームＶoutのビットレートが減少し、一方再符号化誤差増加率λが小さければ、最適量子化ステップＱｄが小さくなって再符号化ストリームＶoutのビットレートが増加するようになっているためである。
【０１６０】
さらに、この再符号化システム５０は、上記実施の形態４の再符号化システム４０における量子化ステップ導出器Ｕ７４に代えて、上記第１の模擬符号化器Ｕ２ａから出力される量子化ステップＱａ，模擬符号化増加誤差Ｄａ，及び模擬符号化ビット数Ｒａと、第２の模擬符号化器Ｕ２ｂから出力される量子化ステップＱｂ，模擬符号化増加誤差Ｄｂ，及び模擬符号化ビット数Ｒｂと、第３の模擬符号化器Ｕ２ｃから出力される量子化ステップＱｃ，模擬符号化増加誤差Ｄｃ，及び模擬符号化ビット数Ｒｃと、上記レート歪計算器Ｕ５からの再符号化誤差増加率λとに基づいて、各符号化単位に対応する最適量子化ステップＱｄとして上記量子化ステップＱａ，Ｑｂ及びＱｃのうちの１つを選択して出力する量子化ステップ導出器Ｕ７５を有している。
そして、この実施の形態５の再符号化システム５０におけるその他の構成は、図１１に示す実施の形態４の再符号化システム４０と同一となっている。
【０１６１】
図１６はこの実施の形態５の再符号化システム５０を構成する量子化ステップ導出器Ｕ７５の具体的構成を示すブロック図である。
上記量子化ステップ導出器Ｕ７５は、上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂからの第１，第２の模擬符号化ビット数Ｒａ，Ｒｂを受け、これらの差分（模擬符号化ビット数変動量）ΔＲabを算出する第１のビット数減算器Ｕ８ｂと、上記第２，第３の模擬符号化器Ｕ２ｂ，Ｕ２ｃからの第２，第３の模擬符号化ビット数Ｒｂ，Ｒｃを受け、これらの差分（模擬符号化ビット数変動量）ΔＲbcを算出する第２のビット数減算器Ｕ８ｃとを有している。
【０１６２】
また、上記量子化ステップ導出器Ｕ７５は、上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂからの模擬符号化増加誤差Ｄａ，Ｄｂを受け、これらの差分（模擬符号化誤差変動量）Ｄabを算出する第１の誤差減算器Ｕ９ｂと、上記第２，第３の模擬符号化器Ｕ２ｂ，Ｕ２ｃからの模擬符号化増加誤差Ｄｂ，Ｄｃを受け、これらの差分（模擬符号化誤差変動量）Ｄbcを算出する第２の誤差減算器Ｕ９ｃとを有している。
【０１６３】
また、上記量子化ステップ導出器Ｕ７５は、模擬符号化誤差変動量ΔＤabを模擬符号化ビット数変動量ΔＲabにより除算して、各符号化単位に対応する第１の再符号化誤差増加率λ1を導出する第１の除算器Ｕ１０ｂと、模擬符号化誤差変動量ΔＤbcを模擬符号化ビット数変動量ΔＲbcにより除算して、各符号化単位に対応する第２の再符号化誤差増加率λ２を導出する第２の除算器Ｕ１０ｃとを有している。
【０１６４】
また、上記量子化ステップ導出器Ｕ７５は、上記レート歪計算器Ｕ５からの現在の再符号化処理における再符号化誤差増加率λと、上記除算器Ｕ１０ｂからの第１の再符号化誤差増加率λ1とを比較して、比較結果に応じた第１のスイッチ制御信号Ｑsebを出力する第１の比較器Ｕ１１ｂと、上記現在の再符号化処理における再符号化誤差増加率λと、上記除算器Ｕ１０ｃからの第２の再符号化誤差増加率λ２とを比較して、比較結果に応じた第２のスイッチ制御信号Ｑsecを出力する第２の比較器Ｕ１１ｃとを有している。
【０１６５】
そして、上記上記量子化ステップ導出器Ｕ７５は、上記第１，第２のスイッチ制御信号Ｑseb，Ｑsecに基づいて、上記各模擬符号化器Ｕ２ａ，Ｕ２ｂ，Ｕ２ｃから供給される量子化ステップＱａ，Ｑｂ，Ｑｃのうちの１つを選択し、選択された量子化ステップを最適量子化ステップＱｄとして出力する選択スイッチＵ５０を有している。
【０１６６】
具体的には、上記量子化ステップ導出器Ｕ７５は、再符号化誤差増加率λが上記再符号化誤差増加率λ１以下であるときには、スイッチＵ５０では、上記スイッチ制御信号Ｑsebにより、量子化ステップＱａが最適量子化ステップＱｄとして選択され、上記再符号化誤差増加率λが再符号化誤差増加率λ１より大きくかつ再符号化誤差増加率λ２以下であるときには、スイッチＵ５０では、スイッチ制御信号Ｑseb及びスイッチ制御信号Ｑsecにより、量子化ステップＱｂが最適量子化ステップＱｄとして選択され、さらに上記再符号化誤差増加率λが再符号化誤差増加率λ２より大きいときには、スイッチＵ５０では、スイッチ制御信号Ｑsecにより、量子化ステップＱｃが最適量子化ステップＱｄとして選択されるようになっている。
【０１６７】
次に動作について説明する。
この再符号化システム５０に入力ストリームＶinが供給されると、復号化器Ｕ１では、実施の形態４と同様、符号化ストリームである入力ストリームＶinに対して復号化処理が施され、第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂにて復号化ストリームＶdecに対して第１，第２の模擬符号化処理が施される。
このとき、本実施の形態５では、第３の模擬符号化器Ｕ２ｃにて、上記第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂにおける第１，第２の模擬符号化処理と同様な第３の模擬符号化処理が上記復号化ストリームＶdecに対して施される。
【０１６８】
つまり、第３の模擬符号化器Ｕ２ｃでは、第３の模擬メモリＵ３ｃに格納されている参照画像データＶｃあるいは主メモリＵ３ｄに格納されている参照画像データＶrefcを参照して、処理対象となっている処理画面の復号化ストリームＶdecに対して、量子化ステップＱｃ（Ｑｃ＞Ｑｂ＞Ｑａ）による量子化処理及び局所復号化処理を含む第３の模擬符号化処理が施される。なお、上記量子化ステップＱｃは上記逆量子化処理で用いられた量子化ステップＱinより小さくならいよう設定される。これにより上記第３の模擬符号化器Ｕ２ｃからは、局所復号化画像データＶstrcが出力されるとともに、各符号化単位に対応する量子化ステップＱｃ，模擬符号化ビット数Ｒｃ，及び模擬符号化誤差Ｄｃが出力される。
【０１６９】
このとき、上記第３の模擬メモリＵ３ｃには上記局所復号化画像データＶstrcが、符号化処理済みの画面（フレーム）に対応する画像データとして格納される。このように第３の模擬メモリＵ３ｃに格納された画像データは、未処理画面に対応する画像データの模擬符号化処理の際に、上記参照画面データＶｃとして用いられる。
【０１７０】
そして、上記量子化ステップ導出部Ｕ７５では、上記第１，第２，第３の模擬符号化器Ｕ２ａ，Ｕ２ｂ，Ｕ２ｃからの量子化ステップＱａ，Ｑｂ,Ｑｃ、模擬符号化ビット数Ｒａ，Ｒｂ，Ｒｃ、及び模擬符号化誤差Ｄａ，Ｄｂ，Ｄｃに基づいて、各ブロック（符号化単位）に対応する再符号化誤差増加率が、被処理画面に対応する平均的な再符号化誤差増加率（目標再符号化誤差増加率）λを超えないよう、各符号化単位に対応する最適量子化ステップＱｄが導出される。
【０１７１】
すると、上記主符号化器Ｕ２ｄでは、実施の形態４と同様、上記復号画像データＶdecに対して、最適量子化ステップＱｄによる量子化処理及び局所復号化処理を含む再符号化処理が、主メモリＵ３ｄに格納されている参照画像データＶrefdを参照して施される。これにより、主符号化器Ｕ２ｄからは再符号化ストリームＶoutが出力されるとともに、局所復号化画像データＶstrdが出力される。
【０１７２】
また、レート歪計算器Ｕ５では、各フレームに対応する再符号化ストリームＶoutに基づいて、符号化処理中のフレームの平均的なビットレートが該フレームの目標ビットレートより大きくなりそうであれば、再符号化誤差増加率λとして大きな値が出力され、符号化処理中のフレームの平均的なビットレートが該フレームの目標ビットレートより少なくなりそうであれば、再符号化誤差増加率λとして小さな値が出力される。
【０１７３】
以下、上記量子化ステップ導出器Ｕ７５の具体的な動作について説明する。
まず、この実施の形態５では、第１のビット数減算器Ｕ８ｂにおける模擬符号化ビット数変動量ΔＲabを算出する減算処理、第１の誤差減算器Ｕ９ｂにおける模擬符号化誤差変動量ΔＤabを算出する減算処理、及び第１の除算器Ｕ１０ｂにおける再符号化誤差増加率λ１を導出する演算処理が行われるとともに、第２のビット数減算器Ｕ８ｃにおける模擬符号化ビット数変動量ΔＲbcを算出する減算処理、第２の誤差減算器Ｕ９ｃにおける模擬符号化誤差変動量ΔＤbcを算出する減算処理、及び第２の除算器Ｕ１０ｃにおける再符号化誤差増加率λ２を導出する演算処理が行われる。
【０１７４】
ここで、第１のビット数減算器Ｕ８ｂ，第１の誤差減算器Ｕ９ｂ，第１の除算器Ｕ１０ｂにおける処理は、実施の形態４のものと全く同一であり、第２のビット数減算器Ｕ８ｃ，第２の誤差減算器Ｕ９ｃ，第２の除算器Ｕ１０ｃにおける処理は、上記減算器Ｕ８ｂ，減算器Ｕ９ｂ，除算器Ｕ１０ｂにおける処理と同様なものとなっている。
【０１７５】
つまり、上記第２のビット数減算器Ｕ８ｃでは、第２の模擬符号化ビット数Ｒｂから第３の模擬符号化ビット数Ｒｃを引き算する減算処理が行われて、これらの差分（模擬符号化ビット数変動量）ΔＲbcが算出される。また、第２の誤差減算器Ｕ９ｃでは、上記第３の模擬符号化器Ｕ２ｃからの模擬符号化増加誤差Ｄｃから上記第２の模擬符号化器Ｕ２ｂからの模擬符号化増加誤差Ｄｂを引き算する減算処理が行われて、これらの差分（模擬符号化誤差変動量）ΔＤbcが算出される。さらに、第２の除算器Ｕ１０ｃでは、模擬符号化誤差変動量ΔＤbcを模擬符号化ビット数変動量ΔＲbcで除算する演算処理が行われて、上記第２の再符号化誤差増加率λ２が導出される。
【０１７６】
また、上記除算器Ｕ１０ｂからの第１の再符号化誤差増加率λ１は、第１の比較器Ｕ１１ｂにて、現在の再符号化処理における再符号化誤差増加率λと比較されて、比較結果に応じた第１のスイッチ制御信号Ｑsebが出力される。上記除算器Ｕ１０ｃからの第２の再符号化誤差増加率λ２は、第２の比較器Ｕ１１ｃにて、現在の再符号化処理における再符号化誤差増加率λと比較されて、比較結果に応じた第２のスイッチ制御信号Ｑsecが出力される。
【０１７７】
そして、上記選択スイッチＵ５０では、上記第１，第２のスイッチ制御信号Ｑseb，Ｑsecに基づいて、上記各模擬符号化器Ｕ２ａ，Ｕ２ｂ，Ｕ２ｃから供給される量子化ステップＱａ，Ｑｂ，Ｑｃのうちの１つが選択され、選択された量子化ステップが最適量子化ステップＱｄとして出力される。
【０１７８】
具体的には、再符号化誤差増加率λが上記再符号化誤差増加率λ１以下であるときには、スイッチＵ５０では、上記スイッチ制御信号Ｑsebにより、量子化ステップＱａが最適量子化ステップＱｄとして選択される。また、上記再符号化誤差増加率λが再符号化誤差増加率λ１より大きくかつ再符号化誤差増加率λ２以下であるときには、スイッチＵ５０では、スイッチ制御信号Ｑseb及びスイッチ制御信号Ｑsecにより、量子化ステップＱｂが最適量子化ステップＱｄとして選択される。さらに上記再符号化誤差増加率λが再符号化誤差増加率λ２より大きいときには、スイッチＵ５０では、スイッチ制御信号Ｑsecにより、量子化ステップＱｃが最適量子化ステップＱｄとして選択される。
【０１７９】
このように本実施の形態５では、主符号化器Ｕ２ｄからの再符号化ストリームＶoutに基づいて、再符号化ストリームＶoutのビットレート（現在のビットレート）を外部からの目標ビットレートＲａｔｅと比較し、この比較結果に応じて、被処理フレームに対応する画質の指標となる平均的な再符号化誤差増加率λを計算するレート歪計算器Ｕ５を備え、それぞれ、量子化ステップＱａ，Ｑｂ．Ｑｃ（Ｑａ＜Ｑｂ＜Ｑｃ）が異なる第１，第２，第３の模擬符号化器Ｕ２ａ，Ｕ２ｂ，Ｕ２ｂでの符号化結果から得られる、符号化単位に対応する第１，第２の再符号化誤差増加率λ1，λ２（λ１＜λ２）が、上記１フレームの平均的な再符号化誤差増加率λより小さいときには、そのブロックに対応する最適量子化ステップＱｄを量子化ステップＱｂ，Ｑｃにするようにしたので、画質の劣化を抑えつつ、ビットレートを低減することができる。
【０１８０】
なお、上記実施の形態５では、３つの模擬符号化器を有し、第１，第２の再符号化誤差増加率λ1，λ２を、上記１フレームの平均的な再符号化誤差増加率λと比較して、各ブロックに対応する最適量子化ステップＱｄを決定するものを示したが、再符号化システムにおける模擬符号化器の個数は３つに限るものではなく、実施の形態４における再符号化システム４０のように２つであっても、あるいは４つ以上であってもよい。
【０１８１】
例えば、模擬符号化器として第１，第２の模擬符号化器を有する再符号化システムでは、上記量子化ステップ導出器Ｕ７５は、量子化ステップＱａ，Ｑｂ（Ｑａ＜Ｑｂ）が異なる第１，第２の模擬符号化器Ｕ２ａ，Ｕ２ｂでの符号化結果から得られる、符号化単位に対応する第１の再符号化誤差増加率λ1が、上記１フレームの平均的な再符号化誤差増加率λより小さいときには、そのブロックに対応する最適量子化ステップＱｄを量子化ステップＱａ及びＱｂのうちの大きい方を選択し、第１の再符号化誤差増加率λ1が、上記１フレームの平均的な再符号化誤差増加率λより小さくないときには、量子化ステップＱａ及びＱｂのうちの小さい方を選択する構成となる。
【０１８２】
（実施の形態６）
図１７は本発明の実施の形態６による再符号化システムを説明するためのブロック図であり、この実施の形態６の再符号化システムにおける量子化ステップ導出器の構成を示している。
この実施の形態６の再符号化システムは、上記実施の形態５の再符号化システム５０の量子化ステップ導出器Ｕ７５に代えて、各模擬符号化器での模擬符号化処理の結果得られる量子化ステップＱｂ，Ｑｃ、模擬符号化ビット数Ｒａ，Ｒｂ，Ｒｃ、及び模擬符号化増加誤差Ｄａ，Ｄｂ，Ｄｃに基づいて、再符号化誤差増加率λと量子化ステップＱとの関係式を求め、この関係式と、レート歪計算器Ｕ５からの目標再符号化誤差増加率λとに基づいて、各符号化単位に対応する最適量子化ステップＱｄを求める量子化ステップ導出器Ｕ７６を備えたものである。そして、この実施の形態６の再符号化システムにおけるその他の構成は、上記実施の形態５の再符号化システムと同一である。
【０１８３】
以下、図１７を用いて、この実施の形態６の再符号化システムを構成する量子化ステップ導出器Ｕ７６の具体的構成について説明する。
本実施の形態６の量子化ステップ導出器Ｕ７６は、実施の形態５の量子化ステップ導出器Ｕ７５の第１，第２の比較器Ｕ１１ｂ，Ｕ１１ｃ及びスイッチＵ５０に代えて、目標再符号化誤差増加率λとビットレートＲとの関係を示す誤差ＲＤ関数ｆを導出する誤差ＲＤ導出器Ｕ１２と、この誤差ＲＤ関数ｆを用いて、量子化ステップＱと再符号化ビット数（復号化ストリームＶdecの符号化処理により得られる符号化単位に対応するビット数）Ｒとの関係から、再符号化誤差増加率λに対応する最適量子化ステップを符号化単位毎に算出する量子化ステップ計算器Ｕ３１とを備えている。ここで、ビットレートは、符号化単位に対応して発生するビット数と等価である。
【０１８４】
以下、上記誤差ＲＤ導出器Ｕ１２及び量子化ステップ計算器Ｕ３１について具体的に説明する。
一般に各ブロック（符号化単位）に対応する符号化ビット数Ｒと、各ブロックに対応する符号化誤差Ｄとの間には、下記の式６で表される関数（レート誤差関数）が成立する。
Ｄ＝ｇ（Ｒ） （式６）
【０１８５】
そこで、再符号化処理では、再符号化ストリームに含まれる符号化誤差Ｄは、下記の式７により表される。
ΔＤ＋Ｄin＝ｇ（Ｒ） (式７)
ここで、ΔＤは、再符号化増加誤差（再符号化処理により増加する符号化誤差）、Ｄinは、入力ストリームＶinの符号化誤差である。
【０１８６】
従って、再符号化誤差増加率λは、下記の式８で表される。
λ＝∂Ｄ／∂Ｒ＝∂ΔＤ／∂Ｒ＝∂ｇ(Ｒ)／∂Ｒ (式８)
ここで、上記関数ｇ(Ｒ)は、下記の式９に示すように近似できることが知られている。
ｇ(Ｒ)＝Ａ・Ｒ^B （式９）
ここで、ＡとＢは定数である。
【０１８７】
従って、上記式８及び式９より、再符号化誤差増加率λは以下の式１０により表される。
λ＝Ａ・Ｒ^B-1 (式１０)
【０１８８】
ここで、再符号化誤差増加率λ１を、Ｒ＝Ｒｂであるときの再符号化誤差増加率λとし、再符号化誤差増加率λ２を、Ｒ＝Ｒｃであるときの再符号化誤差増加率λであるとすれば、上記の式１０より上記定数Ａ，Ｂを求めることができる。この結果、下記の式１１で示す誤差ＲＤ関数fが導出される。
Ｒ＝ｆ（λ） (式１１)
上記誤差ＲＤ導出器Ｕ１２は、第２，第３の模擬符号化器Ｕ２ｂ，Ｕ２ｃからの再符号化ストリームのビットレートＲｂ，Ｒｃ、及び除算器Ｕ１０ｂ，Ｕ１０ｃからの再符号化誤差増加率λ１，λ２に基づいて、上記式１１で示される関数ｆを導出する演算処理を行う構成となっている。
【０１８９】
一方、量子化ステップＱとビットレートＲとの間には、以下の式１２で示す関係が成立する。
Ｒ＝α・Ｑ^β (式１２)
【０１９０】
ここで、αとβは定数であり、上記式１２に、ビットレートＲｂ，Ｒｃと、量子化ステップＱｂ，Ｑｃを代入すれば、αとβが得られる。この結果、下記の式１３で示す関数ｈが導出される。
Ｒ＝ｈ（Ｑ） （式１３）
【０１９１】
従って、上記式１１と式１３から、再符号化誤差増加率λに対応する量子化ステップＱの関係を示す関数ｓが以下の式１４で示すように求められる。
Ｑ＝ｓ（λ） （式１４）
【０１９２】
言い換えると、この式１４を用いて、再符号化誤差増加率λに対応する量子化ステップを、最適量子化ステップＱｄとして導出できる。
上記量子化ステップ計算器Ｕ３１は、第２の模擬符号化器Ｕ２ｂからの模擬符号化ビット数Ｒｂ及び第２の模擬符号化処理における量子化ステップＱｂと、第３の模擬符号化器Ｕ２ｃからの模擬符号化ビット数Ｒｃ及び第３の模擬符号化処理における量子化ステップＱｃとに基づいて、上記式１３で示される関数ｈを導出する演算処理を行うとともに、この関数ｈと、上記誤差ＲＤ導出器Ｕ１２で求められた関数ｆとから上記関数ｓを求め、さらに、この関数ｓから、上記レート歪計算器Ｕ５にて求められた目標再符号化誤差増加率λに対応する量子化ステップを最適量子化ステップＱｄとして求める構成となっている。
【０１９３】
次に動作について説明する。
この実施の形態６の再符号化システムは、量子化ステップ導出器Ｕ７６の動作以外は実施の形態５の再符号化システム５０と全く同様な動作をする。
そこで以下、量子化ステップ導出器Ｕ７６の動作について説明する。
まず、この実施の形態６では、第１のビット数減算器Ｕ８ｂにおける模擬符号化ビット数変動量ΔＲabを算出する減算処理、第１の誤差減算器Ｕ９ｂにおける模擬符号化誤差変動量ΔＤabを算出する減算処理、及び第１の除算器Ｕ１０ｂにおける再符号化誤差増加率λ１を導出する演算処理が行われとともに、第２のビット数減算器Ｕ８ｃにおける模擬符号化ビット数変動量ΔＲbcを算出する減算処理、第２の誤差減算器Ｕ９ｃにおける模擬符号化誤差変動量ΔＤbcを算出する減算処理、及び第２の除算器Ｕ１０ｃにおける再符号化誤差増加率λ２を導出する演算処理が行われる。
【０１９４】
すると、誤差ＲＤ導出器Ｕ１２は、第２，第３の模擬符号化器Ｕ２ｂ，Ｕ２ｃにて得られる模擬符号化ビット数Ｒｂ，Ｒｃ、及び第１，第２の除算器Ｕ１０ｂ，Ｕ１０ｃからの再符号化誤差増加率λ１，λ２に基づいて、上記式１１で示される関数ｆ（Ｒ＝ｆ（λ））が導出される。
【０１９５】
また、上記量子化ステップ計算器Ｕ３１では、第２の模擬符号化処理による模擬符号化ビット数Ｒｂ及び第２の模擬符号化処理における量子化ステップＱｂと、第３の模擬符号化処理による模擬符号化ビット数Ｒｃ及び第３の模擬符号化処理における量子化ステップＱｃとに基づいて、上記式１３で示される関数ｈ（Ｒ＝ｈ（Ｑ））を導出する演算処理が行われる。さらに、この関数ｈと、上記誤差ＲＤ導出器Ｕ１２で求められた関数ｆとから、上記式１４で示される関数ｓ（Ｑ＝ｓ（λ））が求められる。そして、この関数ｓを用いて、上記レート歪計算器Ｕ５にて求められた目標再符号化誤差増加率λに対応する量子化ステップが最適量子化ステップＱｄとして求められる。
【０１９６】
このように本実施の形態６の再符号化システムでは、量子化ステップ導出器Ｕ７６を、模擬符号化処理の結果に基づいて、再符号化誤差増加率λとビットレートの関係を示す関数ｆ（Ｒ＝ｆ（λ））を導出する誤差ＲＤ導出器Ｕ１２と、該関数ｆと上記模擬符号化処理の結果に基づいて、再符号化誤差増加率λと量子化ステップとの関係を示す関数ｓ（Ｑ＝ｓ（λ））を求め、この関数ｓを用いて、レート歪計算器Ｕ５にて求められた目標再符号化誤差増加率λに対応する量子化ステップを最適量子化ステップＱｄとして各符号化単位毎に導出する量子化ステップ計算機Ｕ３１とを有する構成としたので、各符号化単位に対応する最適量子化ステップＱｄを細かく設定することができる。
【０１９７】
なお、この実施の形態６では、模擬符号化増加誤差Ｄｂ，Ｄａの差、模擬符号化ビット数Ｒａ，Ｒｂの差、模擬符号化増加誤差Ｄｂ，Ｄｃの差、模擬符号化ビット数Ｒｂ，Ｒｃの差に基づいて、誤差ＲＤ関数fを導出したが、上記模擬符号化増加誤差の差分には、模擬符号化増加誤差Ｄｃ，Ｄａの差分を用いてもよく、また、符号化単位（ブロック）当りの模擬符号化ビット数の差分には、再符号化ビット数Ｒａ，Ｒｃの差分を用いてもよい。
【０１９８】
（実施の形態７）
図１８は本発明の実施の形態７による再符号化システムを説明するためのブロック図であり、この実施の形態７の再符号化システムにおける量子化ステップ導出器の構成を示している。
この実施の形態７の再符号化システムは、上記実施の形態６の再符号化システムの量子化ステップ導出器Ｕ７６に代えて、再符号化誤差増加率λ１の大きさに応じて、量子化ステップ計算器Ｕ３１から出力される量子化ステップＱｆと、上記量子化ステップＱａ，Ｑｂ，Ｑｃのうちでの最小の量子化ステップＱａの一方を選択し、該選択された量子化ステップを最適量子化ステップＱｄとして出力する量子化ステップ導出器Ｕ７７を備えたものである。
【０１９９】
以下、図１８を用いて、この実施の形態７の再符号化システムを構成する量子化ステップ導出器Ｕ７７の具体的構成について説明する。
この量子化ステップ導出器Ｕ７７は、上記実施の形態６の量子化ステップ導出器Ｕ７６の構成に加えて、第１の除算器Ｕ１０ｂからの第１の再符号化誤差増加率λ１と、レート歪計算器からの目標再符号化誤差増加率λとを比較してスイッチ制御信号Ｑseを出力する比較器Ｕ１１と、該スイッチ制御信号Ｑseに応じて、量子化ステップ計算器Ｕ３１から出力される量子化ステップＱｆ及び上記最小の量子化ステップＱａの一方を選択する選択スイッチＵ７０とを備え、該選択された量子化ステップを最適量子化ステップＱｄとして出力する構成となっている。
【０２００】
以下、上記比較器Ｕ１１の具体的な構成について簡単に説明する。
一般的に再符号化システムでは、入力ストリームＶinに施された符号化処理における量子化ステップＱinの大きさと、再符号化処理における量子化ステップＱｄの大きさの差が大きい場合は、つまり、再符号化誤差増加率が大きい場合は、量子化ステップＱｄが大きくなるにつれて再符号化誤差増加率λが単調増加するという現象が現れる。一方、入力ストリームＶinに対する符号化処理における量子化ステップＱinの大きさと、再符号化処理における量子化ステップＱｄの大きさの差が小さい場合は、つまり、再符号化誤差増加率が小さい場合は、量子化ステップＱｄが大きくなっても必ずしも再符号化誤差増加率λが増加するとは限らず、場合によっては減少することもありうる。この点については、上記実施の形態２にて図７を用いて説明した通りであり、また文献（電子情報通信学会研究会報告IE99-32 MPEG2再符号化における再量子化誤差の検討）に詳しく記載されている。
【０２０１】
つまり、図７では、再符号化データにおける量子化誤差は、そのビットレートが高い場合、即ち、第１の量子化処理（符号化処理における量子化処理）における量子化ステップ値ＱＰｉと、第２の量子化処理（再符号化処理における量子化処理）における量子化ステップ値ＱＰｒとの差が小さい場合に大きく、一方、第２の量子化処理における量子化ステップ値ＱＰｒが２ＱＰ（ＱＰｉ＝ＱＰ）以上であって、再符号化データのビットレートが低い場合には、直接符号化処理における量子化誤差と再符号化処理による量子化誤差の差は殆ど無くなることが示されている。ここで、再符号化データにおける量子化誤差の増減は、再符号化誤差増加率の増減に対応したものとなっている。
【０２０２】
そこで、上記比較器Ｕ１１は、模擬符号化処理により得られる符号化単位（被処理ブロック）に対応する再符号化誤差増加率λ１が、被処理フレームに対する目標再符号化誤差増加率λより小さいときには、上記選択スイッチＵ７０が、第１，第２，第３の模擬符号化処理における量子化ステップＱａ，Ｑｂ，Ｑｃ（Ｑａ＜Ｑｂ＜Ｑｃ）のうちでの最小の量子化ステップＱａを選択し、上記再符号化誤差増加率λ１が再符号化誤差増加率λ以上であるときには、上記選択スイッチＵ７０が、上記量子化ステップ計算器Ｕ３１からの量子化ステップＱｆを選択するよう、上記選択スイッチＵ７０を制御する構成となっている。
言い替えると、この実施の形態７は、上記実施の形態６の再符号化システムと実施の形態２の再符号化システムとを組み合わせて得られる構成に相当している。具体的には、この実施の形態７の量子化ステップ導出器Ｕ７７における比較器Ｕ１１及び選択スイッチＵ７０は、上記実施の形態２の量子化装置１５２における量子化ステップ導出器２５２に相当し、上記量子化ステップ導出器Ｕ７７における比較器Ｕ１１及び選択スイッチＵ７０以外の部分が、上記実施の形態２の量子化装置１５２における量子化ステップ候補導出器２５０に相当している。
そして、この実施の形態７の量子化ステップ導出器Ｕ７７では、模擬符号化処理により得られる再符号化誤差増加率λ１を被処理フレームに対する目標再符号化誤差増加率λと比較し、λ１＜λのとき、上記各模擬符号化処理における最小の量子化ステップＱａを、λ１≧λのとき、上記量子化ステップ計算器Ｕ３１からの量子化ステップＱｆを、再符号化処理における量子化ステップとして選択するようにしている。このような量子化ステップの導出処理は、上記実施の形態２にて、量子化ステップ候補Ｑｓｂを閾値Ｑｔｈ（＝ｎ×Ｑｓ１）及び定数倍値Ｑｍｕ（＝ｍ×Ｑｓ１＞Ｑｔｈ）と比較し、Ｑｓｂ＜Ｑｍｕのとき、量子化ステップとして第１の量子化ステップＱｓ１あるいは定数倍値Ｑｍｕを選択し、Ｑｍｕ≦Ｑｓｂのとき、量子化ステップとして量子化ステップ候補Ｑｓｂを選択する処理と同等なものである。
【０２０３】
次に動作について説明する。
この実施の形態７の再符号化システムは、量子化ステップ導出器Ｕ７７の動作以外は実施の形態５の再符号化システム５０と全く同様な動作をする。
そこで以下、量子化ステップ導出器Ｕ７７の動作について説明する。
この実施の形態７では、減算器Ｕ８ｂ，Ｕ８ｃ、減算器Ｕ９ｂ，Ｕ９ｃ、除算器Ｕ１０ｂ，Ｕ１０ｃ、誤差ＲＤ計算器Ｕ１２、及び量子化ステップ計算器Ｕ３１では、上記実施の形態６と全く同一の演算処理が行われる。これにより上記除算器Ｕ１０ｂ，Ｕ１０ｃからは、符号化単位（被処理ブロック）に対応する第１，第２の再符号化誤差増加率λ１，λ２が出力される。また、誤差ＲＤ計算器Ｕ１２からは、誤差ＲＤ関数ｆが導出され、量子化ステップ計算器Ｕ３１からは、被処理ブロックに対応する量子化ステップとして、被処理フレームに対応する目標再符号化誤差増加率λに応じた値Ｑｆが出力される。
【０２０４】
そして、上記比較器Ｕ１１では、被処理ブロックに対応する第１の再符号化誤差増加率λ１と、被処理フレームに対応する目標再符号化誤差増加率λとの大小比較が行われ、比較結果に応じてスイッチ制御信号Ｑseが上記選択スイッチＵ７０に出力される。該選択スイッチＵ７０では、スイッチ制御信号Ｑseに応じて、量子化ステップ計算器Ｕ３１からの量子化ステップＱｆと、第１の模擬符号化処理における量子化ステップＱａの一方が最適量子化ステップＱｄとして選択されて出力される。
【０２０５】
具体的には、上記被処理ブロックに対応する第１の再符号化誤差増加率λ１が、被処理フレームに対応する目標の再符号化誤差増加率λより小さいときには、上記スイッチ制御信号Ｑseにより、上記選択スイッチＵ７０では量子化ステップＱａが最適量子化ステップＱｄとして選択され、上記第１の再符号化誤差増加率λ１が目標の再符号化誤差増加率λより小さくないときには、上記選択スイッチＵ７０では量子化ステップ計算器Ｕ３１からの量子化ステップＱｆが最適量子化ステップＱｄとして選択される。
【０２０６】
このように本実施の形態７の再符号化システムでは、量子化ステップ導出器Ｕ７７を、上記実施の形態６の量子化ステップ導出器Ｕ７６の構成に加えて、除算器Ｕ１０ｂからの再符号化誤差増加率λ１をレート歪計算器からの目標再符号化誤差増加率λと比較して、比較結果に応じたスイッチ制御信号Ｑseを出力する比較器Ｕ１１を有し、再符号化誤差増加率λ１がレート歪計算器からの目標再符号化誤差増加率λより小さいときのみ、被処理ブロックに対応する量子化ステップとして、量子化ステップ計算器Ｕ３１により得られる量子化ステップＱｆに代えて、模擬符号化処理における最小の量子化ステップＱａを選択するようにしたので、再符号化誤差増加率が、量子化ステップの増加に対する再符号化誤差増加率の変化が単調増加でなく、量子化ステップ計算器Ｕ３１により、再符号化誤差が最小となる最適量子化ステップＱｄを導出困難な範囲内の値であるときには、常に、模擬符号化処理における最小の量子化ステップＱａが、被処理ブロックの最適量子化ステップＱｄとして用いられることとなる。
【０２０７】
このため、被処理フレームの目標再符号化誤差増加率λが、入力ストリームＶinの量子化ステップＱinと、入力ストリームＶinに対する再符号化処理における量子化ステップＱｄとの差分が小さくなる範囲内の値である場合には、動作が不安定になることを防止することができる。また、上記被処理フレームの目標再符号化誤差増加率λが上記範囲外の値であるときには、量子化ステップ計算器Ｕ３１により導出した量子化ステップＱｆを量子化ステップＱｄとすることにより、再符号化誤差を最小化することができる。
【０２０８】
なお、上記実施の形態６及び７では、再符号化ストリームの符号化単位当たりの符号化ビット数Ｒと再符号化誤差増加率λとの関係を示す関数として、式１１に示す誤差ＲＤ関数ｆを示したが、これらの関係を示す関数はこれに限るものではない。
【０２０９】
例えば、模擬符号化増加誤差Ｄａ，Ｄｂ，Ｄｃ、及び模擬符号化ビット数Ｒａ，Ｒｂ，Ｒｃから、上記式１１に示す誤差ＲＤ関数ｆと同様な傾向，性質を有する他の誤差ＲＤ関数が導出できれば、この他の誤差ＲＤ関数を、符号化ビット数Ｒと再符号化誤差増加率λとの関係を示す関数として使用してもよい。
【０２１０】
また、上記実施の形態５ないし７では、再符号化システムとして、第１，第２，第３の模擬符号化器Ｕ２ａ，Ｕ２ｂ，Ｕ２ｃでは主符号化器Ｕ２ｄでの再符号化処理の対象となるフレームに対してのみ、量子化処理を含む模擬符号化処理を行うものを示しているが、上記再符号化システムの構成はこれに限るものではない。
【０２１１】
例えば、上記実施の形態４にて具体的に説明したように、再符号化システムは、ＭＰＥＧにおける画面間予測符号化処理を行う場合には、第１，第２，第３の模擬符号化器Ｕ２ａ，Ｕ２ｂ，Ｕ２ｃでは、主符号化器Ｕ２ｄでの再符号化処理の対象となる被処理フレームに対してだけでなく、再符号化処理の際にこの被処理フレームを参照フレームとして用いるその他のフレームに対しても模擬符号化処理を施す構成であってもよい。
【０２１２】
さらに、上記実施の形態１〜７の再符号化システムによる再符号化処理をソフトウエアにより行うための処理プログラムを、フロッピディスクなどのデータ記憶媒体に記録するようにすることにより、上記各実施の形態の再符号化処理を、独立したコンピュータシステムにより簡単に実現することが可能となる。
【０２１３】
図１９は、上記各実施の形態の再符号化処理をコンピュータシステムにより行うためのプログラムを格納したデータ記録媒体（図１９(a)，(b)）、及び上記コンピュータシステム（図１９(c)）を説明するための図である。
図１９(a)は、フロッピーディスクの正面からみた外観、断面構造、及びフロッピーディスクを示し、図１９(b) は、記録媒体本体であるフロッピーディスクの物理フォーマットの例を示している。フロッピーディスクＦＤはケースＦ内に内蔵され、該ディスクの表面には、同心円状に外周からは内周に向かって複数のトラックＴｒが形成され、各トラックは角度方向に１６のセクタＳｅに分割されている。従って、上記プログラムを格納したフロッピーディスクでは、上記フロッピーディスクＦＤ上に割り当てられた領域に、上記プログラムが記録されている。
また、図１９(c) は、フロッピーディスクＦＤに上記プログラムの記録再生を行うための構成を示す。上記プログラムをフロッピーディスクＦＤに記録する場合は、コンピュータシステムＣｓによりから上記プログラムとしてのデータをフロッピーディスクドライブを介してフロッピーディスクＦＤに書き込む。また、フロッピーディスク内のプログラムにより上記各実施の形態の再符号化処理を行うシステムをコンピュータシステム中に構築する場合は、フロッピーディスクドライブによりプログラムをフロッピーディスクから読み出し、コンピュータシステムに転送する。
【０２１４】
なお、上記説明では、データ記憶媒体の具体例としてフロッピーディスクを挙げたが、光ディスクを用いても上記フロッピーディスクの場合と同様にソフトウェアによる再符号化処理を行うことができる。さらに、データ記憶媒体は上記光ディスクやフロッピーディスクに限るものではなく、ＩＣカード、ＲＯＭカセット等、プログラムを記録できるものであればどのようなものでもよく、これらのデータ記録媒体を用いる場合でも、上記フロッピーディスク等を用いる場合と同様にソフトウェアによる再符号化処理を実施することができる。
【０２１５】
【発明の効果】
以上のようにこの発明に係る符号化データ変換方法によれば、第１の直交変換処理及び第１の量子化処理を含む符号化処理により得られた符号化データを復号化して復号化データを生成する復号化処理と、該復号化データに対して第２の直交変換処理及び第２の量子化処理を施して再符号化データを生成する再符号化処理とを含み、上記再符号化処理では、上記第２の量子化処理を、上記再符号化データ及び上記第１の量子化処理における量子化ステップに基づいて行うので、上記第２の量子化処理における量子化ステップを、上記第１の量子化ステップにおける量子化ステップに応じて設定することが可能となる。つまり、上記再符号化データに基づく再符号化処理における目標ビット数の制約の下で、上記第２の量子化処理における量子化ステップを、再符号化処理におけるビットレートと量子化歪（量子化誤差）との非線形な関係を考慮して、量子化誤差ができるだけ小さくなるよう設定することができる。これにより再符号化処理における量子化誤差の増大を、ビットレートの制約の下で効果的に抑制することができるという効果がある。
【０２１６】
この発明によれば、上記符号化データ変換方法において、上記第２の量子化処理，つまり再符号化処理における量子化処理では、上記再符号化データに基づいて量子化ステップ候補を導出し、該量子化ステップ候補と上記第１の量子化処理における量子化ステップとに基づいて量子化ステップを導出するので、上記量子化ステップ候補と上記第１の量子化処理における量子化ステップのうちで大きい方を第２の量子化処理における量子化ステップとして選択するという簡単な処理により、量子化誤差の増大を抑えつつ再符号化処理により発生するビット数を目標ビット数以下にすることができるという効果がある。
【０２１７】
この発明によれば、上記符号化データ変換方法において、上記第２の量子化処理（再符号化処理における量子化処理）における量子化ステップを導出する処理では、上記量子化ステップ候補の大きさに応じて、上記第２の量子化処理における量子化ステップとして、上記第１の量子化処理における量子化ステップと同じ値の量子化ステップ、その２倍以上である量子化ステップ、あるいは上記量子化ステップ候補を導出するので、第２の量子化処理における量子化ステップとしては、上記第１の量子化処理における量子化ステップの１倍からその２倍までの範囲以外の値を設定することが可能となる。これにより、符号化データに対してビット数を増やさずに、量子化誤差の著しい増大を招くことなく、再符号化処理により発生するビット数を目標ビット数以下にすることができるという効果がある。
【０２２２】
この発明に係るデータ記録媒体によれば、上記符号化データ変換方法により第１の符号化データを第２の符号化データに変換する処理をコンピュータにより行うプログラムを格納したので、再符号化処理を、量子化誤差の増大を効果的に抑制して行うことができるという効果を有する。
【図面の簡単な説明】
【図１】本発明の実施の形態１による再符号化システム１０を説明するためのブロック図である。
【図２】上記実施の形態１の再符号化システム１０を構成する量子化装置１５１を説明するためのブロック図である。
【図３】上記実施の形態１の量子化装置１５１を構成する量子化ステップ導出器２５１を説明するためのブロック図である。
【図４】本発明の実施の形態２による再符号化システムを構成する量子化装置１５２を説明するためのブロック図である。
【図５】上記実施の形態２の量子化装置１５２を構成する量子化ステップ導出器２５２を説明するためのブロック図である。
【図６】上記実施の形態２の量子化ステップ導出器２５２により得られる第２の量子化ステップＱｓ２と、上記実施の形態２の量子化装置１５２を構成する量子化ステップ候補導出器２５０より出力される量子化ステップ候補Ｑｓｂとの関係をグラフにより示す図である。
【図７】再符号化処理によるビットレートと量子化歪（量子化誤差）の関係を示す図である。
【図８】本発明の実施の形態３による再符号化システム３０を説明するためのブロック図である。
【図９】上記実施の形態３の再符号化システム３０を構成する量子化装置１５３を説明するためのブロック図である。
【図１０】上記実施の形態３の量子化装置１５３を構成する量子化ステップ導出器２７３を説明するためのブロック図である。
【図１１】本発明の実施の形態４による再符号化システム４０を説明するためのブロック図である。
【図１２】上記実施の形態４の再符号化システム４０にて復号画像データＶdecの模擬符号化処理により生ずる模擬符号化誤差と、該模擬符号化処理により発生する符号化単位当たりのビット数（模擬符号化ビット数）との関係をグラフにより示す図である。
【図１３】上記実施の形態４の再符号化システム４０を構成する量子化ステップ導出器Ｕ７４の具体的構成を示すブロック図である。
【図１４】上記実施の形態４における各符号化単位の最適量子化ステップを導出する処理を説明するための図であり、該処理のフロー（図(a)）、１フレームにおける符号化単位の配列（図(b)）、及び各符号化単位に対して最適量子化ステップＱｄが設定された状態（図(c)）を示している。
【図１５】本発明の実施の形態５による再符号化システム５０を説明するためのブロック図である。
【図１６】上記実施の形態５の再符号化システム５０を構成する量子化ステップ導出器Ｕ７５の具体的構成を示すブロック図である。
【図１７】本発明の実施の形態６による再符号化システムを説明するためのブロック図であり、この再符号化システムにおける量子化ステップ導出器Ｕ７６の構成を示している。
【図１８】本発明の実施の形態７による再符号化システムを説明するためのブロック図であり、この再符号化システムにおける量子化ステップ導出器Ｕ７７の構成を示している。
【図１９】上記実施の形態１〜７の再符号化システムによる再符号化処理を、コンピュータシステムにより行うためのプログラムを格納したデータ記録媒体（図(a)，(b)）、及び上記コンピュータシステム（図(c)）を説明するための図である。
【図２０】従来の再符号化システム１００ａを説明するためのブロック図である。
【図２１】従来の再符号化システム１００ａを構成する量子化装置１０７を説明するためのブロック図である。
【図２２】符号化ストリームのビットレートと符号化ストリームに含まれる符号化誤差の関係をグラフにより示す図である。
【図２３】ＭＰＥＧにおける画面間予測符号化処理を説明するための模式図である。
【符号の説明】
１０，３０，４０，５０ 再符号化システム
１００ ＶＬＤ器
１０１ａ，１０８ 逆量子化装置
１０２，１０９ ＩＤＣＴ器
１０３，１１０ 加算器
１０４，１１１ フレームメモリ
１０５ 減算器
１０６ ＤＣＴ器
１１２ ＶＬＣ器
１１３ レート制御装置
１５１，１５２，１５３ 量子化装置
２０１ 量子化器
２５０ 量子化ステップ候補導出器
２５１，２５２，２７３，Ｕ７４，Ｕ７５，Ｕ７６，Ｕ７７ 量子化ステップ導出器
２６０，２６３，２６６ 比較器
２６１，２６４，２６７ スイッチ
２６２ 閾値導出器
２６５ 定数倍器
２７０，２７２ａ 画面内平均量子化ステップ導出器
２７１，２７２ｂ 画面間平均量子化ステップ導出器
ＣＰ１，ＣＰ２，ＣＰ３ 比較出力
Ｄａ，Ｄｂ，Ｄｃ 第１，第２，第３の模擬符号化増加誤差
Ｄａ１ 復号化ユニット
Ｅａ１ 符号化ユニット
Ｅｇ１ 符号化データ
Ｅｇ２ 再符号化データ
ｆ 誤差RD関数
Ｑａ，Ｑｂ，Ｑｃ，Ｑｆ，Ｑin 量子化ステップ
Ｑｄ 最適量子化ステップ
Ｑｓ１ 第１の量子化ステップ
Ｑｓ２ 第２の量子化ステップ
Ｑｓｂ 量子化ステップ候補
Ｑｓｅ 選択量子化ステップ
Ｑseb，Ｑsec，Ｑse１ スイッチ制御信号
Ｑｔｈ 閾値
Ｑｍｕ 定数倍値
Ｒａ，Ｒｂ，Ｒｃ 第１，第２，第３の模擬符号化ビット数
Ｒate 目標ビットレート
Ｒｄ フレーム目標ビット数
Ｕ１ 復号化器
Ｕ２ａ，Ｕ２ｂ，Ｕ２ｃ 第１，第２，第３の模擬符号化器
Ｕ２ｄ 主符号化器
Ｕ３ａ，Ｕ３ｂ，Ｕ３ｃ 第１，第２，第３の模擬メモリ
Ｕ３ｄ 主メモリ
Ｕ５ レート歪計算器
Ｕ６ フレームビット数計算器
Ｕ８ｂ，Ｕ８ｃ 第１，第２のビット数減算器
Ｕ９ｂ，Ｕ９ｃ 第１，第２の誤差減算器
Ｕ１０ｂ，Ｕ１０ｃ 第１，第２の除算器
Ｕ１１ｂ，Ｕ１１ｃ 第１，第２の比較器
Ｕ１２ 誤差ＲＤ計算器
Ｕ１４，Ｕ５０，Ｕ７０ 選択スイッチ
Ｕ２０ 最小誤差選択器
Ｕ３１ 量子化ステップ計算器
Ｖrefa，Ｖrefb，Ｖrefc，Ｖrefd，Ｖａ，Ｖｂ，Ｖｃ 参照画像データ
Ｖstra，Ｖstrb，Ｖstrc，Ｖstrd 局所復号化画像データ
Ｖdec 復号画像データ（復号化ストリーム）
Ｖin 入力ストリーム
Ｖout 再符号化ストリーム
λ 目標再符号化誤差増加率
λ１，λ２ 第１，第２の再符号化誤差増加率
ΔＤab，ΔＤac，ΔＤbc 模擬符号化誤差変動量
ΔＲab，ΔＲac，ΔＲbc 模擬符号化ビット数変動量
Ｃｓ コンピュータシステム
Ｆ フロッピディスクケース
ＦＤ フロッピディスク
ＦDD フロッピディスクドライブ
Ｓｅ セクタ
Ｔｒ トラック[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an encoded data conversion method. , And In particular, with respect to data recording media, re-encoding of encoded data stored in a database or the like and obtained by performing encoding processing on a moving image signal with an encoding method or encoding parameters different from the encoding processing Encoded data conversion method for converting into encoded data that can be decoded by receiver by processing , And And a data recording medium storing a program for executing the re-encoding processing by software.
[0002]
[Prior art]
In recent years, the multimedia era has come in which audio, image, and other information are handled in an integrated manner, and conventional information media, that is, means for transmitting information such as newspapers, magazines, television, radio, and telephones to people are targeted for multimedia. It has come to be taken up as. In general, multimedia refers to not only characters but also figures, sounds, especially images, etc. that are associated with each other at the same time. Is a digital format information (digital data).
[0003]
However, when the amount of information handled by each information medium is estimated as the amount of information in digital format, the amount of information per character is 1 to 2 bytes for characters, whereas 64 Kbits per second for speech. (Telephone quality) Furthermore, for moving images, an information amount of 100 Mbits (current television broadcast quality) or more per second is required. In other words, it is not realistic to handle digital information such as a moving image whose information amount is enormous as it is with a corresponding information medium. For example, a video phone has already been put into practical use by an integrated services digital network (ISDN) having a transmission rate of 64 Kbps to 1.5 Mbps, but digital video information corresponding to video output of a TV camera is used as it is. It is impossible to send by ISDN.
[0004]
Therefore, what is required is information compression technology. For example, for videophones, H.264 has been internationally standardized by ITU-T (International Telecommunication Union Telecommunication Standardization Sector). 261 and H.264. H.263 standard video compression technology is used. Further, according to the information compression technology of the MPEG1 standard, it is possible to record image information together with audio information on a normal music CD (compact disc).
[0005]
Here, MPEG (Moving Picture Experts Group) is an international standard relating to the compression technology of moving image data (moving image signal), and MPEG1 has moving image data up to 1.5 Mbps, that is, information of a television signal is about 100. It is a standard that compresses to a fraction. In addition, since the transmission speed for the MPEG1 standard is mainly limited to about 1.5 Mbps, in MPEG2 standardized to meet the demand for higher image quality, moving image data is compressed to 2 to 15 Mbps. .
MPEG2 is a standard relating to the most typical digital image encoding system of the world standard, and is now rapidly spreading in technical fields related to digital TV broadcasting, digital video discs, and the like.
[0006]
Furthermore, the current working group (ISO / IEC JTC1 / SC29 / WG11), which has been standardizing with MPEG1 and MPEG2, enables encoding processing and signal manipulation on an object basis, and realizes new functions required in the multimedia era. The moving image data compression technology is being standardized as MPEG4. MPEG4 originally aimed at standardization of a low bit rate encoding method, but at present, the object of standardization has been extended to a more general encoding process of high bit rate corresponding to interlaced images. Yes.
[0007]
MPEG2 is a standard that supports general-purpose encoding processing, and can be operated under various conditions depending on the application. Here, the operating conditions of MPEG2 are determined by factors related to image quality, such as the number of pixels on the display screen and the bit rate of an image encoded signal (bit stream).
However, in each image device, since the hardware performance is limited by cost constraints, the bitstream that can be handled as the input image signal is limited to the bitstream encoded under a predetermined condition. Often done.
For example, a normal quality TV (television set) decoder cannot decode a HDTV (High Definition Television) quality bitstream (corresponding to a high pixel count image).
On the other hand, in a recording apparatus capable of recording a bit stream obtained by encoding an image signal so that the bit rate becomes 6 Mbps, an input bit stream having a bit rate of 6 Mbps is recorded in the apparatus. By internally compressing the bit rate to 3 Mbps, it is possible to record for a long time by recording the bit stream by an amount corresponding to 4 hours of video.
[0008]
Therefore, a re-encoding technique for converting an MPEG2 bitstream input to each image device into an MPEG2 bitstream corresponding to the hardware performance and purpose of use at each image device becomes important. In recent years, a lot of research results have been published on such re-encoding techniques (Gertjan Keesman, Robert Hellinghuizen, Fokke Hoeksema, Geert Heideman, "Transcoding of MPEG bitstreams", Signal Processing: Image Communication Vol. 8, 1996, pp.481-500 etc.).
[0009]
FIG. 20 is a block diagram for explaining a conventional re-encoding system 100a.
The conventional re-encoding system 100a receives an MPEG2 bit stream Eg1 obtained by an MPEG2-compliant encoding process for image data, and performs a decoding process on the bit stream Eg1 to generate decoded data Rg1. And a coding unit E1 that performs MPEG2 compliant coding processing on the decoded data Rg1 under conditions different from those of the coding processing and outputs re-coded data Eg2. Has been. Here, the MPEG2 bit stream is obtained by encoding image data for each image space (block) as a unit of encoding composed of a predetermined number of pixels. Accordingly, the decoding unit D1 is configured to perform a decoding process on the bitstream for each block, and the encoding unit E1 performs an encoding process on the decoded data Rg1 for each block. It is configured to do.
[0010]
Next, a detailed configuration of the decoding unit D1 constituting the re-encoding system 100a will be described.
The decoding unit D1 performs VLD (variable length decoding device) 100 that performs variable length decoding processing on the encoded MPEG2 bit stream Eg1, and performs inverse quantization on the output Vg of the VLD 100. An inverse quantization apparatus 101; and an IDCT device 102 that performs an IDCT (Inverse Discrete Cosine Transform) process for converting frequency domain data into spatial domain data on an output IQg of the inverse quantization apparatus 101. Yes. The decoding unit D1 includes an adder 103 that adds the output data ITg of the IDCT unit 102 and the prediction data Mg1, and a frame memory 104 that stores the output Rg1 of the adder 103 as the prediction data Mg1. The output Rg1 of the adder 103 is output as the decoded data.
[0011]
Next, a detailed configuration of the encoding unit E1 constituting the re-encoding system 100a will be described.
The encoding unit E1 includes a subtractor 105 that calculates a difference value Dg between the output data Rg1 from the decoding unit D1 and the prediction data Mg2, and spatial domain data for the output Dg of the subtractor 105. A DCT unit 106 that performs DCT (discrete cosine transform) processing to convert the data into frequency domain, and a quantization device 107 that performs quantization processing on the output Tg of the DCT unit 106 based on a quantization control signal Cq; have. The encoding unit E1 also includes a VLC (variable length encoding) unit 112 that performs variable length encoding processing on the output Qg of the quantization device 107, and the quantization control based on the output Eg2 of the VLC unit. A rate control device 113 that outputs the signal Cq to the quantization device 107, and outputs the output Eg2 of the VLC unit 112 as re-encoded data.
[0012]
Here, the rate control device 113 sets the target number of bits when encoding the DCT output Tg corresponding to the block (processed block) that is the target of the encoding process based on the re-encoded data Eg2. The calculated target bit number is output to the quantization device 107 as the quantization control signal Cq.
[0013]
The encoding unit E1 also performs inverse quantization on the output Qg of the quantization device 107, and IDCT (inverse discrete cosine transform) on the output IQg2 of the inverse quantization device 108. And an IDCT device 109 that performs processing. The encoding unit E1 includes an adder 110 that adds the output data ITg2 from the IDCT unit 109 and the prediction data Mg2, and a frame memory 111 that stores the output Rg2 of the adder 110. The output Mg2 of the memory 111 is output as the prediction data.
[0014]
FIG. 21 is a block diagram showing a detailed configuration of the quantizing device 107.
The quantization device 107 receives the target number of bits Cq from the rate control device 113, derives a quantization step Qs2, and outputs the output Tg of the DCT device 106 based on the quantization step Qs2. It also has a quantizer 201 that performs quantization processing.
[0015]
Next, the operation will be described.
First, encoded data Eg1 obtained by performing an encoding process on an image signal is input to the decoding unit D1.
In the VLD unit 100, the encoded data Eg1 is converted into a quantized coefficient Vg by variable length decoding processing and output to the inverse quantization apparatus 101. The quantization coefficient Vg is subjected to an inverse quantization process based on a quantization step in an encoding process for an image signal by the inverse quantization apparatus 101 to restore the frequency component IQg. The frequency component IQg is converted into spatial domain data ITg by IDCT (Inverse Discrete Cosine Transform) processing in which the frequency domain data is converted into spatial domain data by the IDCT unit 102. When the spatial region data ITg is input to the adder 103, the adder 103 performs addition processing of the spatial region data ITg and the prediction data Mg1. The reproduction data Rg1 obtained by the addition process is stored as decoded image data (predicted data) Mg1 in the frame memory 104 and is output as decoded data.
[0016]
Next, the operation of the encoding unit E1 in the re-encoding system 100a will be described.
First, the reproduction data Rg1 output from the decoding unit D1 is input to the subtractor 105. In the subtractor 105, a difference value between the reproduction data Rg1 from the decoding unit D1 and the prediction data Mg2 is obtained as difference data Dg. The difference data Dg is output to the DCT unit 106. In the DCT unit 106, the difference data Dg is converted into a DCT coefficient (frequency component) Tg by a DCT (discrete cosine transform) process for converting spatial domain data into frequency domain data, and the DCT coefficient Tg is quantized. It is output to the device 107.
[0017]
In the quantization device 107, the quantization process is performed on the DCT coefficient Tg from the DCT unit 106 based on the quantization control signal Cq from the rate control device 113. That is, the quantization step deriving unit 200 of the quantization apparatus 107 derives a quantization step different from the quantization step in the inverse quantization process in the decoding unit based on the quantization control signal Cq. . In the quantizer 201, the DCT coefficient Tg is quantized based on the derived quantization step.
[0018]
The quantized value Qg obtained by this quantization processing is output to the VLC unit 112 and the inverse quantization device 108. In the VLC unit 112, variable length coding processing for converting the quantized value Qg from the quantization device 107 into a variable length code is performed, and the variable length code is output as re-encoded data Eg2. Further, the rate control device 113 generates the quantization control signal Cq based on the output Eg2 of the VLC and outputs it to the quantization device 107.
[0019]
On the other hand, in the inverse quantization device 108, the quantization value Qg from the quantization device 107 is subjected to inverse quantization processing, and the DCT coefficient IQg 2 obtained by this inverse quantization processing is output to the IDCT device 109. . The DCT coefficient IQg2 is converted into spatial domain data ITg2 by IDCT (Inverse Discrete Cosine Transform) processing in the IDCT unit 109, and the data ITg2 is output to the adder 110. In the adder 110, the addition process of the output data ITg2 from the IDCT unit 109 and the prediction data Mg2 is performed. The reproduction data Rg2 obtained by this addition processing is stored as prediction data Mg2 in the frame memory 111.
In the re-encoding system 100a shown in FIG. 20, the input encoded data (bit stream) and the encoded data output from this system correspond to the same encoding method (MPEG2 method). However, the re-encoding system 100a converts encoded data corresponding to the H261 standard, H263 standard, MPEG1 standard, or MPEG2 standard into encoded data corresponding to the MPEG4 standard. Good. The re-encoding system 100a may convert encoded data corresponding to the MPEG4 standard into encoded data corresponding to the H263 standard.
[0020]
[Problems to be solved by the invention]
However, the conventional re-encoding system has a problem that it is difficult to reduce the quantization error included in the re-encoded stream.
That is, as described above, the encoded data Eg1 input to the re-encoding system 100a is data obtained by performing an encoding process including a quantization process on the image data. Includes a quantization error. Therefore, the re-encoded data Eg2 obtained by performing the decoding process and the re-encoding process on the encoded data Eg1 includes a quantization error included in the encoded data Eg1. In addition, depending on the quantization condition in the re-encoding process, the quantization error included in the re-encoded data Eg2 may be significantly larger than the quantization error included in the encoded data Eg1. There is a point.
[0021]
Furthermore, in the conventional re-encoding system 100a, there is a problem that it is difficult to set the quantization step in the re-encoding process so that the encoding error can be minimized, and this problem will be described in detail below.
FIG. 22 is a diagram for explaining the relationship between the bit rate of the encoded stream and the encoding error included in the encoded stream. FIG. 22 shows the relationship between the two based on the rate error theory on two-dimensional coordinates. This is illustrated by graph C. In this coordinate, the horizontal axis corresponds to the bit rate and the vertical axis corresponds to the encoding error.
[0022]
In general, a relationship based on the rate error theory is established between the bit rate and the coding error, and a lower limit value of the coding error is determined according to the bit rate. In other words, if the bit rate is high, the encoding error can be made smaller, but if the bit rate is low, the encoding error cannot be reduced so much.
Therefore, in the direct encoding process, that is, the process of encoding the image signal that has not been subjected to the encoding process, the optimum quantization step is determined as follows.
[0023]
First, based on two sets of bit rates and encoding errors obtained by performing an encoding process including a quantization process on the image signal in advance using two quantization steps, an image to be encoded A relational expression (exponential function) corresponding to the bit rate and encoding error is obtained. From this relational expression, the lower limit value of the encoding error corresponding to the bit rate of the encoded stream is known.
[0024]
Next, based on this relational expression, the quantization step is determined so that the coding error is minimized for each frame within a range where the total number of bits corresponding to each frame (screen) does not exceed the frame target bit number. ing. That is, the quantization step is determined so that the actual coding error is closest to the lower limit value of the coding error corresponding to the maximum allowable bit rate.
However, such a method for deriving the optimum quantization step is based on a relational expression (exponential function) indicating the relation between the bit rate and the coding error, and cannot be used in re-encoding processing in which this relational expression cannot be derived. There's a problem.
[0025]
That is, in the stream obtained by the re-encoding process, the encoding error is a combination of the encoding error included in the input stream and the encoding error generated by the re-encoding process. In this case, since the encoding error included in the input stream is unknown, a relational expression (exponential function) indicating the relationship between the bit rate and the encoding error cannot be obtained as in the direct encoding process.
In addition, since the quantization step derivation method determines the quantization step in units of frames (screens), there is a problem in that the encoding error cannot be reduced efficiently.
[0026]
Further, the quantization step derivation method is to determine a quantization step so that a coding error with respect to a target screen (frame to be processed) to be encoded is reduced. There is a problem that does not correspond to the above, and this problem will be briefly described below.
FIG. 23 is a schematic diagram for explaining inter-picture predictive encoding processing in MPEG, and includes image data of typical moving images to be subjected to MPEG-compatible encoding processing, including I frame, P frame, and B frame. It is shown.
[0027]
Here, the I frame F (1) is a frame on which image data corresponding to the I frame F (1) is subjected to an intra-screen encoding process that does not refer to image data corresponding to another frame. P frames F (3) and F (5) are inter-frame predictions that refer to image data corresponding to encoded frames whose display order is earlier than these frames with respect to the image data corresponding thereto. It is a frame on which encoding processing is performed. The B frames F (2) and F (4) are inter-picture predictions that refer to image data corresponding to encoded frames whose display order is before and after these frames. It is a frame on which encoding processing is performed. In addition, display times T1 to T5 (T1 <T2 <T3 <T4 <T5) are set in the frames F (1) to F (5).
[0028]
In this case, the encoding process for the P frame F (3) is performed with reference to the image data corresponding to the I frame F (1), and the image data corresponding to the P frame F (3) is the P frame F. (5) It will be referred to when encoding the B frames F (2) and F (4). Therefore, the coding error associated with the coding process for the P frame F (3) increases at least the prediction residual in the inter-frame prediction coding process for the frames F (2), F (4), and F (5). It will be.
[0029]
In other words, in the inter-picture predictive encoding process, it is possible to correspond to the frame F (3) only by setting the quantization step corresponding to the frame F (3) so as to minimize the encoding error for the frame F (3). There has been a problem that the encoding error corresponding to the frames F (2), F (4), and F (5) that are encoded with reference to the image data cannot be effectively minimized.
[0030]
The present invention has been made to solve the above-described problems, and performs re-encoding processing on encoded data obtained by encoding image data to increase a quantization error included in the encoded data. Encoded data conversion method capable of effectively suppressing The It is an object of the present invention to obtain a data recording medium storing a program for performing processing by an encoded data conversion method by a computer.
[0032]
[Means for Solving the Problems]
The encoded data conversion method according to the present invention (Claim 1) is the first encoded data obtained by performing the encoding process including the first orthogonal transform process and the first quantization process on the image data. A decoding process that generates decoded data by decoding for each coding unit and a re-encoding process that generates second encoded data by encoding the decoded data for each coding unit A method of transforming a quantized data, wherein the decoding process is performed by converting a quantization coefficient obtained from the first encoded data into an inverse quantum by the first quantization step used in the first quantization process. The re-encoding process is a second orthogonal transform process for orthogonally transforming the decoded data to generate frequency domain data, the second encoded data, and the re-encoding process. Second based on the first quantization step; Deriving a quantization step, a process that includes a second quantization process for quantizing with data of the frequency domain in the second quantization step The second quantization process is based on a candidate derivation process for deriving a quantization step candidate based on the second encoded data, and the quantization step candidate and the first quantization step. A quantization step derivation process for deriving the second quantization step, wherein the quantization step derivation process is performed when the quantization step candidate is greater than or equal to the value of the first quantization step, and When having a value within a range smaller than twice the value of the first quantization step, as the second quantization step, a quantization step having the same value as the value of the first quantization step, Alternatively, when a quantization step having a value twice or more the value of the first quantization step is derived and the quantization step candidate has a value outside the above range, the second quantization step is as follows: The amount And process of deriving the reduction step candidate It is a thing.
[0039]
This invention (claim) 2 The data recording medium according to claim 1 stores a data conversion program for performing the encoded data conversion method according to claim 1 by a computer.
[0057]
DETAILED DESCRIPTION OF THE INVENTION
First, the focus and basic principles of the present invention will be described.
As described in the related art, the encoded data input to the re-encoding system is obtained by performing encoding processing including quantization processing (first quantization processing) on image data. The encoded data includes a quantization error.
Further, in the re-encoding system, decoding processing including inverse quantization processing is performed on the encoded data to generate decoded data, and the decoded data is re-quantized (first processing). Re-encoded data is generated by performing an encoding process including a second quantization process.
[0058]
The inventor of the present invention, in the re-encoded data obtained in this way, depending on the quantization condition in the re-encoding process, the quantization error is significantly larger than the quantization error included in the encoded data. As a result of repeated research on the subject, the second quantization process included in the re-encoded data is determined by the magnitude relationship between the quantization step in the first quantization process and the quantization step in the second quantization process. We found that the magnitude of the resulting quantization error changed significantly.
[0059]
This will be briefly described below using graphs.
FIG. 7 is a graph showing the relationship between the bit rate of re-encoded data and the quantization distortion included in the re-encoded data, using a graph on two-dimensional coordinates. Here, the horizontal axis corresponds to the bit rate, and the vertical axis corresponds to the inverse of the quantization error as the quantization distortion. Here, a solid line graph A indicates the bit rate and the quantization corresponding to the encoded data (hereinafter also referred to as direct encoded data) obtained by performing the encoding process including the quantization process only once on the image data. The relationship of distortion is shown. A dotted line graph B shows the relationship between the bit rate and the quantization distortion corresponding to the re-encoded data obtained by re-encoding the directly encoded data.
[0060]
As can be seen from the graph A of the solid line, in the encoding process (direct encoding process) in which the image data is quantized once, the bit rate and the quantization distortion using the quantization step in the encoding process as parameters. The function of the inverse of (quantization error) is almost linear. On the other hand, in the re-encoding process for the directly encoded data, as shown by the dotted line B, the inverse of the bit rate and the quantization distortion (quantization error) using the quantization step in the re-encoding process as a parameter. The function of and is non-linear.
[0061]
For example, when the quantization process in the direct encoding process is performed with the quantization step value (first quantization step value) QPi (QPi = QP), the quantization step value (the first quantization step value in the re-encoding process) 2 quantization step value) QPr is set within a predetermined range (QP ≦ QPr ≦ 2QP), the quantization step value (first quantization step value) QPi in the direct encoding process is set within the predetermined range (QP ≦ QPi ≦ It can be seen that the quantization error is remarkably increased as compared to when it is set within 2QP).
[0062]
Specifically, the quantization error in the re-encoded data has a high bit rate, that is, the quantization step value QPi in the first quantization process and the quantization step value QPr in the second quantization process. On the other hand, when the quantization step value QPr in the second quantization process is 2QP (QPi = QP) or more and the bit rate of the re-encoded data is low, the direct code Experiments have now shown that there is almost no difference between the quantization error in the quantization process and the quantization error due to the re-encoding process.
[0063]
In addition, when the second quantization process is performed in a quantization step that is denser than the quantization step of the first quantization process, the quantization error in the re-encoded data is caused by the quantization error caused by the second quantization process. The quantization error resulting from the first quantization process is larger and dominant than the quantization error. Therefore, even if the second quantization process is performed in a quantization step that is denser than the quantization step in the first quantization process, the bit rate in the re-encoded data only increases and the quantization error can be reduced. It can be said that it is meaningless.
[0064]
Therefore, the present inventor pays attention to the relationship between the quantization step and the quantization error in the re-encoding process as described above, and the quantization error of the re-encoded data obtained by the re-encoding process is directly encoded. In order to solve the problem that it may be significantly larger than the quantization error of the encoded data obtained by the processing, in the re-encoding processing for the encoded data obtained by directly performing the encoding processing on the image data, Then, the quantization step value (second quantization step value) QPr in the quantization process is set to 2 of the quantization step value (first quantization step value) QPi of the quantization process included in the direct encoding process. I came up with a way to make it more than double.
[0065]
Furthermore, in the MPEG encoding method, quantization processing optimized for each of the intra-screen coding processing and the inter-screen coding processing is used, and therefore, the quantization method for intra-screen coding is an inter-screen coding method. This is different from the quantization method for encoding. Also, the magnitude of the quantization error generated by the re-encoding process is closely related to the quantization method in the re-encoding process.
[0066]
For example, in the intra-picture coding process and the inter-picture coding process, the quantization process based on MPEG is performed in the same first quantization step, and the bit streams obtained by these coding processes are similarly applied to the same. When the re-encoding process including the second quantization process by the second quantization step which is k times the first quantization step is performed, the quantization error due to the intra-picture encoding process is the inter-picture encoding process. This experiment also revealed that the error is larger than the quantization error due to.
[0067]
Accordingly, the present inventor has found that the ratio of the second quantization step to the first quantization step in the intra-picture encoding process (requantization ratio) is smaller than the re-quantization ratio in the inter-picture encoding process. A method for deriving the second quantization step was devised.
[0068]
In addition, as a result of intensive studies to solve the problem that it is difficult to set the quantization step Qrd in the re-encoding process described above so that the encoding error can be minimized, the inventor has conducted a bit rate. The relationship between the coding error and the coding error varies depending on the coding method and the image to be coded, but the variation of the coding error relative to the unit variation of the bit rate (that is, the slope of the curve graph C shown in FIG. 23). If all the coding units (for example, a block consisting of 8 × 8 pixels or a macro block consisting of 16 × 16 pixels) constituting one frame are substantially constant, all codes in one frame It has been found that the average value of the encoding error corresponding to the encoding unit is minimized.
[0069]
Therefore, the re-encoding method and re-encoding system according to the present invention quantizes and encodes an input encoded stream so that the bit rate is reduced, and a plurality of types of simulated encoding with different quantization steps. Processing is performed for each coding unit, and the fluctuation amount of the coding error with respect to the unit amount fluctuation of the bit rate is obtained as the re-coding error increase rate, and the re-coding error increase rate corresponding to each coding unit is as constant as possible. Thus, the quantization step is determined for each coding unit.
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
[0070]
(Embodiment 1)
FIG. 1 is a block diagram for explaining a re-encoding system 10 according to an embodiment of the present invention.
The re-encoding system 10 according to the first embodiment receives encoded data Eg1 obtained by performing an encoding process including a quantization process (first quantization process) on image data. Decoding unit Da1 that performs decoding processing including inverse quantization processing on data Eg1 to generate decoded data Rg1, and quantization processing (second quantization processing) again on this decoded data Rg1 ) Including the encoding unit Ea1 that generates the re-encoded data Eg2.
[0071]
The decoding unit Da1 of the re-encoding system 10 according to the first embodiment is the inverse of the output Vg of the VLD (variable length decoder) 100 instead of the inverse quantization device 101 in the conventional decoding unit D1. In addition to performing the quantization process, the apparatus includes an inverse quantization device 101a that outputs the first quantization step Qs1 used at this time to the encoding unit E1. Here, the first quantization step Qs1 used in the inverse quantization process is the same as the quantization step used in the quantization process (first quantization process) for the image data. Further, the re-encoding unit Ea1 of the re-encoding system 10 according to the first embodiment replaces the quantization device 107 in the conventional re-encoding unit E1 with respect to the output Tg of the DCT unit 106, and a rate control device 113. And a quantization device 151 that performs a quantization process based on the quantization control signal Cq from the first quantization step Qs1 from the inverse quantization device 101a.
The remaining configuration of the re-encoding system 10 according to the first embodiment is the same as that of the conventional re-encoding system 100a.
[0072]
FIG. 2 is a block diagram showing a specific configuration of the quantization device 151 in the encoding unit Ea1.
The quantization device 151 performs a quantization step based on the quantization control signal Cq from the rate control device 113 so that the number of encoded bits for the target frame to be encoded approaches the target number of bits for the target frame. Quantization step candidate derivation unit 250 for deriving the candidate Qsb, and a quantization step in the second quantization process (second quantization step) based on the quantization step candidate Qsb and the first quantization step Qs1 A quantization step derivation unit 251 for deriving Qs2, and a quantization unit 201 for performing quantization on the output Tg of the DCT unit 106 based on the second quantization step Qs2 and outputting a quantization coefficient Qg have.
[0073]
FIG. 3 is a block diagram showing a specific configuration of the quantization step deriving unit 251 in the quantization apparatus 151.
The quantization step derivation unit 251 includes a comparator 260 that compares the quantization step candidate Qsb from the quantization step candidate derivation unit 250 with the first quantization step Qs1 from the inverse quantization apparatus 101a, and the comparator A switch 261 that selects and outputs one of the quantization step candidate Qsb and the first quantization step Qs1 based on the comparison result CP1 of 260, and outputs the output of the switch 261 to the second quantization step. It is configured to output as Qs2.
Specifically, the switch 261 selects the first quantization step Qs1 if the quantization step candidate Qsb is less than the first quantization step Qs1, and the quantization step candidate Qsb is the first quantization step. If Qs1 or more, the quantization step candidate Qsb is selected.
[0074]
Next, the operation will be described.
When the encoded data Eg1 obtained by performing the encoding process including the quantization process on the image data is input to the re-encoding system 10 of the first embodiment, the decoding unit Da1 receives the encoded data The decoded data Eg1 is subjected to a decoding process including an inverse quantization process to generate decoded data (reproduced data) Rg1. In the case of the inverse quantization process, the first quantization step Qs1 used in the quantization process is output from the inverse quantization apparatus 101a to the quantization apparatus 151 of the encoding unit Ea1. .
[0075]
When the reproduction data Rg1 output from the decoding unit Da1 is input to the encoding unit Ea1, the subtracter 105 obtains a difference value between the reproduction data Rg1 from the decoding unit Da1 and the prediction data Mg2. This is output to the DCT unit 106 as difference data Dg. In the DCT unit 106, the difference data Dg is converted into a DCT coefficient Tg by DCT (Discrete Cosine Transform) processing, and the DCT coefficient Tg is output to the quantization device 151.
[0076]
In the quantization device 151, the DCT coefficient Tg from the DCT unit 106 is based on the first quantization step Qs1 from the inverse quantization device 101a of the decoding unit Da1 and the quantization control signal Cq from the rate control device 113. Is subjected to a quantization process (second quantization process). The quantization value (quantization coefficient) Qg obtained by this quantization processing is output to the VLC unit 112 and the inverse quantization device 108.
[0077]
Then, the VLC unit 112 performs variable length coding processing for converting the quantized value Qg from the quantization device 151 into a variable length code, and the variable length code is output as re-encoded data Eg2. Further, the rate control device 113 generates a quantization control signal Cq indicating the target number of bits for the target frame based on the output Eg2 of the VLC unit 112 and outputs the generated quantization control signal Cq to the quantization device 151.
[0078]
On the other hand, in the inverse quantization device 108, the quantization value Qg from the quantization device 151 is subjected to inverse quantization processing, and the DCT coefficient IQg2 obtained by this inverse quantization processing is output to the IDCT device 109. . The DCT coefficient IQg2 is converted into data ITg2 in the spatial domain by IDCT (Inverse Discrete Cosine Transform) processing in the IDCT unit 109 and output to the adder 110. The adder 110 adds the output data ITg2 from the IDCT unit 109 and the prediction data Mg2, and the reproduction data Rg2 obtained by the addition processing is stored in the frame memory 111 as prediction data Mg2.
[0079]
Hereinafter, the operation of the quantization apparatus 151 will be described in detail with reference to FIG.
A quantization control signal Cq that is output from the rate control device 113 and indicates the target number of bits for the target frame to be encoded is input to the quantization step candidate derivation unit 250. The quantization step candidate derivation unit 250 derives a quantization step candidate Qsb such that the number of coded bits for the target frame approaches the target number of bits for the target frame, and the quantization step candidate Qsb is obtained from the quantization step derivation unit 251. Is output.
Then, the quantization step deriving unit 251 derives the second quantization step Qs2 based on the quantization step candidate Qsb and the first quantization step Qs1 from the decoding unit Da1, and the second quantization step Qs2 is derived. Step Qs2 is output to the quantizer 201. The quantizer 201 performs a quantization process on the output Tg of the DCT device based on the second quantization step Qs2.
[0080]
At this time, in the quantization step derivation unit 251 shown in FIG. 3, the output 260 of the quantization step candidate derivation unit 250 is output to the comparator 260 and the output of the inverse quantization apparatus 101a of the decoding unit Da1. Qs1 (first quantization step) is input. The comparator 260 compares the output Qsb of the quantization step candidate derivation unit 250 with the output Qs1 of the inverse quantization apparatus 101a, and outputs a comparison result CP1 to the switch 261. Based on the comparison result CP1, the switch 261 selects one of the output Qsb of the quantization step candidate derivation unit 250 and the output Qs1 of the inverse quantization apparatus 101a and derives it as the second quantization step Qs2. .
[0081]
As described above, according to the re-encoding system according to the first embodiment, the inverse quantization apparatus 101a in the decoding unit Da1 performs the inverse quantization process on the output Vg of the VLD unit 100 and performs the inverse quantization process. The first quantization step Qs1 used at the time is configured to be output to the encoding unit Ea1, and the quantization device 151 in the encoding unit Ea1 is connected to the quantization control signal Cq indicating the target number of bits for the target frame and Based on the first quantization step Qs1, since the quantization process is performed with a larger quantization step than the first quantization step Qs1, the re-encoding process for the encoded data Eg1 is performed in the number of bits. This can be performed while suppressing an increase in quantization error without causing an increase in.
[0082]
In the first embodiment, as the second quantization step Qs2, if necessary, the quantization step candidate Qsb obtained based on the quantization control signal Cq (target bit number) and the first quantization step Qs2 Since one of the quantization steps is used, the number of bits per frame of the re-encoded data Eg2 slightly increases or decreases with respect to the target number of bits as compared with the case where only the quantization step candidate Qsb is used as the second quantization step. However, the increase / decrease in the number of bits is negligible. That is, in the first embodiment, the quantization process in the re-encoding process is performed in a block unit having a predetermined number of pixels in the frame and with a quantization step larger than the first quantization step Qs1. . For this reason, in an actual application, the increase or decrease in the macro number of bits due to the change in the number of bits in frame units, which is important, is negligible. Therefore, the configuration in which the second quantization process is performed in a quantization step larger than the first quantization step Qs1 in the first embodiment is based on the rate control in this first embodiment, that is, the re-encoded data. It does not hinder the feedback control that controls the number of bits per frame by the quantization step.
[0083]
(Embodiment 2)
FIG. 4 is a block diagram for explaining the quantizing device 152 constituting the re-encoding system according to Embodiment 2 of the present invention.
The quantization device 152 in the re-encoding system of the second embodiment replaces the quantization step derivation unit 251 in the quantization device 151 of the first embodiment with the quantization step candidate Qsb as the first quantization process. Quantization step (first quantization step) at Qs1 is compared with a threshold value Qth obtained from Qs1 and a constant multiple value Qmu obtained by multiplying the first quantization step Qs1 by a constant number. The quantization step derivation unit 252 for deriving the quantization step Qs2 is provided. Here, the threshold value Qth is m times the first quantization step Qs1, and the constant multiple value Qmu is n times (n> m) the first quantization step Qs1, specifically, , M is 1.5, and n is 2.
The other configurations in the re-encoding system according to the second embodiment are the same as those in the re-encoding system 10 according to the first embodiment.
[0084]
FIG. 5 shows a quantization step deriving unit 252 constituting the quantization device 152.
The quantization step derivation unit 252 generates a threshold value derivation unit 262 that derives a threshold value Qth (= m × Qs1) based on the first quantization step Qs1, and the threshold value Qth and the quantization step candidate derivation unit 250. The comparison with the quantized quantization step candidate Qsb, and outputs a comparison output CP2 indicating the comparison result, and based on the output CP2 of the comparator 263, the first quantization step Qs1 and the quantum step And a switch 264 that selects one of the quantization step candidates Qsb and outputs it as the selected quantization step Qse. Here, when the result of the comparison by the comparator 263 is that the quantization step candidate Qsb is less than the threshold value Qth, the switch 264 outputs the first quantization step Qs1 as the selective quantization step Qse, When the quantization step candidate Qsb is equal to or greater than the threshold value Qth, the quantization step candidate Qsb is output as the selective quantization step Qse.
[0085]
The quantization step derivation unit 252 includes a constant multiplier 265 that outputs a constant multiple value Qmu (= n × Qs1) by multiplying the first quantization step Qs1 by a constant number (n times), and the constant multiple value. Qmu is compared with the quantization step candidate Qsb from the quantization step candidate derivation unit 250, and a comparator 266 that outputs a comparison output CP3 indicating the comparison result, and a comparison output CP3 from the comparator 266 And a switch 267 that selects one of the selected quantization step Qse from the switch 264 and the constant multiple value Qmu from the constant multiplier 265 and outputs it as the second quantization step Qs2. Here, when the result of the comparison by the comparator 266 is that the quantization step candidate Qsb is less than the constant multiple value Qmu, the switch 267 outputs the constant value Qmu as the second quantization step Qs2. When the quantization step candidate Qsb is equal to or larger than the constant multiple value Qmu, the selected quantization step Qse from the switch 264 is output as the second quantization step Qs2.
The multiple value n in the constant multiplier 265 is equal to or greater than the multiple value m in the threshold deriving unit 262. The multiple value m in the threshold deriving unit 262 is a target bit rate, frame rate, quantization method, or the like. It is possible to switch by.
[0086]
FIG. 6 is a graph showing the relationship between the second quantization step Qs2 obtained by the quantization step derivation unit 252 configured as described above and the quantization step candidate Qsb output from the quantization step candidate derivation unit 250. Is shown. Note that m and n are m = 1.5 and n = 2, respectively.
As can be seen from the graph D, if the quantization step candidate Qsb is less than the threshold value Qth, the quantization step derivation unit 252 outputs the first quantization step Qs1 as the second quantization step Qs2. If the quantization step candidate Qsb is equal to or greater than the threshold value Qth (1.5 × Qs1) and less than the constant multiple value Qmu (= 2 × Qs1), it is twice the first quantization step Qs1 (2 × Qs1). Is selected as the second quantization step Qs2. Further, if the quantization step candidate Qsb is equal to or greater than the multiple value Qmu (= 2 × Qs1), the quantization step candidate Qsb is selected as the second quantization step Qs2.
[0087]
Next, the operation will be described.
In the re-encoding system of the second embodiment, the operations other than the quantization step derivation unit 252 constituting the quantization device 152 are the same as those in the re-encoding system 10 of the first embodiment. Therefore, only the operation of the quantization step derivation unit 252 will be described in detail below.
[0088]
In the re-encoding system of the second embodiment, when the encoding process including the quantization process is performed on the data Rg reproduced by the decoding unit Da1, the quantization apparatus 152 The quantization step candidate derivation unit 250 generates a quantization step candidate Qsb. Then, in the quantization step deriving device 252, based on the threshold value Qth and the constant multiple value Qmu obtained from the first quantization step Qs1 supplied from the inverse quantization device 101a of the decoding unit Da1, the first quantum value is calculated. One of the quantization step Qs1, the constant multiple value Qmu, and the quantization step candidate Qsb is selected as the second quantization step Qs2. Then, the quantizer 201 performs a quantization process on the frequency domain data Tg based on the second quantization step Qs2.
[0089]
Hereinafter, the operation of the quantization step deriving unit 252 will be specifically described.
When the first quantization step Qs1 is input from the decoding unit to the quantization step deriving unit 252, the threshold deriving unit 262 derives a predetermined threshold Qth by an operation of multiplying the first quantization step Qs1 by m. The threshold value Qth is output to the comparator 263. Then, the comparator 263 compares the quantization step candidate Qsb from the quantization step candidate derivation 250 with the threshold Qth from the threshold derivation 262, and outputs a comparison output CP2 indicating the comparison result to the switch 264. The switch 264 selects one of the first quantization step Qs1 and the quantization step candidate Qsb based on the comparison output CP2 and outputs the selected quantization step Qse to the switch 267.
[0090]
At this time, the constant multiplier 265 generates a constant multiple value Qmu by an operation of multiplying the first quantization step Qs1 from the decoding unit Da1 by n, and the constant multiple value Qmu is supplied to the switch 267 and the comparator 266. Is output. In this comparator 266, the quantization step candidate Qsb from the quantization step candidate derivation unit 250 is compared with the constant multiple value Qmu from the constant multiplier 265, and the comparison output CP3 indicating the comparison result is output to the switch 267. Is done. Then, in the switch 267, one of the constant multiplication value Qmu from the constant multiplier 265 and the selected quantization step Qse selected by the switch 264 is selected based on the comparison output CP3, and the second quantum is selected. Step Qs2.
[0091]
As described above, in the re-encoding system according to the second embodiment, quantization for deriving the quantization step candidate Qsb based on the relationship between the bit rate of the re-encoded data and the quantization distortion included in the re-encoded data. Deriving a quantization step (second quantization step) Qs2 in the re-encoding process based on the step candidate derivation unit 250, the quantization step candidate Qsb, and the first quantization step Qs1 used in the inverse quantization process The quantization step candidate Qsb is within an optimum range determined from the magnitude relationship between the quantization step candidate Qsb, the first quantization step Qs1 and its constant multiple value Qmu. If it has a value, the quantization step candidate Qsb is output as a second quantization step Qs2, and the quantization step candidate Qsb When the value is out of the range, the first quantization step Qs1 or a quantization step Qmu that is a multiple of the first quantization step Qs1 is output, so that the re-encoding process on the encoded data Eg1 is performed without increasing the number of bits. This can be performed while effectively suppressing an increase in the conversion error.
[0092]
In the second embodiment, when the quantization step candidate Qsb is less than the constant multiple value Qmu (n times the first quantization step Qs1), the second quantization step Qs2 is set to the threshold value Qth. With (m × Qs1) as a reference, rounding is performed to either the first quantization step Qs1 or a constant multiple value Qmu that is n times the first quantization step Qs1, but the threshold value Qth is varied. You may do it.
For example, the threshold value Qth is frequently switched between the second quantization step Qs2 and the constant multiple value Qmu, which is n times the first quantization step Qs1. By changing it so that it changes, it is possible to make the rate control with a predetermined bit rate the encoding bit rate highly responsive.
[0093]
Specifically, the threshold value Qth is changed as follows, and the quantization step Qs2 is determined based on the obtained new threshold value Qth ′.
First, the average of the quantization step candidates Qsb is obtained as the target average quantization step Qt, and the average of the second quantization step Qs2 is obtained as the actual average quantization step Qave.
When the actual average quantization step Qave is larger than the target average quantization step Qt, in other words, when the quantization step candidate Qsb has an average small value, Qth ′ = Qth / 2 is set as a new threshold value. And However, when Qth ′ is smaller than Qs1, Qth ′ = Qs1.
Further, when the actual average quantization step Qave is smaller than the target average quantization step Qt, in other words, when the quantization step candidate Qsb has an average large value, Qth ′ = Qth + Qth / 2 is set as a new threshold value. And However, when Qth ′ is larger than Qmu, Qth ′ = Qmu.
[0094]
(Embodiment 3)
FIG. 8 is a block diagram for explaining the re-encoding system 30 according to the third embodiment.
The re-encoding system 30 according to the third embodiment replaces the quantization device 151 in the encoding unit Ea1 according to the first embodiment with quantization steps corresponding to the intra-frame coding process and the inter-frame coding process, respectively. And a quantization device 153 that performs quantization processing in quantization steps corresponding to each encoding processing, and switches between intra-screen encoding processing and inter-screen encoding processing in units of blocks or frames. The quantization process can be switched between the one corresponding to the intra-frame encoding process (intra-screen quantization process) and the one corresponding to the inter-picture encoding process (inter-screen quantization process). ing.
[0095]
FIG. 9 is a block diagram showing the configuration of the quantization device 153. As shown in FIG.
The quantization device 153 performs one frame quantization step for each macroblock in the in-screen quantization process based on the first quantization step Qs1 used in the inverse quantization process by the decoding unit Da1. On the basis of the in-screen average quantization step deriving device 270 for calculating a value Qintra (first in-screen average quantization step QsI1) obtained by averaging every time, and the inter-screen quantum based on the first quantization step Qs1. An inter-screen average quantization step derivation unit 271 that calculates a value Qinter (first inter-screen average quantization step QsP1) obtained by averaging the quantization steps for each macroblock in the quantization process for each frame. ing.
[0096]
Further, in the quantization device 153, in the in-screen quantization process based on the second quantization step Qs2 used in the quantization process up to the previous frame immediately before the target frame to be encoded. An in-screen average quantization step derivation unit 272a for calculating a value Qintra (second in-screen average quantization step QsI2) obtained by averaging the quantization steps for each macroblock for each frame; and the second quantum The inter-screen average for calculating a value Qinter (second inter-screen average quantization step QsP2) obtained by averaging the quantization steps for each macroblock in the inter-screen quantization processing for each frame based on the quantization step Qs2 A quantization step deriving device 272b.
[0097]
Further, the quantization device 153 refers to the first and second intra-screen average quantization steps SQsI1 and QsI2 and the first and second inter-screen average quantization steps QsP1 and QsP2, and thereby performs a quantization control signal. A quantization step derivation unit 273 that derives the quantization step Qs2 from the target number of bits input as Cq, and a quantizer 201 that quantizes the output Tg from the DCT unit 106 based on the second quantization step Qs2. And have.
[0098]
FIG. 10 is a block diagram showing a specific configuration of the quantization step deriving device 273.
The quantization step derivation unit 273 corresponds to the processed macroblock indicated by the quantization control signal Cq based on the first intra-screen average quantization step QsI1 and the first inter-screen average quantization step QsP1. A frame target bit number determiner 710 for calculating a target bit number fCg for the processing target frame to be requantized from the target bit number to be requantized, and the target bit number fCg for the processing target frame and the quantum from the rate control device 113 A macroblock target bit number determiner 711 for generating a bit number mCg that can be used for the processed macroblock based on the control signal Cq, and the bit number mCg, the second in-screen average quantization step QsI2 , The second inter-screen average quantization step QsP2 and the quantum from the rate control device 113 Based on the control signal Cq, and a quantization step determiner 712 determines a quantization step Qs2 for the processing macro block.
[0099]
Here, the value of the first intra-screen average quantization step QsI1 is Qintra, and the value of the first inter-screen average quantization step QsP1 is Qinter. The ratio between the intra-screen requantization step and the inter-screen requantization step is set so that the number of encoded bits is Nintra and Ninter, respectively, and the ratio of the requantization error in the intra-frame encoding process and the inter-screen encoding process is corrected. Is α × Qintra: Qinter. Then, since the quantization step and the number of encoded bits are in an inversely proportional relationship, the ratio of the number of bits per frame between the intra-coded frame after re-quantization and the inter-coded frame is Nintra / α: Ninter. Here, α is a value satisfying 0 <α <1.
[0100]
Therefore, the frame target bit number determiner 710 determines that the ratio between the intra-frame encoded frame and the inter-frame encoded frame regarding the number of bits per unit time output by the re-encoding process is Nintra / α × screen. The target number of bits fCg per frame is generated so that the number of inner encoded frames is Ninter × the number of interframe encoded frames.
[0101]
Further, the macroblock target bit number determiner 711 uses the bit generated in the encoding process for the already processed macroblock in the frame to be processed from the target bit number fCg per frame derived by the frame target bit number determiner 710. The number of bits is subtracted, and the remaining number of bits corresponding to the processed frame (that is, the number of bits that can be used for encoding the unprocessed macroblock in the processed frame) is divided by the number of unprocessed macroblocks. The number of bits is output to the macroblock quantization step determiner 712 as the number of bits that can be used for the encoded macroblock.
[0102]
The number of bits corresponding to a macroblock and the quantization step are generally in the following relationship.
Intrascreen coding quantization step
= Kintra / Number of bits that can be used for coded macroblock (Formula A)
[0103]
Inter-screen coding quantization step
= Kinter / number of bits available for coded macroblock (formula B)
Here, Kintra and Kinter are constants. In addition, the intra-frame coding quantization step is a quantization step used for each macroblock to be processed in the quantization process (intra-screen quantization process) in the intra-screen coding process. The quantization quantization step is a quantization step used for each macroblock to be processed in the quantization processing (inter-screen quantization processing) in the inter-screen encoding processing.
[0104]
In the macroblock quantization step determiner 712, the following (formula C) and (formula D) are based on the target bit number Cg from the rate controller 113, the in-screen average quantization step QsI2, and the inter-screen average quantization step QsP2. ) To obtain the values of Kintra and Kinter for each macroblock. Next, Kintra and Kinter in the above (formula A) or (formula B) are updated with the obtained values of Kintra and Kinter, and these (formula A) and (formula B) are updated with respect to the encoded macroblock. By substituting the number of bits that can be used in this manner, the quantization step Qs2 corresponding to each macroblock is derived.
Kintra
= In-screen average quantization step
× (Number of intra-coded bits / number of intra-coded macro blocks) (Formula C)
Kinter
= Inter-screen average quantization step
× (number of inter-coded bits / number of inter-coded macro blocks) (Formula D)
[0105]
Next, the function and effect will be described.
In an encoding method such as MPEG, an encoding process for an image signal (image data) includes an intra-screen encoding process that uses a pixel value correlation within a screen and an inter-screen encoding process that uses a pixel value correlation between screens. Are switched in units of macroblocks or frames. Further, in the encoding process, the quantization method is switched between a method corresponding to the intra-screen encoding process and a method corresponding to the inter-screen encoding process.
[0106]
By the way, since the quantization error caused by the re-encoding process differs depending on the quantization method, it is necessary to derive a quantization step corresponding to the type of the encoding process in order to reduce re-encoding distortion. .
In particular, in the MPEG system, when re-encoding processing is performed on intra-screen encoded data obtained by intra-screen encoding processing and inter-screen encoded data obtained by inter-screen encoding processing, On the other hand, when the quantization process is performed with the same quantization step, the re-encoding error for intra-frame encoded data tends to be larger than the re-encoding error for inter-frame encoded data.
Therefore, in the re-encoding process for the intra-picture encoded data, it is necessary to perform the re-quantization process in a denser quantization step (that is, a smaller quantization step) compared to the re-encoding process for the inter-picture encoded data. is there. In addition, the number of bits generated by the re-encoding process for the intra-picture encoded data needs to be the target number of bits.
[0107]
That is, in the quantization step derivation unit 273 of the third embodiment, the quantizer is based on the average quantization steps that are the outputs of the intra-screen average quantization step derivation unit 270 and the inter-screen average quantization step derivation unit 271. The number of bits corresponding to one frame generated by the intra-frame coding quantization step, the inter-frame coding quantization step, and the re-coding process in the quantization process 201 is predicted. Then, in the quantization step deriving device 273, based on these prediction values, the above-mentioned intra-frame encoding quantization step and inter-frame encoding quantization step are such that the number of bits corresponding to each frame is a predetermined number of bits on average. In addition, the intra-picture encoding quantization step is determined to be denser than the inter-picture encoding quantization step.
Further, the intra-screen average quantization step derivation unit 272a and the inter-screen average quantization step derivation unit 272b respectively perform the intra-screen quantization step and the inter-screen quantization derived as the second quantization step by the quantization step derivation unit 273, respectively. The average value of the conversion step is calculated. Further, in the quantization step deriving device 273, based on these average values, a relational expression indicating the relationship between the number of target bits corresponding to each macroblock necessary for the second quantization step deriving process and the quantization step ( The above (formula A) and (formula B)) are corrected.
[0108]
Hereinafter, a specific operation of the re-encoding system according to the third embodiment will be described.
In the re-encoding system according to the third embodiment, the operations other than the quantization device 153 constituting the encoding unit Ea1 are the same as those in the re-encoding system 10 according to the first embodiment. Therefore, the operation of the quantization device 153 will be described below.
[0109]
In the re-encoding system of the third embodiment, when the encoding unit Ea1 performs the encoding process including the quantization process on the data Rg generated by the decoding unit Da1, the quantization device 153 Then, the quantization step derivation unit 273 derives the second quantization step Qs2 corresponding to each of the intra-frame coding processing and the inter-screen coding processing, and the frequency based on the second quantization step. A quantization process is performed on the region data Tg.
[0110]
That is, when the first quantization step Qs1 is input from the decoding unit Da1 to the quantization device 153, the average quantization step deriving unit 270 and the inter-screen average quantization step deriving unit 271 input the first quantization step Qs1. From the first quantization step Qs1, a first intra-screen average quantization step QsI1 and a first inter-screen average quantization step QsP1 are respectively calculated, and these quantization steps QsI1 and QsP1 are quantized step deriving device 273. Is output.
[0111]
In the quantization step derivation unit 273, both the quantization steps QsI1 and QsP1, and the second intra-screen average quantization step QsI2 and the second intra-screen average quantization step QsP2 for the re-encoded frame are performed. Referring to FIG. 8, second quantization step Qs 2 is derived based on the target number of bits indicated by quantization control signal Cq, and second quantization step Qs 2 is output to quantizer 201.
[0112]
Then, in this quantizer 201, based on the derived second quantization step Qs2, the quantization process is performed on the frequency domain data Tg from the DCT unit 106 in the encoding unit Ea1. The intra-screen average quantization step derivation unit 272a and the inter-screen average quantization step derivation unit 272b are based on the output Qs2 of the quantization step derivation unit 273, respectively, and the second intra-screen average quantization step QsI2 and A second inter-screen average quantization step QsP2 is calculated.
[0113]
Hereinafter, the operation of the quantization step deriving device 273 will be described in detail with reference to FIG.
The quantization step deriving unit 273 includes a first intra-screen average quantization step QsI1 from the intra-screen average quantization step deriving unit 270 and a first inter-screen average quantization step deriving unit 271. When the quantization step QsP1 is input, the frame target bit number determiner 710, based on these quantization steps QsI1 and QsP1, sets the target bit number for each macroblock indicated by the quantization control signal Cq from the rate control device 113 The target bit number fCg per frame is calculated and output to the macroblock target bit number determiner 711.
[0114]
The macroblock target bit number determiner 711 first calculates the number of bits generated in the encoding process of the processed macroblock in the processed frame and the number of unprocessed macroblocks based on the quantization control signal Cq. . Next, in the macroblock target bit number determiner 711, based on the target bit number fCg per frame from the frame target bit number determiner 710, the processed macroblock in the processed frame is calculated from the target bit number fCg. The number of bits generated in the encoding process is subtracted, and the remaining number of bits of the processed frame is calculated. Then, the calculated remaining number of bits of the frame to be processed is divided by the number of unprocessed macroblocks. The number of bits obtained in this way is output to the macroblock quantization step determiner 712 as the number of bits mCg that can be used for the processed macroblock.
[0115]
When the number of bits mCg that can be used for the encoded macroblock is input to the macroblock quantization step determiner 712, the quantization control signal Cq that is the output of the rate control device 113 and the in-screen average quantization step With reference to the second average quantization step QsI2 that is the output of the derivation unit 272a and the second average quantization step QsP2 that is the output of the inter-screen average quantization step derivation unit 272b, the number of bits corresponding to the macroblock And the quantization step Qs2 for the macro block to be processed is derived based on the relationship between the quantization step (the above (formula A) to (formula D)).
[0116]
As described above, in the re-encoding system 30 according to the third embodiment, the quantization step derivation unit 273 causes each macro to correct the ratio of the re-quantization error in the intra-frame coding process and the inter-frame coding process. Since the second quantization step corresponding to the block is derived, re-encoding processing including intra-screen encoding processing and inter-screen encoding processing is performed while effectively suppressing an increase in quantization error. be able to.
[0117]
(Embodiment 4)
FIG. 11 is a block diagram for explaining a re-encoding system according to Embodiment 4 of the present invention.
The re-encoding system 40 of the fourth embodiment performs a decoding process including an inverse quantization process for each encoding unit on the input stream Vin and outputs decoded image data (decoded stream) Vdec. , A decoder U1 that outputs the quantization step Qin used in the inverse quantization process, and a quantization process by the quantization step Qa with reference to the image data of the reference screen with respect to the decoded image data Vdec And a first simulated encoder U2a that performs a first simulated encoding process including a local decoding process for each encoding unit, and the image data of the reference screen with respect to the image decoded data Vdec, A second simulated encoder U2b that performs a second simulated encoding process including a quantization process by a quantization step Qb larger than the quantization step Qa and a local decoding process for each encoding unit; The input stream Vin is image encoded data obtained by performing an encoding process including a quantization process for each encoding unit on the image data. The coding unit is an area (macroblock) composed of 16 × 16 pixels in one screen (frame).
[0118]
Here, the first simulated encoder U2a outputs the local decoded image data Vstra obtained by the local decoding process included in the first simulated encoding process, and is included in the simulated encoding process. A quantization step Qa corresponding to each coding unit used in the quantization process, a coding error (simulated coding increase error) Da corresponding to each coding unit generated by the simulation coding process, and The number of bits per coding unit (number of simulated coding bits) Ra generated by the simulation coding process is output for each coding unit. The second simulated encoder U2b outputs local decoded image data Vstrb obtained by the local decoding process included in the second simulated encoding process, and is included in the simulated encoding process. The quantization step Qb used in the quantization process, the coding error (simulated coding increase error) Db caused by the simulation coding process, and the number of bits per coding unit (simulation) generated by the simulation coding process The encoding bit number) Rb is output for each encoding unit.
[0119]
Further, the re-encoding system 40 outputs a first simulated memory U3a for storing the locally decoded image data Vstra output from the first simulated encoder U2a and an output from the second simulated encoder U2b. And a second simulated memory U3b for storing the locally decoded image data Vstrb.
[0120]
In addition, the re-encoding system 40 includes a quantization step Qa, a simulated encoding increase error Da, a simulated encoding bit number Ra output from the first simulated encoder U2a, and a second simulated encoding. On the basis of the quantization step Qb, the simulated encoding increase error Db, the simulated encoded bit number Rb, and the number of bits (frame target bit number) Rd assigned to each frame (screen) output from the unit U2b A quantization step derivation unit U74 that selects and outputs one of the quantization steps Qa and Qb as the optimum quantization step Qd corresponding to the coding unit is provided. Specifically, in this quantization step derivation unit U74, recoding is performed for each coding unit from the quantization steps Qa, Qb, simulated coding increase errors Da, Db, and simulated coding bit numbers Ra, Rb. One of the quantization steps Qa and Qb is selected as a quantization step corresponding to each encoding unit so that the increase rate of the encoding error λ is obtained and the re-encoding error increase rate corresponding to each encoding unit is as constant as possible. It has come to be.
[0121]
The re-encoding system 40 performs re-encoding processing including quantization processing and local decoding processing in the quantization step Qd on the decoded image data Vdec with reference to the image data on the reference screen. A main encoder U2d that outputs a re-encoded stream Vout and outputs locally decoded image data Vstrd obtained by the local decoding process, a main memory U3d that stores the locally decoded image data Vstrd, and an external A frame target bit number calculator U6 for calculating the frame target bit number Rd based on the target bit rate Rate supplied from the bit rate and the bit rate of the re-encoded stream Vout.
[0122]
Here, the first simulated memory U3a stores the locally decoded image data Vstra from the first simulated encoder U2a, and the stored image data is simulated for an unprocessed screen following the screen to be processed. In the encoding process, the reference screen image data (reference image data) Va is output to the first simulated encoder U2a. The second simulated memory U3b stores the locally decoded image data Vstrb from the second simulated encoder U2b, and the stored image data is subjected to a simulated encoding process for an unprocessed screen following the screen to be processed. In this case, the image data (reference image data) Vb of the reference screen is output to the second simulated encoder U2b. Further, the main memory U3d converts the stored local decoded image data Vstrd as image data (reference image data) Vrefd of the reference screen during re-encoding processing on the unprocessed screen following the processing target screen. Output to the converter U2d, and the first and second reference image data (reference image data) Vrefa and Vrefb at the time of the first and second simulation encoding processes for the unprocessed screen following the screen to be processed. It is configured to output to two simulated encoders U2a and U2b.
[0123]
As described above, since the locally decoded image data corresponding to the re-encoded stream that is actually output is stored in the main memory U3d, the first and second simulated encoders U2a and U2b Of the image data of each encoded screen stored in the main memory U3d, it corresponds to the same screen as the image data of the encoded screen stored in the first and second simulated memories U3a and U3b. For the image data, instead of the encoded screen image data Va and Vb stored in the first and second simulated memories U3a and U3b, the image of each encoded screen stored in the main memory U3d. Data Vrefa and Vrefb are referred to.
[0124]
Next, the recoding error increase rate λ1 used in the quantization step derivation unit U74 of the fourth embodiment will be described.
FIG. 12 shows a simulation encoding error caused by the simulation encoding process of the decoded image data Vdec by the first and second simulation encoders U3a and U3b of the re-encoding system 40 and the simulation encoding process. It is a figure for demonstrating the relationship with the number of bits per encoding unit (simulated encoding bit number).
[0125]
Here, the actual encoding errors Dra and Drb included in the simulated encoded stream generated by each simulated encoder are the encoding error Din included in the input stream Vin and the simulation generated by each simulated encoding process. This is the sum of encoding errors Da and Db.
That is, the actual encoding error Dra included in the first simulated encoded stream obtained by applying the first simulated encoding process including the quantization process of the quantization step Qa to the decoded image data Vdec is expressed by the following equation (1). It is represented by
Dra = Din + Da (Formula 1)
[0126]
The actual coding error Drb included in the second simulated encoded stream obtained by applying the second simulated encoding process including the quantization process of the quantization step Qb to the decoded image data Vdec is expressed by the following equation (2). It is represented by
Drb = Din + Db (Formula 2)
[0127]
Therefore, the actual encoding error difference ΔDab included in the first and second simulated encoded streams is expressed by the following Equation 3. However, here, since the quantization step Qb in the second simulation encoding process is larger than the quantization step Qa in the first simulation encoding process, the encoding error Db by the second simulation encoding process is equal to the second simulation encoding process. It is larger than the coding error Da by the simulation coding process.

[0128]
Further, the difference ΔRab between the number of bits per coding unit (first and second simulated coding bits) Ra and Rb obtained by the first and second simulated coding processes is expressed by the following equation (4). Is done. However, here, since the quantization step Qb in the second simulation encoding process is larger than the quantization step Qa in the first simulation encoding process, the second simulation encoding bit number Rb is the first simulation code. Smaller than the number of bits Ra.
ΔRab = Ra−Rb (Formula 4)
[0129]
Therefore, the re-encoding error increase rate (a variation in the number of simulated encoded bits per unit variation of the bit rate) λ1 is expressed by the following Equation 5.

[0130]
In general, as the quantization step in the encoding process increases, the amount of variation in encoding error per unit bit number in the encoded stream increases.
Therefore, a quantization step derivation for selecting one of the quantization step Qa in the first simulation encoding process and the quantization step Qb in the second simulation encoding process as the optimum quantization step Qd for each encoding unit. In the unit U74, the re-encoding error increase rate λ1 is small as a condition for error minimization so that the re-encoding error increase rate λ1 has the same value as much as possible between the respective encoding units in one frame. For the coding unit, the larger quantization step Qb is used as the optimum quantization step Qd, and for the coding unit having the larger recoding error increase rate λ1, the smaller one is used as the optimum quantization step Qd. The quantization step Qa is used.
[0131]
FIG. 13 is a block diagram showing a specific configuration of the quantization step derivation unit U74 constituting the re-encoding system 40 of the fourth embodiment.
The quantization step deriving unit U74 generates first and first corresponding to each coding unit generated by the first and second simulated encoding processes from the first and second simulated encoders U2a and U2b. A bit number subtracter U8b which receives the simulated coded bit numbers Ra and Rb of 2 and calculates a difference between these simulated coded bit numbers as a simulated coded bit number increase amount ΔRab; and the first and second simulated codes The encoders U2a and U2b receive simulated encoding errors (recoding increase errors) Da and Db corresponding to the respective encoding units, and the difference between these recoding increase errors is used as a simulated encoding error increase amount Dab. And an error subtracter U9b for calculation.
[0132]
Further, the quantization step derivation unit U74 divides the simulated coding error increase amount ΔDab by the simulated coding bit number increase amount ΔRab to derive a recoding error increase rate λ1 corresponding to each coding unit. One of the quantization steps Qa and Qb corresponding to each coding unit from the unit U10b and the first and second simulated encoders U2a and U2b is selected based on the control signal Qse1 and processed The selection switch U14 output as the optimum quantization step Qd corresponding to the coding unit is compared with the size of the recoding error increase rate λ1 between the coding units, and the number of frame bits (1 frame) A minimum error selector U20 that controls the selection switch 14 with a control signal Qse1 so that the number of bits in the re-encoded stream) becomes the frame target bit number Rd.
[0133]
Next, the operation will be described.
When the input stream Vin is supplied to the re-encoding system 40, the decoder U1 performs a decoding process including an inverse quantization process on the input stream Vin that is the encoded stream, and the decoded stream (Decoded image data) Vdec and the quantization step Qin in the inverse quantization process are output for each coding unit.
Then, in the first simulated encoder U2a, the reference image data Va stored in the first simulated memory U3a or the reference image data Vrefa stored in the main memory U3d is referred to as a processing target. A first simulated encoding process including a quantization process by the quantization step Qa and a local decoding process is performed for each decoding unit on the decoded stream Vdec of the target screen. The quantization step Qa is set not to be smaller than the quantization step Qin used in the inverse quantization process. Accordingly, the first simulated encoder U2a outputs the locally decoded image data Vstra, and also outputs the quantization step Qa, the simulated encoded bit number Ra, and the simulated encoding error Da.
[0134]
Similarly, in the second simulated encoder U2b, the reference image data Vb stored in the second simulated memory U3b or the reference image data Vrefb stored in the main memory U3d is referred to as a processing target. A second simulated encoding process including a quantization process by the quantization step Qb and a local decoding process is performed on the decoded stream Vdec of the target screen. Note that the quantization step Qb is set not to be smaller than the quantization step Qin in the inverse quantization process included in the first simulated encoding process, and to a value larger than the quantization step Qa. Thus, the second simulated encoder U2b outputs the locally decoded image data Vstrb, and also outputs the quantization step Qb, the simulated encoded bit number Rb, and the simulated encoding error Db.
[0135]
At this time, the locally decoded image data Vstra and Vstrb are stored in the first and second simulated memories U3a and U3b as image data corresponding to the encoded screen (frame). Thus, the image data stored in the first and second simulated memories U3a and U3b are used as the reference image data Va and Vb in the process of encoding the decoded data corresponding to the unprocessed screen.
[0136]
In the quantization step deriving unit U74, the quantization steps Qa and Qb from the first and second simulated encoders U2a and U2b, the number of simulated encoded bits Ra and Rb, and the simulated encoding error Da, Based on Db, a process of deriving an optimal quantization step Qd corresponding to each encoding unit is performed so that the number of encoded bits corresponding to the target screen being processed does not exceed the frame target bit number Rd. .
[0137]
This optimum quantization step Qd is supplied to the main encoder U2d, and the main encoder U2d re-encodes the decoded image data Vdec including the quantization process by the quantization step Qd and the local decoding process. Processing is performed with reference to the reference image data Vrefd stored in the main memory U3d. As a result, the re-encoded stream Vout is output from the main encoder U2d, and the locally decoded image data Vstrd is output.
[0138]
At this time, the locally decoded image data Vstrd is stored in the main memory U3d as image data corresponding to the encoded screen (frame). The image data stored in the main memory U3d in this way is used as the reference screen data Vrefd in the re-encoding process of the image data corresponding to the unprocessed screen, and the image data corresponding to the unprocessed screen is stored. The reference screen data Vrefa and Vrefb are also used in the first and second simulation encoding processes.
[0139]
Since the main memory U3d stores locally decoded image data corresponding to the re-encoded stream Vout that is actually output, the first and second simulated encoders U2a and U2b Of the image data of each encoded screen stored in the main memory U3d, it corresponds to the same screen as the image data of the encoded screen stored in the first and second simulated memories U3a and U3b. For the image data, each code stored in the main memory U3d instead of the image data (reference image data) Va and Vb of the encoded screen stored in the first and second simulated memories U3a and U3b. The image data of the converted screen is used as reference image data Vrefa and Vref.
[0140]
The re-encoded stream Vout is supplied to the frame target bit number calculator U6. The calculator U6 performs processing based on the bit rate of the re-encoded stream Vout and the target bit rate Rate supplied from the outside. The frame target bit number Rd corresponding to the processing target screen following the completed screen is calculated and output to the quantization step derivation unit U74.
[0141]
Hereinafter, a specific operation of the quantization step derivation unit U74 will be described.
First, in the bit number subtracter U8b, a subtraction process for subtracting the second simulated encoded bit number Rb from the first simulated encoded bit number Ra is performed, and a difference (simulated code) between these simulated encoded bit numbers is performed. Bit rate variation amount) ΔRab is calculated. The error subtracter U9b performs a subtraction process for subtracting the simulated coding error Da from the first simulated coder U2a from the simulated coding error Db from the second simulated coder U2b. Then, a difference (simulated coding error fluctuation amount) ΔDab between these simulated coding errors is calculated. Further, the divider U10b performs arithmetic processing for dividing the simulated coding error fluctuation amount ΔDab by the simulated coding bit number fluctuation amount ΔRab to derive the recoding error increase rate λ1.
[0142]
Then, the minimum error selector U20 performs a process of comparing the re-encoding error increase rate λ1 between the respective encoding units, and the number of frame bits (the number of bits in the re-encoded stream for one frame). In order not to exceed the frame target bit number Rd, one of the quantization steps Qa and Qb from the first and second simulated encoders U2a and U2b is determined for each encoding unit according to the comparison processing result. A control signal Qse1 for selection is output to the selection switch U14.
In the selection switch U14, one of the quantization steps Qa and Qb is selected for each encoding unit based on the control signal Qse1, and the selected quantization step is output as the optimum quantization step Qd.
[0143]
Next, a specific operation of the minimum error selector U20 will be described.
FIG. 14 is a diagram for explaining a process of deriving an optimal quantization step for each coding unit by the minimum error selector U20. FIG. 14A shows the flow of the quantization step derivation process, and FIG. 14B shows the arrangement of coding units in one screen (one frame). In FIG. 14 (c), the optimum quantization step Qd corresponding to each coding unit in one frame is set to one of the quantization steps Qa and Qb in the first and second simulation coding processes. The state is shown schematically.
[0144]
Here, the encoding unit is a display area (macroblock) composed of 16 × 16 pixels in one screen (frame), and the number of macroblocks in one frame is n. Further, the variable indicating the quantization step corresponding to the i (i = 1, 2,..., N) -th macroblock B [i] in one frame is Q [i], and the i-th macroblock B [i]. Ra [i] and Rb [i] are the numbers of simulated coded bits obtained by performing simulated coding processing including quantization processing by the quantization steps Qa and Qb on the decoded image data corresponding to . In the following description of FIG. 4, a macro block is simply referred to as a block.
[0145]
In the process of determining the optimal quantization step of each block in the target screen (frame to be processed) by the minimum error selector U20, first, the decoded image data of each block B [i] is determined. Thus, the first and second simulated encoded bit numbers Ra [i] and Rb [i] when the first and second simulated encoding processes including the quantization process by the quantization steps Qa and Qb are performed are obtained. Further, the sum R (= ΣRa [i]) of the first simulated encoded bit number Ra [i] of all the blocks in the processed frame is calculated (step S1).
[0146]
Next, for all blocks in the frame to be processed, the variable Q [i] indicating the corresponding quantization step is initialized by the quantization step Qa (step S2). That is, at this time, all the quantization steps Q [i] corresponding to the respective blocks B [i] in the frame to be processed once satisfy Q [i] = Qa. As a result, the sum R of the simulated coding bit numbers Ra [i] of all blocks in the processed frame is R = ΣRa [i].
Thereafter, a process of searching for a block B [k] in which the quantization step Q [i] is Qa and the recoding error increase rate λ1 (= (Db−Da) / (Ra−Rb)) is minimized. Is performed (step S3).
[0147]
Subsequently, the quantization step Q [k] of the block B [k] found by the search processing is changed from the quantization step Qa to a larger quantization step Qb, and the simulated codes of all blocks in the processed frame The sum R of the number of bits is updated to R + Rb [k] −Ra [k] (step S4).
[0148]
Then, it is determined whether or not the sum R of the simulated encoded bit numbers of all blocks in the processed frame is larger than the frame target bit number Rd (step S5). As a result of this determination, if the sum R of the number of simulated coding bits is larger than the frame target bit number Rd, the processing of step S3 to step S5 is repeated again. On the other hand, if the result of determination in step S5 is that the sum R of the simulated encoded bit numbers is equal to or less than the frame target bit number Rd, the value of the quantization step Q [i] of each block in the processed frame at this time (Qa or Qb) (see FIG. 14C) is output as the optimum quantization step Qd corresponding to each block (step S6).
[0149]
As described above, in the re-encoding system 40 according to the fourth embodiment, the quantization steps Qa and Qb are performed in advance on the decoded image data (decoded stream) Vdec corresponding to the processing frame obtained by decoding the input stream. Are provided with first and second simulated encoders U2a and U2b that perform first and second simulated encoding processes including a quantization process for each encoding unit, and each code is obtained from the result of each simulated encoding process. A re-encoding error increase rate λ1 corresponding to the encoding unit is obtained, and the re-encoding error in the processing frame is set so that the total number of encoding bits of all the encoding units in the processing frame does not exceed the target frame bit number Rd. The larger Qb of the two quantization steps is assigned in order from the coding unit with the smallest increase rate λ1, and the smaller Qa is assigned to the remaining coding units in the frame to be processed. Therefore, the re-encoding error increase rate corresponding to each encoding unit in the frame to be processed approaches a constant value. Thereby, even in the re-encoding process in which the encoding error included in the input stream Vin is not known, the re-encoding error can be reduced, and the deterioration of the image quality of the image reproduced from the re-encoded stream Vout can be suppressed to a small level. .
[0150]
In the fourth embodiment, the unit of the encoding process is a macro block (an area composed of 16 × 16 pixels in one frame), but the unit of the encoding process is limited to the macro block in MPEG as described above. is not. For example, the unit of the encoding process may be a sub-block composed of 8 × 8 pixels constituting the macroblock, or a slice composed of several macroblocks.
[0151]
In Embodiment 4 described above, as the re-encoding system, the first and second simulated encoders U2a and U2b only perform the re-encoding process on the main encoder U2d. Although a simulation encoding process including a quantization process is shown, the configuration of the re-encoding system is not limited to this.
For example, when the re-encoding system performs inter-picture predictive encoding processing in MPEG, the first and second simulated encoders U2a and U2b are subject to re-encoding processing in the main encoder U2d. A configuration may be employed in which the simulation encoding process is performed not only on the processing target frame to be, but also on other frames using the processing target frame as a reference frame in the re-encoding process.
[0152]
That is, in the re-encoding system having such a configuration, specifically, the main encoder U2d performs re-encoding processing for the P frame F (3) for which the display time T3 shown in FIG. 24 is set. In this case, in the first and second simulated encoders U2a and U2b, not only the P frame F (3) but also the B frame F (2), in which the display times T2 and T4 are set, Simulated encoding processing is performed on P frame F (5) in which T (4) and display time T5 are set. Also, for each coding unit in each of the frames F (2) to F (5), the corresponding simulated coding increase errors Da and Db and simulated coding bit numbers Ra and Rb are calculated, and the recoding error increases. A rate λ1 is determined. Further, each coding unit in the frame F (3) is optimal based on the recoding error increase rate λ1 corresponding to every coding unit in each frame F (2) to F (5). One of the quantization steps Qa and Qb is set as the quantization step.
[0153]
In this case, the optimum quantization step corresponding to each coding unit in the frame F (3) has the smallest coding error corresponding to the frames F (3), F (2), F (4), F (5). Is set to be
Here, the P frame F (3) is a frame in which the image data is referred to in the inter-frame encoding process for the B frames F (2), T (4), and the P frame F (5). Needless to say.
[0154]
(Embodiment 5)
FIG. 15 is a block diagram for explaining a re-encoding system according to Embodiment 5 of the present invention.
The re-encoding system 50 according to the fifth embodiment includes an image from the decoder U1 in addition to the first and second simulated encoders U2a and U2b in the re-encoding system 40 according to the fourth embodiment. A third simulated encoding including a quantization process and a local decoding process by a quantization step Qc larger than the quantization step Qb with reference to the image data of the reference screen with respect to the decoded data (decoded stream) Vdec A third simulated encoder U2c that performs processing for each encoding unit is included. The third simulated encoder U2c outputs local decoded image data Vstrc obtained by the local decoding process included in the third simulated encoding process, and also includes a quantization process included in the simulated encoding process. The quantization step Qc used in FIG. 1, the coding error (simulated coding increase error) Dc generated by the simulated coding process, and the simulated coding bit number Rc generated by the simulated coding process It is configured to output every time.
[0155]
Further, the re-encoding system 50 is output from the third simulated encoder U2c in addition to the first and second simulated memories U3a and U3b in the re-encoding system 40 of the fourth embodiment. A third simulated memory U3c for storing the locally decoded image data Vstrc is provided. The third simulated memory U3c stores the locally decoded image data Vstrc from the third simulated encoder U2c, and the stored image data is used as a simulated code for an unprocessed screen following the screen to be processed. It is configured to output to the third simulated encoder U2c as image data Vc of the reference screen during the conversion process.
[0156]
Further, in the re-encoding system 50, the main memory U3d uses the stored local decoded image data Vstrd as the reference screen image data (reference) in the re-encoding process for the unprocessed screen following the processing target screen. (Image data) Vrefd is output to the main encoder U2d, and image data (reference image data) of the reference screen is displayed during the first, second, and third simulation encoding processes for the unprocessed screen that follows the screen to be processed. ) Vrefa, Vrefb, Vrefc are output to the first, second, and third simulated encoders U2a, U2b, U2c.
[0157]
As described above, since the locally decoded image data corresponding to the re-encoded stream that is actually output is stored in the main memory U3d, the first, second, and third simulated encoders U2a are stored. , U2b, U2c are encoded screens stored in the first, second, and third simulated memories U3a, U3b, U3b among the image data of the encoded screens stored in the main memory U3d. For the image data corresponding to the same screen as the image data of, the image data Va, Vb, Vc of the encoded screen stored in the first, second, and third simulated memories U3a, U3b, U3c are used. Thus, the image data Vrefa, Vrefb, Vrefc of each encoded screen stored in the main memory U3d is referred to.
[0158]
Further, the re-encoding system 50 re-encoded based on the re-encoded stream Vout from the main encoder U2d instead of the frame target bit number calculator U6 in the re-encoding system 40 of the fourth embodiment. The bit rate (current bit rate) of the encoded stream Vout is compared with the target bit rate Rate from the outside, and the re-encoding error increase rate λ corresponding to the processed frame is calculated for each frame according to the comparison result. A rate distortion calculator U5.
[0159]
Here, in the rate distortion calculator U5, based on the re-encoded stream Vout corresponding to each frame, the average bit rate of the frame being processed (frame to be processed) is likely to be larger than the target bit rate. If so, a large value is output as the re-encoding error increase rate λ corresponding to the encoding unit to be encoded, and the average bit rate of the frame being processed (processed frame) Is smaller than the target bit rate, a small value is output as the re-encoding error increase rate λ corresponding to the encoding unit to be encoded. This is because in the re-encoding system 50 of the fifth embodiment, if the re-encoding error increase rate λ is large, the optimum quantization step Qd becomes large and the bit rate of the re-encoded stream Vout decreases, while the re-encoding error increase rate λ decreases. This is because if the coding error increase rate λ is small, the optimum quantization step Qd becomes small and the bit rate of the re-encoded stream Vout increases.
[0160]
Furthermore, this re-encoding system 50 is replaced with the quantization step Qa output from the first simulated encoder U2a in place of the quantization step derivation unit U74 in the re-encoding system 40 of the fourth embodiment. The simulated encoding increase error Da and the simulated encoded bit number Ra, the quantization step Qb, the simulated encoded increase error Db, and the simulated encoded bit number Rb output from the second simulated encoder U2b, 3 based on the quantization step Qc, the simulated coding increase error Dc, the simulated coding bit number Rc output from the simulated encoder U2c, and the recoding error increase rate λ from the rate distortion calculator U5. A quantization step derivation unit U75 that selects and outputs one of the quantization steps Qa, Qb, and Qc as the optimum quantization step Qd corresponding to each coding unit. To have.
Other configurations in the re-encoding system 50 of the fifth embodiment are the same as those of the re-encoding system 40 of the fourth embodiment shown in FIG.
[0161]
FIG. 16 is a block diagram showing a specific configuration of a quantization step derivation unit U75 constituting the re-encoding system 50 of the fifth embodiment.
The quantization step derivation unit U75 receives the first and second simulated encoded bit numbers Ra and Rb from the first and second simulated encoders U2a and U2b, and the difference between these (simulated encoded bits). A first bit number subtracter U8b for calculating (number fluctuation amount) ΔRab, and second and third simulated encoded bit numbers Rb and Rc from the second and third simulated encoders U2b and U2c. And a second bit number subtracter U8c for calculating the difference (simulated coding bit number fluctuation amount) ΔRbc.
[0162]
Further, the quantization step derivation unit U75 receives the simulated encoding increase errors Da and Db from the first and second simulated encoders U2a and U2b, and the difference (simulated encoding error fluctuation amount) Dab. Are received by the first error subtracter U9b that calculates the error and the simulated encoding increase errors Db and Dc from the second and third simulated encoders U2b and U2c, and the difference between these (the simulated encoding error fluctuation amount). And a second error subtracter U9c for calculating Dbc.
[0163]
The quantization step derivation unit U75 divides the simulated coding error fluctuation amount ΔDab by the simulated coding bit number fluctuation amount ΔRab to obtain the first recoding error increase rate λ1 corresponding to each coding unit. The first divider U10b to be derived and the simulated coding error variation ΔDbc are divided by the simulated coding bit number variation ΔRbc to derive the second re-encoding error increase rate λ2 corresponding to each coding unit. And a second divider U10c.
[0164]
Also, the quantization step derivation unit U75 includes the re-encoding error increase rate λ in the current re-encoding process from the rate distortion calculator U5 and the first re-encoding error increase rate from the divider U10b. a first comparator U11b that compares λ1 and outputs a first switch control signal Qseb according to the comparison result, a recoding error increase rate λ in the current recoding process, and the divider A second comparator U11c that compares the second re-encoding error increase rate λ2 from U10c and outputs a second switch control signal Qsec according to the comparison result is provided.
[0165]
The quantization step deriving unit U75 is supplied with the quantization steps Qa, Qb supplied from the simulated encoders U2a, U2b, U2c based on the first and second switch control signals Qseb, Qsec. , Qc, and a selection switch U50 that outputs the selected quantization step as the optimum quantization step Qd.
[0166]
Specifically, when the recoding error increase rate λ is equal to or less than the recoding error increase rate λ1, the quantization step derivation unit U75 uses the switch control signal Qseb to generate the quantization step Qa. Is selected as the optimal quantization step Qd, and the re-encoding error increase rate λ is greater than the re-encoding error increase rate λ 1 and less than or equal to the re-encoding error increase rate λ 2, the switch U50 selects the switch control signal Qseb and When the quantization step Qb is selected as the optimum quantization step Qd by the switch control signal Qsec, and the recoding error increase rate λ is larger than the recoding error increase rate λ2, the switch U50 uses the switch control signal Qsec. The quantization step Qc is selected as the optimum quantization step Qd.
[0167]
Next, the operation will be described.
When the input stream Vin is supplied to the re-encoding system 50, the decoder U1 performs a decoding process on the input stream Vin, which is an encoded stream, in the same manner as in the fourth embodiment. First and second simulation encoding processes are performed on the decoded stream Vdec by the second simulation encoders U2a and U2b.
At this time, in the fifth embodiment, the third simulated encoder U2c performs the same processing as the first and second simulated encoding processes in the first and second simulated encoders U2a and U2b. 3 is performed on the decoded stream Vdec.
[0168]
That is, in the third simulated encoder U2c, the reference image data Vc stored in the third simulated memory U3c or the reference image data Vrefc stored in the main memory U3d is referred to as a processing target. A third simulated encoding process including a quantization process by a quantization step Qc (Qc>Qb> Qa) and a local decoding process is performed on the decoded stream Vdec of the processing screen. The quantization step Qc is set not to be smaller than the quantization step Qin used in the inverse quantization process. As a result, the third simulated encoder U2c outputs the locally decoded image data Vstrc, the quantization step Qc corresponding to each encoding unit, the simulated encoded bit number Rc, and the simulated encoding error. Dc is output.
[0169]
At this time, the locally decoded image data Vstrc is stored in the third simulated memory U3c as image data corresponding to a screen (frame) that has been encoded. Thus, the image data stored in the third simulated memory U3c is used as the reference screen data Vc in the simulated encoding process of the image data corresponding to the unprocessed screen.
[0170]
Then, in the quantization step deriving unit U75, the quantization steps Qa, Qb, Qc from the first, second, and third simulated encoders U2a, U2b, U2c, the number of simulated encoded bits Ra, Rb, Based on Rc and simulated encoding errors Da, Db, and Dc, the re-encoding error increase rate corresponding to each block (encoding unit) becomes an average re-encoding error increase rate corresponding to the screen to be processed ( The optimal quantization step Qd corresponding to each coding unit is derived so as not to exceed the target recoding error increase rate (λ).
[0171]
Then, in the main encoder U2d, as in the fourth embodiment, the re-encoding process including the quantization process by the optimum quantization step Qd and the local decoding process is performed on the decoded image data Vdec in the main memory. The reference image data Vrefd stored in U3d is referred to. As a result, the re-encoded stream Vout is output from the main encoder U2d, and the locally decoded image data Vstrd is output.
[0172]
Further, in the rate distortion calculator U5, based on the re-encoded stream Vout corresponding to each frame, if the average bit rate of the frame being encoded is likely to be larger than the target bit rate of the frame, If a large value is output as the recoding error increase rate λ and the average bit rate of the frame being encoded is likely to be smaller than the target bit rate of the frame, the recoding error increase rate λ is small. The value is output.
[0173]
Hereinafter, a specific operation of the quantization step derivation unit U75 will be described.
First, in the fifth embodiment, a subtraction process for calculating the simulated encoded bit number fluctuation amount ΔRab in the first bit number subtractor U8b, and a simulated encoding error fluctuation amount ΔDab in the first error subtractor U9b are calculated. Subtraction processing and arithmetic processing for deriving the re-encoding error increase rate λ1 in the first divider U10b are performed, and subtraction processing for calculating the simulated encoded bit number variation ΔRbc in the second bit number subtractor U8c Then, a subtraction process for calculating the simulated coding error fluctuation amount ΔDbc in the second error subtractor U9c and a calculation process for deriving the recoding error increase rate λ2 in the second divider U10c are performed.
[0174]
Here, the processing in the first bit number subtracter U8b, the first error subtractor U9b, and the first divider U10b is exactly the same as that in the fourth embodiment, and the second bit number subtracter U8c. The processes in the second error subtracter U9c and the second divider U10c are the same as the processes in the subtractor U8b, subtractor U9b and divider U10b.
[0175]
That is, in the second bit number subtracter U8c, a subtraction process for subtracting the third simulated encoded bit number Rc from the second simulated encoded bit number Rb is performed, and these differences (simulated encoded bits) are performed. (Number fluctuation amount) ΔRbc is calculated. In the second error subtracter U9c, the subtraction for subtracting the simulated coding increase error Db from the second simulated encoder U2b from the simulated coding increase error Dc from the third simulated encoder U2c. Processing is performed to calculate the difference (simulated coding error fluctuation amount) ΔDbc. Further, in the second divider U10c, arithmetic processing for dividing the simulated coding error fluctuation amount ΔDbc by the simulated coding bit number fluctuation amount ΔRbc is performed, and the second recoding error increase rate λ2 is derived. The
[0176]
Also, the first re-encoding error increase rate λ1 from the divider U10b is compared with the re-encoding error increase rate λ in the current re-encoding process by the first comparator U11b, and the comparison result The first switch control signal Qseb corresponding to is output. The second re-encoding error increase rate λ2 from the divider U10c is compared with the re-encoding error increase rate λ in the current re-encoding process by the second comparator U11c, according to the comparison result. The second switch control signal Qsec is output.
[0177]
In the selection switch U50, based on the first and second switch control signals Qseb and Qsec, among the quantization steps Qa, Qb and Qc supplied from the simulation encoders U2a, U2b and U2c. Are selected, and the selected quantization step is output as the optimum quantization step Qd.
[0178]
Specifically, when the recoding error increase rate λ is equal to or less than the recoding error increase rate λ1, the switch U50 selects the quantization step Qa as the optimum quantization step Qd by the switch control signal Qseb. The When the re-encoding error increase rate λ is larger than the re-encoding error increase rate λ 1 and less than or equal to the re-encoding error increase rate λ 2, the switch U 50 performs quantization using the switch control signal Qseb and the switch control signal Qsec. Step Qb is selected as the optimal quantization step Qd. Further, when the recoding error increase rate λ is greater than the recoding error increase rate λ2, the switch U50 selects the quantization step Qc as the optimum quantization step Qd by the switch control signal Qsec.
[0179]
As described above, in the fifth embodiment, the bit rate (current bit rate) of the re-encoded stream Vout is compared with the external target bit rate Rate based on the re-encoded stream Vout from the main encoder U2d. And a rate distortion calculator U5 for calculating an average re-encoding error increase rate λ, which is an index of image quality corresponding to the frame to be processed, according to the comparison result, and includes quantization steps Qa, Qb. The first and second reproductions corresponding to the encoding units, obtained from the encoding results in the first, second and third simulated encoders U2a, U2b and U2b having different Qc (Qa <Qb <Qc). When the coding error increase rate λ1, λ2 (λ1 <λ2) is smaller than the average recoding error increase rate λ of the one frame, the optimum quantization step Qd corresponding to the block is quantized by the quantization steps Qb, Qc. Therefore, the bit rate can be reduced while suppressing the deterioration of the image quality.
[0180]
In the fifth embodiment, three simulated encoders are provided, and the first and second recoding error increase rates λ1 and λ2 are set to the average recoding error increase rate λ1 of the one frame. Compared to the above, the determination of the optimum quantization step Qd corresponding to each block is shown. However, the number of simulated encoders in the re-encoding system is not limited to three, and the re-encoding in the fourth embodiment is not limited. There may be two as in the encoding system 40, or four or more.
[0181]
For example, in a re-encoding system having first and second simulated encoders as simulated encoders, the quantization step derivation unit U75 has first and second quantization steps Qa and Qb (Qa <Qb) different from each other. The first re-encoding error increase rate λ1 corresponding to the encoding unit obtained from the encoding results of the second simulated encoders U2a and U2b is the average re-encoding error increase rate of the one frame. When smaller than λ, the optimum quantization step Qd corresponding to the block is selected as the larger one of the quantization steps Qa and Qb, and the first re-encoding error increase rate λ1 is the average of the one frame. When it is not smaller than the re-encoding error increase rate λ, the smaller one of the quantization steps Qa and Qb is selected.
[0182]
(Embodiment 6)
FIG. 17 is a block diagram for explaining a re-encoding system according to Embodiment 6 of the present invention, and shows a configuration of a quantization step derivation unit in the re-encoding system of Embodiment 6.
In the re-encoding system of the sixth embodiment, instead of the quantization step derivation unit U75 of the re-encoding system 50 of the above-described fifth embodiment, the quantum obtained as a result of the simulation encoding process in each simulation encoder Based on the encoding steps Qb and Qc, the simulated encoding bit numbers Ra, Rb and Rc, and the simulated encoding increase errors Da, Db and Dc, a relational expression between the recoding error increase rate λ and the quantization step Q is obtained. A quantization step derivation unit U76 for obtaining an optimum quantization step Qd corresponding to each coding unit based on this relational expression and the target recoding error increase rate λ from the rate distortion calculator U5 It is. The other configurations of the re-encoding system according to the sixth embodiment are the same as those of the re-encoding system according to the fifth embodiment.
[0183]
Hereinafter, the specific configuration of the quantization step derivation unit U76 constituting the re-encoding system of the sixth embodiment will be described with reference to FIG.
The quantization step derivation unit U76 of the sixth embodiment replaces the first and second comparators U11b and U11c and the switch U50 of the quantization step derivation unit U75 of the fifth embodiment, and increases the target recoding error. An error RD deriving unit U12 for deriving an error RD function f indicating the relationship between the rate λ and the bit rate R, and using this error RD function f, the quantization step Q and the number of re-encoded bits (decoding stream Vdec) A quantization step calculator U31 for calculating an optimum quantization step corresponding to the re-encoding error increase rate λ for each encoding unit from the relationship with the number of bits (R) corresponding to the encoding unit obtained by the encoding process; It has. Here, the bit rate is equivalent to the number of bits generated corresponding to the coding unit.
[0184]
Hereinafter, the error RD derivation unit U12 and the quantization step calculator U31 will be specifically described.
In general, a function (rate error function) expressed by the following equation 6 is established between the number of coding bits R corresponding to each block (coding unit) and the coding error D corresponding to each block. .
D = g (R) (Formula 6)
[0185]
Therefore, in the re-encoding process, the encoding error D included in the re-encoded stream is expressed by the following Expression 7.
ΔD + Din = g (R) (Formula 7)
Here, ΔD is a re-encoding increase error (encoding error that increases due to the re-encoding process), and Din is an encoding error of the input stream Vin.
[0186]
Therefore, the re-encoding error increase rate λ is expressed by the following Equation 8.
λ = ∂D / ∂R = ∂ΔD / ∂R = ∂g (R) / ∂R (Formula 8)
Here, it is known that the function g (R) can be approximated as shown in Equation 9 below.
g (R) = A ・ R ^B (Formula 9)
Here, A and B are constants.
[0187]
Therefore, the recoding error increase rate λ is expressed by the following expression 10 from the above expressions 8 and 9.
λ = A ・ R ^B-1 (Formula 10)
[0188]
Here, the recoding error increase rate λ1 is the recoding error increase rate λ when R = Rb, and the recoding error increase rate λ2 is the recoding error increase rate when R = Rc. Assuming that λ, the constants A and B can be obtained from Equation 10 above. As a result, an error RD function f expressed by the following equation 11 is derived.
R = f (λ) (Formula 11)
The error RD derivation unit U12 includes the bit rate Rb, Rc of the re-encoded stream from the second and third simulated encoders U2b, U2c, and the re-encoding error increase rate λ1, from the dividers U10b, U10c. Based on λ2, a calculation process for deriving the function f expressed by the above equation 11 is performed.
[0189]
On the other hand, between the quantization step Q and the bit rate R, the relationship shown by the following Expression 12 is established.
R = α ・ Q ^β (Formula 12)
[0190]
Here, α and β are constants, and α and β can be obtained by substituting the bit rates Rb and Rc and the quantization steps Qb and Qc into the above equation 12. As a result, a function h represented by the following expression 13 is derived.
R = h (Q) (Formula 13)
[0191]
Accordingly, a function s indicating the relationship of the quantization step Q corresponding to the re-encoding error increase rate λ is obtained as shown in the following expression 14 from the above expressions 11 and 13.
Q = s (λ) (Formula 14)
[0192]
In other words, the quantization step corresponding to the re-encoding error increase rate λ can be derived as the optimum quantization step Qd using this equation (14).
The quantization step calculator U31 includes the simulated encoded bit number Rb from the second simulated encoder U2b, the quantization step Qb in the second simulated encoding process, and the third simulated encoder U2c. Based on the simulated coding bit number Rc and the quantization step Qc in the third simulated coding process, an arithmetic process for deriving the function h represented by the above equation 13 is performed, and the function h and the error RD derivation are performed. The function s is obtained from the function f obtained by the unit U12, and the quantization step corresponding to the target recoding error increase rate λ obtained by the rate distortion calculator U5 is optimized from the function s. The quantization step Qd is obtained.
[0193]
Next, the operation will be described.
The re-encoding system according to the sixth embodiment performs exactly the same operation as the re-encoding system 50 according to the fifth embodiment except for the operation of the quantization step derivation unit U76.
Therefore, the operation of the quantization step derivation unit U76 will be described below.
First, in the sixth embodiment, a subtraction process for calculating the simulated encoded bit number variation ΔRab in the first bit number subtractor U8b, and a simulated encoding error variation ΔDab in the first error subtractor U9b are calculated. Subtraction processing and arithmetic processing for deriving the re-encoding error increase rate λ1 in the first divider U10b are performed, and subtraction processing for calculating the simulated encoded bit number variation ΔRbc in the second bit number subtractor U8c Then, a subtraction process for calculating the simulated coding error fluctuation amount ΔDbc in the second error subtractor U9c and a calculation process for deriving the recoding error increase rate λ2 in the second divider U10c are performed.
[0194]
Then, the error RD derivation unit U12 regenerates the simulated encoded bit numbers Rb and Rc obtained by the second and third simulated encoders U2b and U2c and the first and second dividers U10b and U10c. Based on the coding error increase rates λ1 and λ2, the function f (R = f (λ)) expressed by the above equation 11 is derived.
[0195]
In the quantization step calculator U31, the simulated coding bit number Rb in the second simulated coding process, the quantization step Qb in the second simulated coding process, and the simulated code in the third simulated coding process Based on the number of quantization bits Rc and the quantization step Qc in the third simulation encoding process, a calculation process for deriving the function h (R = h (Q)) expressed by the above equation 13 is performed. Further, from this function h and the function f obtained by the error RD deriving unit U12, a function s (Q = s (λ)) represented by the equation 14 is obtained. Then, using this function s, the quantization step corresponding to the target recoding error increase rate λ obtained by the rate distortion calculator U5 is obtained as the optimum quantization step Qd.
[0196]
As described above, in the re-encoding system of the sixth embodiment, the quantization step derivation unit U76 causes the function f () indicating the relationship between the re-encoding error increase rate λ and the bit rate based on the result of the simulation encoding process. R = f (λ)), an error RD derivation unit U12, and a function s indicating the relationship between the recoding error increase rate λ and the quantization step based on the function f and the result of the simulation encoding process. (Q = s (λ)) is obtained, and using this function s, each quantization step corresponding to the target recoding error increase rate λ obtained by the rate distortion calculator U5 is set as an optimum quantization step Qd. Since the quantization step calculator U31 derived for each coding unit is included, the optimum quantization step Qd corresponding to each coding unit can be set finely.
[0197]
In the sixth embodiment, the difference between simulated coding increase errors Db and Da, the difference between simulated coding bit numbers Ra and Rb, the difference between simulated coding increase errors Db and Dc, and the simulated coding bit numbers Rb and Rc. Although the error RD function f is derived based on the difference between the above, the difference between the simulated coding increase errors Dc and Da may be used as the difference between the simulated coding increase errors and the coding unit (block). The difference between the recoded bit numbers Ra and Rc may be used as the difference in the number of simulated coded bits per hit.
[0198]
(Embodiment 7)
FIG. 18 is a block diagram for explaining a re-encoding system according to the seventh embodiment of the present invention, and shows a configuration of a quantization step derivation unit in the re-encoding system according to the seventh embodiment.
In this re-encoding system of the seventh embodiment, instead of the quantization step derivation unit U76 of the re-encoding system of the sixth embodiment, a quantization step is performed according to the magnitude of the re-encoding error increase rate λ1. One of the quantization step Qf output from the calculator U31 and the minimum quantization step Qa among the quantization steps Qa, Qb, and Qc is selected, and the selected quantization step is selected as the optimum quantization step. A quantization step derivation unit U77 that outputs Qd is provided.
[0199]
Hereinafter, the specific configuration of the quantization step derivation unit U77 constituting the re-encoding system of the seventh embodiment will be described with reference to FIG.
In addition to the configuration of the quantization step derivation unit U76 of the sixth embodiment, the quantization step derivation unit U77 includes the first re-encoding error increase rate λ1 from the first divider U10b and the rate distortion calculation. A comparator U11 that compares the target re-encoding error increase rate λ from the comparator and outputs a switch control signal Qse, and a quantization step output from the quantization step calculator U31 in response to the switch control signal Qse A selection switch U70 for selecting one of Qf and the minimum quantization step Qa, and outputting the selected quantization step as an optimum quantization step Qd.
[0200]
Hereinafter, a specific configuration of the comparator U11 will be briefly described.
In general, in a re-encoding system, if the difference between the quantization step Qin in the encoding process performed on the input stream Vin and the quantization step Qd in the re-encoding process is large, When the coding error increase rate is large, a phenomenon appears in which the recoding error increase rate λ monotonously increases as the quantization step Qd increases. On the other hand, when the difference between the quantization step Qin in the encoding process for the input stream Vin and the quantization step Qd in the re-encoding process is small, that is, when the re-encoding error increase rate is small, Even if the quantization step Qd increases, the re-encoding error increase rate λ does not necessarily increase, and may decrease depending on circumstances. This point is as described in the second embodiment with reference to FIG. 7, and is described in detail in the literature (Research on requantization error in IE99-32 MPEG2 re-encoding by IEICE Technical Committee). Are listed.
[0201]
That is, in FIG. 7, the quantization error in the re-encoded data indicates the quantization step value QPi in the first quantization process (quantization process in the encoding process) and the second value when the bit rate is high. When the difference from the quantization step value QPr in the quantization process (quantization process in the re-encoding process) is small, the quantization step value QPr in the second quantization process is 2 QP (QPi = QP). As described above, it is shown that when the bit rate of the re-encoded data is low, there is almost no difference between the quantization error in the direct encoding process and the quantization error in the re-encoding process. Here, the increase / decrease in the quantization error in the re-encoded data corresponds to the increase / decrease in the re-encoding error increase rate.
[0202]
Therefore, the comparator U11 determines that the re-encoding error increase rate λ1 corresponding to the encoding unit (processed block) obtained by the simulation encoding process is smaller than the target re-encoding error increase rate λ for the processed frame. The selection switch U70 selects the minimum quantization step Qa among the quantization steps Qa, Qb, Qc (Qa <Qb <Qc) in the first, second, and third simulation encoding processes, When the re-encoding error increase rate λ1 is equal to or higher than the re-encoding error increase rate λ, the selection switch U70 is set so that the selection switch U70 selects the quantization step Qf from the quantization step calculator U31. It is the structure to control.
In other words, the seventh embodiment corresponds to a configuration obtained by combining the re-encoding system of the sixth embodiment and the re-encoding system of the second embodiment. Specifically, the comparator U11 and the selection switch U70 in the quantization step derivation unit U77 of the seventh embodiment correspond to the quantization step derivation unit 252 in the quantization device 152 of the second embodiment, and The portion other than the comparator U11 and the selection switch U70 in the quantization step derivation unit U77 corresponds to the quantization step candidate derivation unit 250 in the quantization device 152 of the second embodiment.
Then, the quantization step derivation unit U77 of the seventh embodiment compares the re-encoding error increase rate λ1 obtained by the simulation encoding process with the target re-encoding error increase rate λ for the frame to be processed, and λ1 <λ At this time, the minimum quantization step Qa in each simulation encoding process is selected, and when λ1 ≧ λ, the quantization step Qf from the quantization step calculator U31 is selected as the quantization step in the re-encoding process. I am doing so. In this second embodiment, the quantization step derivation process compares the quantization step candidate Qsb with the threshold value Qth (= n × Qs1) and the constant multiple value Qmu (= m × Qs1> Qth). When Qsb <Qmu, the first quantization step Qs1 or the constant multiple value Qmu is selected as the quantization step, and when Qmu ≦ Qsb, the processing is equivalent to selecting the quantization step candidate Qsb as the quantization step. is there.
[0203]
Next, the operation will be described.
The re-encoding system of the seventh embodiment operates in exactly the same manner as the re-encoding system 50 of the fifth embodiment except for the operation of the quantization step derivation unit U77.
Therefore, the operation of the quantization step derivation unit U77 will be described below.
In the seventh embodiment, the subtracters U8b and U8c, the subtracters U9b and U9c, the dividers U10b and U10c, the error RD calculator U12, and the quantization step calculator U31 are exactly the same as those in the sixth embodiment. Processing is performed. Thereby, the dividers U10b and U10c output the first and second re-encoding error increase rates λ1 and λ2 corresponding to the encoding unit (processed block). The error RD function f is derived from the error RD calculator U12, and the target re-encoding error increase corresponding to the processing frame is increased from the quantization step calculator U31 as the quantization step corresponding to the processing target block. A value Qf corresponding to the rate λ is output.
[0204]
The comparator U11 compares the first recoding error increase rate λ1 corresponding to the processing target block with the target recoding error increase rate λ corresponding to the processing target frame, and compares the result. In response to this, the switch control signal Qse is output to the selection switch U70. In the selection switch U70, one of the quantization step Qf from the quantization step calculator U31 and the quantization step Qa in the first simulation encoding process is selected as the optimum quantization step Qd according to the switch control signal Qse. Is output.
[0205]
Specifically, when the first recoding error increase rate λ1 corresponding to the processing target block is smaller than the target recoding error increase rate λ corresponding to the processing target frame, the switch control signal Qse In the selection switch U70, the quantization step Qa is selected as the optimum quantization step Qd, and when the first recoding error increase rate λ1 is not smaller than the target recoding error increase rate λ, the selection switch U70 The quantization step Qf from the quantization step calculator U31 is selected as the optimum quantization step Qd.
[0206]
As described above, in the re-encoding system of the seventh embodiment, the quantization step derivation unit U77 is added to the configuration of the quantization step derivation unit U76 of the sixth embodiment, and the re-encoding error from the divider U10b. The increase rate λ1 is compared with the target re-encoding error increase rate λ from the rate distortion calculator, and has a comparator U11 that outputs a switch control signal Qse according to the comparison result, and the re-encoding error increase rate λ1 is Only when it is smaller than the target re-encoding error increase rate λ from the rate distortion calculator, instead of the quantization step Qf obtained by the quantization step calculator U31 as a quantization step corresponding to the block to be processed, simulated encoding is performed. Since the minimum quantization step Qa in the processing is selected, the re-encoding error increase rate is not monotonically increasing due to the change in the re-encoding error increasing rate with respect to the increase of the quantization step. When the quantization step calculator U31 has a value within a range in which it is difficult to derive the optimum quantization step Qd that minimizes the re-encoding error, the minimum quantization step Qa in the simulation encoding process is always processed. This is used as the optimum quantization step Qd of the block.
[0207]
Therefore, the target re-encoding error increase rate λ of the frame to be processed is a value within a range where the difference between the quantization step Qin of the input stream Vin and the quantization step Qd in the re-encoding process for the input stream Vin becomes small. In this case, it is possible to prevent the operation from becoming unstable. When the target re-encoding error increase rate λ of the frame to be processed is a value outside the above range, the re-encoding is performed by setting the quantization step Qf derived by the quantization step calculator U31 as the quantization step Qd. Error can be minimized.
[0208]
In Embodiments 6 and 7, the error RD function f shown in Expression 11 is used as a function indicating the relationship between the number R of coded bits per coding unit of the recoded stream and the recoding error increase rate λ. However, the function indicating these relationships is not limited to this.
[0209]
For example, another error RD function having the same tendency and property as the error RD function f shown in the above equation 11 is derived from the simulated coding increase errors Da, Db, Dc and the number of simulated coding bits Ra, Rb, Rc. If possible, this other error RD function may be used as a function indicating the relationship between the number R of encoded bits and the re-encoding error increase rate λ.
[0210]
In Embodiments 5 to 7, the first, second, and third simulated encoders U2a, U2b, and U2c are re-encoding systems that are subject to re-encoding processing in the main encoder U2d. Although the simulation encoding process including the quantization process is performed only on the frame, the configuration of the re-encoding system is not limited to this.
[0211]
For example, as specifically described in the fourth embodiment, when the re-encoding system performs the inter-picture predictive encoding process in MPEG, the first, second, and third simulated encoders are used. In U2a, U2b, and U2c, not only the processing target frame to be re-encoded by the main encoder U2d, but also other frames that use this processed frame as a reference frame in the re-encoding processing. A configuration in which a simulation encoding process is performed on a frame may also be used.
[0212]
Furthermore, by recording a processing program for performing re-encoding processing by the re-encoding system of the first to seventh embodiments by software on a data storage medium such as a floppy disk, each of the above-described embodiments. The form re-encoding process can be easily realized by an independent computer system.
[0213]
FIG. 19 shows a data recording medium (FIGS. 19 (a) and 19 (b)) storing a program for performing the re-encoding process of each of the above embodiments by a computer system, and the computer system (FIG. 19 (c)). FIG.
FIG. 19A shows an external appearance, a cross-sectional structure, and a floppy disk as viewed from the front of the floppy disk, and FIG. 19B shows an example of a physical format of the floppy disk that is a recording medium body. The floppy disk FD is built in the case F, and on the surface of the disk, a plurality of tracks Tr are formed concentrically from the outer periphery toward the inner periphery, and each track is divided into 16 sectors Se in the angular direction. ing. Therefore, in the floppy disk storing the program, the program is recorded in an area allocated on the floppy disk FD.
FIG. 19C shows a configuration for recording and reproducing the program on the floppy disk FD. When recording the program on the floppy disk FD, the computer system Cs writes data as the program on the floppy disk FD via the floppy disk drive. When a system that performs the re-encoding process of each of the above embodiments using a program in a floppy disk is built in a computer system, the program is read from the floppy disk by a floppy disk drive and transferred to the computer system.
[0214]
In the above description, a floppy disk is used as a specific example of the data storage medium. However, even if an optical disk is used, re-encoding processing by software can be performed as in the case of the floppy disk. Further, the data storage medium is not limited to the optical disk and the floppy disk, and any data recording medium can be used as long as it can record a program, such as an IC card and a ROM cassette. Similar to the case of using a floppy disk or the like, re-encoding processing by software can be performed.
[0215]
【The invention's effect】
As above Clearly According to the encoded data conversion method, a decoding process for generating decoded data by decoding encoded data obtained by the encoding process including the first orthogonal transform process and the first quantization process; A re-encoding process for generating re-encoded data by performing a second orthogonal transform process and a second quantization process on the decoded data, and in the re-encoding process, the second quantum Since the quantization process is performed based on the re-encoded data and the quantization step in the first quantization process, the quantization step in the second quantization process is changed to the quantization in the first quantization step. It becomes possible to set according to the step. That is, under the restriction of the target number of bits in the re-encoding process based on the re-encoded data, the quantization step in the second quantization process is changed to the bit rate and the quantization distortion (quantization in the re-encoding process). In consideration of the non-linear relationship with the error), the quantization error can be set as small as possible. As a result, an increase in quantization error in the re-encoding process can be effectively suppressed under the restriction of the bit rate.
[0216]
This departure Clearly According to the above In the encoded data conversion method, in the second quantization process, that is, the quantization process in the re-encoding process, a quantization step candidate is derived based on the re-encoded data, and the quantization step candidate and the first Since the quantization step is derived based on the quantization step in one quantization process, the larger one of the quantization step candidates and the quantization step in the first quantization process is the second quantization process. By the simple process of selecting as the quantization step in FIG. 4, there is an effect that the number of bits generated by the re-encoding process can be made equal to or less than the target number of bits while suppressing an increase in quantization error.
[0217]
This departure Clearly According to the above In the encoded data conversion method, in the process of deriving the quantization step in the second quantization process (quantization process in the re-encoding process), the second step is performed according to the size of the quantization step candidate. As a quantization step in the quantization process, a quantization step having the same value as the quantization step in the first quantization process, a quantization step that is twice or more, or the quantization step candidate is derived. As the quantization step in the second quantization process, it is possible to set a value outside the range from 1 to 2 times the quantization step in the first quantization process. Accordingly, there is an effect that the number of bits generated by the re-encoding process can be made equal to or less than the target number of bits without increasing the number of bits with respect to the encoded data and without causing a significant increase in quantization error. .
[0222]
This departure Clearly According to such a data recording medium, the above Since the computer program for performing the process of converting the first encoded data into the second encoded data by the encoded data conversion method is stored, the re-encoding process effectively suppresses the increase of the quantization error. The effect that it can be performed.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining a re-encoding system 10 according to a first embodiment of the present invention.
FIG. 2 is a block diagram for explaining a quantization device 151 constituting the re-encoding system 10 of the first embodiment.
FIG. 3 is a block diagram for explaining a quantization step deriving unit 251 constituting the quantization apparatus 151 according to the first embodiment.
FIG. 4 is a block diagram for explaining a quantizing device 152 constituting a re-encoding system according to Embodiment 2 of the present invention.
FIG. 5 is a block diagram for explaining a quantization step derivation unit 252 constituting the quantization device 152 of the second embodiment.
FIG. 6 shows a second quantization step Qs2 obtained by the quantization step derivation unit 252 of the second embodiment and an output from the quantization step candidate derivation unit 250 constituting the quantization device 152 of the second embodiment. It is a figure which shows the relationship with the quantization step candidate Qsb performed with a graph.
FIG. 7 is a diagram illustrating a relationship between a bit rate and quantization distortion (quantization error) by re-encoding processing.
FIG. 8 is a block diagram for explaining a re-encoding system 30 according to a third embodiment of the present invention.
FIG. 9 is a block diagram for explaining a quantization device 153 constituting the re-encoding system 30 of the third embodiment.
FIG. 10 is a block diagram for explaining a quantization step deriving device 273 constituting the quantization device 153 of the third embodiment.
FIG. 11 is a block diagram for explaining a re-encoding system 40 according to a fourth embodiment of the present invention.
12 shows a simulated coding error caused by a simulated coding process of decoded image data Vdec in the re-encoding system 40 of the fourth embodiment, and the number of bits per coding unit generated by the simulated coding process ( It is a figure which shows the relationship with a simulation encoding bit number) with a graph.
FIG. 13 is a block diagram showing a specific configuration of a quantization step derivation unit U74 that constitutes the re-encoding system 40 of the fourth embodiment.
FIG. 14 is a diagram for explaining a process for deriving an optimal quantization step for each coding unit in the fourth embodiment, and shows a flow of the process (FIG. (A)) of coding units in one frame; The arrangement (FIG. (B)) and the state (FIG. (C)) in which the optimum quantization step Qd is set for each coding unit are shown.
FIG. 15 is a block diagram for explaining a re-encoding system 50 according to a fifth embodiment of the present invention.
FIG. 16 is a block diagram showing a specific configuration of a quantization step derivation unit U75 constituting the re-encoding system 50 of the fifth embodiment.
FIG. 17 is a block diagram for explaining a re-encoding system according to a sixth embodiment of the present invention, and shows a configuration of a quantization step derivation unit U76 in this re-encoding system.
FIG. 18 is a block diagram for explaining a re-encoding system according to a seventh embodiment of the present invention, and shows a configuration of a quantization step derivation unit U77 in this re-encoding system.
FIG. 19 is a data recording medium (FIGS. (A) and (b)) storing a program for performing re-encoding processing by the re-encoding system of the first to seventh embodiments by a computer system, and the computer. It is a figure for demonstrating a system (FIG. (C)).
FIG. 20 is a block diagram for explaining a conventional re-encoding system 100a.
FIG. 21 is a block diagram for explaining a quantization apparatus 107 constituting a conventional re-encoding system 100a.
FIG. 22 is a graph showing the relationship between the bit rate of the encoded stream and the encoding error included in the encoded stream.
FIG. 23 is a schematic diagram for explaining inter-picture predictive encoding processing in MPEG.
[Explanation of symbols]
10, 30, 40, 50 Re-encoding system
100 VLD device
101a, 108 inverse quantizer
102,109 IDCT device
103,110 adder
104,111 frame memory
105 Subtractor
106 DCT device
112 VLC unit
113 Rate control device
151, 152, 153 Quantizer
201 Quantizer
250 Quantization step candidate derivation
251 252 273 U74 U75 U76 U77 quantization step derivation
260, 263, 266 comparator
261,264,267 switch
262 Threshold Derivator
265 constant multiplier
270,272a In-screen average quantization step derivation
271 and 272b Average quantization step derivation between screens
CP1, CP2, CP3 comparative output
Da, Db, Dc 1st, 2nd, 3rd simulated coding increase error
Da1 decoding unit
Ea1 encoding unit
Eg1 encoded data
Eg2 re-encoded data
f Error RD function
Qa, Qb, Qc, Qf, Qin quantization step
Qd Optimal quantization step
Qs1 first quantization step
Qs2 second quantization step
Qsb Quantization step candidate
Qse selective quantization step
Qseb, Qsec, Qse1 Switch control signal
Qth threshold
Qmu constant multiple
Ra, Rb, Rc Number of first, second and third simulated encoded bits
Rate Target bit rate
Rd Frame target bit number
U1 decoder
U2a, U2b, U2c first, second and third simulated encoders
U2d main encoder
U3a, U3b, U3c 1st, 2nd, 3rd simulated memory
U3d main memory
U5 rate distortion calculator
U6 frame bit number calculator
U8b, U8c first and second bit number subtracters
U9b, U9c first and second error subtracters
U10b, U10c first and second dividers
U11b, U11c first and second comparators
U12 error RD calculator
U14, U50, U70 selection switch
U20 Minimum error selector
U31 quantization step calculator
Vrefa, Vrefb, Vrefc, Vrefd, Va, Vb, Vc Reference image data
Vstra, Vstrb, Vstrc, Vstrd Locally decoded image data
Vdec decoded image data (decoded stream)
Vin input stream
Vout re-encoded stream
λ Target recoding error increase rate
λ1, λ2 First and second re-encoding error increase rate
ΔDab, ΔDac, ΔDbc Simulated coding error variation
ΔRab, ΔRac, ΔRbc Simulated coding bit number variation
Cs computer system
F floppy disk case
FD floppy disk
FDD floppy disk drive
Se sector
Tr track

Claims (2)

Decoding that decodes first encoded data obtained by performing encoding processing including first orthogonal transformation processing and first quantization processing on image data for each encoding unit to generate decoded data An encoded data conversion method comprising: an encoding process; and a re-encoding process for encoding the decoded data for each encoding unit to generate second encoded data,
The decryption process
Including a dequantization process for dequantizing a quantized coefficient obtained from the first encoded data by the first quantization step used in the first quantization process,
The re-encoding process is
A second orthogonal transform process for orthogonally transforming the decoded data to generate frequency domain data;
A second quantization step for deriving a second quantization step based on the second encoded data and the first quantization step, and for quantizing the frequency domain data by the second quantization step look at including the processing,
The second quantization process is as follows.
Candidate derivation processing for deriving quantization step candidates based on the second encoded data;
A quantization step deriving process for deriving the second quantization step based on the quantization step candidate and the first quantization step;
In the quantization step derivation process,
When the quantization step candidate has a value that is greater than or equal to the value of the first quantization step and less than twice the value of the first quantization step, the second quantization step As a result, a quantization step having the same value as the value of the first quantization step or a quantization step having a value more than twice the value of the first quantization step is derived.
When the quantization step candidate has a value outside the range, the quantization step candidate is derived as the second quantization step .
An encoded data conversion method characterized by the above.   A data recording medium storing a data conversion program for performing the encoded data conversion method according to claim 1 by a computer.

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