JP4421659B2 - Electronic device having flash memory - Google Patents

Description

  The present invention relates to recovery and processing of a system in the event of a system failure or system error due to a power failure in an electronic device having a flash memory including a nonvolatile memory such as a memory card or a portable electronic device and a control unit that controls the flash memory. The present invention relates to an electronic device having a flash memory that can appropriately and easily perform the above.

  A portable electronic device such as a memory card with a built-in flash memory or an electronic notebook with a built-in flash memory records data in the built-in flash memory and reads the recorded data as appropriate. The flash memory is usually composed of a nonvolatile memory composed of floating gate type MOS transistors, and has a program for recording data, an erase for erasing data, and a read operation for reading data. In general, program mode and erase mode operations require a longer time than read mode, but flash memory is non-volatile that retains recorded data even while the power is turned off. The memory is optimal for electronic devices used in situations where the use of power sources such as memory cards and portable electronic devices is restricted.

  FIG. 13 is a configuration diagram of a relatively small electronic device such as a conventional memory card. The electronic device 100 includes a main memory 2 composed of a flash memory and a control circuit 1 that controls the main memory 2, which are connected by a bus 4. The electronic device 100 is mounted on a personal computer or the like, and user data or the like is recorded in the main memory 2. In response to a request from the personal computer, the control circuit 1 supplies a command of several cycles to the main memory via the bus 4, and in response to this, the main memory 2 performs erase, program operation, and the like.

  FIG. 14 is a configuration diagram of a relatively large-scale electronic device such as a conventional portable electronic device. The electronic device 100 includes a temporary memory 3 that can write data at a relatively high speed, such as a DRAM and an SRAM, in addition to a control circuit 1 and a main memory 2 including a flash memory. The temporary memory 3 is connected to the control circuit 1 via a bus 5 and a temporary memory control line 6. A battery 8 is connected to the temporary memory 3 composed of a volatile memory, and data can be retained when the power is shut off.

  The temporary memory 3 temporarily stores write data when the control circuit 1 writes to the main memory 2, and the write data temporarily recorded in the temporary memory 3 requires a relatively long time for writing. 2 is written over time. Further, attribute information such as vendor information of the electronic device 100 is also recorded in the temporary memory 3.

  The electronic device incorporating the above-described conventional flash memory has no means of knowing the situation at the time of power failure or error after recovery when a power failure or error occurs during program or erase to the flash memory. Therefore, in the case of card memory, it is necessary to provide the card driver and file system on the personal computer side with a function to detect and deal with the situation when the power failure or error occurs. There is a tendency to increase the burden of.

  Furthermore, the card memory or the like is rich in portability, but when an error occurrence factor is included in the card memory, it cannot be detected, and there is a problem that the diversion of the card memory is impaired.

  In the case of having the temporary memory 3 shown in FIG. 14 as well, if the program or erase to the main memory 2 is interrupted due to a power failure or an error, it is difficult to detect the situation after the return. There is a problem that it takes time to return.

  Therefore, even if the program operation or erase operation is interrupted due to the occurrence of a power failure or error, the object of the present invention is to easily detect the information at the time of the interruption at the time of recovery, and for a short time against the occurrence of a power failure or error. It is another object of the present invention to provide an electronic device with a built-in flash memory that can be easily restored.

  Furthermore, an object of the present invention is to provide an electronic device with a built-in flash memory that can retain information when a malfunction occurs in the operation of the flash memory and can easily recover in a short time when the malfunction occurs. Is to provide.

  It is another object of the present invention to provide an electronic device with a built-in flash memory that can be used continuously even when a defective bit occurs in the flash memory during use.

  In order to achieve the above object, the present invention provides an auxiliary nonvolatile memory that records information of a bus connecting a flash memory and a control unit that controls the flash memory at a predetermined timing in an electronic device incorporating the flash memory. Have This auxiliary non-volatile memory is preferably a memory capable of writing at a higher speed than a flash memory, and for example, FeRAM (Ferroelectric RAM) is a practical example. The FeRAM is a memory that utilizes the polarization action of a ferroelectric, and normally operates in the same manner as a DRAM, and retains recorded data even when the power is turned off. In addition, the time required for the writing is faster than that of a nonvolatile memory composed of a floating gate type MOS transistor used in a conventional flash memory.

  In order to achieve the above object, the present invention provides a flash memory composed of a nonvolatile memory and a control connected to the flash memory via a bus and supplying a control command via the bus to control the flash memory. An electronic device having an auxiliary nonvolatile memory having a faster write operation than the flash memory, and the control unit stores the bus information in the auxiliary nonvolatile memory at a predetermined timing. And

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to the embodiment.

  FIG. 1 is a configuration diagram of an electronic apparatus according to a first embodiment of the present invention. As shown in FIG. 1, an electronic device 100 has a main memory 2 composed of a flash memory and a control circuit (CPU) 1 that controls the main memory 2, and these are a bus 4 having address signal lines, data signal lines, and the like. Connected. Furthermore, the electronic device 100 includes an auxiliary nonvolatile memory 10 made of FeRAM, and a bus 12 branched from the bus 4 is connected thereto. The auxiliary nonvolatile memory 10 is controlled by a control signal 14 for FeRAM from the control circuit 1.

  The auxiliary non-volatile memory 10 is a memory that uses the polarization action of a ferroelectric material. For example, a ferroelectric material is used for a gate oxide film of a MOS type cell transistor, and a voltage is applied to the gate oxide film to polarize the auxiliary nonvolatile memory 10. A state is created, and this polarization state is maintained even when the power is cut off, so that it has a function of a nonvolatile memory. Reading is performed by turning on and off the cell transistor in accordance with the polarization state. In addition, the time required for writing to obtain a polarization state is shorter than that of a flash memory using a floating gate type MOS transistor.

  FIG. 2 is an operation timing chart of the electronic device of FIG. FIG. 2 illustrates a chip erase S1 for erasing in units of chips, a sector erase S2 for erasing in units of sectors, a read S3 for reading, and a program S4 for performing programs as FeRAM statuses. In each status, the CPU 1 serving as a control circuit supplies a control command, a target address, and the like to the address bus and data bus of the bus 4. Correspondingly, the main memory 2 composed of the flash memory becomes an operation period in each status.

  For example, in the first half of the operation period of the flash memory 2, a control command is supplied to the bus 4 so that the flash memory 2 recognizes the operation of the status. Accordingly, the control circuit 1 supplies the FeRAM control signal 14 to the auxiliary nonvolatile memory 10, and the auxiliary nonvolatile memory 10 records the information on the bus 4 in response to the control signal 14. The bus information is recorded for each status, and only the bus information with the latest status or the latest plural statuses is recorded in the auxiliary nonvolatile memory 10. Therefore, the auxiliary non-volatile memory 10 does not need a large storage capacity.

  In the example of FIG. 2, in the statuses S1, S2, and S3, the operation is normally completed, but some error or power failure occurs during the program operation of the cycle S4. In that case, at the time of power-on of the electronic device thereafter, the control circuit 1 reads the bus information immediately before the occurrence of the error recorded in the auxiliary nonvolatile memory 10. Then, the control circuit 1 can know the status at the time of error occurrence from the bus information at the time of error occurrence. This status includes any information of chip erase, sector erase, read, and program. In the case of sector erase or program, an address to be erased or programmed is also included. Therefore, since the control circuit 1 can know at which address an error has occurred during erasing or programming when the power is turned on, the control circuit 1 can start the erasing or programming operation when an error occurs immediately after the power is turned on. Can do. In the conventional electronic device, when an error occurs, it is necessary to check the content of data in the main memory after the power is turned on and detect the address of the unprogrammed cell.

  Furthermore, when the error is not a power failure or the like but a program failure due to a cell failure, the address address of the defective cell is recorded in the auxiliary nonvolatile memory 10 as a mask address. By using such a mask address, subsequent programming to a defective cell can be prohibited. This point will be described in detail later.

  Only the latest bus information is recorded in the auxiliary nonvolatile memory 10. Assume that the bus information is updated in the auxiliary nonvolatile memory 10 every cycle. If the main memory is 4M bits and the number of input / output terminals I / O is 16, the address bus is 18 bits, the data bus for input / output terminals is 16 bits, and the number of control pins to the main memory is 40 bits. It is sufficient that the auxiliary nonvolatile memory 10 has a capacity.

  For example, in the case of a memory card, electronic device 100 is connected to a different personal computer. In that case, since the bus information at the time of the previous error occurrence is held in the auxiliary nonvolatile memory 10 in the memory card, even different personal computers can read the information and recognize the situation at the time of the error occurrence. Can improve the reliability of the system.

  FIG. 3 is a detailed view of the electronic apparatus according to the first embodiment. In this example, the main memory 2 composed of flash memory has a capacity of 4 Mbits, the bus 4 includes 18 address buses ADD, 16 data buses DI / O, and several control buses. CTL. The control bus CTL includes, for example, a chip enable / CE, an output enable / OE, a write enable / WE, and the like. These buses are further branched and connected to the auxiliary nonvolatile memory 10.

  4 is an operation timing chart of the electronic device of FIG. FIG. 4 shows an example of chip erase among a plurality of operation statuses. Since chip erase erases important stored data, the control circuit 1 supplies the control command of 6 cycles so that the flash memory 2 recognizes the stored data so that the stored data is not erased due to an error. That is, from the first cycle to the sixth cycle, control commands as shown are supplied to the address bus ADD and the data bus DI / O. The control circuit 1 records the control command in each cycle in the auxiliary nonvolatile memory 10 by the FeRAM control signal 14. That is, control commands for 6 cycles are recorded in the auxiliary nonvolatile memory 10. Thereafter, the entire chip is erased.

  The cycle for supplying the above control command requires, for example, about 100 nsec, while the subsequent erase operation requires, for example, several seconds. Therefore, the time for supplying the command sequence of 6 cycles to the bus 4 is about 600 nsec, but the subsequent erasing operation takes much longer than several seconds. Therefore, as explained in FIG. 2, the control commands supplied to the bus 4 are recorded in the first half of the operation period of each status, and the control commands for 6 cycles immediately before the error occurrence are analyzed at the power-up after the error occurrence. Thus, the control circuit 1 can easily detect the operation state immediately before the error occurs.

  FIG. 5 is a diagram illustrating an example of a control command. In the read operation, in response to the control command for the third cycle and the read address RA for the fourth cycle, the flash memory 2 outputs the read data RD to the data bus DI / O. In the program operation, the flash memory 2 performs the program operation in response to the control command for the third cycle, the program address PA and the program data PD for the fourth cycle. The program operation requires erasing the target address once, then programming, program verification, etc., and requires a longer time than the command sequence. Further, in the chip erase and sector erase operations, a control command of 6 cycles is supplied, and in response to this, the flash memory 2 performs an erase operation. Both erases are distinguished by a control command in the sixth cycle. In the case of sector erase, the sector address SA is supplied in the sixth cycle.

  As is clear from the example of the control command in FIG. 5, by recording the control command output to the bus 4 in the auxiliary nonvolatile memory 10 in the first half of each status, an error occurs during the subsequent program operation or erase operation. In this case, it is possible to read the operation content immediately before the error occurrence and the operation target addresses PA and SA. In the erase operation, since the erase target address is supplied to the bus 4 after the seventh cycle, the erase target address immediately before the occurrence of the error is known by recording the erase target address in the auxiliary nonvolatile memory 10. Can do.

  FIG. 6 is a configuration diagram of an electronic apparatus according to the second embodiment. In this example, a ready busy signal RY / BY and a timing limit excess signal DQ5, which are flag signals included in the bus 4 and supplied from the flash memory 2 to the control circuit 1, are also connected to the auxiliary nonvolatile memory 10. . At the timing of these flag signals, the data on the bus line 13 including the address bus ADD, the data bus DI / O, and the control bus CTL in the bus 4 are recorded in the auxiliary nonvolatile memory 10 as bus information. .

  FIG. 7 is an operation timing chart of FIG. FIG. 7 shows erase, program, program, and examples of programs as statuses S11 to S14. The flag signal described above is output from the flash memory 2 in the erase operation and the program operation. For example, the ready / busy signal RY / BY becomes L level when an erase or program operation is being executed in the flash memory, and becomes H level when these operations are completed. In the program operation, the ready / busy signal RY / BY becomes L level in the fourth cycle of the command sequence shown in FIG. Similarly, in the erase operation, it becomes L level in the sixth cycle of the command shown in FIG. Then, when the operation is finished, it becomes H level. As shown in FIG. Therefore, in response to the ready / busy signal RY / BY, the control circuit 1 causes the auxiliary nonvolatile memory 10 to record the information on the bus 13 by the FeRAM control signal 14. Thereby, the bus information after the erase or program operation is actually started is recorded in the auxiliary nonvolatile memory 10. As a result, when an error occurs, the operation history immediately before the error can be read from the auxiliary nonvolatile memory 10.

  The timing limit excess signal DQ5, which is another flag signal, is output from the flash memory 2 when the program or erase time exceeds a specified limit. Therefore, while the timing limit excess signal DQ5 is at the L level, it means that the specified limit is not exceeded. Therefore, as long as the signal DQ5 maintains the L level during the operation period of each status, Means that the program is operating normally. Further, as shown in the status S14 of FIG. 7, when the signal DQ5 becomes H level during the operation, it means that a program error has occurred. Accordingly, in response to the change of the signal DQ5 from the L level to the H level, the control circuit 1 causes the auxiliary nonvolatile memory 10 to record the bus information by the FeRAM control 14. As a result, address information or the like where a program error has occurred can be recorded in the auxiliary nonvolatile memory 10.

  By using the recorded address at the time of error occurrence, it can be used for reprogram execution from that address, or for prohibiting the program to the error occurrence address thereafter.

  The bus information is recorded in response to the ready / busy signal RY / BY shown in FIG. 7 and the bus information is recorded in response to the timing limit excess signal DQ5. Error information can be recorded in the auxiliary nonvolatile memory 10.

  FIG. 8 is a configuration diagram of an electronic apparatus according to the third embodiment. In this example, in the bus 4 connecting the control circuit 1 and the main memory 2, the history of the ready busy signal RY / BY is recorded in the auxiliary nonvolatile memory 10 in response to the FeRAM control signal 14.

  FIG. 9 is an operation timing chart of FIG. As described above, the ready / busy signal RY / BY becomes L level during the erase operation or program operation, and becomes H level when the operation is completed. Therefore, by recording the state of the ready / busy signal RY / BY in the auxiliary non-volatile memory 10, when an error occurs and the system goes down, it is determined whether the error has occurred during the erase or program operation. I can know. By recording such information, it can be used to determine whether or not to erase or program again when the system is restored.

  As shown in FIG. 9, when the ready / busy signal RY / BY is switched from the H level to the L level, and when the ready busy signal RY / BY is switched from the L level to the H level, the control circuit 1 is ready to the auxiliary nonvolatile memory 10 by the control signal 14. The state of the busy signal RY / BY is recorded. Therefore, at the time of system recovery after an error occurs, the last ready / busy signal RY / BY recorded in the auxiliary nonvolatile memory 10 is checked to determine whether an error has occurred during operation (RY / BY = L). It can be detected whether an error has occurred after the operation is finished (RY / BY = H). In other words, it is possible to detect whether the process has been completed normally or abnormally. In addition, since the auxiliary nonvolatile memory 10 only records one bit of the ready / busy signal RY / BY, the storage capacity can be reduced.

  FIG. 10 is a configuration diagram of an electronic apparatus according to the fourth embodiment. This example has a bus storage area 101 and a mask address area 102 in the auxiliary nonvolatile memory 10. Information on the bus 12 branched from the bus 4 is recorded in the bus storage area 101 at the predetermined timing described above. On the other hand, in the mask address area 102, an address when a program failure or an erase failure occurs is recorded. The bus information in the bus storage area 101 is read out by automatic analysis when the system is restored and used for operations after the system is restored. On the other hand, the address recorded in the mask address area 102 is read by the control circuit 1 after the system is restored, and subsequent access is prohibited.

  FIG. 11 is a configuration diagram of an electronic apparatus according to the fifth embodiment. This example has a bus storage area 101 and a temporary area 104 in the auxiliary nonvolatile memory 10. In the bus storage area 101, bus information is recorded at a predetermined timing as in FIG. The temporary area 104 is used for temporarily recording write data and recording attribute data of the memory card, like the temporary memory 3 described in the conventional example. By using FeRAM that does not require a battery and performs high-speed writing and reading operations, the same functions as those of the conventional temporary memory 3 can be provided.

  FIG. 12 is a block diagram of the electronic apparatus of the sixth embodiment. In this example, an auxiliary nonvolatile memory area 32 made of FeRAM is provided in the chip of the main memory 2 made of the flash memory area 30. Accordingly, the bus information supplied to the flash memory area 30 is supplied to the auxiliary nonvolatile memory 32 via the connection line 34 and recorded at a predetermined timing.

  As described above, according to the present invention, even if an error occurs during operation in a flash memory that requires a long time for a program operation or an erase operation, the bus information immediately before that is recorded in the auxiliary nonvolatile memory. By analyzing the bus information recorded in the auxiliary non-volatile memory after the system is restored, it is possible to easily know the operation status at the time of occurrence of an error and facilitate the work after the restoration.

It is a block diagram of the electronic device of the 1st Example of this invention. FIG. 2 is an operation timing chart of the electronic device of FIG. 1. 1 is a detailed view of an electronic device according to a first embodiment. FIG. 4 is an operation timing chart of the electronic device of FIG. 3. It is a figure which shows the example of a control command. It is a block diagram of the electronic device of a 2nd embodiment. FIG. 7 is an operation timing chart of FIG. 6. It is a block diagram of the electronic device of the example of 3rd Embodiment. FIG. 9 is an operation timing chart of FIG. 8. It is a block diagram of the electronic device of the example of 4th Embodiment. It is a block diagram of the electronic device of a 5th embodiment. It is a block diagram of the electronic device of a 6th embodiment. It is a block diagram of the electronic device of a prior art example. It is a block diagram of the electronic device of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control circuit 2 Flash memory, main memory 4 Bus 10 Auxiliary non-volatile memory, FeRAM
14 FeRAM control signal

Claims (10)

  In a control circuit connected to a flash memory composed of a non-volatile memory via a bus and supplying a control command via the bus to control the flash memory,
  Connected to the auxiliary non-volatile memory having a faster write operation than the flash memory via the bus,
  The bus information is stored in the auxiliary nonvolatile memory when a read operation, a program operation or an erase operation is instructed to the flash memory.
A control circuit characterized by.   The control circuit according to claim 1, wherein the control circuit is connected to the flash memory and the auxiliary nonvolatile memory via an address bus or a data bus.   The control circuit according to claim 1, wherein the control circuit reads information on the bus stored in the auxiliary nonvolatile memory at a predetermined timing.   The control circuit according to claim 3, wherein the predetermined timing is when a power source of an electronic device equipped with the control circuit is turned on.   The storage of the bus information in the auxiliary non-volatile memory is performed in synchronization with a control signal supplied from the control circuit to the auxiliary non-volatile memory. The control circuit according to claim 3 or 4.   The flash memory has a status period corresponding to the control command, and storage of the bus information in the auxiliary nonvolatile memory is performed in a period before the middle of the status period. The control circuit according to claim 1, claim 2, claim 3, claim 4 or claim 5.   The said control circuit divides | segments the said control command or an address into several cycles, and supplies it to the said flash memory memory, The claim 1, Claim 3, Claim 4, Claim 5 or Claim 5 characterized by the above-mentioned. The control circuit according to claim 6.   A control command indicating any one of a read operation, a program operation or an erase operation is supplied to the nonvolatile memory via the bus,
  When supplying the control command, the information of the bus is stored in an auxiliary nonvolatile memory that has a faster write operation than the flash memory,
  A method for controlling a flash memory, comprising: reading information on the bus from the auxiliary nonvolatile memory when power is turned on.   9. The flash memory control method according to claim 8, wherein the bus information is stored in the auxiliary nonvolatile memory in the first half of a cycle time for processing the control command.   10. The flash memory control method according to claim 8, wherein the control command or address is divided into a plurality of cycles and supplied to the flash memory memory.

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