JP4419480B2 - Image processing apparatus and method - Google Patents

Description

  The present invention relates to an image processing apparatus and method for expressing a model by a combination of unit graphics, generating pixels in a drawing target area of a screen coordinate system, and performing a rendering process on a memory.

  Combined with improvements in computing speed and enhancement of drawing functions in recent computer systems, research and development of “computer graphics (CG)” technology that creates and processes graphics and images using computer resources is actively conducted. Has been put to practical use.

For example, in 3D graphics, optical phenomena when a 3D object is illuminated by a predetermined light source are expressed by a mathematical model, and the object surface is shaded or shaded based on this model. By pasting, a more realistic and three-dimensional two-dimensional high-definition image is generated.
Such computer graphics are increasingly used in CAD / CAM in development fields such as science, engineering and manufacturing, and in various other application fields.
In recent years, computer graphics technology has been used for mobile phones, personal digital assistants (PDAs), car navigation systems, and the like.

  Three-dimensional graphics is generally composed of a “geometry subsystem” positioned as a front end and a “raster subsystem” positioned as a back end.

The geometry subsystem is a process of performing geometric calculation processing such as the position and orientation of a three-dimensional object displayed on a display screen.
In the geometry subsystem, an object is generally handled as a collection of a large number of polygons, and geometric calculation processing such as “coordinate transformation”, “clipping”, “light source calculation”, and the like is performed for each polygon.

On the other hand, the raster subsystem is a process of painting each pixel constituting an object.
The rasterization process is realized by interpolating the image parameters of all the pixels included in the polygon based on the image parameters obtained for each vertex of the polygon, for example.
The image parameters referred to here include color (drawing color) data expressed in a so-called RGB format and the like, a z value indicating a distance in the depth direction, and the like.
In addition, in recent high-definition 3D graphics processing, f (fog: fog) for creating a sense of perspective, texture t (texture) for expressing the texture and pattern of the object surface and providing reality, It is included as one of the image parameters.

Here, the process of generating the pixels inside the polygon from the vertex information of the polygon is often performed using a linear interpolation method called DDA (Digital Differential Analyzer).
In the DDA process, the inclination of the data in the side direction of the polygon is obtained from the vertex information, the data on the side is calculated using this inclination, and then the inclination in the raster scanning direction (X direction) is calculated. An internal pixel is generated by adding the change amount of the parameter obtained from the above to the parameter value of the scanning start point.

In 3D computer graphics, when determining the color corresponding to each pixel, the color of each pixel is calculated, and the calculated color value is stored in a display buffer (frame buffer) corresponding to the pixel. Rendering processing to write to the address is performed.
In order to perform such rendering processing, a pixel engine (rendering engine) is provided.

The drawing speed in three-dimensional computer graphics is affected by the writing speed from the drawing engine to the frame buffer, and the drawing speed decreases when the access speed of the frame buffer is low.
In order to solve this problem, using an expensive high-speed memory for a large-capacity frame buffer leads to an increase in the price of the system. Therefore, on the premise that an inexpensive general-purpose memory is used, an image processing apparatus using a cache mechanism is proposed. It has been proposed (see, for example, Patent Document 1).

The image processing apparatus described in Patent Document 1 temporarily stores image data generated by a drawing engine in a prefetchable FIFO memory or the like, and caches the prefetched FIFO memory or the like between the frame buffer and the frame buffer. A memory is provided, and the contents of the prefetchable FIFO memory and the like are prefetched into the cache memory, and read / write control of the cache memory is performed.
JP-A-9-212661

However, in the conventional three-dimensional computer graphics, in order to realize the function, an exclusive memory system or an architecture configuration depending on (adhering to) the memory system has been adopted.
In terms of general-purpose memory compatibility, as described in Patent Document 1 described above, a cache mechanism based on a general-purpose DRAM is used.

On the other hand, high-function modules represented by IP are also required for three-dimensional computer graphics (3DCG) functions in order to cope with high integration and multi-function like SOC. At this time, in the case of the conventional method, when the memory system is different, it is necessary to use a dedicated memory as an IP or to redesign it to a different system memory.
Adding a dedicated memory causes an increase in area, power, and complexity of the memory access mechanism. Performing the redesign brings about a design load including a three-dimensional computer graphics function implementation structure.
As described above, the conventional image processing architecture corresponding to three-dimensional computer graphics cannot be configured separately from the memory architecture depending on the memory architecture, and is a system such as a high-function module represented by IP. There was the disadvantage that it was difficult to easily apply.

  The present invention has been made in view of such circumstances, and its purpose is to suppress an increase in area and power, to simplify a memory access mechanism, to reduce design load, and without depending on a memory system. Another object of the present invention is to provide an image processing apparatus and method that can be easily adapted to various systems.

In order to achieve the above object, a first aspect of the present invention is an image processing apparatus that performs a rendering process on a memory, generates pixel data based on information on a primitive to be drawn, and information on access to the memory a pixel engine for outputting a two-dimensional coordinate as receives two-dimensional coordinates that by the above pixel engine takes a two-dimensional structure corresponding to the two-dimensional coordinate for the pixel data, 2 for accessing the memory A command corresponding to the dimension coordinate information and a cache for outputting a cache command standardized to data are provided.

  Preferably, the cache command includes general-purpose information necessary for the real address of the memory.

  Preferably, it has a memory interface that receives a cache command from the cache and generates a real address of the memory.

  Preferably, a memory interface that receives a cache command from the cache and generates a real address of the memory depending on a memory architecture is provided.

According to a second aspect of the present invention, there is provided an image processing apparatus that performs a rendering process on a memory, an external interface that controls an interface with an external apparatus, a memory interface that controls an interface with the memory, and the external interface. the pixel data generated based on information about the primitive to be rendered input receives the pixel engine for outputting a two-dimensional coordinate as information about access to the memory, the 2-dimensional coordinates that by the above pixel engine, the pixel data A memory having a two-dimensional structure corresponding to the two-dimensional coordinates and outputting a command corresponding to the two-dimensional coordinate information and a cache command standardized to data in order to access the memory; The above cache In response to the cache command by generating the real address of the memory.

  According to a third aspect of the present invention, there is provided an image processing method for performing a rendering process on a memory, wherein a first step for generating pixel data based on information on a primitive to be drawn and information on access to the memory are 2 A second step of generating and providing a dimensional coordinate to the cache, and a third step of outputting a cache command standardized to data and a command corresponding to the two-dimensional coordinate information in order to access the memory in the cache. Have.

According to the present invention, pixel data is generated in the pixel engine based on information on primitives to be drawn, for example, various data (z, color, etc.).
In the pixel engine, two-dimensional coordinates are output to the cache as information relating to access to the memory.
The cache receives the two-dimensional coordinates that by the pixel engine, taking a two-dimensional structure corresponding to the two-dimensional coordinate for the pixel data, the commands and data corresponding to the two-dimensional coordinate information to access the memory A standardized cache command is output.
The memory interface receives a cache command from the cache and generates a memory real address depending on the memory architecture.

According to the present invention, there is an advantage that an increase in area and power can be suppressed, a memory access mechanism can be simplified, and a design load can be reduced.
As a result, when the image processing, which is conventionally configured depending on the memory architecture, that is, the three-dimensional computer graphics architecture is separated from the memory and used as an IP used for general-purpose SOCs, etc., the functional block specifications depending on the memory system Can be easily adapted to the system.

Hereinafter, this embodiment will be described with reference to the accompanying drawings.
In the present embodiment, memory access in image processing is controlled by switching the function of performing real address generation depending on the image memory architecture in the form of command and data that is independent of the image memory architecture. Separated into a cache independent of processing memory architecture.
Thus, when image processing, which is conventionally configured depending on a memory architecture, that is, a three-dimensional computer graphics architecture is separated from a memory and used as an IP for general-purpose SOCs, etc., functional block specifications depending on the memory system Is standardized, it is possible to easily adopt a configuration adapted to the system.

  FIG. 1 is a configuration diagram showing an embodiment of a main part of an image processing apparatus according to the present invention.

The image processing apparatus 10 is applied to a three-dimensional computer graphics system. For example, a three-dimensional model is expressed as a combination of triangles (polygons) that are unit figures, and the colors of each pixel on the display screen are displayed by drawing the polygons. Determine and perform polygon rendering processing for the memory.
In the three-dimensional computer graphics system, in addition to the (x, y) coordinate representing the position on the plane, the z coordinate representing the depth is used to represent the three-dimensional object, and this (x, y, z) An arbitrary point in the three-dimensional space is specified by three coordinates.

  As shown in FIG. 1, the image processing apparatus 1 includes a system-dependent block 2 and a core block 3 as main components.

  As shown in FIG. 1, the system-dependent block 2 includes a CPU interface (BB) 21 and a memory interface (MEMIF) 22 as external interfaces.

  The CPU interface 21 is connected to, for example, a CPU (main processor) as a host device (not shown) via the CPU bus 4, and is an interface such as data exchange between the CPU and the core block 3 or between functional blocks in the core block 3. Process.

  The memory interface 22 performs interface processing such as data exchange between the core block 3 and a memory connected through a memory bus (not shown) or a system bus.

  As illustrated in FIG. 2, the core block 3 includes a geometry engine (GE) 31 and a rasterization engine (RE) 33.

When the geometry engine 31 is transferred to the CPU bus 4 by a CPU (not shown), for example, and each vertex data of three-dimensional coordinates, normal vectors, and texture coordinates transferred through the CPU interface is input, For example, floating point arithmetic is performed.
Typical calculations include coordinate conversion calculation processing that performs deformation of an object, projection onto a screen, lighting calculation processing, and clipping calculation processing.
The geometry engine 31 transfers the calculation processing result to the rasterization engine 32 through the CPU interface 21 as, for example, polygon rendering data.

This polygon rendering data includes (x, y, z, R, G, B, α, s, t, q) data of each of the three vertices of the polygon.
Here, (x, y, z) data indicates the three-dimensional coordinates of the vertices of the polygon, and (R, G, B) data indicates the luminance values of red, green, and blue at the three-dimensional coordinates, respectively. Yes.
Α represents a blend value (coefficient).
Of the (s, t, q) data, (s, t) indicates the homogeneous coordinates of the corresponding texture, and q indicates the homogeneous term. Here, “s / q” and “t / q” are multiplied by the texture sizes USIZE and VSIZE, respectively, to obtain actual texture coordinate data (u, v).
Access to the texture data stored in the memory of the rasterization engine 32 is performed using the texture coordinate data (u, v).
That is, the polygon rendering data is a physical coordinate value of each vertex of the triangle, a color of each vertex, and texture data.

The rasterization engine 32 receives polygon rendering data from the geometry engine 31 and calculates DDA parameters such as inclinations of various data (depth (Z), color (C), texture coordinates, etc.) necessary for rasterization. The various data are rasterized, a perspective collection of texture coordinates (Perspective Correction) is performed, and texture filtering is performed.
The texture coordinate perspective collection processing includes calculation of a mipmap (MIPMAP) level by LOD (Level of Detail) calculation and calculation of (u, v) address for texture access. In the texture filtering process, a filtering process such as 4-neighbor interpolation is performed on the data read from the memory (not shown) and the decimal part obtained when the (u, v) address is calculated.
The rasterization engine 32 then performs pixel level processing. In this processing, calculation in units of pixels is performed using the texture data after filtering and the various data (Z, C) after rasterization. In this processing, in addition to pixel operations such as lighting at the pixel level, various processes such as an alpha test, a Z (depth) test, and alpha blending are performed.
The rasterization engine 32 writes pixel data that has passed various tests in pixel level processing to an external memory through the memory interface 22.

  The rasterization engine 32 in this embodiment accesses the memory through the memory interface 22, but a cache mechanism is provided between the texture pixel engine and the memory interface that perform the texture and pixel level processing described above, and The memory access in image processing does not depend on the image processing memory architecture by switching the function of generating real addresses depending on the image memory architecture in the form of command and data that is independent of the image memory architecture. Separated into cache.

Specifically, the rasterization engine 32 in the present embodiment is
1) Handle virtual 2D screen coordinates at addresses up to the cache mechanism.
2) For memory access from the cache, standardize with commands and data according to the above contents.
3) Standardize general-purpose information (memory start address, etc.) required for real addresses by including them in commands.
4) The real address space is divided into dedicated mechanisms and is realized with the minimum necessary scale.
It has a characteristic configuration.

  Hereinafter, a more specific configuration of the rasterization engine 32 including this characteristic cache mechanism will be described.

FIG. 2 is a block diagram showing a specific configuration example of the rasterization engine 32 according to the present embodiment.
As shown in FIG. 2, the rasterization engine 32 includes a DDA (Digital Differential Analizer) setup circuit 321 as an initial setting calculation block for linear interpolation calculation, a triangle DDA circuit 322 as a linear interpolation processing block, and a texture map engine. (TME) pixel operation engine (POE) (hereinafter referred to as TME_POE) 323 and cache system 324.

Prior to obtaining the color and depth information of each pixel inside the triangle by linearly interpolating the value of each vertex of the triangle on the physical coordinate system in the triangle DDA circuit 322 in the subsequent stage, the DDA setup circuit 321 is polygon rendering data. For the (z, R, G, B, α, s, t, q) data indicated by S11, a setup calculation is performed to find the difference between the sides of the triangle and the horizontal direction.
Specifically, this set-up calculation uses the start point value, end point value, and distance between the start point and end point to calculate the variation of the value to be obtained when the unit length is moved. .
The DDA setup circuit 321 outputs setup data S321 as information on the primitive including the calculated variation data to the triangle DDA circuit 322.

The function of the DDA setup circuit 321 will be further described with reference to FIG.
As described above, the main processing of the DDA setup circuit 321 is the three vertices P0 (x0, y0) given various information (color, texture coordinates) at each vertex that has fallen down to physical coordinates after the previous geometry processing. ), P1 (x1, y1), and P2 (x2, y2) to obtain the variation within the triangle, and calculate the basic data of the subsequent linear interpolation processing.
Triangular drawing is summarized into drawing of every pixel, and for this purpose, it is necessary to obtain the first value at the drawing start point.
Various information at the first drawing point is the sum of the value obtained by multiplying the horizontal distance from the vertex to the first drawing point by the horizontal variation and the value obtained by multiplying the vertical distance by the vertical variation. Become. Once the values on one integer grid inside the target triangle are found, the values at other grid points inside the target triangle can be found by integer multiples of the variation.

  Each vertex data of the triangle is, for example, 16 bits for x and y coordinates, 24 bits for z coordinates, 12 bits for RGB color values (= 8 + 4), and 32 bits for s, t, q texture coordinates (IEEE). Format).

Note that the DDA setup circuit 321 is mounted by an ASIC technique instead of a DSP structure as in the prior art.
Specifically, as shown in FIG. 4, full data in which arithmetic unit groups 3212-1 to 2122-3 in which a plurality of arithmetic units are arranged in parallel are inserted between registers 3211-1 to 2112-4 arranged in multiple stages. It is configured as a path logic, in other words, a time parallel structure of a synchronous pipeline system.

The triangle DDA circuit 322 is linearly interpolated (z, R, G, B, α) in each pixel inside the triangle based on the setup data S321 as information regarding primitives including variation data input from the DDA setup circuit 321. , S, t, q) data is calculated.
The triangle DDA circuit 322 converts (x, y) data of each pixel and (z, R, G, B, α, s, t, q) data at the (x, y) coordinates into DDA data (interpolation). Data) Output to TME_POE 323 as S322.

That is, the triangle DDA circuit 322 performs a rasterization process (rasterization) that interpolates the image parameters of all the pixels included in the polygon based on the image parameters obtained for each vertex of the polygon.
Specifically, the triangle DDA circuit 322 rasterizes various data (z, texture coordinates, color, etc.).

  The TME_POE 323 performs, for example, a texture blending process, an alpha test, a depth (depth) test, an alpha blending process, and a pixel operation. In pixel operation, pixel data that passes various tests is written to an external memory through the cache system 324 and the memory interface 22.

  As described above, after predetermined processing in the DDA setup circuit 321, the triangle DDA circuit 322, and the TME_POE 323, the final memory access becomes a drawing pixel unit called a pixel (Pixel; Picture Cell Element).

  The cache system 324 includes a texture cache (T cache) 3241, a color cache (C cache) 3242, and a depth cache (Z cache) 3242.

Texture data for blending in the TME_POE 323 is accessed via the memory interface 22 through the texture coordinates arranged in the T cache 3241.
Color data for color / depth operation in the TME_POE 323 is accessed through the memory interface 22 through two-dimensional pixel coordinates arranged in the C cache 3242 and the Z cache 3243.
As described above, in TME_POE 323 according to the present embodiment, a separate memory system that depends on the coordinates and address blocks (MEMIF) based on the cache system, and a command-based system that depends on the interface between the cache system 324 and the memory interface 22 Is adopted.

In the present embodiment, the coordinate space in the pixel operation in TME_POE 323 does not depend on the memory system used.
Coordinates based on the cache system 324 can be configured for any memory system.
A system that relies on an address block (MEMIF) can be separated from the cache system 324.

  FIG. 5 is a diagram showing a command-based cache data access structure in which the TME_POE 334 (RE) side of the cache system 324 and the memory interface (MEMIF) 22 as a memory access block are separated.

  The cache command (C / CMD) shown in FIG. 5 includes, for example, a 1-bit register set bit, coordinates arranged in a multi-bit cache, tag (TAG) address information, line information, 1 bit, as shown in FIG. Fill / write back direction, and a plurality of write back data mask bits.

By using this structure, an address feature dependent system such as page allocation or bus protocol need only be installed in the memory interface (MEMIF) 22.
Therefore, it is possible to construct a low-cost system that is easy to design.

  As described above, the memory access in the rasterization engine 32 according to the present embodiment is divided into the pixel having the color (C), the Z having the three-dimensional depth, and the T having the texture, and is first separated from the real address. This is performed for a cache mechanism corresponding to a two-dimensional coordinate system.

FIG. 7 is a diagram showing a specific access control system of the C cache and the Z cache in the present embodiment.
The access control system 100 includes a POE controller (POECTL) 101, a cache line tag / flag unit 102, cache lines 103-1 to 103-n (n is 8, 16, 32...), A control register (CTLREG). 105 and DMA 104.
The DMA 104 corresponds to the memory interface 22 in FIGS. 1 and 2 and is a system-dependent part.

In this access control system 100, the access unit is one pixel, which is indicated by two-dimensional coordinates of x and y. One cache line 103 (-1 to -n) is 128 bits / 256 bits, and takes a two-dimensional structure corresponding to two-dimensional coordinates for pixel data.
A POE controller (POECTL) 101 performs control corresponding to pixel read / write from the TME_POE 33.
The control register (CTLREG) 105 determines the cache pixel format and the cache access attributes (R / W, W).
As described above, the address of the real address space is set by the DMA 105, and these settings are transmitted by the DMA command.
The tag / flag in the cache line tag / flag unit 102 links the cache line and the memory two-dimensionally and indicates the status of the cache line.
For example, 128-bit access is realized from the DMA 105 and a maximum of 32-bit access is realized from the POE 33 side.

Next, an example will be described for two-dimensional (2D) map processing of a C (color) / Z (depth / depth) cache.
In this case, the C / Z cache line number corresponding to the two-dimensional address is calculated, and the reference position when the POE 33 is read / written (R / W) is determined.
Line maps are classified into the following three types that differ depending on the pixel format in accordance with the register setting shown in the control register 104.

That is,
1) 16-bit pixel format in 16-line .C cache, 16-bit pixel format in Z-cache,
2) 8 lines (4 × 2) .. 32 bit pixel format in C cache, 32 pixel format in Z cache,
3) 8 lines (4 × 4) .. 8 bit pixel format in C cache,
There are three types.

  Here, specific processing will be described by taking the case of 16 lines of C / Z cache as an example. Since 8 lines (4 × 2) and 8 lines (4 × 4) are performed in the same manner as in the case of 16 lines, detailed description thereof is omitted in this embodiment.

In the case of 16 lines in the C / Z cache, the access coordinates (address) are blocked at 4 × 2 so as to be the cache size. The relationship between the block address (xb, yb) and the reference address (xo, yo) is as follows.
xb = xo >> 2
yb = yo >> 1

For this block address (xb, yb), the tag Nonum is calculated as follows.
num = (xb & 0X3) | ((yb & 0X3) << 2)

Since the two-dimensional coordinate value is an address (the page address of the memory reference physical address by the DMA 105 is determined on the DMA 105 side), the address stored in the tag is higher than the block address (xb, yb).
xtag = xb >> 2
ytag = yb >> 2

The cache bit reference is performed by comparing this value after tag addressing.
The relationship with reference coordinate input in this case is shown in FIG.

Next, pixel data allocation in the case of 16 lines in the C / Z cache will be described.
The assignment of one cache line 128-bit data to the two-dimensional 8-pixel arrangement on the DMA 105 side and the POE 33 side will be described. The pixel assignment for the 128-bit line data on the DMA side has the form shown in FIG.
The allocation of 32 bit pixels is 16 bits on the LSB side.

Next, stamp access (stamp access) in the case of 16 lines in the C / Z cache will be described.
The read / write (R / W) reference from the POE 33 is performed by one pixel for one 16-bit stamp.
The reference is a read / write (R / W) pair because of its nature. If writing is not performed as a result of the processing, write (write) must be issued as invalid.
The stamp reference block address (xsb, ysb) for the stamp reference coordinates (xs0, ys0) (xs011 bits, ys011 bits) is given as follows.
xsb = xso >> 2
ysb = yso >> 1

  The relationship of stamp reference within 128 bits / line is as shown in FIG. 10 using LSB side bits of stamp reference coordinates (xs0, ys0).

Next, the memory interface (MEMIF) 22 according to the present embodiment will be described.
As described above, access to the C / Z cache is interfaced with the memory interface (MEMIF) 22 that realizes access to the real system as a general-purpose command (transfer matching is performed). The T-cache access is interfaced with a memory interface (MEMIF) 22 that realizes access to the real system as a similar general-purpose command.
Such a memory interface (MEMIF) 22 adopts a real address configuration in consideration of the characteristics of memory access (at the time of a cache miss) of the two-dimensional cache mechanism in accordance with the memory access interface (IF) specification in the SOC. A C / Z / T interface independent of a memory system of computer graphics (3DCG) is realized.

The function specification of the memory interface (MEMIF) 22 is a specification separated from the 3DCG function, and in the case of C / Z, for example, a function for processing general-purpose commands so as to have an address that matches the bus specification of the target SOC and the SDRAM specification. Specifications are adopted.
In order to realize a real memory address of the memory interface (MEMIF) 22, a head address and an address calculation coefficient are set by a general-purpose command. The same applies to the T-cache.
What should be noted in this embodiment is that the largest and most complicated 3DCG is completely separated, and the function block that matches the requirements of the target system is simply adjusted to the interface specified by the 3DCG function block. This is a realization. Therefore, only a design corresponding to the MEMIF needs to respond to other function requests (other SOC, etc.).

  Next, the operation according to the above configuration will be described.

First, in the geometry engine 31, for example, when the CPU bus 4 is transferred by a CPU (not shown) and the vertex data of the three-dimensional coordinates, the normal vector, and the texture that are transferred through the CPU interface are input, On the other hand, for example, a floating-point operation is performed. For example, as necessary, data such as graphics drawing is subjected to geometry processing such as coordinate conversion, clip processing, and lighting processing in the main processor 11 or the like.
The calculation processing result of the geometry engine 31 is transferred to the rasterization engine 32 through the CPU interface 21 as polygon rendering data, for example.

In the rasterization engine 32, first, the DDA setup circuit 321 generates variation data indicating the difference between the sides of the triangle and the horizontal direction based on the polygon rendering data.
Specifically, using the starting point value and the ending point value, and the distance between them, a variation that is a change in the value to be obtained when the unit length is moved is calculated, and the variation data Is output to the triangle DDA circuit 322 as setup data S321.

In the triangle DDA circuit 322, linearly interpolated (z, R, G, B, α, s, t, q) data for each pixel inside the triangle is calculated using the setup data S321 including variation data. Is done.
The calculated (z, R, G, B, α, s, t, q) data and (x, y) data of each vertex of the triangle are used as DDA data S322 from the triangle DDA circuit 322. It is output to TME_POE 323.
That is, in the triangle DDA circuit 322, rasterization processing is performed for interpolating image parameters (z, texture coordinates, color, etc.) of all pixels included in the polygon based on the image parameters obtained for each vertex of the polygon. .

In TME_POE 323, for example, a texture blending process, an alpha test, a depth (depth) test, an alpha blending process, and a pixel operation are performed. In the pixel operation, pixel data that passes various tests is written to an external memory through the cache system 324 and the memory interface 22.
Texture data for blending in the TME_POE 323 is accessed via the memory interface 22 through the texture coordinates arranged in the T cache 3241.
Color data for color / depth operation in the TME_POE 323 is accessed through the memory interface 22 through two-dimensional pixel coordinates arranged in the C cache 3242 and the Z cache 3243.

  As described above, according to the present embodiment, the rasterization engine 32 accesses the memory through the memory interface 22, but between the texture and pixel engine that performs texture and pixel level processing and the memory interface. A cache system 324 is provided, and the function of generating real addresses depending on the image memory architecture is divided into a command format independent of the image memory architecture and a form of passing data, thereby enabling memory access in image processing. Since the cache is independent of the image processing memory architecture, the following effects can be obtained.

That is, there is an advantage that an increase in area and power can be suppressed, a memory access mechanism can be simplified, and a design load can be reduced.
As a result, when the image processing, which is conventionally configured depending on the memory architecture, that is, the three-dimensional computer graphics architecture is separated from the memory and used as an IP used for general-purpose SOCs, etc., the functional block specifications depending on the memory system Can be easily adapted to the system.

It is a block diagram which shows one Embodiment of the principal part of the image processing apparatus which concerns on this invention. It is a block diagram which shows the structural example of the core block which concerns on this embodiment. It is a figure for demonstrating the function of the triangle DDA circuit which concerns on this embodiment. It is a block diagram which shows the principal part structure of the triangle DDA circuit which concerns on this embodiment. It is a figure which shows the command base cache data access structure which the memory interface (MEMIF) which is a memory access block and TME_POE (RE) side of the cache system which concerns on this embodiment isolate | separated. FIG. 6 is a diagram illustrating a structure example of a cache command (C / CMD) in FIG. 5. It is a figure which shows the specific access control system of C cache and Z cache in this embodiment. It is a figure which shows the two-dimensional map process in the case of C / Z cache 16 lines. It is a figure which shows the pixel allocation by the side of DMA in the case of 16 lines of C / Z cache. It is a figure which shows an example of the relationship of the stamp reference in the case of C / Z cache 16 lines.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus, 2 ... System dependent block, 21 ... CPU interface (BB), 22 ... Memory interface (MEMIF), 3 ... Core block, 31 ... Geometry engine (GE), 32 ... Rasterization engine (RE), 321 ... Triangle setup circuit, 322 ... Triangle DDA circuit, 323 ... Texture map engine (TME) / Pixel operation engine (POE) (TME_POE), 324 ... Cache system.

Claims (12)

An image processing apparatus that performs a rendering process on a memory,
A pixel engine that generates pixel data based on information about a primitive to be drawn and outputs two-dimensional coordinates as information about access to the memory;
In response to two-dimensional coordinates that by the above pixel engine, the taking a two-dimensional structure corresponding to the two-dimensional coordinates, normalized to commands and data corresponding to the two-dimensional coordinate information for accessing the memory for the pixel data An image processing apparatus having a cache that outputs the cache command. The image processing apparatus according to claim 1, wherein the cache command includes general-purpose information necessary for an actual address of the memory. The image processing apparatus according to claim 1, further comprising a memory interface that receives a cache command from the cache and generates a real address of the memory. The image processing apparatus according to claim 1, further comprising: a memory interface that receives a cache command from the cache and generates a real address of the memory depending on a memory architecture. The image processing apparatus according to claim 2, further comprising a memory interface that receives a cache command from the cache and generates a real address of the memory. The image processing apparatus according to claim 3, further comprising a memory interface that receives a cache command from the cache and generates a real address of the memory depending on a memory architecture. An image processing apparatus that performs a rendering process on a memory,
An external interface that controls the interface with external devices;
A memory interface for controlling the interface with the memory;
A pixel engine that generates pixel data based on information about a primitive to be drawn input via the external interface, and outputs two-dimensional coordinates as information about access to the memory;
In response to two-dimensional coordinates that by the above pixel engine, the taking a two-dimensional structure corresponding to the two-dimensional coordinates, normalized to commands and data corresponding to the two-dimensional coordinate information for accessing the memory for the pixel data A cache that outputs the cache command
The image processing apparatus, wherein the memory interface receives a cache command from the cache and generates a real address of the memory. The external interface and the memory interface that controls the interface with the memory constitute a system-dependent block,
The image processing apparatus according to claim 7, wherein the pixel engine and the cache constitute a system-independent core block. The image processing apparatus according to claim 7, wherein the cache command includes general-purpose information necessary for a real address of the memory. The image processing apparatus according to claim 9, further comprising: a memory interface that receives a cache command from the cache and generates a real address of the memory depending on a memory architecture. An image processing method for rendering a memory,
A first step of generating pixel data based on information about the primitive to be drawn;
A second step of generating two-dimensional coordinates as information relating to access to the memory and providing the same to a cache;
An image processing method comprising: a third step of outputting a cache command standardized to data and a command corresponding to two-dimensional coordinate information in order to access the memory in the cache. The image processing method according to claim 11, further comprising a fourth step of receiving the cache command and generating a real address of the memory depending on a memory architecture.

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