JP4419381B2

JP4419381B2 - Semiconductor element

Info

Publication number: JP4419381B2
Application number: JP2002329831A
Authority: JP
Inventors: 勉上杉; 将一兼近; 雅人樹神; 秀記細川
Original assignee: Toyota Central R&D Labs Inc
Current assignee: Toyota Central R&D Labs Inc
Priority date: 2002-11-13
Filing date: 2002-11-13
Publication date: 2010-02-24
Anticipated expiration: 2022-11-13
Also published as: JP2004165449A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子に関する。
【０００２】
【従来の技術】
特許文献１に記載の横型ＭＯＳＦＥＴは、半導体部と、電極部を備えている。半導体部は、ドレイン領域、ドリフト領域、ボディ領域、ソース領域を有する。電極部は、トレンチに沿って形成された絶縁膜と、その絶縁膜で覆われた状態でトレンチ内に形成された導電層を有する。電極部（トレンチ）は、ドリフト領域とソース領域の間のボディ領域と、ドレイン領域とボディ領域の間のドリフト領域の両方に隣合っている。この半導体素子は、前記電極部を備えることで、低オン抵抗で高耐圧の素子を実現しようとするものである。前記電極部を以下では便宜上「トレンチ電極部」という。
【０００３】
【特許文献１】
特開平１１−１０３０５８号公報（第２図）
【０００４】
【発明が解決しようとする課題】
特許文献１に記載の横型ＭＯＳＦＥＴでは、前記絶縁膜は１つのトレンチの壁面に沿って一体的に形成され、厚さはほぼ一定である。しかし、前記したドリフト領域とソース領域の間のボディ領域に隣合う絶縁膜（以下「前者の絶縁膜」という）と、ドレイン領域とボディ領域の間のドリフト領域に隣合う絶縁膜（以下「後者の絶縁膜」という）の厚さは異ならせる方が本来的には望ましい。具体的には、前者の絶縁膜は薄く形成し、後者の絶縁膜は厚く形成するのが望ましい。なぜなら、前者の絶縁膜を厚く形成すると、横型ＭＯＳＦＥＴをオンさせるためにトレンチ電極部に印加する電圧を高く設定する必要があるからである。また、後者の絶縁膜を薄く形成すると、絶縁破壊が生じ易くなり、耐圧が大幅に低下してしまうからである。従って、前者の絶縁膜と後者の絶縁膜の厚さが同じであると、素子特性の適正化が行いにくい。
【０００５】
特許文献１に記載の横型ＭＯＳＦＥＴでは、前者の絶縁膜と後者の絶縁膜は前記したように１つのトレンチの壁面に沿って一体的に形成されている。しかし、１つのトレンチの壁面に沿って一体的に形成される絶縁膜の厚さを部分的に異ならせるには、煩雑ないしは高度な製造工程を経る必要がある。通常は、深くて狭いトレンチの壁面（側面や底面）に部分的にマスクを形成あるいは除去するような工程等を経る必要がある。このように、特許文献１に記載の横型ＭＯＳＦＥＴは、前者の絶縁膜と後者の絶縁膜の厚さを異ならせることが実質的に困難であり、素子特性の適正化が行いにくい構造となっている。
【０００６】
本発明は、素子特性の適正化が行いやすい構造であるとともに、低オン抵抗で高耐圧な半導体素子を実現することを目的とする。
【０００７】
【課題を解決するための手段及び作用と効果】
〔１〕本発明に係る半導体素子は、半導体部と、チャネルトレンチ電極部と、ドリフトトレンチ電極部を備えている。半導体部は、第１半導体領域と、第２半導体領域と、第３半導体領域と、第４半導体領域を有する。第１〜第４半導体領域は、その順序又はその逆の順序で電流が流れるように配置されている。第１半導体領域と第４半導体領域は、半導体部の第１主面に隣接する領域を含む。第２半導体領域と第４半導体領域は第１導電型である。第３半導体領域は第２導電型である。
チャネルトレンチ電極部は、第２半導体領域と第４半導体領域の間の第３半導体領域に隣合う第１トレンチに沿って形成された第１絶縁膜と、第１絶縁膜に覆われた状態で第１トレンチ内に形成された第１導電層を有する。ドリフトトレンチ電極部は、第２半導体領域に隣合うとともに第３半導体領域によって第４半導体領域から分離されている第２トレンチに沿って形成された第２絶縁膜と、第２絶縁膜に覆われた状態で第２トレンチ内に形成された第２導電層を有する。チャネルトレンチ電極部の第１絶縁膜の厚さは、ドリフトトレンチ電極部の第２絶縁膜の厚さよりも薄い。
【０００８】
〔２〕本発明に係る他の半導体素子は、半導体部と、チャネルトレンチ電極部と、ドリフトトレンチ電極部を備えている。半導体部は、第１半導体領域と、これに接する第２半導体領域と、これに接する第３半導体領域と、これに接する第４半導体領域を有する。第１半導体領域と第４半導体領域は、半導体部の第１主面に隣接する領域を含む。第２半導体領域と第４半導体領域は第１導電型である。第３半導体領域は第２導電型である。
チャネルトレンチ電極部は、第２半導体領域と第４半導体領域の間の第３半導体領域に隣合う第１トレンチに沿って形成された第１絶縁膜と、第１絶縁膜に覆われた状態で第１トレンチ内に形成された第１導電層を有する。ドリフトトレンチ電極部は、第２半導体領域に隣合うとともに第３半導体領域によって第４半導体領域から分離されている第２トレンチに沿って形成された第２絶縁膜と、第２絶縁膜に覆われた状態で第２トレンチ内に形成された第２導電層を有する。チャネルトレンチ電極部の第１絶縁膜の厚さは、ドリフトトレンチ電極部の第２絶縁膜の厚さよりも薄い。
【０００９】
これらの半導体素子は、第２半導体領域と第４半導体領域の間の第３半導体領域に隣合う第１トレンチに沿って第１絶縁膜が形成されている。また、第２半導体領域に隣合う第１トレンチとは別個の第２トレンチに沿って第２絶縁膜が形成されている。このように、これらの半導体素子では、第３半導体領域に隣合う絶縁膜（第１絶縁膜）と、第２半導体領域に隣合う絶縁膜（第２絶縁膜）が別個に形成されている。よって、製造時には、これらの絶縁膜を別個に形成できる。このため、これらの絶縁膜の厚さを、煩雑ないしは高度な製造工程を経ずに異ならせることができる。よって、第１絶縁膜は薄くして、素子をオンさせるためにチャネルトレンチ電極部に印加する電圧を低く設定することを容易に行える。一方、第２絶縁膜は厚くして、絶縁破壊を生じにくくすることで、高耐圧化を実現することを容易に行える。このように、これらの半導体素子の構造によると、素子特性の適正化が行いやすい。
【００１０】
また、これらの半導体素子は、素子をオンさせる場合には、チャネルトレンチ電極部に所定電圧を印加することで、チャネルトレンチ電極部に隣合う第３半導体領域にチャネルを形成できる。これに加えて、ドリフトトレンチ電極部に所定電圧を印加することで、ドリフトトレンチ電極部に隣合う第２半導体領域にキャリアの蓄積領域を形成できる。よって、ドリフトトレンチ電極部がない場合に比べて第２半導体領域におけるオン抵抗を低減できる。
また、これらの半導体素子は、第２半導体領域と第３半導体領域の接合部に逆バイアス電圧が印加されたときに、第２半導体領域と第３半導体領域の間の接合部から空乏層を伸ばすだけでなく、ドリフトトレンチ電極部に隣合う第２半導体領域からも空乏層を伸ばすことができる。よって、高耐圧化を実現できる。
このように、本発明によると、素子特性の適正化が行いやすい構造であるとともに、低オン抵抗で高耐圧な半導体素子を実現できる。
【００１１】
〔４〕半導体部の第１主面と反対側に位置する第２主面に隣接する分離部をさらに備え、チャネルトレンチ電極部と、ドリフトトレンチ電極部と、第１半導体領域の少なくとも１つが前記第１主面に垂直な方向に分離部に達するまで伸びていることが好ましい。
〔５〕ドリフトトレンチ電極部は、第２半導体領域のうち第１半導体領域と第３半導体領域の間を接続する領域全体にわたって隣合うことが好ましい。
〔６〕ドリフトトレンチ電極部を複数有し、これらのドリフトトレンチ電極部群は、素子のオフ時にドリフトトレンチ電極部群に隣合う第２半導体領域からその内部に伸びる空乏層同士がつながるような間隔で配置されていることが好ましい。
【００１２】
〔７〕第２半導体領域は、前記第１主面に平行な方向に不純物濃度の濃度勾配が形成されている一方、前記第１主面に垂直な方向の不純物濃度はほぼ一定であることが好ましい。
〔８〕上記〔７〕に記載の半導体素子の製造方法としては、第２半導体領域となる領域の側面からその領域の内部に向けてイオンを注入する工程と、熱処理を行う工程を順に行うことが好ましい。
〔９〕また、上記〔７〕に記載の半導体素子の製造方法としては、第２半導体領域となる領域に隣接するとともに第２半導体領域の底部と底部の位置がほぼ等しいトレンチ内に第１導電型の不純物が添加された半導体材料を形成する工程と、熱処理を行う工程を順に行うことが好ましい。
【００１３】
〔１０〕第１〜第４半導体領域は、前記第１主面に平行な第１方向に順に形成された領域を含み、チャネルトレンチ電極部は、第２半導体領域と第４半導体領域の間の第３半導体領域のうち前記第１方向にぼぼ垂直な面領域に隣合うことが好ましい。
〔１１〕第２〜第４半導体領域は、前記第１主面に垂直な方向に順に形成された領域を含み、チャネルトレンチ電極部は、前記第１主面に垂直な方向に順に形成された第２半導体領域と第４半導体領域の間の第３半導体領域に隣合うことが好ましい。
〔１２〕第１〜第４半導体領域は、前記第１主面に平行な第１方向に順に形成された領域を含み、チャネルトレンチ電極部は、第２半導体領域と第４半導体領域の間の第３半導体領域のうち前記第１方向と前記第１主面に垂直な方向の両方にぼぼ平行な面領域に隣合うことが好ましい。
【００１５】
【発明の実施の形態】
（第１実施形態）図１は、本発明の第１実施形態の半導体素子（横型半導体素子、より詳細には横型パワーＭＯＳＦＥＴ）の平面図を示す。図２は、図１のII−II線断面図を示す。図３は、図１のIII−III線断面図を示す。
この半導体素子は、図２に示すように、分離部１０と、半導体部１６と、第１電極部（以下では「チャネルトレンチ電極部」という）３３と、第２電極部（図１と図３参照、以下では「ドリフトトレンチ電極部」という）２３を備えている。
【００１６】
図２に示すように、分離部１０は、半導体基板（本実施形態ではシリコン基板）１２と、絶縁層（本実施形態ではシリコン酸化層）１４によって構成されている。分離部１０は、半導体部１６を絶縁分離するものである。
半導体部（本実施形態ではシリコン部）１６は、分離部１０上に形成されている。分離部１０は、半導体部１６の第１主面（表面）Ｍ１と反対側に位置する第２主面（裏面）Ｍ２に隣接しているともいえる。半導体部１６は、第１半導体領域（以下では「ドレイン領域」という）１８と、第２半導体領域（以下では「ドリフト領域」という）２８と、第３半導体領域（以下では「ボディ領域」という）３０と、第４半導体領域（以下では「ソース領域」という）３２を有し、その順序で電流が流れるように配置されている。本実施形態では、ドレイン領域１８とドリフト領域２８、ドリフト領域２８とボディ領域３０、及びボディ領域３０とソース領域３２はそれぞれ接している。また、ドレイン領域１８、ドリフト領域２８、ボディ領域３０、ソース領域３２は、半導体部１６の第１主面（表面）Ｍ１に平行な方向のうち第１方向（図１と図２では横方向）に順に形成された領域を含む。また、ドリフト領域２８、ボディ領域３０、ソース領域３２は、第１主面Ｍ１に垂直な方向（素子深さ方向ともいえる。図２では縦方向）に順に形成された領域を含む。
【００１７】
ドレイン領域１８とソース領域３２は、半導体部１６の第１主面Ｍ１に隣接する領域を含む。ドレイン領域１８とソース領域３２のうち第１主面Ｍ１に露出した部位にそれぞれ、ドレイン電極２０とソース電極３１が接している。なお、ソース電極３１は、ｐ型ボディ領域３０（より詳細にはｐ^＋型ボディコンタクト領域）にも接している。ドレイン領域１８はｎ^＋型であり、ドリフト領域２８はｎ⁻型であり、ソース領域３２はｎ^＋型である。ボディ領域３０はｐ型である。
なお、図１の平面図では、説明の便宜のため、ドレイン電極２０とソース電極３１の図示を省略している。
【００１８】
図１の平面図でみると、チャネルトレンチ電極部３３は、第１主面Ｍ１（図２参照）に平行な方向のうち、前記第１方向（図１の横方向）に直交する第２方向（図１の縦方向）に伸びている。一方、ドリフトトレンチ電極部２３は、前記第１方向（図１の横方向）に伸びている。ドリフトトレンチ電極部２３は、前記第２方向（図１の縦方向）にストライプ状に複数本形成されている。このように、本実施形態では、平面視すると、チャネルトレンチ電極部３３とドリフトトレンチ電極部２３の伸びる方向は直交している。
【００１９】
図２に示すように、チャネルトレンチ電極部３３は、ドリフト領域２８とソース領域３２の間のボディ領域３０（領域３０ａ）に隣合う第１トレンチ３５に沿って形成された第１絶縁膜３４と、第１絶縁膜３４に覆われた状態で第１トレンチ３５内に形成された第１導電層３６を有する。チャネルトレンチ電極部３３は、ドリフト領域２８とソース領域３２の間のボディ領域３０（領域３０ａ）のうち前記第１方向（図２の横方向）にぼぼ垂直な面領域３０ｂに第１絶縁膜３４を介して隣合っている。チャネルトレンチ電極部３３は、第１主面Ｍ１に垂直な方向（図２では縦方向）に順に形成されたドリフト領域２８とソース領域３２の間のボディ領域３０（領域３０ａ）に隣合っているともいえる。チャネルトレンチ電極部３３は、分離部１０とボディ領域３０の間のドリフト領域２８（領域２８ａ）のうち前記第１方向（図２の横方向）にぼぼ垂直な面領域２８ｂに隣合っている。チャネルトレンチ電極部３３は、第１主面Ｍ１に垂直な方向（図２では縦方向）に順に形成された分離部１０とボディ領域３０の間のドリフト領域２８（領域２８ａ）に隣合っているともいえる。
【００２０】
図１に示すように、ドリフトトレンチ電極部２３は、ドリフト領域２８に隣合う第２トレンチ２５に沿って形成された第２絶縁膜２４と、第２絶縁膜２４に覆われた状態で第２トレンチ２５内に形成された第２導電層２６を有する。ドリフトトレンチ電極部２３は、ドレイン領域１８とボディ領域３０の間を接続するドリフト領域２８（領域２８ｃ）の全体にわたって隣合っている。ドリフトトレンチ電極部２３は、ドリフト領域２８のうち前記第１方向（図１の横方向）と前記第１主面Ｍ１に垂直な方向（図１の紙面垂直方向）の両方にぼぼ平行な面領域２８ｄに隣合っている。ドリフトトレンチ電極部２３は、前記第１方向（図１の横方向）に順に形成されたドレイン領域１８とボディ領域３０の間のドリフト領域２８（領域２８ｃ、図１参照）に隣合っているともいえる。ドリフトトレンチ電極部２３は、ボディ領域３０にも隣合っている。ドリフトトレンチ電極部２３群は、素子のオフ時にこれらの電極部２３群に隣合うドリフト領域２８からその内部に伸びる空乏層同士がつながるような間隔で配置されていることが好ましい。図３には、図１のIII−III線での断面図、即ち、ドリフトトレンチ電極部２３の断面図が示されている。
【００２１】
図１と図３に示すように、第１絶縁膜３４の厚さは、第２絶縁膜２４の厚さよりも薄い。図３に示すように、本実施形態では、チャネルトレンチ電極部３３と、ドリフトトレンチ電極部２３と、ドレイン領域１８の３つが共に、半導体部１６の第１主面Ｍ１に隣接する部位から第１主面Ｍ１に垂直な方向（図３では縦方向）に、分離部１０（絶縁層１４）に達するまで伸びている。また、本実施形態では、図１と図２に示すように、チャネルトレンチ電極部３３を基準としたときに、ドレイン領域１８、ドリフト領域２８、ボディ領域３０、ソース領域３２が全て同じ側に配置されている。
【００２２】
図２と同じ断面を表す図４の一点鎖線Ａ１〜Ａ４はそれぞれ、不純物濃度が等しい領域（線）を模式的に示したものである。即ち、この一点鎖線Ａ１〜Ａ４はそれぞれ、いわば「等不純物濃度線」といえるものである。Ａ１側からＡ４側に進むにつれて、不純物濃度は低くなっている。本実施形態では、等不純物濃度線Ａ１〜Ａ４に示すように、ドリフト領域２８は、第１主面Ｍ１に平行な方向に不純物濃度の濃度勾配が形成されている。その一方、ドリフト領域２８の第１主面Ｍ１に垂直な方向の不純物濃度はほぼ一定である。ここで、「ほぼ一定」の範囲としては、ドリフト領域２８の第１主面Ｍ１に垂直な方向に伸びる所定領域のうち、半導体部１６の第１主面Ｍ１側と第２主面Ｍ２側の不純物濃度の差（（第１主面Ｍ１側の濃度−第２主面側の濃度）／第１主面Ｍ１側の濃度、の絶対値）が５５％以内であることが好ましい。
【００２３】
この半導体素子の製造方法の一例を説明する。この半導体素子は例えばＳＯＩ（Silicon On Insulater）基板を用いると製造しやすい。
ＳＯＩ基板を用いる場合、ＳＯＩ基板の下層（シリコン基板）が半導体基板１２に対応する。ＳＯＩ基板の中間層（シリコン酸化層）が絶縁層１４に対応する。ＳＯＩ基板の上層（シリコン単結晶層）が半導体部１６に対応する。
ＳＯＩ基板を用いる場合、まずＳＯＩ基板の上層にＲＩＥ（Reactive Ion Etching）等の異方性エッチングによって、図３に示すような第１トレンチ３５を形成する。次に、第１トレンチ３５の壁面を熱酸化法によって酸化する。これにより、シリコン酸化膜からなる第１絶縁膜３４が形成される。このとき、熱酸化法の条件（熱酸化の時間や、雰囲気中の酸素濃度等）を調整することで、所望の厚さの（薄い）第１絶縁膜３４を形成できる。
次に、ＳＯＩ基板の上層にＲＩＥ等の異方性エッチングによって、図３に示すような第２トレンチ２５を形成する。次に、第２トレンチ２５の壁面を熱酸化法等によって酸化する。これにより、シリコン酸化膜からなる第２絶縁膜３４が形成される。このとき、熱酸化法の条件を調整することで、所望の厚さの（厚い）第２絶縁膜２４を形成できる。
【００２４】
このように、本実施形態では、ボディ領域３０ａに隣合う絶縁膜（第１絶縁膜３４）と、ドリフト領域２８に隣合う絶縁膜（第２絶縁膜２４）を形成するためのトレンチを別個（第１トレンチ３５、第２トレンチ２５）に形成する。よって、第１絶縁膜３４と第２絶縁膜２４はそれぞれ別個のトレンチ３３，２５に対して形成できる。このため、第１絶縁膜３４と第２絶縁膜２４を形成する際の熱酸化法の条件は別個に独立して設定できるので、第１絶縁膜３４と第２絶縁膜２４の厚さを容易に異ならせることができる。
第１絶縁膜３４の厚さを薄くすれば、素子をオンさせるためにチャネルトレンチ電極部３３に印加する電圧を低く設定できる。一方、第２絶縁膜２４の厚さを厚くすれば、絶縁破壊を生じにくくすることができ、高耐圧化を実現できる。第１絶縁膜３４と第２絶縁膜２４の厚さを別個独立に設定することが容易であるため、素子特性の適正化が行いやすい。
【００２５】
次に、第１トレンチ３５と第２トレンチ２５内にそれぞれ、第１導電層３６と第２導電層２６となる材料（例えば多結晶シリコン、金属等の導電性材料）を充填する。次に、ＳＯＩ基板の上層にＲＩＥ等の異方性エッチングによって、図２に示すような第３トレンチ１９を形成する。次に、第３トレンチ１９を形成することで露出したドリフト領域２８が形成される領域の側面から、ドリフト領域２８が形成される領域に向けて、ｎ型不純物をイオン注入（斜めイオン注入）する。このようにイオン注入を行うと、ドリフト領域２８に、図４の等不純物濃度線Ａ１〜Ａ４に示すように、第１主面Ｍ１に平行な方向には不純物濃度の濃度勾配を形成できる一方、第１主面Ｍ１に垂直な方向の不純物濃度はほぼ一定にできる。この場合、図５に示すように、第３トレンチ１９の開孔幅をＷ、深さをＤとすると、イオン注入角（イオンの入射線と垂線が成す角度）θは、次式のように設定することが好ましい。
θ≦ｔａｎ^−１（Ｗ／Ｄ）
例えば、開孔幅Ｗが１μｍ、深さＤが１０μｍの場合は、イオン注入角θが５．７度以下の角度でイオン注入を行うことが好ましい。
【００２６】
次に、第３トレンチ１９内に、ドレイン領域１８となるｎ型不純物が高濃度にドープされた半導体材料（単結晶・多結晶シリコン等）を充填する。次に、ＳＯＩ基板の上層の表面から、ボディ領域３０を形成したい領域に向けて、ｐ型不純物をイオン注入する。次に、ＳＯＩ基板の上層の表面から、ソース領域３２を形成したい領域に向けて、ｎ型不純物をイオン注入する。次に、ドレイン領域１８上にドレイン電極２０を形成し、ソース領域３２とボディ領域３０上にソース電極３１を形成する。次に、イオン注入した不純物の活性化や電極のコンタクト性の向上を目的とする処理（熱処理等）を行う。
以上の工程によって、本実施形態の半導体素子を製造できる。
【００２７】
本実施形態の半導体素子の製造方法は上記方法に限らないのは勿論である。例えば、上記した製造工程の順序は様々に変更してもよい。
例えば、上記方法では、第１トレンチ３５の形成、第１絶縁膜３４の形成、第２トレンチ２５の形成、第２絶縁膜２４の形成というように、トレンチと絶縁膜の形成を交互に行ったが、第１及び第２トレンチ３５，２５を先に形成してもよい。この場合、最初に第１及び第２トレンチ３５，２５の壁面に熱酸化法で第１絶縁膜３４の厚さ分だけ酸化膜を形成し、次に、第１トレンチ３５の壁面が酸化されないような対策（例えばマスク）を施しながら、第２トレンチ２５の壁面をさらに熱酸化法で酸化するとよい。この方法によると、薄い第１絶縁膜３４と厚い第２絶縁膜２４を効率良く形成できる。なお、第１トレンチ３５の壁面が酸化されないようにマスクをする場合、このマスクはＳＯＩ基板の上層の頂面上に第１トレンチ３５をふさぐように配置すれば、配置及び除去の手間が少なくて済む。また、第１トレンチ３５内にマスクを配置する場合でも、本実施形態の場合は、第１トレンチ３５の壁面全体にマスクを配置すればよいので、深くて狭いトレンチの壁面に部分的にマスクを配置する場合に比べれば、簡便で容易な製造技術で対応できる。
【００２８】
第１絶縁膜３４と第２絶縁膜２４をＣＶＤ法等で形成する場合においても、第１絶縁膜３４と第２絶縁膜２４を形成する際のＣＶＤ法等の条件は別個に独立して設定できるので、第１絶縁膜３４と第２絶縁膜２４の厚さを容易に異ならせることができる。第１絶縁膜３４と第２絶縁膜２４はシリコン窒化膜等で形成してもよいのは勿論である。
【００２９】
ドリフト領域２８に、第１主面Ｍ１に平行な方向には不純物濃度の濃度勾配を形成する一方、第１主面Ｍ１に垂直な方向の不純物濃度はほぼ一定にする方法としては、上記した斜めイオン注入法に代えて、第３トレンチ１９に高濃度のｎ型不純物（リン等）が添加された半導体材料を埋め込み、その後、熱処理を行うことで、そのｎ型不純物を熱拡散によって第１主面Ｍ１に平行な方向にドリフト領域２８側に向けて拡散させる方法等を採用してもよい。
【００３０】
また、上記方法では、ドレイン領域１８を形成するために第３トレンチ１９を形成し、その後、その第３トレンチ１９内にｎ型不純物が高濃度にドープされた半導体材料を充填している。しかし、第３トレンチ１９を形成せずに、ＳＯＩ基板の上層の表面から、ｎ型不純物をドープすることでｎ^＋型のドレイン領域１８を形成してもよい。
【００３１】
次に、本実施形態の半導体素子の動作を説明する。まず、図２に示すソース領域３２に接続されたソース電極３１を接地する。この状態で、ドレイン領域１８に接続されたドレイン電極２０とチャネルトレンチ電極部３３（第１導電層３６）に所定の正電圧を印加して、半導体素子をオンさせる。また、図１や図３に示すドリフトトレンチ電極部２３（第２導電層２６）にも所定の正電圧を印加する。すると、図２に示すボディ領域３０のうち、チャネルトレンチ電極部３３に隣合う領域３０ａにｎ型チャネルが形成される。また、ドリフト領域２８のうち、チャネルトレンチ電極部３３に隣合う領域２８ａに電子の蓄積領域が形成される。さらに、ドリフト領域２８のうち、ドリフトトレンチ電極部２３に隣合う領域２８ｃ（図１参照）に電子の蓄積領域が形成される。すると、電子がソース領域３２から、ｎ型チャネル３０ａ，電子の蓄積領域２８ａ，２８ｃを通って、ドレイン領域１８に流れ込む。電流の向きは電子の向きと逆であり、図２の矢印に示すような向きである。このように、電流は、ドレイン領域１８、ドリフト領域２８、ボディ領域３０、ソース領域３２の順に流れる。
【００３２】
本実施形態では、上記のように、ドリフトトレンチ電極部２３によってドリフト領域２８に電子の蓄積領域２８ｃが形成される。しかも、本実施形態では、ドリフトトレンチ電極部２３は、ドレイン領域１８とボディ領域３０の間を接続するドリフト領域２８ｃ（図１参照）の全体にわたって第２絶縁膜２４を介して隣合っている。よって、このようなドリフトトレンチ電極部２３がない場合に比べてドリフト領域２８におけるオン抵抗を大幅に低減できる。
【００３３】
また、本実施形態では、図３に示すように、チャネルトレンチ電極部３３と、ドリフトトレンチ電極部２３と、ドレイン領域１８の３つが共に、半導体部１６の第１主面Ｍ１に隣接する部位から第１主面Ｍ１に垂直な方向（図３では縦方向）に、分離部１０（絶縁層１４）に達するまで伸びている。この構成によると、ドリフト領域２８の深い領域まで電流が流れる領域を広げることができる。よって、オン抵抗を低減できる。チャネルトレンチ電極部３３とドレイン領域１８の両方が分離部１０に達しているとより大幅にオン抵抗を低減できるが、チャネルトレンチ電極部３３とドレイン領域１８のいずれか一方が分離部１０に達していればオン抵抗を効果的に低減できる。
【００３４】
また、チャネルトレンチ電極部３３とドリフトトレンチ電極部２３が第１主面Ｍ１に垂直な方向に分離部１０に達するまで伸びていると、逆バイアス電圧が印加されたときに、これらの電極部３３，２３の下端（特に下端のコーナー部）に電界が集中することを回避できる。よって、絶縁破壊を生じにくくすることができる。このため、高耐圧化を実現できる。これらの電極部３３，２３の両方が分離部１０に達しているとより充分に高耐圧化を実現できるが、これらの電極部３３，２３のいずれか一方が分離部１０に達していれば高耐圧化を効果的に実現できる。
【００３５】
また、本実施形態によると、逆バイアス電圧が印加されたときに、ドリフト領域２８とボディ領域３０の間のｐｎ接合部からドリフト領域２８側に空乏層が伸びるだけでなく、ドリフト領域２８とドリフトトレンチ電極部２３の接触部からもドリフト領域２８側に空乏層を伸ばすことができる。よって、高耐圧化を実現できる。さらに、ドリフトトレンチ電極部２３群が、素子のオフ時にこれらの電極部２３群に隣合うドリフト領域２８からその内部に伸びる空乏層同士がつながるような間隔で配置されていると、より高耐圧化を実現できる。
【００３６】
このような半導体素子では、最大の耐圧を得るために、ドリフト領域２８において最適な不純物濃度の濃度勾配が存在する。例えば図６に示すように等不純物濃度線Ｂ１〜Ｂ４が分布している場合、第１主面Ｍ１に平行な方向のみならず、垂直な方向にも不純物濃度の濃度勾配が形成されていることになる。このように、第１主面Ｍ１に垂直な方向にも不純物濃度の濃度勾配が形成されていると、半導体部１６の第１主面Ｍ１側（表面側）では最適な不純物濃度であっても、半導体部１６の第２主面Ｍ２側（裏面側）では、最適な不純物濃度から大きくずれてしまう。この問題は、半導体部１６の厚さを厚くする程、その第１主面Ｍ１側と第２主面Ｍ２側で不純物濃度のずれが大きくなることから、大きな問題となり、高耐圧化を妨げる要因となる。その一方、本実施形態の構造を採用した場合は、半導体部１６の厚さを厚くする程、より電流を広く分布させることができ、オン抵抗を低減できる。このため、半導体部１６の厚さを厚くしたいという要請がある。
【００３７】
これに対し、本実施形態では、図４の等不純物濃度線Ａ１〜Ａ４に示すように、ドリフト領域２８は、第１主面Ｍ１に平行な方向に不純物濃度の濃度勾配が形成されている一方、ドリフト領域２８の第１主面Ｍ１に垂直な方向の不純物濃度はほぼ一定である。よって、本実施形態によると、半導体部１６の第１主面Ｍ１側（表面側）から第２主面側Ｍ２にわたって最適な不純物濃度をほぼ維持できる。このため、半導体部１６の厚さを厚くしても高耐圧化が妨げられず、低オン抵抗で高耐圧な素子を実現できる。但し、図６のように不純物濃度が分布している構造も、本発明に適用範囲に含まれる。
【００３８】
本発明者らは、上記した本実施形態の半導体素子の中でも、さらに以下のような構成の半導体素子を製作し、そのオン抵抗と耐圧を測定した。
第１絶縁膜３４を熱酸化膜で構成し、厚さを約５０ｎｍとした。第２絶縁膜２４を熱酸化膜で構成し、厚さを約５００ｎｍとした。この第２絶縁膜２４の厚さは、ドレイン領域１８とチャネルトレンチ電極部３３間に約８０Ｖ程度の電圧が印加されることを想定して設定した。第１導電層３６と、第２導電層２６と、ドレイン領域１８を、不純物濃度が約１×２０ｃｍ^−３程度のリンをドープしたｎ^＋多結晶シリコンによって形成した。半導体部１６の厚さ（ＳＯＩ基板の上層の厚さ）は約７μｍとした。隣合うドリフトトレンチ電極部２３間の間隔は約１μｍとした。ドリフト領域２８にイオン注入する不純物としてリンを用い、濃度勾配はドリフト領域２８のうちドレイン領域１８に隣接する側では約６×１０^１６ｃｍ^−３となり、チャネルトレンチ領域３６に隣接する側では約１×１０^１６ｃｍ^−３となるようにした。
【００３９】
この半導体素子の耐圧を測定した結果、図７に示すように耐圧が９０Ｖという結果が得られた。また、オン抵抗を測定した結果、図８に示すようにオン抵抗が５８ｍΩ・ｍｍ^２という結果が得られた。これは、パワーＩＣに用いられる横型パワーＭＯＳＦＥＴとしては、非常に高い性能を示す。
【００４０】
（第２実施形態）図９は、本発明の第２実施形態の半導体素子（横型半導体素子、より詳細には横型パワーＭＯＳＦＥＴ）の平面図を示す。図１０は、図９のVII−VII線断面図を示す。図１１は、図９のVIII−VIII線断面図を示す。図１２は、図９のIX−IX線断面図を示す。第１実施形態と概ね同様の構成と作用効果については、本実施形態の説明に必要な内容を除いて原則として説明を省略する。
第２実施形態も第１実施形態と同様に、ドレイン領域４８、ドリフト領域５８、ボディ領域６０、ソース領域６２は、図９と図１０に示すように、半導体部４６の第１主面（表面）Ｍ１に平行な方向のうち第１方向（図９と図１０では横方向）に順に形成された領域を含む。
【００４１】
図９の平面図でみると、チャネルトレンチ電極部６３は、前記第１方向（図９の横方向）に伸びている。チャネルトレンチ電極部６３は、第１主面Ｍ１に平行な方向のうち、前記第１方向に直交する第２方向（図９の縦方向）にストライプ状に複数本形成されている。同様に、ドリフトトレンチ電極部５３は、前記第１方向に伸びており、前記第２方向にストライプ状に複数本形成されている。このように、本実施形態では、平面視すると、チャネルトレンチ電極部６３とドリフトトレンチ電極部５３の伸びる方向は平行である。
【００４２】
図９に示すように、チャネルトレンチ電極部６３は、ドリフト領域５８とソース領域６２の間のボディ領域６０のうち前記第１方向（図９の横方向）と第１主面Ｍ１に垂直な方向（図９の紙面垂直方向）の両方にぼぼ平行な面領域６０ｂに隣合っている（図１０参照）。
この構成によると、チャネルトレンチ電極部６３に所定電圧を印加することで、ドレイン領域４８、ドリフト領域５８、ボディ領域６０、ソース領域６２が順に形成された前記第１方向にほぼ平行な面領域６０ｂに沿ってチャネルを形成できる。よって、キャリア経路の面積の増加やキャリア経路の短縮化を実現しやすいので、オン抵抗の低減を実現しやすい。
【００４３】
例えば、上記第２実施形態の構成によると、第１実施形態の構造（図２参照）に比して、図１１に示すようにボディ領域６０がキャリアの流れの妨げとならない。即ち、第１実施形態（図２参照）のようにキャリア経路（電流経路）がボディ領域３０を迂回するような経路とならない。よって、オン抵抗の低減を実現しやすい。半導体部４６の厚さを薄くした場合でも、耐圧確保のためボディ領域６０の深さを浅くすることは困難である。第１実施形態の構成（図２参照）の場合、半導体部１６の厚さを薄くした場合は、ボディ領域３０と分離部１０の間の距離が小さくなる。この結果、キャリア経路の面積が小さくなり、オン抵抗の増加の要因となり得る。これに対し、第２実施形態の構成では、ボディ領域６０がキャリアの流れの妨げとならない。よって、上記した作用効果は、半導体部４６の厚さが薄い場合に特に顕著に発揮される。
【００４４】
チャネルトレンチ電極部６３は、図９や図１１に示すように、前記第１方向（図９や図１１の横方向）に順に形成されたドリフト領域５０とソース領域６２の間のボディ領域６０ａに隣合った領域を有する。チャネルトレンチ電極部６３はまた、ドリフト領域５８とソース領域６２にも隣合っている。
【００４５】
図９に示すように、ドリフトトレンチ電極部５３は、第１実施形態と同様に、ドリフト領域５８のうち前記第１方向（図９の横方向）と前記第１主面Ｍ１に垂直な方向（図９の紙面垂直方向）の両方にぼぼ平行な面領域５８ｄに隣合っている。さらに、ドリフトトレンチ電極部５６は、ドリフト領域５８とソース領域６２の間のボディ領域６０ａと、ソース領域６２にも隣合っている。
【００４６】
チャネルトレンチ電極部６３とドリフトトレンチ電極部５３は、前記第２方向（図９の縦方向）からみたときにドリフト領域５８とボディ領域６０を挟んで重複している。但し、両電極部６３，５３が重複しておらず、隣接している構成であってもよい。
このような構成を実現するためには、図１０〜図１２に示すように、ボディ領域６０の底部が、分離部４０（絶縁層４４）に達していることが好ましい。先に述べた本実施形態の構成によると、このようにボディ領域６０を深い方向まで伸ばしても、ボディ領域６０がキャリア経路の妨げとならず、低オン抵抗を実現し得る。
【００４７】
この構成によると、素子のオン時には、チャネルトレンチ電極部６３により形成されるチャネルとドリフトトレンチ電極部５３により形成されるキャリア蓄積領域が近接した位置に配置される。特に、両電極部６３，５３がドリフト領域５８とボディ領域６０と挟んで重複している場合は、チャネルトレンチ電極部６３は、ボディ領域６０のみならずドリフト領域５８にも隣合っているので、キャリア蓄積領域の形成の補助的役割も果たす。一方、ドリフトトレンチ電極部５３は、ドリフト領域５８のみならずボディ領域６０にも隣合っているので、チャネルの形成の補助的役割も果たす。従って、オン抵抗を大幅に低減できる。
また、両電極部６３，５３がドリフト領域５８を挟んで重複している場合は、素子のオフ時には、両電極部６３，５３から、ドリフト領域５８に空乏層を効果的に伸ばすことができ、高耐圧化を実現できる。さらに両電極部６３，５３がｎ⁻型ドリフト領域５８とｐ型ボディ領域６０のｐｎ接合部を挟んで重複している場合は、空乏層をより効果的に伸ばすことができ、より高耐圧化を実現できる。
【００４８】
また、図９に示す第２トレンチ５５（ドリフトトレンチ電極部５３）は、第１トレンチ６５（チャネルトレンチ電極部６３）がドリフト領域５８に延在する（張り出している）ことで発生する耐圧低下を抑制する働きをする。
即ち、第２トレンチ５５が存在しない場合は、ドリフト領域５８に延在する第１トレンチ６６のコーナー部に電界集中が生じ耐圧が低下する。しかし、第２トレンチ５５を設けることで、ドリフト領域５８に延在する第１トレンチ６６のコーナー部での電界集中を緩和できる。よって、耐圧の低下を抑制できる。
また、本実施形態では、図９と図１１に示すように、チャネルトレンチ電極部６３を基準としたときに、ボディ領域６０の一部とソース領域６２の一部が、ドレイン領域４８及びドリフト領域５８と反対側に配置されている。言い換えると、ソース領域６２は、チャネルトレンチ電極部６６を挟んで、ドリフト領域５８と反対側に位置する領域６２ａを有する。
ソース領域６２がチャネルトレンチ電極部６３とドリフト領域５８の間にしか存在しない構造（例えば第１実施形態の構造（図１や図２参照））の場合、チャネルトレンチ電極部６３とドリフト領域５８の間のソース領域６２上に配線層（ソース電極）を形成する必要がある。よって、チャネルトレンチ電極部６３とドリフト領域５８の間のスペースを大きくしなければならない。これは、素子サイズの増加を招き、オン抵抗の増加をも招く。
これに対し、上記のように、ソース領域６２が、チャネルトレンチ電極部６３を挟んで、ドリフト領域５８と反対側に位置する領域６２ａを有する場合、その領域６２ａ上に配線層（ソース電極６１）を形成して、ソース領域６２とのコンタクトを取ることができる。よって、チャネルトレンチ電極部６３とドリフト領域５８の間のスペースを大きくする必要がない。
【００４９】
以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
（１）分離部１０は絶縁層１４のみによって形成されていてもよい。また、分離部１０は半導体基板１２のみによって形成されていてもよい。半導体基板１２のみで構成する場合、半導体部１６（本実施形態ではｎ型のドレイン領域１８とドリフト領域２８）との間がｐｎ接合分離されるような導電型の不純物（本実施形態ではｐ型不純物）が半導体基板１２に添加されていることが原則的には必要である。
（２）第１〜第４半導体領域（第１実施形態ではドレイン領域１８、ドリフト領域２８、ボディ領域３０、ソース領域３２）は、その順序又はその逆の順序で電流が流れるように構成されていれば、これらの半導体領域の間に他の領域が介在していてもよい。
（３）上記半導体素子では、ｎ型とｐ型を入れ換えてもよいのは勿論である。
（４）上記実施形態では半導体素子としてＭＯＳＦＥＴを例にして説明したが、本発明はＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）や絶縁ゲートサイリスタ等にも適用し得る。例えば図１〜図３に示す半導体素子の第１半導体領域１８、あるいは図９〜図１２に示す半導体素子の第１半導体領域４８の導電型をｐ型（ｐ^＋型）とした場合、これらの半導体素子はＩＧＢＴとして機能する。本発明は、このようなＩＧＢＴにも適用できる。
【００５０】
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
【図面の簡単な説明】
【図１】本発明の第１実施形態の半導体素子の平面図を示す。
【図２】図１のII−II線断面図を示す。
【図３】図１のIII−III線断面図を示す。
【図４】本発明の第１実施形態の半導体素子におけるドリフト領域の不純物濃度分布を示す。
【図５】イオン注入角の説明図を示す。
【図６】ドリフト領域の不純物濃度分布の説明図を示す。
【図７】本発明の実施例として製作した半導体素子の耐圧特性を示す。
【図８】本発明の実施例として製作した半導体素子のオン抵抗特性を示す。
【図９】本発明の第２実施形態の半導体素子の平面図を示す。
【図１０】図９のVII−VII線断面図を示す。
【図１１】図９のVIII−VIII線断面図を示す。
【図１２】図９のIX−IX線断面図を示す。
【符号の説明】
１０，４０：分離部
１２，４２：半導体基板
１４，４４：絶縁層
１６，４６：半導体部
１８，４８：第１半導体領域（ドレイン領域）
１９，４９：第３トレンチ
２３，５３：第２電極部（ドリフトトレンチ電極部）
２４，５４：第２絶縁膜
２５，５５：第２トレンチ
２６，５６：第２導電層
２８，５８：第２半導体領域（ドリフト領域）
３０，６０：第３半導体領域（ボディ領域）
３２，６２：第４半導体領域（ソース領域）
３３，６３：第１電極部（チャネルトレンチ電極部）
３４，６４：第１絶縁膜
３５，６５：第１トレンチ
３６，６６：第１導電層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element.
[0002]
[Prior art]
The lateral MOSFET described in Patent Document 1 includes a semiconductor portion and an electrode portion. The semiconductor portion has a drain region, a drift region, a body region, and a source region. The electrode portion includes an insulating film formed along the trench and a conductive layer formed in the trench while being covered with the insulating film. The electrode part (trench) is adjacent to both the body region between the drift region and the source region and the drift region between the drain region and the body region. This semiconductor element is intended to realize an element having a low on-resistance and a high breakdown voltage by including the electrode portion. Hereinafter, the electrode part is referred to as a “trench electrode part” for convenience.
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-103058 (FIG. 2)
[0004]
[Problems to be solved by the invention]
In the lateral MOSFET described in Patent Document 1, the insulating film is integrally formed along the wall surface of one trench, and the thickness is substantially constant. However, the insulating film adjacent to the body region between the drift region and the source region (hereinafter referred to as “the former insulating film”) and the insulating film adjacent to the drift region between the drain region and the body region (hereinafter referred to as “the latter”). It is inherently desirable that the thickness of the insulating film is different. Specifically, it is desirable to form the former insulating film thin and the latter insulating film thick. This is because, when the former insulating film is formed thick, it is necessary to set a high voltage to be applied to the trench electrode portion in order to turn on the lateral MOSFET. Moreover, if the latter insulating film is formed thin, dielectric breakdown is likely to occur, and the withstand voltage is greatly reduced. Therefore, if the thicknesses of the former insulating film and the latter insulating film are the same, it is difficult to optimize the element characteristics.
[0005]
In the lateral MOSFET described in Patent Document 1, the former insulating film and the latter insulating film are integrally formed along the wall surface of one trench as described above. However, in order to partially change the thickness of the insulating film formed integrally along the wall surface of one trench, it is necessary to go through complicated or advanced manufacturing processes. Usually, it is necessary to go through a process of partially forming or removing a mask on the wall surface (side surface or bottom surface) of a deep and narrow trench. As described above, the lateral MOSFET described in Patent Document 1 has a structure in which it is difficult to make the thickness of the former insulating film different from the thickness of the latter insulating film, and it is difficult to optimize the element characteristics. Yes.
[0006]
It is an object of the present invention to realize a semiconductor element that has a structure that facilitates optimization of element characteristics and that has a low on-resistance and a high breakdown voltage.
[0007]
[Means for solving the problem, operation and effect]
[1] A semiconductor element according to the present invention includes a semiconductor portion;Channel trenchAn electrode part;Drift trenchAn electrode part is provided. The semiconductor portion has a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first to fourth semiconductor regions are arranged such that current flows in the order or in the reverse order. The first semiconductor region and the fourth semiconductor region include a region adjacent to the first main surface of the semiconductor part. The second semiconductor region and the fourth semiconductor region are of the first conductivity type. The third semiconductor region is the second conductivity type.
  Channel trenchThe electrode portion includes a first insulating film formed along the first trench adjacent to the third semiconductor region between the second semiconductor region and the fourth semiconductor region, and the first insulating film covered with the first insulating film. A first conductive layer is formed in the trench.Drift trenchThe electrode part is adjacent to the second semiconductor regionAnd separated from the fourth semiconductor region by the third semiconductor region.A second insulating film formed along the second trench; and a second conductive layer formed in the second trench while being covered with the second insulating film.. The thickness of the first insulating film in the channel trench electrode portion is thinner than the thickness of the second insulating film in the drift trench electrode portion..
[0008]
[2] Another semiconductor element according to the present invention includes a semiconductor portion,Channel trenchAn electrode part;Drift trenchAn electrode part is provided. The semiconductor portion includes a first semiconductor region, a second semiconductor region in contact with the first semiconductor region, a third semiconductor region in contact with the first semiconductor region, and a fourth semiconductor region in contact with the third semiconductor region. The first semiconductor region and the fourth semiconductor region include a region adjacent to the first main surface of the semiconductor part. The second semiconductor region and the fourth semiconductor region are of the first conductivity type. The third semiconductor region is the second conductivity type.
  Channel trenchThe electrode portion includes a first insulating film formed along the first trench adjacent to the third semiconductor region between the second semiconductor region and the fourth semiconductor region, and the first insulating film covered with the first insulating film. A first conductive layer is formed in the trench.Drift trenchThe electrode part is adjacent to the second semiconductor regionAnd separated from the fourth semiconductor region by the third semiconductor region.A second insulating film formed along the second trench and a second conductive layer formed in the second trench in a state of being covered with the second insulating film.The thickness of the first insulating film in the channel trench electrode portion is thinner than the thickness of the second insulating film in the drift trench electrode portion..
[0009]
  In these semiconductor elements, a first insulating film is formed along a first trench adjacent to a third semiconductor region between the second semiconductor region and the fourth semiconductor region. A second insulating film is formed along a second trench separate from the first trench adjacent to the second semiconductor region. As described above, in these semiconductor elements, the insulating film (first insulating film) adjacent to the third semiconductor region and the insulating film (second insulating film) adjacent to the second semiconductor region are separately formed. Therefore, these insulating films can be formed separately at the time of manufacture. For this reason, the thickness of these insulating films can be varied without complicated or sophisticated manufacturing steps. Therefore, in order to turn on the element by thinning the first insulating filmChannel trenchThe voltage applied to the electrode part can be easily set low. On the other hand, by increasing the thickness of the second insulating film to make it difficult for dielectric breakdown to occur, it is possible to easily achieve a high breakdown voltage. Thus, according to the structure of these semiconductor elements, it is easy to optimize the element characteristics.
[0010]
  In addition, when these semiconductor elements are turned on,Channel trenchBy applying a predetermined voltage to the electrode part,Channel trenchA channel can be formed in the third semiconductor region adjacent to the electrode portion. In addition to this,Drift trenchBy applying a predetermined voltage to the electrode part,Drift trenchA carrier accumulation region can be formed in the second semiconductor region adjacent to the electrode portion. Therefore,Drift trenchThe on-resistance in the second semiconductor region can be reduced compared to the case where there is no electrode portion.
  Also, these semiconductor elements extend a depletion layer from the junction between the second semiconductor region and the third semiconductor region when a reverse bias voltage is applied to the junction between the second semiconductor region and the third semiconductor region. not only,Drift trenchThe depletion layer can also be extended from the second semiconductor region adjacent to the electrode portion. Therefore, high breakdown voltage can be realized.
  As described above, according to the present invention, it is possible to realize a semiconductor element having a structure that facilitates optimization of element characteristics and a low on-resistance and a high breakdown voltage.
[0011]
[4) further comprising a separation part adjacent to the second principal surface located on the opposite side of the first principal surface of the semiconductor part;Channel trenchAn electrode part;Drift trenchPreferably, at least one of the electrode portion and the first semiconductor region extends in a direction perpendicular to the first main surface until reaching the separation portion.Yes.
[5]Drift trenchIt is preferable that the electrode portions are adjacent to each other over the entire region connecting the first semiconductor region and the third semiconductor region in the second semiconductor region.Yes.
[6]Drift trenchHave multiple electrode parts, theseDrift trenchThe electrode unit group isDrift trenchIt is preferable that the depletion layers extending from the second semiconductor region adjacent to the electrode portion group to each other are arranged at intervals.
[0012]
[7] In the second semiconductor region, a concentration gradient of impurity concentration is formed in a direction parallel to the first main surface, while an impurity concentration in a direction perpendicular to the first main surface is substantially constant. LikeYes.
[8] The method for manufacturing a semiconductor device according to [7] includes sequentially performing a step of implanting ions from a side surface of a region to be the second semiconductor region toward the inside of the region and a step of performing a heat treatment. Is preferred.
[9] Further, in the method of manufacturing a semiconductor device according to [7], the first conductive layer is formed in a trench that is adjacent to a region to be the second semiconductor region and has the same position at the bottom and bottom of the second semiconductor region. It is preferable to sequentially perform a step of forming a semiconductor material to which a mold impurity is added and a step of performing a heat treatment.
[0013]
[10] The first to fourth semiconductor regions include regions formed in order in a first direction parallel to the first main surface,Channel trenchThe electrode portion is preferably adjacent to a surface region that is substantially perpendicular to the first direction in the third semiconductor region between the second semiconductor region and the fourth semiconductor region.
[11] The second to fourth semiconductor regions include regions formed in order in a direction perpendicular to the first main surface,Channel trenchThe electrode part is preferably adjacent to a third semiconductor region between the second semiconductor region and the fourth semiconductor region, which are sequentially formed in a direction perpendicular to the first main surface.
[12] The first to fourth semiconductor regions include regions formed in order in a first direction parallel to the first main surface,Channel trenchPreferably, the electrode portion is adjacent to a surface region substantially parallel to both the first direction and the direction perpendicular to the first main surface in the third semiconductor region between the second semiconductor region and the fourth semiconductor region. BetterYes.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
First Embodiment FIG. 1 is a plan view of a semiconductor device (horizontal semiconductor device, more specifically a lateral power MOSFET) according to a first embodiment of the present invention. 2 shows a cross-sectional view taken along line II-II in FIG. 3 shows a cross-sectional view taken along line III-III in FIG.
As shown in FIG. 2, the semiconductor element includes a separation part 10, a semiconductor part 16, a first electrode part (hereinafter referred to as “channel trench electrode part”) 33, and a second electrode part (FIGS. 1 and 3). (Hereinafter referred to as “drift trench electrode portion”) 23.
[0016]
As shown in FIG. 2, the separation unit 10 includes a semiconductor substrate (silicon substrate in this embodiment) 12 and an insulating layer (silicon oxide layer in this embodiment) 14. The separation unit 10 is for insulating and separating the semiconductor unit 16.
The semiconductor part (silicon part in this embodiment) 16 is formed on the separation part 10. It can be said that the separation unit 10 is adjacent to the second main surface (back surface) M2 located on the opposite side of the first main surface (front surface) M1 of the semiconductor unit 16. The semiconductor portion 16 includes a first semiconductor region (hereinafter referred to as “drain region”) 18, a second semiconductor region (hereinafter referred to as “drift region”) 28, and a third semiconductor region (hereinafter referred to as “body region”). 30 and a fourth semiconductor region (hereinafter referred to as “source region”) 32, which are arranged so that current flows in that order. In the present embodiment, the drain region 18 and the drift region 28, the drift region 28 and the body region 30, and the body region 30 and the source region 32 are in contact with each other. In addition, the drain region 18, the drift region 28, the body region 30, and the source region 32 are in the first direction (lateral direction in FIGS. 1 and 2) in the direction parallel to the first main surface (surface) M 1 of the semiconductor portion 16. Includes regions formed in order. The drift region 28, the body region 30, and the source region 32 include regions formed in order in a direction perpendicular to the first major surface M1 (also referred to as an element depth direction, which is the longitudinal direction in FIG. 2).
[0017]
The drain region 18 and the source region 32 include a region adjacent to the first major surface M1 of the semiconductor unit 16. The drain electrode 20 and the source electrode 31 are in contact with portions of the drain region 18 and the source region 32 that are exposed at the first main surface M1. The source electrode 31 is formed of the p-type body region 30 (more specifically, p-type body region 30).⁺It is also in contact with the mold body contact area). The drain region 18 is n⁺The drift region 28 is n⁻The source region 32 is n⁺It is a type. Body region 30 is p-type.
In the plan view of FIG. 1, illustration of the drain electrode 20 and the source electrode 31 is omitted for convenience of explanation.
[0018]
Referring to the plan view of FIG. 1, the channel trench electrode portion 33 has a second direction orthogonal to the first direction (lateral direction of FIG. 1) among the directions parallel to the first major surface M <b> 1 (see FIG. 2). It extends in the (vertical direction of FIG. 1). On the other hand, the drift trench electrode portion 23 extends in the first direction (lateral direction in FIG. 1). A plurality of drift trench electrode portions 23 are formed in stripes in the second direction (vertical direction in FIG. 1). Thus, in the present embodiment, when viewed in plan, the extending directions of the channel trench electrode part 33 and the drift trench electrode part 23 are orthogonal to each other.
[0019]
As shown in FIG. 2, the channel trench electrode portion 33 includes a first insulating film 34 formed along the first trench 35 adjacent to the body region 30 (region 30 a) between the drift region 28 and the source region 32. The first conductive layer 36 is formed in the first trench 35 while being covered with the first insulating film 34. The channel trench electrode portion 33 includes a first insulating film 34 in a surface region 30b substantially perpendicular to the first direction (lateral direction in FIG. 2) in the body region 30 (region 30a) between the drift region 28 and the source region 32. Are next to each other. The channel trench electrode portion 33 is adjacent to the body region 30 (region 30a) between the drift region 28 and the source region 32 formed in order in a direction perpendicular to the first main surface M1 (vertical direction in FIG. 2). It can be said. The channel trench electrode portion 33 is adjacent to the surface region 28b which is substantially perpendicular to the first direction (lateral direction in FIG. 2) in the drift region 28 (region 28a) between the isolation portion 10 and the body region 30. Channel trench electrode portion 33 is adjacent to drift region 28 (region 28a) between isolation region 10 and body region 30 formed in this order in the direction perpendicular to first main surface M1 (the vertical direction in FIG. 2). It can be said.
[0020]
As shown in FIG. 1, the drift trench electrode portion 23 includes a second insulating film 24 formed along the second trench 25 adjacent to the drift region 28, and a second insulating film 24 covered with the second insulating film 24. A second conductive layer 26 is formed in the trench 25. The drift trench electrode portion 23 is adjacent to the entire drift region 28 (region 28 c) connecting the drain region 18 and the body region 30. The drift trench electrode portion 23 is a surface region substantially parallel to both the first direction (lateral direction in FIG. 1) and the direction perpendicular to the first main surface M1 (perpendicular direction in FIG. 1) in the drift region 28. Next to 28d. The drift trench electrode portion 23 is adjacent to a drift region 28 (region 28c, see FIG. 1) between the drain region 18 and the body region 30 formed in order in the first direction (lateral direction in FIG. 1). I can say that. The drift trench electrode portion 23 is also adjacent to the body region 30. It is preferable that the drift trench electrode portion 23 group is arranged at an interval such that depletion layers extending from the drift region 28 adjacent to the electrode portion 23 group to each other are connected when the element is turned off. FIG. 3 shows a cross-sectional view taken along line III-III in FIG. 1, that is, a cross-sectional view of the drift trench electrode portion 23.
[0021]
As shown in FIGS. 1 and 3, the first insulating film 34 is thinner than the second insulating film 24. As shown in FIG. 3, in this embodiment, the channel trench electrode part 33, the drift trench electrode part 23, and the drain region 18 are all first to the first part from the part adjacent to the first main surface M <b> 1 of the semiconductor part 16. It extends in a direction perpendicular to the main surface M1 (longitudinal direction in FIG. 3) until it reaches the separation part 10 (insulating layer 14). In the present embodiment, as shown in FIGS. 1 and 2, when the channel trench electrode portion 33 is used as a reference, the drain region 18, the drift region 28, the body region 30, and the source region 32 are all arranged on the same side. Has been.
[0022]
Dotted lines A1 to A4 in FIG. 4 representing the same cross section as in FIG. 2 schematically show regions (lines) having the same impurity concentration. That is, each of the alternate long and short dash lines A1 to A4 can be said to be an “iso-impurity concentration line”. As the process proceeds from the A1 side to the A4 side, the impurity concentration decreases. In the present embodiment, as indicated by the isoimpurity concentration lines A1 to A4, the drift region 28 has a concentration gradient of impurity concentration in a direction parallel to the first main surface M1. On the other hand, the impurity concentration in the direction perpendicular to the first main surface M1 of the drift region 28 is substantially constant. Here, the “substantially constant” range is a predetermined region extending in a direction perpendicular to the first main surface M1 of the drift region 28, on the first main surface M1 side and the second main surface M2 side of the semiconductor portion 16. The difference in impurity concentration (the absolute value of (concentration on the first main surface M1 side−concentration on the second main surface side) / concentration on the first main surface M1 side) is preferably within 55%.
[0023]
An example of a method for manufacturing this semiconductor element will be described. This semiconductor element is easy to manufacture if, for example, an SOI (Silicon On Insulater) substrate is used.
When an SOI substrate is used, the lower layer (silicon substrate) of the SOI substrate corresponds to the semiconductor substrate 12. An intermediate layer (silicon oxide layer) of the SOI substrate corresponds to the insulating layer 14. The upper layer (silicon single crystal layer) of the SOI substrate corresponds to the semiconductor portion 16.
When using the SOI substrate, first, a first trench 35 as shown in FIG. 3 is formed on the upper layer of the SOI substrate by anisotropic etching such as RIE (Reactive Ion Etching). Next, the wall surface of the first trench 35 is oxidized by a thermal oxidation method. Thereby, the first insulating film 34 made of a silicon oxide film is formed. At this time, the first insulating film 34 having a desired thickness (thin) can be formed by adjusting the conditions of the thermal oxidation method (thermal oxidation time, oxygen concentration in the atmosphere, etc.).
Next, the second trench 25 as shown in FIG. 3 is formed in the upper layer of the SOI substrate by anisotropic etching such as RIE. Next, the wall surface of the second trench 25 is oxidized by a thermal oxidation method or the like. As a result, a second insulating film 34 made of a silicon oxide film is formed. At this time, the second insulating film 24 having a desired thickness (thickness) can be formed by adjusting the conditions of the thermal oxidation method.
[0024]
Thus, in this embodiment, the trench for forming the insulating film (first insulating film 34) adjacent to the body region 30a and the insulating film (second insulating film 24) adjacent to the drift region 28 are separated ( The first trench 35 and the second trench 25) are formed. Therefore, the first insulating film 34 and the second insulating film 24 can be formed for the separate trenches 33 and 25, respectively. For this reason, the conditions of the thermal oxidation method when forming the first insulating film 34 and the second insulating film 24 can be set separately and independently, so the thickness of the first insulating film 34 and the second insulating film 24 can be easily set. Can be different.
If the thickness of the first insulating film 34 is reduced, the voltage applied to the channel trench electrode part 33 in order to turn on the element can be set low. On the other hand, if the thickness of the second insulating film 24 is increased, it is possible to make it difficult for dielectric breakdown to occur, and to achieve a high breakdown voltage. Since it is easy to set the thicknesses of the first insulating film 34 and the second insulating film 24 independently, it is easy to optimize the element characteristics.
[0025]
Next, the first trench 35 and the second trench 25 are filled with a material that becomes the first conductive layer 36 and the second conductive layer 26 (for example, a conductive material such as polycrystalline silicon or metal). Next, a third trench 19 as shown in FIG. 2 is formed in the upper layer of the SOI substrate by anisotropic etching such as RIE. Next, n-type impurities are ion-implanted (oblique ion implantation) from the side surface of the region where the drift region 28 exposed by forming the third trench 19 is formed toward the region where the drift region 28 is formed. . When ion implantation is performed in this manner, a concentration gradient of impurity concentration can be formed in the drift region 28 in the direction parallel to the first main surface M1, as shown by the equi-impurity concentration lines A1 to A4 in FIG. The impurity concentration in the direction perpendicular to the first main surface M1 can be made substantially constant. In this case, as shown in FIG. 5, when the opening width of the third trench 19 is W and the depth is D, the ion implantation angle (angle formed by the incident line of the ion and the perpendicular) θ is It is preferable to set.
θ ≦ tan^-1(W / D)
For example, when the aperture width W is 1 μm and the depth D is 10 μm, it is preferable to perform ion implantation at an ion implantation angle θ of 5.7 degrees or less.
[0026]
Next, the third trench 19 is filled with a semiconductor material (single crystal, polycrystalline silicon, or the like) doped with a high concentration of n-type impurities to be the drain region 18. Next, p-type impurities are ion-implanted from the surface of the upper layer of the SOI substrate toward the region where the body region 30 is to be formed. Next, n-type impurities are ion-implanted from the surface of the upper layer of the SOI substrate toward the region where the source region 32 is to be formed. Next, the drain electrode 20 is formed on the drain region 18, and the source electrode 31 is formed on the source region 32 and the body region 30. Next, a treatment (heat treatment or the like) for the purpose of activating the ion-implanted impurity and improving the contact property of the electrode is performed.
The semiconductor element of this embodiment can be manufactured through the above steps.
[0027]
Of course, the method of manufacturing the semiconductor device of this embodiment is not limited to the above method. For example, the order of the manufacturing steps described above may be variously changed.
For example, in the above method, the formation of the first trench 35, the formation of the first insulating film 34, the formation of the second trench 25, the formation of the second insulating film 24, and the like are performed alternately. However, the first and second trenches 35 and 25 may be formed first. In this case, first, an oxide film is formed on the wall surfaces of the first and second trenches 35 and 25 by the thickness of the first insulating film 34 by thermal oxidation, and then the wall surfaces of the first trench 35 are not oxidized. The surface of the second trench 25 may be further oxidized by a thermal oxidation method while taking appropriate measures (for example, a mask). According to this method, the thin first insulating film 34 and the thick second insulating film 24 can be efficiently formed. In addition, when masking so that the wall surface of the 1st trench 35 is not oxidized, if this mask is arrange | positioned so that the 1st trench 35 may be covered on the top surface of the upper layer of an SOI substrate, there will be little effort of arrangement | positioning and removal. That's it. Even in the case where the mask is disposed in the first trench 35, in the present embodiment, the mask may be disposed on the entire wall surface of the first trench 35. Therefore, the mask is partially applied to the wall surface of the deep and narrow trench. Compared to the case of arrangement, it can be handled with a simple and easy manufacturing technique.
[0028]
Even when the first insulating film 34 and the second insulating film 24 are formed by the CVD method or the like, the conditions such as the CVD method when forming the first insulating film 34 and the second insulating film 24 are set independently and independently. Therefore, the thicknesses of the first insulating film 34 and the second insulating film 24 can be easily made different. Of course, the first insulating film 34 and the second insulating film 24 may be formed of a silicon nitride film or the like.
[0029]
As a method of forming a concentration gradient of the impurity concentration in the drift region 28 in the direction parallel to the first main surface M1, the impurity concentration in the direction perpendicular to the first main surface M1 is substantially constant as described above. Instead of the ion implantation method, the third trench 19 is filled with a semiconductor material to which a high-concentration n-type impurity (phosphorus or the like) is added, and then heat treatment is performed, so that the n-type impurity is thermally diffused to form the first main impurity. For example, a method of diffusing toward the drift region 28 in a direction parallel to the surface M1 may be employed.
[0030]
In the above method, the third trench 19 is formed in order to form the drain region 18, and then the semiconductor material in which the n-type impurity is highly doped is filled in the third trench 19. However, the n-type impurity is doped from the surface of the upper layer of the SOI substrate without forming the third trench 19, so that n⁺A mold drain region 18 may be formed.
[0031]
Next, the operation of the semiconductor element of this embodiment will be described. First, the source electrode 31 connected to the source region 32 shown in FIG. 2 is grounded. In this state, a predetermined positive voltage is applied to the drain electrode 20 and the channel trench electrode portion 33 (first conductive layer 36) connected to the drain region 18 to turn on the semiconductor element. A predetermined positive voltage is also applied to the drift trench electrode portion 23 (second conductive layer 26) shown in FIGS. Then, an n-type channel is formed in a region 30a adjacent to the channel trench electrode portion 33 in the body region 30 shown in FIG. In the drift region 28, an electron accumulation region is formed in a region 28 a adjacent to the channel trench electrode portion 33. Further, in the drift region 28, an electron accumulation region is formed in a region 28c (see FIG. 1) adjacent to the drift trench electrode portion 23. Then, electrons flow from the source region 32 to the drain region 18 through the n-type channel 30a and the electron accumulation regions 28a and 28c. The direction of the current is opposite to the direction of the electrons and is the direction shown by the arrow in FIG. Thus, the current flows in the order of the drain region 18, the drift region 28, the body region 30, and the source region 32.
[0032]
In the present embodiment, the electron accumulation region 28 c is formed in the drift region 28 by the drift trench electrode portion 23 as described above. Moreover, in the present embodiment, the drift trench electrode portion 23 is adjacent to the entire drift region 28c (see FIG. 1) connecting the drain region 18 and the body region 30 via the second insulating film 24. Therefore, the on-resistance in the drift region 28 can be greatly reduced as compared with the case where there is no such drift trench electrode portion 23.
[0033]
Further, in the present embodiment, as shown in FIG. 3, the channel trench electrode part 33, the drift trench electrode part 23, and the drain region 18 are all from a part adjacent to the first main surface M <b> 1 of the semiconductor part 16. It extends in a direction perpendicular to the first main surface M1 (longitudinal direction in FIG. 3) until it reaches the separation part 10 (insulating layer 14). According to this configuration, it is possible to expand a region where current flows to a deep region of the drift region 28. Thus, the on-resistance can be reduced. When both the channel trench electrode part 33 and the drain region 18 reach the isolation part 10, the on-resistance can be greatly reduced. However, either the channel trench electrode part 33 or the drain region 18 reaches the isolation part 10. As a result, the on-resistance can be effectively reduced.
[0034]
Further, if the channel trench electrode part 33 and the drift trench electrode part 23 extend in a direction perpendicular to the first main surface M1 until reaching the separation part 10, these electrode parts 33 are applied when a reverse bias voltage is applied. , 23 can be avoided from concentrating the electric field at the lower end (particularly at the lower corner). Therefore, it is possible to make it difficult for dielectric breakdown to occur. For this reason, high breakdown voltage can be realized. When both of these electrode parts 33 and 23 reach the separation part 10, a sufficiently high breakdown voltage can be realized, but if either one of these electrode parts 33 and 23 reaches the separation part 10, the high breakdown voltage can be achieved. The breakdown voltage can be effectively realized.
[0035]
Further, according to the present embodiment, when a reverse bias voltage is applied, not only the depletion layer extends from the pn junction between the drift region 28 and the body region 30 to the drift region 28 side, but also the drift region 28 and the drift region The depletion layer can be extended from the contact portion of the trench electrode portion 23 to the drift region 28 side. Therefore, high breakdown voltage can be realized. Furthermore, when the drift trench electrode portion 23 groups are arranged at such an interval that the depletion layers extending from the drift region 28 adjacent to these electrode portion 23 groups are connected to each other when the device is turned off, the breakdown voltage is further increased. Can be realized.
[0036]
In such a semiconductor element, there is an optimum impurity concentration concentration gradient in the drift region 28 in order to obtain the maximum breakdown voltage. For example, when isoimpurity concentration lines B1 to B4 are distributed as shown in FIG. 6, the concentration gradient of the impurity concentration is formed not only in the direction parallel to the first main surface M1, but also in the vertical direction. become. As described above, when the concentration gradient of the impurity concentration is formed also in the direction perpendicular to the first main surface M1, even if the impurity concentration is optimum on the first main surface M1 side (surface side) of the semiconductor portion 16, On the second main surface M2 side (back surface side) of the semiconductor portion 16, the impurity concentration is greatly deviated from the optimum impurity concentration. This problem becomes a serious problem because the deviation of the impurity concentration between the first main surface M1 side and the second main surface M2 side increases as the thickness of the semiconductor portion 16 increases. It becomes. On the other hand, when the structure of the present embodiment is adopted, the current can be more widely distributed and the on-resistance can be reduced as the thickness of the semiconductor portion 16 is increased. For this reason, there is a demand for increasing the thickness of the semiconductor portion 16.
[0037]
On the other hand, in the present embodiment, as indicated by the equal impurity concentration lines A1 to A4 in FIG. 4, the drift region 28 has a concentration gradient of impurity concentration formed in a direction parallel to the first main surface M1. The impurity concentration in the direction perpendicular to the first main surface M1 of the drift region 28 is substantially constant. Therefore, according to the present embodiment, the optimum impurity concentration can be substantially maintained from the first main surface M1 side (surface side) of the semiconductor portion 16 to the second main surface side M2. For this reason, even if the thickness of the semiconductor portion 16 is increased, a high breakdown voltage is not hindered, and an element having a low on-resistance and a high breakdown voltage can be realized. However, the structure in which the impurity concentration is distributed as shown in FIG. 6 is also included in the scope of the present invention.
[0038]
The inventors manufactured a semiconductor element having the following configuration among the semiconductor elements of the present embodiment described above, and measured the on-resistance and breakdown voltage.
The first insulating film 34 is made of a thermal oxide film and has a thickness of about 50 nm. The second insulating film 24 is made of a thermal oxide film and has a thickness of about 500 nm. The thickness of the second insulating film 24 is set on the assumption that a voltage of about 80 V is applied between the drain region 18 and the channel trench electrode portion 33. The first conductive layer 36, the second conductive layer 26, and the drain region 18 have an impurity concentration of about 1 × 20 cm.^-3N doped with about phosphorus⁺Made of polycrystalline silicon. The thickness of the semiconductor part 16 (the thickness of the upper layer of the SOI substrate) was about 7 μm. The interval between adjacent drift trench electrode portions 23 was about 1 μm. Phosphorus is used as an impurity for ion implantation into the drift region 28, and the concentration gradient is about 6 × 10 6 on the side of the drift region 28 adjacent to the drain region 18.¹⁶cm^-3And on the side adjacent to the channel trench region 36, about 1 × 10¹⁶cm^-3It was made to become.
[0039]
As a result of measuring the breakdown voltage of this semiconductor element, a result that the breakdown voltage was 90 V was obtained as shown in FIG. Further, as a result of measuring the on-resistance, as shown in FIG. 8, the on-resistance was 58 mΩ · mm.²The result was obtained. This shows very high performance as a lateral power MOSFET used in a power IC.
[0040]
Second Embodiment FIG. 9 is a plan view of a semiconductor element (horizontal semiconductor element, more specifically a lateral power MOSFET) according to a second embodiment of the present invention. 10 shows a cross-sectional view taken along line VII-VII in FIG. FIG. 11 shows a cross-sectional view taken along line VIII-VIII in FIG. 12 shows a cross-sectional view taken along line IX-IX in FIG. About the structure and effect substantially similar to 1st Embodiment, description is abbreviate | omitted in principle except the content required for description of this embodiment.
Similarly to the first embodiment, in the second embodiment, the drain region 48, the drift region 58, the body region 60, and the source region 62 are formed on the first main surface (surface) of the semiconductor portion 46, as shown in FIGS. ) It includes regions formed in order in the first direction (lateral direction in FIGS. 9 and 10) among the directions parallel to M1.
[0041]
As seen in the plan view of FIG. 9, the channel trench electrode portion 63 extends in the first direction (lateral direction of FIG. 9). A plurality of channel trench electrode portions 63 are formed in stripes in a second direction (vertical direction in FIG. 9) perpendicular to the first direction among the directions parallel to the first main surface M1. Similarly, the drift trench electrode portion 53 extends in the first direction, and a plurality of drift trench electrode portions 53 are formed in a stripe shape in the second direction. Thus, in the present embodiment, when seen in a plan view, the extending direction of the channel trench electrode portion 63 and the drift trench electrode portion 53 is parallel.
[0042]
As shown in FIG. 9, the channel trench electrode portion 63 has a direction perpendicular to the first direction (lateral direction in FIG. 9) and the first main surface M <b> 1 in the body region 60 between the drift region 58 and the source region 62. It is adjacent to a surface region 60b that is substantially parallel to both (in the direction perpendicular to the plane of FIG. 9) (see FIG. 10).
According to this configuration, by applying a predetermined voltage to the channel trench electrode part 63, the drain region 48, the drift region 58, the body region 60, and the source region 62 are formed in this order in the plane region 60b substantially parallel to the first direction. A channel can be formed along. Therefore, it is easy to realize an increase in the area of the carrier path and a shortening of the carrier path, and thus it is easy to realize a reduction in on-resistance.
[0043]
For example, according to the configuration of the second embodiment, as shown in FIG. 11, the body region 60 does not hinder the flow of carriers as compared to the structure of the first embodiment (see FIG. 2). That is, unlike the first embodiment (see FIG. 2), the carrier path (current path) does not become a path that bypasses the body region 30. Therefore, it is easy to realize reduction of on-resistance. Even when the thickness of the semiconductor portion 46 is reduced, it is difficult to reduce the depth of the body region 60 in order to ensure a breakdown voltage. In the case of the configuration of the first embodiment (see FIG. 2), when the thickness of the semiconductor portion 16 is reduced, the distance between the body region 30 and the separation portion 10 is reduced. As a result, the area of the carrier path is reduced, which can cause an increase in on-resistance. On the other hand, in the configuration of the second embodiment, the body region 60 does not hinder the flow of carriers. Therefore, the above-described operational effects are particularly prominent when the semiconductor portion 46 is thin.
[0044]
As shown in FIGS. 9 and 11, the channel trench electrode portion 63 is formed in a body region 60 a between the drift region 50 and the source region 62 formed in order in the first direction (lateral direction in FIGS. 9 and 11). It has adjacent areas. The channel trench electrode part 63 is also adjacent to the drift region 58 and the source region 62.
[0045]
As shown in FIG. 9, the drift trench electrode portion 53 is formed in the drift region 58 in the direction perpendicular to the first direction (lateral direction in FIG. 9) and the first main surface M1 (as in the first embodiment). Adjacent to a surface region 58d which is substantially parallel to both of the two (in the direction perpendicular to the plane of FIG. 9). Further, the drift trench electrode portion 56 is adjacent to the body region 60 a between the drift region 58 and the source region 62 and the source region 62.
[0046]
The channel trench electrode portion 63 and the drift trench electrode portion 53 overlap with the drift region 58 and the body region 60 sandwiched when viewed from the second direction (the vertical direction in FIG. 9). However, the structure which the both electrode parts 63 and 53 do not overlap and adjoins may be sufficient.
In order to realize such a configuration, it is preferable that the bottom of the body region 60 reaches the isolation part 40 (insulating layer 44) as shown in FIGS. According to the configuration of the present embodiment described above, even if the body region 60 is extended in the deep direction as described above, the body region 60 does not hinder the carrier path, and low on-resistance can be realized.
[0047]
According to this configuration, when the element is turned on, the channel formed by the channel trench electrode portion 63 and the carrier accumulation region formed by the drift trench electrode portion 53 are arranged at close positions. In particular, when both the electrode parts 63 and 53 overlap with each other between the drift region 58 and the body region 60, the channel trench electrode part 63 is adjacent not only to the body region 60 but also to the drift region 58. It also plays an auxiliary role in forming the carrier accumulation region. On the other hand, since the drift trench electrode portion 53 is adjacent not only to the drift region 58 but also to the body region 60, it also plays an auxiliary role in forming a channel. Accordingly, the on-resistance can be greatly reduced.
In addition, when both the electrode parts 63 and 53 overlap with the drift region 58 sandwiched therebetween, a depletion layer can be effectively extended from the both electrode parts 63 and 53 to the drift region 58 when the element is turned off. High breakdown voltage can be realized. Furthermore, both electrode parts 63 and 53 are n⁻When the p-type body region 60 and the p-type body region 60 overlap with each other across the pn junction, the depletion layer can be extended more effectively, and higher breakdown voltage can be realized.
[0048]
Further, the second trench 55 (drift trench electrode portion 53) shown in FIG. 9 has a reduced withstand voltage generated by the first trench 65 (channel trench electrode portion 63) extending (overhanging) to the drift region 58. It works to suppress.
That is, when the second trench 55 does not exist, electric field concentration occurs in the corner portion of the first trench 66 extending to the drift region 58, and the breakdown voltage is reduced. However, by providing the second trench 55, the electric field concentration at the corner portion of the first trench 66 extending to the drift region 58 can be reduced. Therefore, it is possible to suppress a decrease in breakdown voltage.
Further, in this embodiment, as shown in FIGS. 9 and 11, when the channel trench electrode portion 63 is used as a reference, a part of the body region 60 and a part of the source region 62 are made into the drain region 48 and the drift region. 58 on the opposite side. In other words, the source region 62 has a region 62 a located on the opposite side of the drift region 58 with the channel trench electrode portion 66 interposed therebetween.
In the case of a structure in which the source region 62 exists only between the channel trench electrode portion 63 and the drift region 58 (for example, the structure of the first embodiment (see FIG. 1 and FIG. 2)), the channel trench electrode portion 63 and the drift region 58 It is necessary to form a wiring layer (source electrode) on the source region 62 therebetween. Therefore, the space between the channel trench electrode part 63 and the drift region 58 must be increased. This causes an increase in element size and an increase in on-resistance.
On the other hand, as described above, when the source region 62 has the region 62a located on the opposite side of the drift region 58 across the channel trench electrode portion 63, the wiring layer (source electrode 61) is formed on the region 62a. Can be formed to make contact with the source region 62. Therefore, it is not necessary to increase the space between the channel trench electrode part 63 and the drift region 58.
[0049]
Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
(1) The separation part 10 may be formed only by the insulating layer 14. Further, the separation part 10 may be formed only by the semiconductor substrate 12. In the case of the semiconductor substrate 12 alone, the conductivity type impurity (p-type in this embodiment) is such that the semiconductor portion 16 (n-type drain region 18 and drift region 28 in this embodiment) is pn-junction separated. In principle, it is necessary that impurities) be added to the semiconductor substrate 12.
(2) The first to fourth semiconductor regions (in the first embodiment, the drain region 18, the drift region 28, the body region 30, and the source region 32) are configured such that current flows in that order or vice versa. If so, other regions may be interposed between these semiconductor regions.
(3) Of course, in the above semiconductor element, the n-type and p-type may be interchanged.
(4) Although the above embodiment has been described by taking a MOSFET as an example of a semiconductor element, the present invention can also be applied to an IGBT (insulated gate bipolar transistor), an insulated gate thyristor, or the like. For example, the conductivity type of the first semiconductor region 18 of the semiconductor element shown in FIGS. 1 to 3 or the first semiconductor region 48 of the semiconductor element shown in FIGS.⁺In the case of a type), these semiconductor elements function as IGBTs. The present invention can also be applied to such an IGBT.
[0050]
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
2 shows a cross-sectional view taken along line II-II in FIG.
FIG. 3 is a cross-sectional view taken along line III-III in FIG.
FIG. 4 shows an impurity concentration distribution in a drift region in the semiconductor element according to the first embodiment of the present invention.
FIG. 5 is an explanatory diagram of an ion implantation angle.
FIG. 6 is an explanatory diagram of an impurity concentration distribution in a drift region.
FIG. 7 shows a breakdown voltage characteristic of a semiconductor device manufactured as an example of the present invention.
FIG. 8 shows on-resistance characteristics of a semiconductor device manufactured as an example of the present invention.
FIG. 9 is a plan view of a semiconductor device according to a second embodiment of the present invention.
10 is a cross-sectional view taken along line VII-VII in FIG.
11 is a cross-sectional view taken along line VIII-VIII in FIG.
12 is a sectional view taken along line IX-IX in FIG.
[Explanation of symbols]
10, 40: Separation part
12, 42: Semiconductor substrate
14, 44: Insulating layer
16, 46: Semiconductor part
18, 48: first semiconductor region (drain region)
19, 49: Third trench
23, 53: second electrode part (drift trench electrode part)
24, 54: second insulating film
25, 55: Second trench
26, 56: second conductive layer
28, 58: second semiconductor region (drift region)
30, 60: third semiconductor region (body region)
32, 62: Fourth semiconductor region (source region)
33, 63: first electrode part (channel trench electrode part)
34, 64: first insulating film
35, 65: first trench
36, 66: first conductive layer

Claims

A semiconductor portion, a channel trench electrode portion, and a drift trench electrode portion,
The semiconductor portion has a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region,
The first to fourth semiconductor regions are arranged such that current flows in the order or in the reverse order,
The first semiconductor region and the fourth semiconductor region include a region adjacent to the first main surface of the semiconductor part,
The second semiconductor region and the fourth semiconductor region are of the first conductivity type, the third semiconductor region is of the second conductivity type,
The channel trench electrode portion is covered with the first insulating film formed along the first trench adjacent to the third semiconductor region between the second semiconductor region and the fourth semiconductor region, and covered with the first insulating film. A first conductive layer formed in the first trench;
The drift trench electrode portion is covered with a second insulating film formed along the second trench adjacent to the second semiconductor region and separated from the fourth semiconductor region by the third semiconductor region, and the second insulating film. second have a second conductive layer formed in a trench in a state,
A semiconductor element in which the thickness of the first insulating film in the channel trench electrode portion is thinner than the thickness of the second insulating film in the drift trench electrode portion .

Includes a semiconductor unit, and the channel trench electrode portion, and a drift trench electrode portion,
The semiconductor portion includes a first semiconductor region, a second semiconductor region in contact with the first semiconductor region, a third semiconductor region in contact with the first semiconductor region, and a fourth semiconductor region in contact with the third semiconductor region.
The first semiconductor region and the fourth semiconductor region include a region adjacent to the first main surface of the semiconductor part,
The second semiconductor region and the fourth semiconductor region are of the first conductivity type, the third semiconductor region is of the second conductivity type,
The channel trench electrode portion is covered with the first insulating film formed along the first trench adjacent to the third semiconductor region between the second semiconductor region and the fourth semiconductor region, and covered with the first insulating film. A first conductive layer formed in the first trench;
The drift trench electrode portion is covered with a second insulating film formed along the second trench adjacent to the second semiconductor region and separated from the fourth semiconductor region by the third semiconductor region, and the second insulating film. a second conductive layer formed in the second trench in a state,
A semiconductor element in which the thickness of the first insulating film in the channel trench electrode portion is thinner than the thickness of the second insulating film in the drift trench electrode portion .

A separation part adjacent to the second principal surface located on the opposite side of the first principal surface of the semiconductor part;
3. The semiconductor device according to claim 1, wherein at least one of the channel trench electrode portion, the drift trench electrode portion, and the first semiconductor region extends in a direction perpendicular to the first main surface until reaching the separation portion.

Drift trench electrode portion, a semiconductor device according to any one of claims 1 to 3 adjacent across regions for connecting the first semiconductor region and the third semiconductor region of the second semiconductor region.

The second semiconductor region is the one where the concentration gradient of the impurity concentration is formed in the direction parallel to the first main surface, the impurity concentration in the direction perpendicular to the first main surface according to claim 1 which is substantially constant 4 The semiconductor element in any one of.

The first to fourth semiconductor regions include regions formed in order in a first direction parallel to the first main surface,
The channel trench electrode portion is adjacent to a surface region substantially parallel to both the first direction and the direction perpendicular to the first main surface in the third semiconductor region between the second semiconductor region and the fourth semiconductor region. Item 6. The semiconductor element according to any one of Items 1 to 5 .