JP4419071B2 - Semiconductor memory refresh control method and semiconductor memory device - Google Patents

Description

  The present invention relates to the field of refresh technology for pseudo SRAMs and DRAMs (Dynamic Random Access Memory) mounted on, for example, portable devices, and more particularly to a memory array in a long-cycle refresh operation for reducing power consumption compared to normal times. The present invention relates to a technical field of a partial array self-refresh method that targets only a part of a region set therein.

  In recent years, large-capacity DRAMs have been installed in portable devices such as mobile phones. However, in order to reduce power consumption during standby of portable devices, current consumption in the data retention state of DRAMs has been reduced. There is a strong demand for planning. Therefore, a DRAM having a long-cycle refresh function for executing a self-refresh operation at a cycle sufficiently longer than that during normal operation has been developed. A partial array cell refresh method has been proposed as an effective method for further reducing power consumption in long-period refresh (see, for example, Patent Document 1). In this partial array self-refresh method, a self-refresh operation is selectively performed for some banks in a memory array generally composed of a plurality of banks. In this case, it is only necessary to set a part of the banks as the holding area and execute a refresh operation with a long cycle only on the part corresponding to the holding area in a state where data to be held is stored in the holding area. For example, when two of the four banks are used as the holding area, the area to be refreshed is halved compared to the normal refresh, which is an effective technique for reducing the current consumption of the DRAM.

Japanese Patent Laid-Open No. 2004-118938

  However, in a situation where an increase in battery usage time of a portable device is required, even if the conventional partial array self-refresh method is adopted, it is not sufficient for reducing current consumption. In particular, with the increase in the number of functions of portable devices, the tendency to mount large-capacity DRAMs has become stronger, and further reduction of current consumption during self-refreshing has become an issue. As described above, in the partial array self-refresh method, if the number of data holding target banks is reduced, current consumption can be reduced accordingly. However, it is necessary to secure a data holding capacity to some extent from the viewpoint of usability of the portable device, and in this respect, there is a limit to reducing the current consumption of the DRAM during standby.

  Therefore, the present invention has been made to solve these problems. When the self-refresh operation is executed by limiting the holding area for holding data, the refresh cycle can be further extended, and the standby time can be increased. An object of the present invention is to provide a self-refresh control method for a semiconductor memory and the like that can significantly reduce the current consumption of a DRAM.

In order to solve the above-described problem, a refresh control method for a semiconductor memory according to the present invention provides data in a memory array composed of a plurality of memory cells arranged at the intersection of a word line corresponding to a row address and a bit line corresponding to a column address. A method for refresh control of a semiconductor memory for controlling a self-refresh operation for holding data, comprising: a group of memory cells on a predetermined number of word lines that are targets of data retention during the self-refresh operation of the entire memory array. Prior to the execution of the self-refresh operation, a step of distinguishing and setting a certain hold region and a copy region that is a memory cell group on a word line that is a copy destination of all data in the hold region during the self-refresh operation Each memory cell in the holding area is used as a copy source, and the same bit line or the same bit is used. A step of executing a copy operation of bit information to one or a plurality of memory cells of the copy area in the line pair, and sequentially specifying a row address with the holding area as a target of self-refresh, and corresponding to the designated row address and simultaneously select and drive word lines, by corresponding said copy one or a plurality of word lines in the region are sequentially selected and driven as a copy destination of the selected word line, and executing the self-refresh operation The capacity of the holding area is set to be switchable in a plurality of stages, and the number of memory cells of the copy destination corresponding to one bit of the copy source can be selectively changed according to each capacity. And

  According to the present invention having such a feature, the object of data holding is limited to only a holding area that is a part of the entire memory array, and the other area is used as a copy area for copying data in the holding area. . First, a copy operation from the holding area to the data area is executed, and then the word lines of the respective memory cells corresponding to the holding area and the copy area are simultaneously selected and driven to execute the self-refresh operation. At this time, since one copy source memory cell and a predetermined number of copy destination memory cells are in a positional relationship arranged on the same bit line (or the same bit line pair), the drive timing of the word line is appropriately controlled. By doing so, the copy operation and the self-refresh operation can be surely executed. In addition to reducing the capacity of the storage area itself (where capacity means “area size”, the same applies hereafter) when the self-refresh is executed, one bit information is stored. By holding in multiple memory cells, the accumulated charge is increased and the probability of bit information being destroyed is reduced, so that longer cycle refresh is possible and the current consumption during standby of the semiconductor memory is greatly reduced. It becomes possible.

  In the semiconductor memory refresh control method of the present invention, the bit information copying operation sequentially designates the row address of the holding area, selects and drives the word line corresponding to the designated row address. The method is executed by selecting and driving one or more word lines in the copy area corresponding to the copy destination of the selected word line after a predetermined time required for amplification of the bit line output has elapsed. .

  In the semiconductor memory refresh control method of the present invention, the capacity of the holding area is set to be switchable between a plurality of levels, and the number of copy destination memory cells corresponding to one bit of the copy source is set according to each capacity. It can be selectively changed.

In the refresh control method for a semiconductor memory according to the present invention, the capacity of the holding area can be switched between M stages of capacity of 1 / ^N 2 (N: integer from 1 to M) of the entire area of the memory array. The bit information is copied from one copy memory cell to the copy destination 2 ^N -1 memory cells.

  In the semiconductor memory refresh control method according to the present invention, the copy operation and the self-refresh operation are performed by identifying the holding region and the plurality of copy regions based on a predetermined pattern of M bits included in the row address. It is characterized by executing.

  In the semiconductor memory refresh control method of the present invention, the first mode for holding data only in the holding area and the second mode for holding the entire data in the memory array can be selectively set. It is characterized by being.

  Due to the series of features of the present invention as described above, the holding area set in the memory array can be set in various ways such as switching its capacity and number of stages, switching the holding area and the entire memory array depending on the mode, An optimum operation can be realized in accordance with the use state of the semiconductor memory.

  In the semiconductor memory refresh control method of the present invention, when an arbitrary word line is accessed after the self-refresh operation is stopped, it is the first access after the self-refresh exit to the word line or the second time. When determining whether the access is a subsequent access, and when the determination result indicates the first access, simultaneously with the word line to be accessed, one or a plurality of word lines holding the same bit information by the copy operation And when the determination result indicates the second and subsequent accesses, the method further includes a step of shifting to a normal operation and driving only the word line to be accessed.

  In the semiconductor memory refresh control method of the present invention, when the self-refresh operation is stopped, the row address of the holding region is sequentially designated, and the word line corresponding to the designated row address is selected and driven. At the same time, one or a plurality of word lines in the copy area corresponding to the copy destination of the selected word line are selected and driven, and after all the word lines in the holding area and the copy area have been driven, the normal operation is started. The method further includes a step.

  According to the above-described feature of the present invention, when the refresh operation is stopped, each memory cell can take an effective measure against the bit information destruction assumed in the long period refresh. That is, the same bit information held in a plurality of memory cells is amplified by overlapping the accumulated charges by controlling the driving timing of the word line, so that the destroyed bit information can be restored. Therefore, the refresh cycle can be further extended and the current consumption can be further reduced.

In order to solve the above problems, a semiconductor memory according to the present invention is a semiconductor memory having a memory array composed of a plurality of memory cells arranged at the intersection of a word line corresponding to a row address and a bit line corresponding to a column address. Thus, of the entire memory array, a holding area that is a group of memory cells on a predetermined number of word lines that are targets of data holding during the self-refresh operation and a copy destination of all data in the holding area during the self-refresh operation set by dividing the copy area is a memory cell group of word lines, and a self-refresh control means for controlling the self-refresh operation of the holding area by sequentially specifying the row addresses as the target of the self-refresh, the refresh When selecting and driving the word line of the holding area designated by the control means Moni, a word line selection driving means for selecting and driving one or a plurality of word lines of said copy area of a predetermined time required for amplification associated as the copy destination of the selected word line after the elapse of the bit line output, the A copy register area that is selected and driven by the word line selection drive unit according to the contents of the setting register. By changing the number of one or more word lines, the number of copy destination memory cells corresponding to one bit of the copy source can be changed .

  As described above, even when the present invention is applied to a semiconductor memory, the functions and effects of the present invention can be sufficiently achieved as in the above-described refresh control method for a semiconductor memory.

  Further, in the semiconductor memory of the present invention, a setting register capable of switching and setting one capacity from a plurality of stages as the capacity of the holding area is provided, and one bit of the copy source is set according to the contents of the setting register. The number of corresponding copy destination memory cells is identified.

  In the semiconductor memory of the present invention, the setting register can be switched between a first mode for holding data in only the holding area and a second mode for holding the entire data in the memory array. It is characterized by being.

Further, in the semiconductor memory of the present invention, the capacity of the holding area can be switched and set to an M-stage capacity of 1 / ^N 2 (N: an integer from 1 to M) of the entire area of the memory array, The word line drive selection means selects and drives a plurality of copy destination word lines corresponding to different M-bit patterns included in the row address.

  In the semiconductor memory of the present invention, when an arbitrary word line is accessed after the self-refresh operation is stopped, it is the first access after the self-refresh exit to the word line or the second or subsequent access. The word line selection drive circuit holds the same bit information by the copy operation together with the word line to be accessed when the first access is determined based on the output of the determination means. One or a plurality of word lines being driven are simultaneously driven, and when it is determined that the access is the second or subsequent access, the operation shifts to a normal operation and only the word line to be accessed is driven.

In the semiconductor memory of the present invention, the memory array is divided into a plurality of mats , and the word lines and the bit lines are shared in one mat , and the holding area and the copy The area is secured by the mat unit.

  In the semiconductor memory of the present invention, the memory cell is connected to one or the other bit line of a bit line pair connected to a common sense amplifier, and is copied to a copy source memory cell in the same bit line pair. Among the one or more memory cells, the same number of memory cells are connected to the one bit line and the other bit line.

  According to the present invention, the self refresh target is limited to the data holding area set as a part of the memory array, and one or more memory cells in the copy area in the same bit line or the same bit line pair from the data holding area Since the copy source and copy destination word lines are selected and driven at the same time during self-refresh, longer cycle refresh is possible, greatly increasing the current consumption of the semiconductor memory during self-refresh. Can be reduced. In other words, in addition to reducing the size of the holding region itself, holding the same bit information in a plurality of memory cells can reduce the current consumption by the amount that can significantly increase the refresh cycle due to the effect of increasing the accumulated charge. It becomes.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present embodiment, a case will be described in which the present invention is applied to a dynamic RAM (DRAM) having a configuration capable of executing a long-period refresh operation for the purpose of reducing power consumption.

  FIG. 1 is a block diagram showing the overall configuration of the DRAM according to the present embodiment. Here, a DRAM having a storage capacity of 256 Mbit and a 4-bank configuration will be described as an example. The DRAM shown in FIG. 1 includes a memory array 10 in which a large number of memory cells storing 1 bit are arranged in a matrix in the row direction and the column direction. The memory array 10 is divided into four banks (indicated as banks A, B, C, and D in the figure), each of which is a 64 Mbit storage area. Each of these banks has the same configuration. Each bank is specified based on a 2-bit bank selection signal accompanying the address signal.

  Around the memory array 10, there are a main word driver 11, a sense amplifier unit 12, a row decoder 13, a row address buffer 14, a self-refresh control unit 15, a column decoder 16, a column address buffer 17, an I / O control unit 18, a command A decoder 19 and a clock generator 20 are provided, and a row address switching unit 30 for realizing the partial array self-refresh of this embodiment is provided. Further, an address signal and various control signals are supplied to the memory array 10 and data stored in the memory array 10 is input / output.

  A row address or column address to be accessed by the memory array 10 is designated by an address signal supplied from outside. The row address buffer 14 holds a row address specified by an address signal, and the column address buffer 17 holds a column address specified by an address signal. The row decoder 13 selects one word line corresponding to the designated row address. The column decoder 16 selects one bit line corresponding to the designated column address. Since each bank of memory array 10 has a divided structure, the word lines corresponding to the row address include sub-word lines that are subdivided in addition to the entire main word line, as will be described later.

  When a desired word line and bit line are selected by the row decoder 13 and the column decoder 16, a memory cell to be accessed is determined in the memory array 10. Then, the main word driver 11 drives the word line selected by the row decoder 13 to the selection level. The sense amplifier unit 12 amplifies a potential difference corresponding to read data of a memory cell connected to a word line driven to a selected level. The data of the memory cell to be accessed is input / output from / to the outside via the I / O control unit 18. That is, read data from the memory array 10 is output to the outside by the I / O control unit 18, and write data input from the outside is sent to the memory array 10 via the I / O control unit 18.

  The command decoder 19 discriminates a control command defined based on the control signal combination pattern, and sends a control signal corresponding to the operation content to each unit. As control signals input from the outside to the command decoder 19, a chip select signal (/ CS), a row address strobe signal (/ RAS), a column address strobe signal (/ CAS), and a write enable signal (/ WE) are provided. Yes (symbol / means that the signal becomes active when it is at low level), and various control commands are associated with these arbitrary combinations.

  The clock generator 20 generates an internal clock for controlling the operation timing of each component in FIG. 1 based on a clock signal CLK input from the outside. The clock generator 20 determines the validity of the clock signal CLK based on the clock enable signal CKE input from the outside.

  The self-refresh control unit 15 controls a self-refresh operation in the data holding state of the DRAM. When the self-refresh operation is started according to a predetermined control command, the refresh counter 150 is activated. The refresh counter 150 is a circuit that sequentially generates row addresses designated as targets for self-refreshing, and sequentially counts up the row addresses based on the output of an oscillator (not shown) and sends them to the row decoder 13. Details of the self-refresh operation will be described later.

  The row address switching unit 30 is a circuit for switching a row address designated during normal operation to a row address used in partial array self-refresh. In the present embodiment, the row address designation and the word line selection timing are different in the normal operation, the copy operation, and the self-refresh operation, which will be described later. It is necessary to output from the row address switching unit 30 to the row decoder 13 at timing. The configuration and operation of the row address switching unit 30 will be described later in detail.

  In the present embodiment, as a specific example of the 256 Mbit memory array 10, input / output data has a 16-bit word configuration, 13 bits of the address signal are row addresses, and 9 bits are allocated to column addresses. Can be adopted. As a result, in each bank designated by the 2-bit bank selection signal, a 16-bit memory cell at an arbitrary address can be designated from among 8192 rows × 512 columns × 16 bits of memory cells.

  Here, FIG. 2 is a specific configuration example of one bank constituting the memory array 10. As shown in FIG. 2, the memory array 10 corresponding to the four banks A to D includes 8192 word lines and 8192 (512 columns × 16 bits) bit line pairs, and 256 ( 16 × 16) mats 100. Each of these mats 100 is positioned as a unit block having a common word line (sub word line) for each row and a bit line for each column in the memory array 10, and the word lines and the bit lines are divided from each other in different mats 100. ing. In addition, each sense amplifier included in the sense amplifier unit 12 is arranged in a mat 100 unit.

  Each mat 100 includes 512 × 512 memory cells arranged at the intersections of word lines and bit lines. In addition, in order to designate an arbitrary mat 100 from 256 mats 100 in one bank, it is necessary to allocate 4 bits of the row address and 4 bits of the column address, respectively. In the present embodiment, the mat 100 is a basic processing unit because a copy operation, which will be described later, is performed on the assumption that the bit lines are common.

  Next, the concept of long-period partial array self-refresh executed in the DRAM of this embodiment will be described with reference to FIGS. In this embodiment, when an entry command for self-refresh, which is one of control commands to the DRAM, is input, a self-refresh operation is performed on a holding area set as a data holding target area in the entire memory array 10. Is done. At this time, the capacity of data in the holding area in the memory array 10 (data holding capacity) can be set in advance by user settings. For example, the data holding capacity can be selectively set such that half of the 256 M bits of the entire memory array 10 is 128 M bits, which is half, and 64 M bits, which is ¼. In the present embodiment, another area of the memory array 10 that is divided from the holding area is set as a copy area for copying all data in the holding area. Therefore, the data in the copy area is not a data holding target, and the original data is lost by executing the self-refresh operation.

  FIG. 3 is a conceptual diagram for explaining the technique of the present invention in one mat 100. Here, a case where 128 Mbit, which is half of the entire memory array 10, is set as the data holding capacity is taken as an example. In the mat 100 shown in FIG. 3, the sub word driver SWD is connected to one end of each of the plurality of sub word lines SWL arranged in parallel, and the plurality of bit lines BL arranged in parallel perpendicular to the sub word lines SWL are 2 Each pair is connected to two ends of one input end (T side) and the other input end (B side) of the sense amplifier SA. Memory cells MC formed of MOS transistors and capacitors are arranged in a matrix at the intersections of the sub word lines SWL and the bit lines BL. The memory cell MC included in the entire mat 100 is provided with 512 sub-word lines SWL and 512 pairs (1024) of bit lines BL, so that there are 512 × 512 memory cells in total. Therefore, since each memory cell MC carries 1-bit bit information, one mat 100 has a capacity of 512 × 512 bits (256K bits).

  The sub word line SWL takes the logical product of the output of the main word line and the decoded output of the lower bits (X0 to X2) of the row address, but in the following description, for easy understanding, Except for the description of FIG. 3, the description will be made with the output of the main word line as a representative.

  Each memory cell MC is arranged on one of the bit lines BL with respect to the pair of bit lines BL connected to the T side and the B side of the sense amplifier SA among the pair of bit lines BL. At this time, on each bit line BL, the load capacitance (floating capacitance) of both bit lines BL is equalized, and the bit line length is equalized to reduce the chip size or drive noise unbalance. From the viewpoint, it is desirable to make the number of memory cells MC connected to the T side and the B side equal.

  FIG. 3 shows an example in which the sub word line SWL included in the mat 100 is divided into two, the left half is the holding area and the right half is the copy area. In this case, the holding area and the copy area have the same size (128K bits) in a symmetrical arrangement, and each area includes 256 sub-word lines SWL. Prior to the execution of the self-refresh operation, the memory cell MC (shown by a black circle) included in the holding area is used as a copy source, and the memory cell MC (white circle) on the same bit line pair included in the copy area is used. The bit information is copied with the copy destination shown.

  For the purpose of reducing drive noise and maintaining the T-side and B-side bit line loads of the sense amplifier SA equally, if the copy-source memory cell MC is connected to the T-side bit line BL, the copy destination It is desirable to connect the memory cell MC to the bit line BL on the B side. On the other hand, when the copy source memory cell MC is connected to the B side bit line BL, it is desirable to connect the copy destination memory cell MC to the T side bit line BL.

  The bit line BL to which the copy source memory cell MC is connected and the bit line BL to which the copy destination memory cell MC is connected are preferably separated on the T side and the B side, but the sense amplifier SA is shared. The present invention can be applied even to a configuration in which the same bit line pair is connected.

  When performing a self-refresh operation after executing a copy operation from the holding area to the copy area, two subwords intersecting both of the copy source and copy destination memory cells MC on the same bit line pair. Line SWL is selected simultaneously. Therefore, the stored charge associated with the same bit information is output from the copy source and copy destination memory cells MC via the bit line BL in an integrated manner. As a result, refreshing with a longer period becomes possible and the current consumption of the DRAM can be remarkably reduced. Specific copy operations and self-refresh operations and their functions will be described later.

  In the example of FIG. 3, the case where the data holding capacity is set to 128 Mbit which is half of the entire memory array 10 is shown. However, there are various variations in the data holding capacity setting method in the partial array self-refresh of this embodiment. . For example, it is possible to change the data holding capacity in various ways such as ¼ (64 Mbit), ８ (32 Mbit), and 1/16 (16 Mbit) of the entire memory array 10.

Note that one of the ^1,2-half of the half of the entire area of the memory cell as the data storage capacitor, · · · 2 ^M content of 1: at most as (M an integer) when the switchable M phase, circuit The configuration can be easily realized. That is, one holding area and 2 ^M −1 copy areas can be specified separately using M bits in the row address, and a circuit configuration suitable for the operation of this embodiment can be realized.

  Next, FIG. 4 is a diagram showing the relationship in the mat 100 between the holding area that is the copy source and the copy area that is the copy destination when the data holding capacity of the memory array 10 is changed in various ways. is there. FIG. 4A shows a case where the state of the mat 100 different from that in FIG. 3 is set to 64 Mbits (1/4) in accordance with the change in the data holding capacity in the memory array 10, and FIG. ) Is shown in FIG. 4 (b), and the case where it is set to 16M bits (1/16) is shown in FIG. 4 (c).

  First, when the data holding capacity is set to ¼ of the entire memory array 10, the mat 100 is divided into four for every 128 subword lines SWL as shown in FIG. Then, the holding area A1 is set at the end of the mat 100, and the copy areas B1 are set at the other three positions. At the time of self-refresh, all the data in the holding area A1, which is the copy source, is copied to each of the three copy areas B1. Therefore, the bit information of any one memory cell in one holding area A1 is copied to three memory cells in three copy areas B1 to B3, and four memories are combined on the same bit line pair. The same bit information is held in the cell.

  Similarly, when the data holding capacity is set to 1/8 of the entire memory array 10, the mat 100 is divided into eight as shown in FIG. 4B, and one holding area A2 and seven copy areas B2 are obtained. And are set. If the data holding capacity is set to 1/16 of the entire memory array 10, the mat 100 is divided into 16 as shown in FIG. 4C, and one holding area A3 and 15 copy areas B3 are formed. Is set. By executing the copy operation, in the case of FIG. 4B, the same bit information is held in eight memory cells on the same bit line pair, and in the case of FIG. 4C. The same bit information is held in 16 memory cells on the same bit line pair.

  4 shows only the state in one mat 100, for example, when the capacity setting is one quarter of the whole, all the mats 100 included in the four banks A to D are illustrated. 4 (a) state is obtained. For example, with respect to the holding areas A1, A2, and A3 of each mat 100 in FIGS. 4A to 4C, a total of 4 × 256 areas are secured in the memory array 10 as a whole.

  In the present embodiment, in addition to the setting for switching the data holding capacity in a plurality of stages, it is possible to switch between normal self refresh and partial array self refresh for the entire area of the memory array 10. In this case, a setting register for holding the setting contents is provided. On / off information of the partial array self-refresh mode (hereinafter referred to as PASR mode) and selection of a data holding capacity corresponding to the PASR mode are provided in the setting register. It only needs to be able to hold information.

  For example, FIG. 5 shows an example of a setting register for setting information related to the PASR mode. In the example shown in FIG. 5, 3 bits of the setting register can be assigned to information related to the PASR mode, and the setting of the PASR mode can be selectively switched according to the bit pattern. That is, the PASR mode is turned off to hold the data in the entire area of the memory array 10, or half of the memory array 10 is 128M bits, one quarter 64M bits, one eighth 32M bits, Any one of 16/16 16M bits can be selectively set as the data holding capacity.

  Next, the self-refresh operation performed in the DRAM will be described with reference to FIGS. FIG. 6 is a flowchart for explaining the flow of control of the self-refresh of the DRAM, and FIGS. 7 to 12 are diagrams showing an example of a circuit configuration representing a main part related to self-refresh in the DRAM and changes in signal waveforms. .

  In FIG. 6, in a situation where the portable device should be operated with low power consumption, such as during standby, an entry command for self-refresh is input as a control command for the DRAM, thereby starting (entry) the self-refresh operation (step S11). ). At this time, it is assumed that desired information regarding the PASR mode is already set in the setting register.

  Then, the process to be executed is determined by referring to the information in the setting register (step S12), and the following different processes are executed according to the set contents. First, when the PASR mode is set to OFF, the row address is counted up by the refresh counter 150 for the entire area of the memory array 10, and 8192 word lines are sequentially selected and driven to perform distributed refresh. Is executed (step S13). When the distributed refresh is executed, the refresh operation interval for each word line is controlled to be equal.

  On the other hand, when the PASR mode is set to ON, burst copy from the copy source holding area to the copy destination copy area is executed according to the data holding capacity setting (steps S14, S16, S18, S20). ). When the data holding capacity is set to 128M bits, burst copy of the holding area including 4096 word lines is executed (step S14). In step S14, 4096 word lines in the holding area are sequentially selected and driven, and 4096 word lines in the copy area are selected and driven according to a method described later, whereby each bit information is stored in two memory cells. / 1 bit is held. Note that when performing a burst copy, control is performed so that all word lines are selected in a concentrated manner.

  Subsequently, distributed refresh of the holding area including 4096 word lines is executed at a predetermined refresh interval (step S15). In step S15, the 4096 word lines in the holding area are sequentially selected and driven, and the 4096 word lines in the copy area are selected and driven at the same timing, so that the data in all areas of the memory array 10 is transferred. Retained.

  Similar to the above operation, when the data holding capacity is set to 64 Mbits, burst copy and distributed refresh corresponding to the holding area including 2048 word lines are executed (steps S16 and S17), and data holding is performed. When the capacity is set to 32M bits, burst copy and distributed refresh corresponding to the holding area including 1024 word lines are executed (steps S18 and S19), and the data holding capacity is set to 16M bits. In some cases, burst copy and distributed refresh corresponding to the holding area including 512 word lines are executed (steps S20 and S21). As a result, when the data holding capacity is 64 Mbits, it is 4 memory cells / 1 bit, when the data holding capacity is 32 bits, it is 8 memory cells / 1 bit, and when the data holding capacity is 16 Mbits, it is 16 memory cells. Data is held in the / 1 bit state.

  Next, when an exit command for self-refresh is input as a control command at a desired timing during the execution of each of the above distributed refreshes (step S22; Yes), the self-refresh operation is stopped (exit) (step S23). . Thereafter, the normal operation (reading or writing) of the DRAM is started. In step S23, if there is a memory cell in which the bit information is destroyed among a plurality of memory cells holding the same bit information, a process for repairing the memory cell is required. It will be described later.

  On the other hand, when no exit command is input (step S22; No), each distributed refresh is continued, so the process proceeds to any of the above steps S13, S15, S17, S19, and S21 and the same processing is repeated.

  Next, the circuit configuration and operation in the DRAM for realizing the partial array self-refresh of this embodiment will be described. FIG. 7 is a diagram illustrating an example of a circuit configuration of a main part related to the self-refresh operation corresponding to the assumption that only 128 Mbits (1/2 of the whole) is assumed as the data holding capacity for convenience of explanation. . FIG. 7 shows a circuit portion for selectively driving a word line by the operations of the row decoder 13 and the main word driver 11 under the control of the self-refresh control unit 15. Note that the row decoder 13 and the main word driver 11 are originally composed of a number of components corresponding to the number of word lines, but FIG. 7 shows only some of the components.

  Here, of the row addresses X0 to X12 output from the refresh counter 150, the bit X8 is input to the address switching unit 30. In this example, the row address switching unit 30 includes an X8 switching unit 31 that performs switching control for the bit X8 of the row address. As described above, 4 bits of the row address are necessary for designating the mat 100 in the bank. Therefore, 9 bits are assigned to designate the row address in one mat 100, and the most significant bit is the bit X8. .

  In FIG. 7, the X8 switching unit 31 is provided between two inverters 201 and 201 and includes three switches SW1, SW2, and SW3 and a delay unit D. The inverted bit / X8 of the bit X8 output from the inverter 201 is input to each of the switches SW1 to SW3. The on / off switching of the switches SW1 to SW3 is controlled based on a control signal SC supplied from the self-refresh control unit 15.

  Hereinafter, a self-refresh operation of the DRAM corresponding to the circuit configuration of FIG. 7 will be described. FIG. 8 shows the control contents for the X8 switching unit 31 for each operation state. During normal operation of the DRAM, only the switch SW1 is turned on and the switches SW2 and SW3 are turned off. Accordingly, in FIG. 7, the inverted bit / X8 is input to the AND circuit 204 on the copy source side of the row decoder 13, and the bit X8 is input to the AND circuit 206 on the copy destination side of the row decoder 13. In this case, in the mat 100, a predetermined word line in the holding area is selected when X8 = 0, and a predetermined word line in the copy area is selected when X8 = 1. Either the area or the copy area can be accessed.

  On the other hand, as shown in FIG. 8, during burst copy (step S14 in FIG. 6), only the switch SW2 is turned on and the switches SW1 and SW3 are turned off. In this case, the inverted bit / X8 output via the switch SW2 is input to the copy destination side AND circuit 206 after a predetermined delay time has elapsed by the delay unit D. Therefore, when X8 = 0, a predetermined word line in the holding area is selected, and a corresponding word line in the copy area is selected at a slightly delayed timing. By repeating this operation for all word lines in the holding area, all data in the holding area can be copied to the copy area.

  The operation at this time will be described with reference to the signal waveform diagram of FIG. As shown in FIG. 9A, the voltage level rises by driving a predetermined selected word line WLa in the holding region, and subsequently, the output of the bit line BL is output from the memory cell at the intersection with the selected word line WLa. Only a minute voltage changes due to the accumulated charge. This voltage change is amplified by the sense amplifier SA, and the voltage level is determined to be high or low at timing t0. The voltage level of the corresponding word line WLb in the copy area rises at the timing when the delay time by the delay unit D has elapsed from the rise timing of the selected word line WLa. Note that the delay time of the delay unit D needs to ensure the time required to amplify the output of the bit line BL by the sense amplifier SA.

  In FIG. 9A, when the voltage level of the corresponding word line WLb rises, the accumulated charge in the memory cell in the holding area is accumulated in the memory cell in the copy area via the bit line BL, and thereby the bit information is copied. Will be. At this time, the memory cell in the copy area is determined to be high or low at timing t1. Note that the corresponding word line WLb in the copy area corresponds to a row address obtained by adding 256 to the row address of the selected word WLa in the holding area, taking the arrangement in the mat 100 shown in FIG. 3 as an example.

  Next, as shown in FIG. 8, during the self-refresh (step S15 in FIG. 6), only the switch SW3 is turned on and the switches SW1 and SW2 are turned off. In this case, the inverted bit / X8 is input to the AND circuit 206 on the copy destination side without being delayed through the switch SW3. Accordingly, a predetermined word line in the holding area is selected when X8 = 0, and a corresponding word line in the copy area is selected at the same timing.

  The operation at this time will be described with reference to the signal waveform diagram of FIG. As shown in FIG. 9B, the voltage levels of a predetermined selected word line WLa in the holding area and the corresponding word line WLb in the copy area rise simultaneously. At this time, the output of the bit line BL changes under the influence of the accumulated charge of each memory cell at both intersections of the selected word line WLa and the corresponding word line WLb. Therefore, a voltage change approximately twice as large as that in FIG. 9A is generated, which is amplified by the sense amplifier SA and the voltage level is determined to be high or low. In FIG. 9B, a signal waveform diagram in the case of 2 memory cells / 1 bit is shown, but the configuration when the number of memory cells per bit is larger will be described later.

  Next, in the DRAM of the present embodiment, the circuit configuration and operation will be described in the case where the data holding capacity is set to be switched between a plurality of stages. FIG. 10 is a diagram of FIG. 7 when the data holding capacity of the setting register of FIG. 5 is assumed and can be set by selectively switching the data holding capacity of 128 M bits, 64 M bits, 32 M bits, and 16 M bits. It is a figure which shows the example of a corresponding circuit structure. In FIG. 10, the address switching unit 30 performs switching control on the four bits X8, X7, X6, and X5 of the row address, respectively, so the X8 switching unit 41, the X7 switching unit 42, the X6 switching unit 43, and the X5 switching unit. 44. In the circuit configuration of FIG. 10, the row decoder 13 and the main word / word driver 11 are omitted, but are arranged in the same manner as in FIG.

  Each of these four switching units 41 to 44 has the same configuration as that of the X8 switching unit 31 of FIG. 7, and each includes three switches SW1, SW2, and SW3 and a delay unit D, and self-refresh control. On / off control of the switches SW1 to SW3 is controlled based on a control signal SC supplied from the unit 15.

  FIG. 11A shows the control contents for the switching units 41 to 44 for each data holding capacity. The number of memory cells per bit changes by two times, 2, 4, 8, 16 in conjunction with the four data storage capacities described above, and each switching to be controlled corresponding to each. The parts 41 to 44 are different.

  First, in the data holding capacity of 256 Mbit in which the PASR mode is turned off, all four switching units 41 to 44 are in a fixed state. On the other hand, in the data holding capacity 128M bits (2 memory cells / 1 bit), only the X8 switching unit 41 is controlled, and in the data holding capacity 64M bits (4 memory cells / 1 bit), the X8 and X7 switching units 41 and 42 Two of them are controlled, and with a data holding capacity of 32 Mbit (8 memory cells / 1 bit), three of the X8 to X6 switching units 41 to 43 are controlled, and with a data holding capacity of 16 Mbit (16 memory cells / 1 bit) All of the X8 to X5 switching units 41 to 44 are controlled. In any case, the switching units 41 to 44 that are not to be controlled are in a fixed state.

  Next, FIG. 11B shows the control contents for the switching units 41 to 44 to be controlled in FIG. 11A for each operation state. It can be seen that the control content in FIG. 11B is the same as in FIG. FIG. 11C shows the control contents for the switching units 41 to 44 that are in the fixed state in FIG. In this case, only the switch SW1 is always on, the switches SW2 and SW3 are off, and the state during normal operation in FIG. 11B is maintained.

  By performing such control, a predetermined word line in the holding area is selected at the time of burst copy, and each word line in the plurality of copy areas corresponding to the bit patterns of bits X5 to X8 is slightly delayed. Selected. At the time of self refresh, the word lines in the holding area and the plurality of copy areas are simultaneously selected. For example, in the case of 16 memory cells / 1 bit, the case where all 4 bits X5 to X8 of the row address are 0 corresponds to the holding area, and any combination (15) including 1 in these 4 bits (15 Street) corresponds to one of the copy areas, and a total of 16 word lines are selectively driven via the switches SW2 and SW3 of the switching units 41 to 44.

  FIG. 12 is a signal waveform diagram when 16 memory cells / 1 bit is set in the circuit configuration of FIG. First, at the time of burst copy, the signal waveform of FIG. 12A is obtained, and the timing and waveform change are basically the same as in the case of FIG. 9A described above. However, in the case of FIG. 12A, after the voltage level of one selected word line WLa in the holding area rises, the voltage levels of 15 corresponding word lines WLb in 15 copy areas rise simultaneously. The output of the bit line BL changes by a minute voltage when the selected word line WLa rises, and after amplification by the sense amplifier SA, charges are accumulated in each memory cell at the intersection with the 15 corresponding word lines WLb. As a result, the bit information of the memory cells in the holding area is copied to the 15 memory cells in each copy area.

  In addition, the signal waveform of FIG. 12B is obtained at the time of self-refresh, and in this case also, the timing and waveform change are the same as those in FIG. 9B, but a copy is made with one selected word line WLa in the holding area. The voltage levels of a total of 16 word lines of 15 corresponding word lines WLb in the region rise simultaneously. At this time, the output of the bit line BL changes as a result of integration of the charges accumulated in the 16 memory cells, and the voltage change becomes larger than that in the case of FIG. 9B.

  Next, the effect of reducing current consumption when applying partial array self-refresh based on the method of the present invention will be described. FIG. 13 collectively shows the relationship between the data holding capacity that can be selectively set according to the configuration of this embodiment and the operation state of the self-refresh. In FIG. 12, regarding the 256 Mbit memory array 10, the data holding capacity, the total number of word lines in the holding area, and the number of memory cells per bit are as described above. In addition, the amount of stored charge per bit (assuming charge q0 per memory cell) increases by a factor of 2 in order in proportion to the reciprocal of the data retention capacity (or the number of memory cells per bit).

  First, paying attention to the total number of word lines of the data holding capacity, the number of times the word lines are driven is determined. Therefore, it is proportional to the operation time required for one self refresh, that is, the self refresh of all the memory cells in the holding area. Therefore, if the data holding capacity is reduced, the self-refresh operation time can be shortened, and the current consumption can be reduced accordingly (first effect). This first effect is not different from the conventional partial array self-refresh method.

  On the other hand, paying attention to the amount of stored charge per bit, it changes in proportion to the number of times of copying operation for one bit information (that is, the number of memory cells per bit). In other words, if the data retention capacity is reduced and the number of memory cells per bit is increased, the refresh interval can be set longer by the amount of the accumulated charge, thereby reducing the current consumption (the second effect). ). The second effect is a feature unique to the method of the present invention that cannot be obtained by the conventional partial refresh method, and the first effect and the second effect can be combined to significantly reduce current consumption.

  Here, consider the relationship between the number of memory cells per bit and the retention time, which is the time during which bit information can be held by the memory cells. First, in the case of 2 memory cells / 1 bit, it has been experimentally confirmed that the retention time is proportional to the amount of stored charge per bit. For example, the retention time when the data holding capacity is 128 Mbits and 2 memory cells / 1 bit is twice the retention time when there is no PASR, so that the refresh cycle can be set longer. Therefore, by setting the data holding capacity 128M by the first effect and the second effect described above, the current consumption can be reduced to a quarter compared to the normal time (without PASR).

  Hereinafter, the effect of 2 memory cells / 1 bit will be described with reference to FIGS. 14 to 17 in comparison with the case of 1 memory cell / 1 bit. FIG. 14 is a diagram illustrating a configuration of a circuit portion including one copy source memory cell MC1 and one copy destination memory cell MC2. For the bit line pair connected to the sense amplifier SA, the memory cell MC1 is connected to the T-side bit line BL (T), and the memory cell MC2 is connected to the B-side bit line BL (B). Memory cell MC1 is connected to word line WL1, and memory cell MC2 is connected to word line WL2.

  With respect to each of the memory cells MC1 and MC2 of FIG. 14, the operation in the case of 1 memory cell / 1 bit will be described with reference to the signal waveform diagram of FIG. The voltage level of the T-side bit line BL (T) at the timing when the word line WL1 is selectively driven changes in an increasing direction when high bit information is held in the memory cell MC1 (FIG. 15A). ), When the low bit information is held in the memory cell MC1, it changes in the decreasing direction (FIG. 15B). On the other hand, the voltage level of the B-side bit line BL (B) at the timing when the word line WL2 is selectively driven changes in an increasing direction when high bit information is held in the memory cell MC2 (FIG. 15 ( c)) When the low bit information is held in the memory cell MC1, the memory cell MC1 changes in a decreasing direction (FIG. 15D).

  In the case of 1 memory cell / 1 bit, the accumulated charge decreases due to leakage while the memory cells MC1 and MC2 are in the high state. At this time, if the remaining amount of the accumulated charge is reduced to about half, it becomes difficult to identify the change in the voltage level and causes a malfunction, thereby limiting the refresh cycle.

  On the other hand, in the case of 2 memory cells / 1 bit, a longer refresh cycle can be realized based on the action shown in FIGS. FIG. 16 is a signal waveform diagram when the refresh cycle is changed in the case of 2 memory cells / 1 bit. FIG. 17 is a graph showing the relationship between the refresh cycle and the signal level of the bit line BL based on the signal waveform diagram of FIG.

  As shown in FIG. 16, when the two word lines WL1 and WL2 are selected and driven simultaneously, the voltage levels of the T-side bit line BL (T) and the B-side bit line BL (B) change in opposite directions. The level difference decreases as the refresh period is increased in the order of FIGS. 16A, 16B, 16C, and 16D. When the refresh cycle is 100 s, the remaining charge of the T-side bit line BL (T) is about half, and its own voltage level becomes difficult to distinguish, but the level with the B-side bit line BL (B) Since the difference is secured, the bit information can be read normally. On the other hand, when the refresh period becomes 200 s, the remaining amount of accumulated charges on the T-side bit line BL (T) becomes zero, and a level difference from the B-side bit line BL (B) cannot be secured, causing malfunction at this point. . Thus, the refresh cycle of 2 memory cells / 1 bit can be extended to about twice that of 1 memory cell / 1 bit.

  If the result of 2 memory cells / 1 bit is applied to the case of 4 memory cells / 1 bit or more, the retention time becomes longer in proportion to the amount of accumulated charge per bit. However, when the number of memory cells is increased to 4 memory cells / 1 bit or more, not only the effect due to the increase in the amount of accumulated charge but also the failure probability when reading bit information held in a plurality of memory cells is abrupt as described below. Due to the effect of reducing the retention time, the retention time can be greatly prolonged.

  First, regarding a 256 Mbit DRAM, the expected value e1 of the number of failures in the case of 4 memory cells / 1 bit is given by the following equation (1).

（１）
ただし、ｎ：各リフレッシュ周期でのフェイルビット数
_ｎ−２Ｃ_２：ｎ−２ビット中から２を抽出するときの組合せ数
同様に、８メモリセル／１ビット、１６メモリセル／１ビットの場合についてのフェイル数のそれぞれの期待値ｅ２、ｅ３は（２）、（３）式で与えられる。

(1)
Where n is the number of fail bits in each refresh cycle
_n-2 C ₂ : Number of combinations when 2 is extracted from n-2 bits Similarly, expected values e2 and e3 of the number of failures for the case of 8 memory cells / 1 bit and 16 memory cells / 1 bit Is given by equations (2) and (3).

（２）

(2)

（３）

上記の（１）〜（３）式の確率計算によれば、１ビット当たりのメモリセル数が２の場合に比べ、４、８、１６と多重化の度合が高くなることにより、リテンションタイムは１０倍、４０倍、８０倍程度に長くすることができる。

(3)

According to the probability calculation of the above formulas (1) to (3), the retention time is increased as the degree of multiplexing is increased to 4, 8, 16 as compared with the case where the number of memory cells per bit is two. The length can be increased to about 10 times, 40 times, or 80 times.

  FIG. 18 is a graph showing the relationship between the cumulative failure frequency and the refresh cycle when the number of memory cells per bit is changed in the DRAM of this embodiment. In the graph of FIG. 18, when the number of memory cells / bit is 1 or 2, actually measured values are used, and when the number of memory cells / bit is 4, 8, or 16, calculated values of the above formulas (1) to (3) are used. ing. FIG. 18 shows a 1-bit fail position P1 when a 1-bit failure is assumed to be an allowable limit with respect to a 256 Mbit capacity.

  As can be seen from the graph of FIG. 18, for the same refresh period, the cumulative frequency of failure decreases rapidly as the number of memory cells per bit increases. That is, by multiplexing and holding the bit information, the degree of decrease in the failure becomes larger than the increase in the amount of accumulated charge, so that the retention time becomes longer. Hereinafter, the relationship between the number of memory cells per bit and the refresh cycle will be described with reference to FIG.

  FIG. 19 is a graph showing an appropriate refresh cycle for maintaining a fail within an allowable range when the number of memory cells per bit is changed, and two straight lines L1 and L2 are also superimposed on the graph. . When the number of memory cells per bit is 1 or 2, it changes according to the straight line L1, but when the number of memory cells per bit is 4, 8, or 16, there is a tendency to change according to the straight line L2, compared with the straight line L1. Thus, it can be seen that the straight line L2 has a remarkably large degree of extension of the refresh cycle. The straight line L1 reflects the effect that the amount of accumulated charge increases in proportion to the number of memory cells per bit and the retention time becomes longer, whereas the straight line L2 shows bit information as shown in FIG. This reflects the effect of decreasing the fail probability due to the multiplexing, thereby increasing the retention time. Thus, as the number of memory cells per bit is increased, the refresh cycle can be drastically increased, and the current consumption of the DRAM can be greatly reduced.

  Next, processing performed after the exit of the self-refresh operation (step S23 in FIG. 6) in the present embodiment will be described. As described above, when one bit is held in a plurality of memory cells, a process for repairing bit information destroyed in a specific memory cell is required. In the present embodiment, since a long-cycle self-refresh operation is performed, a word line that has not been accessed for a long time from the last refresh operation to the time of exit has a high probability that the bit information of the memory cell is destroyed. A first method for avoiding this problem is to execute a self-refresh operation similar to that in FIG. 9B or FIG. 12B on the entire area of the memory array 10 at the time of exit. . However, this first method has a demerit in that the transition to the next processing is delayed by a certain amount of time required for refreshing the memory array 10 in the DRAM. Therefore, a modified example in which a circuit having a predetermined function is added to the DRAM will be described as a configuration that can surely avoid the above-described problem at the time of exit and can quickly shift to the next processing.

  FIG. 20 shows a circuit configuration example of a main part of the DRAM corresponding to such a modification. In the present modification, it is assumed that the data holding capacity in the PASR mode is switched between four stages as in the case of FIG. As shown in FIG. 20, a row decoder 52 and a main word driver 51 for selecting and driving a word line are included, and each has a circuit configuration different from those in FIGS. For convenience of description of the row decoder 52 and the main word driver 51, only some circuits are shown.

  In FIG. 20, a row decoder 52 to which a 13-bit row address is input is provided with a large number of unit circuits for each word line. Each unit circuit is provided with four AND circuits 302 to 305 in addition to the original AND circuit 301 to which the bits X0 to X5 and X9 to X12 of the row address are input. The AND circuit 302 receives the output of the preceding AND circuit 301 and the bit X5. Similarly, the AND circuits 303 to 305 are configured such that the outputs of the preceding AND circuits 302 to 304 and the bits X6 to X8 are sequentially input. In the example shown in FIG. 20, two unit circuits corresponding to X8 = 0 and X8 = 1 are shown for the row decoder 52 and the main word driver 51, respectively.

  The main word driver 51 includes as many additional MWD switching units 53 as the number of word lines. Each MWD switching unit 53 is connected to a main word driver (MWD) that drives one word line. As shown in FIG. 20, the MWD switching unit 53 includes four switches SWa, SWb, SWc, SWd, four control registers Ra, Rb, Rc, Rd, and an OR circuit 310. One end of each of the switches SWa to SWd is sequentially connected to the output side of the AND circuits 301 to 304, and the other end is connected to the OR circuit 310. Each of the control registers Ra to Rd is provided for performing on / off switching control while determining the states of the corresponding switches SWa to SWd under the control of the self-refresh control unit 15.

  In such a configuration, a control procedure of each control register Ra to Rd at the time of self refresh will be described. First, immediately after power-on of the DRAM (during normal operation), the switches SWa to SWd corresponding to the four control registers Ra to Rd are set to the collective OFF state. Similarly, when an entry command is input, the switches SWa to SWd are set to the collective OFF state. That is, since the output of the AND circuit 305 is input to the main word driver MWD via the OR circuit 310 before and during the execution of the self-refresh operation, one word line corresponding to the designated row address. Are selectively driven.

  On the other hand, when an exit command is input during execution of self-refresh, the control shifts to the control content shown in FIG. In FIG. 21, control registers Ra to Rd that differ for each data holding capacity are controlled, and only the switches SWa to SWd corresponding to the control registers Ra to Rd are set to the ON state. However, in the data holding capacity 256M bits, the PASR mode is off, and the switches SWa to SWd corresponding to all the control registers Ra to Rd are always set to the off state. In this state, as in the normal operation, one word line is selectively driven. On the other hand, in the data holding capacity 128M to 16M bits, the switches SWa to SWd corresponding to any of the control registers Ra to Rd are set to the on state, and the other states are kept to the off state. In this case, any output of the AND circuits 301 to 304 corresponding to the data holding capacity is input to the OR circuit 310 together with the output of the AND circuit 305.

  For example, considering the operation with a data holding capacity of 128 Mbits, when the switch SWa is on in FIG. 20, the row address excluding the bit X8 is input to the OR circuit 310 via the AND circuit 304 and the switch SWa. As a result, the word line that is the output destination of the OR circuit 310 is selectively driven regardless of whether the bit X8 is 0 or 1 (two types). In the same way, a predetermined word line is selectively driven regardless of whether the bits X7 and X8 are 0 and 1 (4 types) when the data holding capacity is 64M bits, and the bits X6 to X8 are 0 when the data holding capacity is 32M bits. Predetermined word lines are selectively driven regardless of the presence or absence of 1 (eight ways), and the predetermined word lines are selectively driven regardless of whether or not bits X5 to X8 are 0 and 1 (16 ways) with a 16 Mbit data storage capacity. Will be.

  When an arbitrary address is accessed after exiting to the DRAM of this modification, the operation states of the switches SWa to SWd that are used to select one word line are determined by the corresponding control registers Ra to Rd. The At this time, the switches SWa to SWd determined to be accessed for the first time after the exit are again switched off by the control registers Ra to Rd. Therefore, when the same address is accessed after the second time after the exit, the MWD switching unit 53 corresponding to the word line at that time returns to the control during the normal operation, and the switches SWa to SWd are turned off so that the access is performed. Sometimes only one word line is selectively driven.

  By adopting the above modification, a specific memory cell (for example, 16 memory cells) can be used during a self-refresh operation in a state where one bit is held in a plurality of memory cells including a copy source and a copy destination on the same bit line pair. Even if the bit information of one of the memory cells is destroyed, it can be repaired upon exit. In other words, since a plurality of word lines (for example, 16 lines) are simultaneously selected at the first access after the exit, data based on the accumulated charges of other normal memory cells is sensed in the memory cell in which the bit information is destroyed. After being amplified by the amplifier SA, it is restored by being restored (rewritten). On the other hand, since the bit information has already been restored at the second access of the word line, it is only necessary to return to the original control and select only one word line. According to this modification, self-refresh is not required for the entire area of the memory array 10 after the exit, and there is an advantage that the transition to the normal operation of the DRAM can be performed quickly.

  As mentioned above, although this invention was concretely demonstrated based on this embodiment, this invention is not limited to the above-mentioned embodiment, A various change can be given in the range which does not deviate from the summary. For example, the capacity and circuit configuration of the memory array 10 are not limited to the specific examples described above, and the present invention can be widely applied to various semiconductor memories. In addition, regarding the setting contents, the number of switching steps, a specific setting method, and the like regarding the holding area and the copy area, a form suitable for the operation can be adopted.

It is a block diagram which shows the whole structure of DRAM which concerns on this embodiment. It is a specific structural example about one bank which comprises a memory array. It is a conceptual diagram explaining the method of this invention within one mat. FIG. 5 is a diagram illustrating a relationship in a mat between a holding area that is a copy source and a copy area that is a copy destination when the data holding capacity of the memory array is variously set. It is a figure which shows an example of the register for a setting for setting the information regarding a PASR mode. It is a figure explaining the flow of control of the self refresh performed in DRAM. It is a figure which shows the circuit structural example of the principal part relevant to the self-refresh operation at the time of assuming only 128 Mbit as data retention capacity. It is a figure which shows the control content with respect to the X8 switching part for every operation state in the circuit structure of FIG. FIG. 8 is a signal waveform diagram corresponding to the circuit configuration of FIG. 7. It is a figure which shows the circuit structural example of the principal part relevant to the self-refresh operation | movement in the case of setting it as a data retention capacity | capacitance which switches a several step. It is a figure which shows the control content with respect to the X5-X8 switching part for every operation state in the circuit structure of FIG. FIG. 11 is a signal waveform diagram corresponding to the circuit configuration of FIG. 10. It is a figure which shows collectively the relationship between the data retention capacity | capacitance which can be selectively set according to the structure of this embodiment, and the operation state of self-refresh. FIG. 4 is a diagram showing a configuration of a circuit portion including two memory cells in order to explain the effect in the case of 2 memory cells / 1 bit in comparison with the case of 1 memory cell / 1 bit. FIG. 15 is a signal waveform diagram corresponding to the configuration of FIG. 14. It is a signal waveform diagram when the refresh cycle is changed for the case of 2 memory cells / 1 bit. 17 is a graph showing the relationship between the refresh cycle and the signal level of the bit line based on the signal waveform diagram of FIG. FIG. 5 is a graph showing the relationship between the cumulative failure frequency and the refresh cycle when the number of memory cells per bit is changed in the DRAM of this embodiment. FIG. 5 is a graph showing the relationship between the number of memory cells per bit and the refresh cycle. It is a figure which shows the circuit structural example of the DRAM principal part corresponding to the modification of this embodiment. It is a figure which shows the control content of the control register in the circuit structure of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Memory array 11 ... Main word driver 12 ... Sense amplifier unit 13 ... Row decoder 14 ... Row address buffer 15 ... Self-refresh control unit 16 ... Column decoder 17 ... Column address buffer 18 ... I / O control unit 19 ... Command decoder 20 ... clock generator 30 ... address switching unit 31, 41 ... X8 switching unit 42 ... X7 switching unit 43 ... X6 switching unit 44 ... X5 switching unit 51 ... main word driver 52 ... row decoder 53 ... MWD switching unit 100 ... mat 150 ... refresh counters 201 and 202 ... inverters 203 to 206, 301 to 305 ... AND circuits 203 to 206 ... OR circuits

Claims (23)

A semiconductor memory refresh control method for controlling a self-refresh operation for holding data in a memory array composed of a plurality of memory cells arranged at an intersection of a word line corresponding to a row address and a bit line corresponding to a column address. And
Of the entire memory array, a holding area that is a group of memory cells on a predetermined number of word lines that is a target of data holding during the self-refresh operation, and a copy destination of all data in the holding area during the self-refresh operation Separating and setting a copy area which is a memory cell group on a word line;
Prior to execution of the self-refresh operation, each memory cell in the holding area is used as a copy source, and bit information is copied to one or a plurality of memory cells in the copy area on the same bit line or the same bit line pair. Steps to perform;
A row address is sequentially designated with the holding region as a target of self-refresh, and a word line corresponding to the designated row address is selected and driven, and at the same time, one or more of the copy regions corresponding as a copy destination of the selected word line Performing the self-refresh operation by sequentially selecting and driving a plurality of word lines , and
The capacity of the holding area is set to be switchable in a plurality of stages, and the number of copy destination memory cells corresponding to one bit of the copy source can be selectively changed according to each capacity. Refresh control method.   The bit information copy operation sequentially designates a row address of the holding area, selects and drives a word line corresponding to the designated row address, and after a predetermined time required for amplification of the bit line output has elapsed. 2. The semiconductor memory refresh control method according to claim 1, wherein the refresh control method is executed by selecting and driving one or a plurality of word lines in the copy area corresponding to a copy destination of the selected word line. Capacity of the holding area, the memory 1 of 2 ^N fraction of the total area of the array (N: 1 or M an integer) is set to be switchable capacity of M stages of one said bit information of the copy source the semiconductor memory refresh control method according to claim 1 or 2 from the memory cells, characterized in that it is copied to the 2 ^N -1 memory cells of the destination. The semiconductor of claim 3, wherein performing said copying operation and the self-refresh operation to identify the holding area and the plurality of the copy area based on a predetermined pattern of M bits included in the row address Memory refresh control method. A first mode for holding data of only the holding area, said claims 1 and second modes, characterized in that it is selectively configurable to retain the data of all areas of the memory array 4 The refresh control method of the semiconductor memory in any one. When stopping the self-refresh operation, the row address of the holding area is sequentially designated, and the word line corresponding to the designated row address is selected and driven, and at the same time, the copy corresponding to the copy destination of the selected word line Selecting and driving one or more word lines in the region, and transitioning to normal operation after driving all the word lines in the holding region and the copy region;
The semiconductor memory refresh control method according to claim 1, further comprising: A semiconductor memory having a memory array composed of a plurality of memory cells arranged at the intersection of a word line corresponding to a row address and a bit line corresponding to a column address,
Of the entire memory array, a holding area that is a group of memory cells on a predetermined number of word lines that are targets of data retention during the self-refresh operation, and a word line that is a copy destination of all data in the retention area during the self-refresh operation a self-refresh control means for controlling the self-refresh operation is set by dividing the copy area, specifies the storage area of the row address sequentially as the target of the self-refresh is a memory cell group,
The word line in the holding area designated by the self-refresh control means is selected and driven, and after a predetermined time required for amplification of the bit line output has elapsed, the copy area corresponding to the copy area of the selected word line is copied. Word line selection driving means for selecting and driving one or a plurality of word lines;
A setting register capable of switching and setting one capacity among a plurality of stages as the capacity of the holding area;
The copy destination corresponding to one bit of the copy source is changed by changing the number of one or more word lines in the copy area selected and driven by the word line selection driving means according to the contents of the setting register. A semiconductor memory characterized in that the number of memory cells can be changed . The setting register can be switched between a first mode for holding data in only the holding area and a second mode for holding data in all areas of the memory array. 8. The semiconductor memory according to 7 . The capacity of the holding area can be set by switching M-stage capacity of 1 / ^N 2 (N: an integer not less than 1 and not more than M) of the entire area of the memory array. 9. The semiconductor memory according to claim 7 , wherein a plurality of copy destination word lines corresponding to different patterns of M bits included in the row address are selected and driven. The memory array is divided into a plurality of mats , and is configured such that the word lines and the bit lines are common in one mat .
The holding area and the copy area is a semiconductor memory according to any one of claims 7 to 9, characterized in that the reserve space in the mat units. The memory cell is connected to one or the other bit line of a bit line pair connected to a common sense amplifier, and the copy source memory cell and the copy destination one or more memory cells in the same bit line pair of semiconductor memory according to any one of claims 7 to 10, wherein the the one of the bit lines and the other bit line in the same number of memory cells are connected. A semiconductor memory refresh control method for controlling a self-refresh operation for holding data in a memory array composed of a plurality of memory cells arranged at an intersection of a word line corresponding to a row address and a bit line corresponding to a column address. And
Of the entire memory array, a holding area which is a memory cell group on a predetermined number of word lines to be data held, and a copy area which is a memory cell group on a word line which is a copy destination of all data in the holding area A step for setting and separately,
Prior to execution of the self-refresh operation, each memory cell in the holding area is used as a copy source, and bit information is copied to one or a plurality of memory cells in the copy area on the same bit line or the same bit line pair. Steps to perform;
A row address is sequentially designated with the holding region as a target of self-refresh, and a word line corresponding to the designated row address is selected and driven, and at the same time, one or more of the copy regions corresponding as a copy destination of the selected word line Performing the self-refresh operation by sequentially selecting and driving a plurality of word lines;
When an arbitrary word line is accessed after the self-refresh operation is stopped, determining whether the access is the first access after the self-refresh exit or the second or later access;
When the determination result indicates the first access, one or more word lines holding the same bit information are simultaneously driven by the copy operation together with the word line to be accessed, and the determination result is the second or later access. A method for controlling refresh of a semiconductor memory, comprising: shifting to a normal operation and driving only the word line to be accessed . The bit information copy operation sequentially designates a row address of the holding area, selects and drives a word line corresponding to the designated row address, and after a predetermined time required for amplification of the bit line output has elapsed. 13. The semiconductor memory refresh control method according to claim 12 , wherein the refresh control method is executed by selecting and driving one or a plurality of word lines corresponding to the copy destination of the selected word line. The capacity of the holding area is set so that a plurality of stages can be switched, and the number of copy destination memory cells corresponding to one bit of the copy source can be selectively changed according to each capacity. 14. A refresh control method for a semiconductor memory according to 12 or 13 . Capacity of the holding area, the memory 1 of 2 ^N fraction of the total area of the array (N: 1 or M an integer) is set to be switchable capacity of M stages of one said bit information of the copy source Note semiconductor memory refresh control method according to claim 14, characterized in that it is copied from Li cell 2 ^N -1 memory cells of the destination. The semiconductor of claim 15, wherein performing said copying operation and the self-refresh operation to identify the holding area and the plurality of the copy area based on a predetermined pattern of M bits included in the row address Memory refresh control method. A first mode for holding data of only the holding area, said memory claims 12 to 16, characterized in that a second mode is selectively settable to retain data in the entire area of the array The refresh control method of the semiconductor memory in any one. A semiconductor memory having a memory array composed of a plurality of memory cells arranged at the intersection of a word line corresponding to a row address and a bit line corresponding to a column address,
Of the entire memory array, a holding area which is a memory cell group on a predetermined number of word lines to be data held, and a copy area which is a memory cell group on a word line which is a copy destination of all data in the holding area preparative set by classifying the self-refresh control means for controlling the self-refresh operation of the holding area by sequentially specifying the row addresses as the target of the self-refresh,
The word line in the holding area designated by the self-refresh control means is selected and driven, and after a predetermined time required for amplification of the bit line output has elapsed, the copy area corresponding to the copy area of the selected word line is copied. Word line selection driving means for selecting and driving one or a plurality of word lines;
When any word line is accessed after the self-refresh operation is stopped, it is provided with a discriminating means for discriminating whether the access is the first access after the self-refresh exit or the second access or later. ,
If the word line selection drive circuit determines that the first access is based on the output of the determination means, the word line selection drive circuit selects one or more word lines in which the same bit information is held by the copy operation together with the word line to be accessed. A semiconductor memory which is driven at the same time, and when it is determined that the access is for the second time or later, shifts to a normal operation and drives only the word line to be accessed. A setting register capable of switching and setting one capacity among a plurality of stages as the capacity of the holding area is provided, and the number of copy destination memory cells corresponding to one bit of the copy source is determined according to the contents of the setting register. 19. The semiconductor memory of claim 18 , wherein the semiconductor memory is identified. The setting register can be switched between a first mode for holding data in only the holding area and a second mode for holding data in all areas of the memory array. 19. The semiconductor memory according to 19 . The capacity of the holding area can be set by switching M-stage capacity of 1 / ^N 2 (N: an integer not less than 1 and not more than M) of the entire area of the memory array. the semiconductor memory according to claim 18, characterized by selecting and driving a plurality of word lines of the copy destination corresponding to different patterns of M bits included in the row address 20. The memory array is divided into a plurality of mats , and is configured such that the word lines and the bit lines are common in one mat .
The holding area and the copy area is a semiconductor memory according to any of claims 18 21, characterized in that the reserve space in the mat units. The memory cell is connected to one or the other bit line of a bit line pair connected to a common sense amplifier, and the copy source memory cell and the copy destination one or more memory cells in the same bit line pair of semiconductor memory according to any of claims 18 22, characterized in that said the one of the bit lines and the other bit line in the same number of memory cells are connected.

Images