JP4417769B2 - Inverter device - Google Patents

Description

  The present invention relates to an inverter device, and more particularly to an inverter device including a filter circuit that cuts a narrow pulse signal.

  In a semiconductor switching element for electric power represented by an IGBT (Insulated Gate Bipolar Transistor), a certain time is required for on / off switching. These are referred to as the minimum on time and the minimum off time. If a gate signal shorter than the minimum on / off time is input, the switching element may be adversely affected and may be destroyed.

  Patent Document 1 discloses a filter circuit that cuts a narrow pulse by using a capacitor charge / discharge circuit in order to prevent the narrow pulse from being input to the switching element.

JP 2001-258268 A (summary and others overall)

  The circuit of Patent Document 1 does not output a pulse when a narrow pulse is input, and outputs a pulse only when a wide pulse is input. When the input pulse width is sufficiently wider than the time constants of the resistor and the capacitor, the input pulse width and the output pulse width are substantially equal. However, when a pulse slightly wider than the border line to be cut (hereinafter referred to as a minimum passing pulse) is input, the output pulse width is narrower than the input pulse width. This is because when the minimum pass pulse is input, the capacitor is charged or discharged, and immediately after the capacitor voltage exceeds or falls below a predetermined level, the capacitor re-discharge or recharge is started, and immediately the capacitor voltage Is again below or above the predetermined level.

  That is, in the technique of Patent Document 1, an input narrow pulse can be cut, but since the pulse width of an input normal pulse may be shortened and output, the narrow pulse is eliminated from the output signal. I can't.

  An object of the present invention is to provide an inverter device that reliably cuts only an input narrow pulse having a width less than a predetermined width and does not give a narrow pulse having a width less than a predetermined width to a switching element in the inverter.

  Another object of the preferred embodiment of the present invention is to reliably cut only narrow pulses having an input width less than a predetermined width, and for an input pulse having a predetermined width or more, a pulse closer to the input pulse width. To provide an inverter device capable of supplying a gate pulse signal having a width to a switching element of an inverter.

  In a preferred embodiment of the present invention, means for detecting a change between “1” and “0” of the input PWM signal, means for detecting that the changed state has continued for a predetermined time, and means for detecting the change The output of the filter circuit is changed in response to the output of the output signal, and the output state is continued for a second predetermined time, and the PWM signal continues while the second predetermined time elapses. Means for continuing the output state are provided.

  In another preferred embodiment of the present invention, the voltage of the capacitor is compared with two threshold values, and changes between on and off with a hysteresis characteristic according to the change in the magnitude relationship between them. A hysteresis circuit for generating an on / off signal is provided.

  Furthermore, in another preferred embodiment of the present invention, a charge / discharge circuit for charging / discharging a capacitor in accordance with an input PWM signal and converting a change in the capacitor voltage into an on / off signal with hysteresis characteristics in one chip. And a drive unit for outputting a gate signal corresponding to the on / off signal to the switching element in the inverter main circuit.

  The inverter device according to the present invention can achieve any of the following effects. First, only pulses having a width less than a predetermined width can be cut reliably, and the inverter can be operated stably. In addition, it is possible to reliably prevent a narrow pulse from being output to the switching element with respect to a normal input pulse having a predetermined width or more. Furthermore, for a normal input pulse having a predetermined width or more, a gate signal having a width that more closely matches the input pulse width can be supplied to the switching element.

  Other objects and features of the present invention will become apparent from the following description of embodiments.

First embodiment:
FIG. 1 is an overall block diagram of an inverter device according to a first embodiment of the present invention. The one-chip inverter 10 has an inverter main circuit 11 and an inverter drive circuit 12 integrated in one semiconductor chip. However, as indicated by a broken line 101, the one-chip inverter 101 includes only a part of the inverter main circuit 11 and the inverter drive circuit 12, that is, the filter circuits 18 and 19 and the upper and lower arm drive units 16 and 17 in the illustrated example. May be integrated in one semiconductor chip.

  The inverter main circuit 11 is a three-phase bridge inverter or the like incorporating six IGBTs (Insulated Gate Bipolar Transistors), and supplies a three-phase alternating current of variable voltage and variable frequency to a load such as a three-phase induction motor. The inverter drive circuit 12 provides an on / off signal to be supplied to the switching element of the three-phase arm in the inverter 11 by the three-phase distribution circuit 13 that distributes the PWM signal from the outside to three phases, the protection circuit 14 and the logic gate 15. decide. The protection circuit 14 is a circuit that outputs a switching element off signal when the power supply voltage drops (hereinafter referred to as an undervoltage protection circuit).

  In this embodiment, filter circuits 18 and 19 are provided between the logic gate 15 and the upper and lower arm drive units 16 and 17. An on / off signal to be given to the switching element, which is an output of the logic gate 15, is transmitted to the upper and lower arm driving units 16 and 17 through the filter circuits 18 and 19, where it is amplified and transmitted to the switching elements in the inverter main circuit 11. This is a gate signal.

  Here, the filter circuits 18 and 19 include charge / discharge circuits 181 and 191 and hysteresis circuits 182 and 192, respectively, and have the following three functions.

  (1) A function for reliably cutting only pulses having a width less than a predetermined width.

  (2) A function for reliably preventing a narrow pulse from being output to the switching element with respect to a normal input pulse having a predetermined width or more.

  (3) A function of supplying a switching element with a gate signal having a width that more closely matches the input pulse width for a normal input pulse having a predetermined width or more.

  First, an example of the reason why the narrow pulse is input will be described.

  Neither the output signal of the three-phase distribution circuit 13 nor the output signal of the protection circuit 14 includes a narrow pulse signal (hereinafter referred to as a narrow pulse). However, a combination of these two signals by the logic gate 15 may generate a narrow pulse.

  FIG. 2 is a pulse signal waveform diagram showing a specific example of narrow pulse input in FIG. 2A shows the output signal of the three-phase distribution circuit 13, FIG. 2B shows the output signal of the protection circuit 14, and FIG. 2C shows the input signals of the filter circuits 18 and 19. This is a case where the protection circuit 14 includes a circuit (hereinafter referred to as an undervoltage protection circuit) that outputs a signal for turning off the switching element when the power supply voltage is lowered. In the inverter device, when the power supply voltage vibrates, when the minimum value of the power supply voltage becomes equal to or lower than the operating voltage of the undervoltage protection circuit, the undervoltage protection circuit 14 outputs a signal for turning off the switching element. Although this signal itself is not a narrow pulse, when the output signal (B) of the protection circuit 14 is output at the timing shown in FIG. 2, the logic of the output signal (A) of the three-phase distribution circuit 13 causes the signal of FIG. ), A narrow pulse Pn may be generated.

  For example, even in such a case, by providing the filter circuits 18 and 19 according to the present embodiment, it is possible to prevent a narrow pulse signal from being transmitted after the filter circuit. In FIG. 2, the signal before synthesis does not include a narrow pulse, and a narrow pulse is generated by synthesizing the signal. However, the signal before synthesis already includes a narrow pulse. Even in this case, it is possible to prevent transmission of the narrow pulse signal to the filter circuit and the subsequent circuits.

  FIG. 3 is a specific circuit diagram of the filter circuits 18 and 19, and FIG. 4 is a block diagram thereof. In this embodiment, a signal is input to a constant speed charging circuit 32 and a constant speed discharging circuit 33, and a capacitor 34 is charged and discharged by these signals. Then, the voltage of the capacitor 34 is input to the hysteresis circuit 35 and the output is taken out from the output terminal 36.

  More specifically, the input terminal 31 is connected to the gate of the PMOS transistor M1 and the gate of the NMOS transistor M2. The drain of the PMOS transistor M1 and the drain of the NMOS transistor M2 are connected, and the PMOS transistor M1 and the NMOS transistor M2 constitute a logic inverter. The drain of the PMOS transistor M1 and the drain of the NMOS transistor M2 are connected to one of the resistors R1, and the other of the resistor R1 is connected to one of the charge / discharge capacitors 34 (C1) and the history circuit 35. The source of the PMOS transistor M1 is connected to the power supply Vcc, and the source of the NMOS transistor M2 is connected to the ground potential GND. The other of the charge / discharge capacitor 34 is connected to the ground potential GND.

  The history circuit 35 includes a Schmitt trigger circuit L1 and a logic inverter L2.

  The PMOS transistor M1 and the resistor R1 constitute a constant speed charging circuit 32. When the PMOS transistor M1 is ON, the capacitor 34 (C1) is charged with a time constant R1 · C1. The NMOS transistor M2 and the resistor R1 constitute a constant speed discharge circuit 33. When the NMOS transistor M2 is on, the capacitor 34 (C1) is discharged with a time constant R1 · C1. The resistor R1 is shared by the charge / discharge circuit. When an input signal of “H” or “L” is input to the input terminal 31, the charge / discharge capacitor 34 is charged at a constant speed or discharged at a constant speed by the constant speed charging circuit 32 or the constant speed discharging circuit 33.

  Here, the Schmitt trigger circuit L1 in the hysteresis circuit 35 has two threshold voltages. When the voltage of the charge / discharge capacitor 34 falls below the lower threshold VthL, the output terminal 36 is turned on ("H"). ) Signal is output, and when it exceeds the upper threshold value VthH, an off (“L”) signal is output.

  FIG. 5 is a timing chart showing the operation of the filter circuit according to the embodiment of FIGS. 1, 3, and 4, and shows the operation of cutting the minimum on-pulse. 5A shows the input signal waveform, FIGS. 5B and 5D show the voltage waveform of the capacitor 34, FIG. 5C shows the output signal waveform without the hysteresis circuit 35, and FIG. 5E shows the hysteresis circuit 35. The output signal waveform in a case is shown.

  A state where the voltage of the input terminal 31 is “L” level (low level, hereinafter simply referred to as L) and the capacitor 34 is charged with a voltage equal to the power supply voltage Vcc is an initial state. In the initial state, the output of the Schmitt trigger circuit L1 is “H”, and the output of the logic inverter L2, that is, the voltage of the output terminal 36 is “L”. When “H” level is input to the input terminal in this initial state, the PMOS transistor M1 is turned off and the NMOS transistor M2 is turned on, so that the capacitor 34 starts discharging from the point a.

  First, consider a case where there is no hysteresis circuit 35, that is, a case where the Schmitt trigger circuit L1 is replaced with a logic inverter circuit having a single threshold value Vth and no hysteresis characteristic is provided. When the voltage of the capacitor 34 is larger than the threshold value VthL of the Schmitt trigger circuit L1, the voltage of the output terminal 36 is “L”. When the input signal changes from “L” to “H”, that is, when the input signal IS1 is given, the capacitor 34 starts discharging from the point a to the point b. When the pulse width of the input signal IS1 is narrow and the input signal returns to “L” (IS1 disappears) before the voltage of the capacitor 34 falls below Vth (IS1 disappears), the signal at the output terminal 36 does not change and is applied to the line c. Along the way, the capacitor 34 is charged again. As a result, the input narrow pulse IS1 can be cut. Next, when the input signal IS2 whose pulse width is wider than the allowable value is given, the voltage of the capacitor 34 discharged from the point d falls below the threshold value Vth at the point e. Therefore, from this point, the output of the output terminal 36 becomes "H", and the output signal OS2 is generated. However, since the input signal IS2 is also relatively narrow and returns to “L” immediately after the output signal OS2 is generated, the voltage of the capacitor 34 is switched from the point f to the charge, and exceeds the threshold value Vth again at the point g immediately after. End up. For this reason, the signal at the output terminal 36 also returns to "L", and the output signal OS2 generated in this way becomes a narrow pulse narrower than the input signal IS2. From this, the narrow pulse cannot be eliminated from the gate signal of the switching element in the method of Patent Document 1 described above.

  On the other hand, when the input signal IS3 having a wide pulse width is given, the voltage of the capacitor 34 falls below the threshold value Vth from the point h to the point i, and the output terminal OS has a wide width of the output signal OS3. An output close to the width of the input signal IS3 can be obtained.

  On the other hand, when there is the hysteresis circuit 35 according to the embodiment of the present invention, the narrow pulse is not output as follows.

  First, when the input signal IS1 narrower than the cut level is given to the input terminal 31, as shown in FIG. 5 (D), the narrow pulse is cut as in FIG. No (does not change). Next, when the input signal IS2 having a pulse width wider than the allowable value is given, the voltage of the capacitor 34 that starts discharging from the point d falls below the threshold value VthL at the point e. Therefore, from this point, the output of the output terminal 36 becomes “H”. The time Tth during which discharge is performed with the time constant of C1 · R1 from the point d to the point e, that is, from the power supply voltage Vcc to the lower threshold value VthL is the set width (time) for cutting the narrow pulse.

  Next, from the point f, the capacitor 34 starts to be charged as described above, and exceeds the threshold value VthL at the point g. The steps so far are the same as those in FIG. However, due to the set hysteresis characteristic, the output signal OS2 of the output terminal 36 continues until the point j at which the voltage of the capacitor 34 exceeds the second threshold value VthH. From this point g to point j, that is, from the lower threshold value VthL to the upper threshold value VthH, the time Tmin for charging with the time constant of C1 · R1 is the second set value. It is a time span. Thus, the output signal OS2 at the output terminal 36 remains “H” only for the time Tmin until the voltage of the capacitor 34 is charged from VthL to VthH. That is, a pulse having a width narrower than Tmin is not output. The output signal OS2 generated in this way has substantially the same width as the input signal IS2.

  Also in the case of IS3 where the pulse width of the input signal is wide, the output terminal 36 is wide as the output signal OS3 from the point h to the point k and closer to the width of the original input signal IS3. An output signal having a width is obtained.

  FIG. 6 is a timing chart showing the operation of the filter circuit according to the embodiment of FIGS. 1, 3, and 4, and shows the operation of cutting the minimum off pulse. The description of FIG. 5 for cutting the minimum on-pulse is a case where “L” is used as an input pulse and “H” voltage appears in a pulse shape, but “H” is used as a reference and “ The same operation is performed in the case of FIG. 6 in which the voltage of L ″ appears and the minimum off-pulse is cut. That is, the output signal of the output terminal 36 becomes “H” when the voltage of the capacitor 34 falls below the lower threshold value VthL, and the output signal of the output terminal 36 when the voltage exceeds the higher threshold value VthH. Becomes “L”.

  In the embodiment described above, the narrow-width pulse can be prevented from being transmitted to the drive units 16 and 17 by the configuration of the filter circuit shown in FIGS. First, means for detecting a change between “1” and “0” (“H” and “L”) of the input PWM signals IS1 to IS3, and detecting that the changed state has continued for a predetermined time Tth. Means. Next, in response to the output of the detection means, the outputs of the filter circuits 18 and 19 are changed from “0” to “1” (“L” to “H”) (output signals OS2 and OS3 are generated). . Further, there is provided means for continuing this state for the second predetermined time Tmin and means for continuing the output state of the OS3 while the PWM signal continues as in IS3 even after the second predetermined time Tmin has elapsed. Yes.

  In the inverter device shown in FIG. 1, filter circuits 18 and 19 are provided immediately after the logic gate 15. However, the position where the filter circuit is provided does not necessarily need to be this position. The purpose is not to transmit a narrow pulse to the switching element. For example, a filter circuit may be provided after synthesizing signals of a three-phase distribution circuit, a protection circuit, a PWM circuit, and the like and before the switching element.

Second embodiment:
FIG. 7 is a specific circuit diagram of a filter circuit according to the second embodiment of the present invention, and FIG. 8 is a block diagram thereof. The outline of the operation principle will be described with reference to FIG. When a signal is input from the input terminal 31 to the constant speed charging circuit 32 and the variable speed discharging circuit 331, the charging / discharging capacitor 34 (C1) is charged by the constant speed charging circuit 32 according to the input signal, or Discharged by the variable speed discharge circuit 331. The discharge speed at this time is controlled by a signal from the hysteresis circuit 35. The voltage of the charge / discharge capacitor 34 is input to the hysteresis circuit 35. The hysteresis circuit 35 outputs a discharge speed command signal to the variable speed discharge circuit 331 and an output signal to the output terminal 36 in accordance with the input signal.

  Next, the circuit according to the present embodiment will be described in detail with reference to FIG. The input terminal 31 is connected to the gate of the PMOS transistor M1, the gate of the NMOS transistor M2, and the input of the logic inverter L3. The drain of the PMOS transistor M1 and the drain of the NMOS transistor M2 are connected, and both transistors M1 and M2 constitute a logic inverter. The drains of both the transistors M1 and M2 are connected to one of the resistors R1, and the other of the resistors R1 is connected to the NMOS transistor M4.

  The source of the PMOS transistor M1 is connected to the power supply Vcc, and the source of the NMOS transistor M2 and the source of the NMOS transistor M4 are connected to the ground potential GND. The drain of the NMOS transistor M4 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to one end of the charge / discharge capacitor 34, the input of the logic inverter L4, and the input of the logic inverter L7. The other of the charge / discharge capacitor 34 is connected to the ground potential GND.

  The output of the logic inverter L4 is connected to the input of the logic inverter L5. The output of the logic inverter L7 is connected to the input of the logic inverter L8, and the output of the logic inverter L8 is connected to the input of the logic inverter L9.

  One input of the NAND circuit L10 is connected to the output of L5, and the other is connected to the output of the NAND circuit L11. The output of the NAND circuit L10 is an output terminal of this circuit. One input of the NAND circuit L11 is connected to the output of the logic inverter L9, and the other is connected to the output of the NAND circuit L10. NAND circuit L10 and NAND circuit L11 constitute a flip-flop circuit.

  One input of the NOR circuit L12 is connected to the output of the logic inverter L9, the other is connected to the output of the logic inverter L3, and the output of the NOR circuit L12 is connected to the gate of the NMOS transistor M4.

  The PMOS transistor M1, the resistor R1, and the resistor R2 constitute a constant speed charging circuit 32. The NMOS transistor M2, the NMOS transistor M4, the resistor R1, the resistor R2, the NOR circuit L12, and the logic inverter L3 constitute a variable speed discharge circuit 331. The resistors R1 and R2 are shared by both the circuits.

  The variable speed discharge circuit 331 discharges the capacitor 34 (C1) at a high speed (time constant R2 · C1) when both the NMOS transistor M2 and the NMOS transistor M4 are on. On the other hand, when the NMOS transistor M2 is on and the NMOS transistor M4 is off, the capacitor 34 (C1) is discharged at a low speed (time constant (R1 + R2) · C1). The constant speed charging circuit 32 charges the capacitor 34 with a time constant (R1 + R2) · C1 when the PMOS transistor M1 is on. The logic inverters L4, L5, L7 to L9 and the NAND circuits L10, L11 constitute a hysteresis circuit 35.

  Here, the threshold voltages VthL and VthH of the logic inverters L4 and L7 are selected so as to satisfy the relationship of VthL <VthH.

  FIG. 9 is a timing chart of the operation according to the embodiment of FIGS. The state where “L” is input to the input terminal and the voltage of the capacitor 34 is the power supply voltage Vcc is the initial state. In the initial state, the outputs of the logic inverters L3 to L5 and the logic inverters L7 to L9 are “H”, “L”, “H” (L5), and “L”, “H”, “L” (L9) in this order. It is. In the NAND circuit L11, since the output “L” of L9 is input to one of the inputs, the output is “H”, and both inputs of the NAND circuit L10 are “H” (output signals of L5 and L11). Since it is input, the output of the NAND circuit L10, that is, the output terminal voltage is “L”.

  In the initial state, since the output “H” of the logical inverter L3 is input to one of the inputs of the NOR circuit L12, the output is “L”, the PMOS transistor M1 is on, the NMOS transistor M2 is off, Transistor M4 is off.

  When “H” is input to the input terminal in such an initial state, the PMOS transistor M1 is turned off and the NMOS transistor M2 is turned on. Further, the output of the logic inverter L3 becomes “L”. In this state, the PMOS transistor M1 is off and the NMOS transistor M2 and the NMOS transistor M4 are both on, so that the capacitor 34 is discharged at high speed.

  If "H" is continuously input to the input terminal, the voltage of the capacitor 34 becomes smaller than VthH. At this time, the output of the logic inverter L7 is “H”, the output of the logic inverter L8 is “L”, and the output of the logic inverter L9 is “H”. Therefore, the NOR circuit L12 becomes “L” because the output “H” of the logic inverter L9 is inputted to one of the inputs, and the NMOS transistor M4 is turned off. As a result, the discharge speed of the capacitor 34 changes from high speed to low speed. Further, the voltage of the output terminal 36 in this state is “L” as in the initial state.

  When the pulse width of the input signal is narrow and the input voltage is returned to “L” before the voltage of the capacitor 34 falls below VthL, the PMOS transistor M1 is turned on and the NMOS transistor M2 is turned off. Further, the output of the logic inverter L3 is “H”, and the NOR circuit L12 has the output “L” because the output “H” of the logic inverter L3 is input to one of the inputs, the NMOS transistor M4 is turned off, and the capacitor 34 is Charged. In this case, the output signal of the output terminal 36 does not change to “H”, and no pulse is output.

  When the pulse width of the input signal is wide and “H” is continuously input to the input terminal, the voltage of the capacitor 34 is lower than VthL. At this time, the output of the logic inverter L4 is “H”, and the output of the logic inverter L5 is “L”. Further, since the output “L” of the logic inverter L5 is input to one of the inputs of the NAND circuit L10, the output of the NAND circuit L10, that is, the voltage of the output terminal 36 becomes “H”. The NAND circuit L11 has an output “L” because both inputs are “H”. The capacitor 34 continues to be discharged at a low speed.

  When the voltage of the capacitor 34 is lower than VthL and the input terminal voltage is set to “L”, the PMOS transistor M1 is turned on and the NMOS transistor M2 is turned off. The output of the logic inverter L3 is “H”, and the output of the NOR circuit L12 is “L” because the output “H” of the logic inverter L3 is input to one of the inputs, the NMOS transistor M4 is turned off, and the capacitor 34 is Charged.

  If “L” is continuously input to the input terminal, the voltage of the capacitor 34 becomes higher than VthL. At this time, the output of the logic inverter L4 is “L”, and the output of the logic inverter L5 is “H”. At this time, the voltage of the output terminal is “H” as before the voltage of the capacitor 34 exceeds VthL.

  When “L” is continuously input to the input terminal, the voltage of the capacitor 34 becomes higher than VthH. At this time, the output of the logic inverter L7 is “L”, the output of the logic inverter L8 is “H”, the output of the logic inverter L9 is “L”, and the NAND circuit L11 has the output “L” of the logic inverter L9 as one of the inputs. Since the signal is input, the output is “H”, and the NAND circuit L10 is input with “H” for the two inputs, so the output of the NAND circuit L10, that is, the output terminal voltage is “L”. The capacitor 34 continues to be charged.

  With this configuration, it is possible to shorten the time during which the voltage of the charge / discharge capacitor 34 is discharged from Vcc to VthH. Therefore, as compared with the first embodiment, the delay time from when “H” is input to the input of the filter circuit to when “H” is output to the output terminal 36 of the filter circuit is reduced, and the speed is increased. be able to.

  As in the case of FIG. 3, the pulse width output when the minimum passing pulse is input is equal to or longer than the time Tmin during which the voltage of the capacitor 34 is charged from VthL to VthH.

  FIG. 10 is a timing chart showing the operation of the filter circuit according to the second embodiment, and shows the operation of cutting the minimum off pulse. In the operation of FIG. 10, the voltage of the capacitor 34 exceeding the high threshold value VthH only increases the speed at which the voltage is discharged to the threshold value VthH, and the operation in the first embodiment shown in FIG. Almost unchanged.

Third embodiment:
FIG. 11 is a block diagram showing a basic configuration of a filter circuit according to the third embodiment of the present invention. In this embodiment, a variable speed charging circuit 321 and a constant speed discharging circuit 33 are used.

  FIG. 12 is an example of a specific circuit for realizing FIG. In this configuration, the delay time from when “L” is input to the input of the filter circuit to when “L” is output to the output terminal of the filter circuit can be reduced and speeded up compared to the circuit of FIG. it can. Since the operation is the same as that of the embodiment described with reference to FIGS.

  According to the above embodiment, a narrow pulse can be eliminated from an output signal no matter what pulse width is input.

  The inverter device of the present invention is not limited to an IGBT whose switching element is an IGBT, and the same applies to a MOS transistor, a bipolar transistor, or the like.

1 is an overall block diagram of an inverter device according to a first embodiment of the present invention. FIG. 2 is a pulse signal waveform diagram showing a specific example of narrow pulse input in FIG. 1. The specific circuit diagram of the filter circuit by the 1st Embodiment of this invention. 1 is a block diagram of a filter circuit according to a first embodiment of the present invention. The timing chart figure which shows the operation | movement at the time of the minimum on-pulse cut by the 1st Embodiment of this invention. The timing chart figure which shows the operation | movement at the time of the minimum off pulse cut by the 1st Embodiment of this invention. The specific circuit diagram of the filter circuit by the 2nd Embodiment of this invention. The block diagram of the filter circuit by the 2nd Embodiment of this invention. The timing chart figure which shows the operation | movement at the time of the minimum on-pulse cut by the 2nd Embodiment of this invention. The timing chart figure which shows the operation | movement at the time of the minimum off pulse cut by the 2nd Embodiment of this invention. The block diagram of the filter circuit by the 3rd Embodiment of this invention. The specific circuit diagram of the filter circuit by the 3rd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,101 ... One-chip inverter, 11 ... Inverter main circuit, 12 ... Inverter drive circuit, 13 ... Three-phase distribution circuit, 14 ... Protection circuit, 15 ... Logic gate, 16, 17 ... Upper and lower arm drive part, 18, 19 ... Filter circuit, 181, 191 ... Charge / discharge circuit, 182, 192 ... Hysteresis circuit, 31 ... Input terminal, 32 ... Constant speed charge circuit, 321 ... Low speed variable speed charge circuit, 33 ... Constant speed discharge circuit, 331 ... Variable speed discharge Circuit 34 ... Capacitor 35 ... Hysteresis circuit 36 ... Output terminal

Claims (2)

An inverter main circuit including a switching element;
A PWM signal generator;
A drive unit that generates a gate signal to be supplied to the switching element in the inverter main circuit based on the PWM signal;
Means for detecting a change between “1” and “0” of the input PWM signal , and means for detecting that the changed state has continued for a predetermined time; and The output is changed in response to the output of, and the output state is continued while the PWM signal continues even after the elapse of the second predetermined time. A filter circuit for cutting a signal having a predetermined width or less in the input PWM signal;
In an inverter device equipped with
The filter circuit includes a capacitor, a constant speed charging circuit that charges the capacitor in response to one change of the input PWM signal, and a variable speed that discharges the capacitor in response to the other change in the input PWM signal. A discharge circuit and a hysteresis circuit that inputs the voltage of the capacitor and compares it with two different threshold values;
The inverter device , wherein the variable-speed discharge circuit is configured to change a discharge rate in accordance with an output of the hysteresis circuit . An inverter main circuit including a switching element;
A PWM signal generator;
A drive unit that generates a gate signal to be supplied to the switching element in the inverter main circuit based on the PWM signal;
Means for detecting a change between “1” and “0” of the input PWM signal , and means for detecting that the changed state has continued for a predetermined time; and The output is changed in response to the output of, and the output state is continued while the PWM signal continues even after the elapse of the second predetermined time. A filter circuit for cutting a signal having a predetermined width or less in the input PWM signal;
In an inverter device equipped with
The filter circuit includes a capacitor, a variable speed charging circuit that charges the capacitor in response to one change of the input PWM signal, and a constant speed that discharges the capacitor in response to the other change in the input PWM signal. A discharge circuit and a hysteresis circuit that inputs the voltage of the capacitor and compares it with two different threshold values;
The inverter device characterized in that the variable speed charging circuit is configured to change a charging speed in accordance with an output of the hysteresis circuit .

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