JP4417643B2 - Digital radio receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital radio receiver used for digital radio communication, and more particularly to a digital radio receiver capable of expanding a compensation range of carrier offset and improving demodulation characteristics.
[0002]
[Prior art]
In a modulation / demodulation apparatus using a multi-level modulation system typified by a 16QAM modulation system, both the transmission / reception apparatus (modulation / demodulation apparatus) basically modulate / demodulate using a carrier signal from a local oscillator that oscillates at the same local frequency. However, a frequency error occurs due to an accuracy error of the oscillation frequency between the transmitter and the receiver, a temperature variation, a secular change, and the like, and the error appears as a frequency offset (also referred to as a carrier offset) of the received signal.
[0003]
This frequency offset (carrier offset) is solved in the field of next-generation subscriber wireless access (FWA) and in the flow of higher frequency of radio communication (Radio Frequency: RF). This is a big problem, and the importance of carrier offset compensation is increasing.
[0004]
This frequency offset appears as a phase rotation at a constant speed in the received signal after detection in the receiver, and it is necessary to compensate for this frequency offset in order to obtain a correct demodulated signal.
In the case of digital wireless communication, as one of general techniques for compensating for this frequency offset, for example, a signal (unique word: UW) known by both the transmitter and receiver for synchronization supplementation or for equalizer training. ) Is added to the transmission data and transmitted, the phase error is detected from the unique word and the received signal at the receiver side, the averaging process is performed by the PLL circuit, etc., and the voltage value is applied to the voltage controlled oscillator which is a local oscillator. There is a technique for controlling the local oscillation frequency on the receiving side and compensating for the frequency offset by inputting.
[0005]
Another conventional technique for compensating for the frequency offset is a frequency offset compensation circuit using an equalizer.
When the carrier offset is corrected by the carrier offset compensation circuit using the equalizer, the frequency versus error (BER) characteristic has a form as shown in FIG. FIG. 19 is a graph showing a simulation result of frequency versus error (BER) characteristics in a conventional carrier offset compensation circuit.
[0006]
As a conventional technique related to frequency offset compensation, Japanese Patent Laid-Open No. 10-98500 “Automatic Frequency Control Method and Circuit” (Applicant: Kokusai Electric Inc., Inventor: Hiroki Goto) published on April 14, 1998 is disclosed. is there.
In this prior art, a phase difference between a plurality of symbols of a received signal including a known symbol and a variable data symbol as UW is obtained by a delay detector, and a residual phase after removing a modulation component of the variable data symbol based on its output It is an automatic frequency compensation control method and circuit configured to obtain a rotation component with a determiner, obtain a frequency offset estimate with a phase shifter, average with an LPF, and compensate for a frequency error with a complex multiplier. It is possible to widen the frequency offset compensation range of AFC used for baseband signal processing in the system reception demodulation circuit without reducing transmission efficiency.
[0007]
[Problems to be solved by the invention]
However, in the conventional carrier offset compensation circuit, when used in a TDD communication system, the local oscillator cannot be controlled during the transmission period, and therefore measures such as holding the control value at the end of reception are taken. Since a frequency offset corresponding to the stability of the local oscillator in the interval is unavoidable, there is a problem in that when the reception interval is reached, the received signal rotates and cannot be demodulated normally.
[0008]
Further, in the case of a carrier offset correction circuit incorporating an equalizer, there is a problem that the frequency-to-BER characteristic has a shape as shown in FIG. 19 and the range that can correspond to the offset frequency is narrow.
[0009]
The present invention has been made in view of the above circumstances, and uses a carrier offset compensation circuit that enables carrier offset compensation even in TDD communication, widens the range of offset frequencies that can be handled, and enables stable operation. An object of the present invention is to provide a digital radio receiver.
[0010]
[Means for Solving the Problems]
The present invention for solving the problems of the above-described conventional example is a digital wireless receiver in which a decoded signal is obtained by performing waveform equalization while updating tap coefficients based on the received signal and the region determination result of the received signal. A digital radio receiver having a first equalizer that outputs
A multiplier is provided on the input side of the first equalizer to multiply the received signal by a tap coefficient updated by the first equalizer to be an input signal of the first equalizer. As a result, the frequency range in which carrier offset compensation control is possible can be expanded.
[0011]
The present invention for solving the problems of the above conventional example is the digital radio receiver according to claim 1, wherein the output signal of the first equalizer and the output signal are provided on the output side of the first equalizer. Since the second equalizer for outputting the decoded signal by performing waveform equalization while updating the tap coefficient based on the region determination result is provided, only the first equalizer is provided. Then, the carrier offset that could not be tracked is compensated by the second equalizer, the frequency range in which the carrier offset compensation can be controlled is widened, and the frequency-to-BER characteristic can be made horizontal over a wide range.
[0012]
According to the present invention for solving the problems of the conventional example, in the digital radio receiver according to claim 1 or 2, the tap coefficient is updated based on a known signal inserted in the received signal. A third equalizer for performing waveform equalization is provided, and the third equalizer is configured on the input side of the multiplier or between the multiplier and the first equalizer. Therefore, in addition to carrier offset compensation, signal interference components can be removed to compensate for degradation of the propagation path and the like.
[0013]
The present invention for solving the problems of the conventional example described above is the digital wireless receiver according to claim 1 to 3, wherein the initial phase is determined by determining a phase shift from a known signal inserted in the received signal. An initial phase correction unit for correction is provided, and the received signal whose initial phase is corrected is used as an input to the multiplication unit or the third equalizer. The equalization error can be converged at high speed.
[0014]
According to another aspect of the present invention, there is provided a digital radio receiver that determines a phase shift from a known signal inserted in a received signal and outputs an initial phase offset value. An initial phase determination unit is provided, and the third equalizer is an equalizer that sets the initial phase offset value as the initial value of the tap coefficient. Therefore, the initial phase can be determined without providing an initial phase correction unit. Thus, while reducing the circuit scale of the carrier offset compensation circuit, it is possible to avoid the initial signal region determination error and to quickly converge the equalization error.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
The function realizing means described below may be any circuit or device as long as it can realize the function, and part or all of the function can be realized by software. is there. Furthermore, the function realizing means may be realized by a plurality of circuits, and the plurality of function realizing means may be realized by a single circuit.
[0016]
The digital radio receiver according to the present invention corrects an initial phase by determining a phase shift from a known signal inserted in a received signal by an initial phase correction unit, and based on the known signal by a third equalizer. The tap coefficient is updated to perform waveform equalization, the multiplier multiplies the received signal by the tap coefficient updated by the first equalizer, and the first equalizer receives the received signal and its region determination result. Waveform equalization while updating the tap coefficient based on the waveform, and the waveform while updating the tap coefficient based on the output signal of the first equalizer and its region determination result by the second equalizer Since it performs equalization, it avoids mistakes in determining the region of the first signal, increases the convergence speed that minimizes the error between the demodulated signal and the region determination result, widens the range of frequencies that can be controlled by carrier offset compensation, The BER characteristics can also be horizontal over a wide range, Those that can compensate the deterioration of the propagation path and the like by performing the removal of the components.
[0017]
In addition, when the correspondence between each part in the embodiment of the present invention and each part of the drawing is shown, the first equalizer corresponds to the equalizer 3 and the second equalizer corresponds to the equalizer 4. Correspondingly, the third equalizer corresponds to the equalizer 5.
[0018]
First, a digital radio receiver according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of a carrier offset compensation circuit portion of a digital radio receiver according to the first embodiment of the present invention.
[0019]
As shown in FIG. 1, the carrier offset compensation circuit portion (first carrier offset compensation circuit) of the digital radio receiver according to the first embodiment of the present invention includes an initial phase correction unit 1, a multiplication unit 2, and , And an equalizer 3.
In FIG. 1, the received signal and each component are connected by a single arrow. However, the received signal is basically subjected to quadrature detection and separated into I-phase and Q-phase component signals and processed. .
[0020]
Each part of the first carrier offset compensation circuit of the present invention will be described.
The initial phase correction unit 1 detects a phase difference at the head of the frame from a known unique word in the received signal and corrects the phase difference.
As shown in FIG. 20, the normal transmission data is composed of a unique word (UW in the figure) and transmission information (DATA in the figure) in which one frame is known between the transceivers. FIG. 20 shows an example of a frame structure of a signal to be transmitted / received.
[0021]
Therefore, on the transmitting side, as shown in FIG. 20, a unique word (UW) (for example, 14 symbols) known between the transmitter and the receiver is incorporated at the beginning of each frame and transmitted, and the initial phase on the receiving side is transmitted. The phase of each symbol is corrected by the correction unit 1
θ = arcTan (Qr / Ir)
And the arithmetic average of the difference between each UW symbol and the original phase is multiplied by the entire frame as a frame phase (initial phase) correction value.
[0022]
The method for obtaining the symbol phase is not limited to the phase calculation by arcTan, and other real-time phase detection means may be used when performing real-time processing in actual hardware. Absent.
[0023]
The purpose of the initial phase correction is to pass the initial value of the tap coefficient as (1 + j0) in the subsequent equalizer. Therefore, if the first signal region determination is wrong, the convergence of the equalization error will occur. This is because the phase of the first signal is set to a desired phase because it is delayed.
[0024]
The multiplier 2 multiplies the received signal whose initial phase is corrected output from the initial phase corrector 1 by the tap coefficient of one symbol before output from the equalizer 3 described later, and outputs the multiplication result. Is a typical multiplier.
Since the received signal is basically quadrature-detected and separated into I-phase and Q-phase component signals and processed, the multiplication unit 2 is composed of a complex multiplier.
[0025]
The frequency offset is different from fading in that rotation is applied in a certain direction. Therefore, the multiplication unit 2 multiplies the current symbol data by the tap coefficient one symbol before, that is, the frequency at which rotation is applied in a certain direction. This is similar to performing carrier offset compensation while predicting the offset, and thus the range of frequency offset that can be handled is expanded.
[0026]
The equalizer 3 performs waveform equalization while adaptively updating the tap coefficient based on the received signal and its region determination result so as to follow the time-varying carrier offset, and the number of taps is 1 TAP. It is an equalizer.
Specifically, the equalizer 3 determines the area of the received signal, and multiplies the received signal by the tap coefficient while updating the tap coefficient to minimize the error based on the error between the determination result and the received signal. Thus, waveform equalization is performed.
[0027]
In the equalizer 3 of the present invention, a least mean square (LMS) algorithm that minimizes the mean square error based on the steepest descent method, which is a typical tap coefficient updating algorithm, is used.
Since the equalizer 3 is a one-tap equalizer, high-speed processing is possible, responsiveness is good, and stable operation can be expected immediately after the start of communication.
[0028]
Here, an example of the internal configuration of the equalizer 3 in the carrier offset compensation circuit of the digital radio receiver of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing an example of the internal configuration of the equalizer of the present invention.
The internal configuration of the equalizer 3 of the present invention includes a multiplier 31, a determiner 32, an adder 33, and a tap coefficient updater 34.
The multiplier 31 multiplies the input reception signal by the tap coefficient updated by the tap coefficient updater 34 described later.
The determiner 32 determines the area of the data multiplied by the tap coefficient.
The adder 33 is an adder (subtracter) for obtaining a difference (error) between the data multiplied by the tap coefficient and the region determination result.
[0029]
The tap coefficient updater 34 calculates and outputs a tap coefficient that minimizes this error according to the input error.
Here, as the tap update algorithm, a minimum mean square (LMS) algorithm that minimizes the mean square error based on the steepest descent method is used, and the number of taps is configured by 1 TAP.
The initial value of the tap coefficient is (1 + j0), and the initial value is set by being reset for each frame. This is for speeding up the convergence of the equalization error of the equalizer 3 and for facilitating when the first signal is input in the multiplier 2.
[0030]
Next, the operation of the first carrier offset compensation circuit of the present invention will be described with reference to FIG. FIG. 3 is a flowchart showing the operation flow for each symbol in the first carrier offset compensation circuit of the present invention.
In the first carrier offset compensation circuit of the present invention, it is determined whether it is a UW section (100), and if it is a UW section (Yes), the phase is determined by the initial phase correction unit 1 (102), and the UW section ends. If the UW section has not ended (No), the process returns to the process 100 to repeat the UW phase determination.
[0031]
In the process 104, if the UW section is completed (Yes), the initial phase correction unit 1 calculates the frame phase correction value (106), and the tap coefficient update unit 34 of the equalizer 3 is reset. The initial value (1 + j0) is set (108), and the processing 100 is returned to.
[0032]
Then, in the process 100, if the UW section is lost, that is, the DATA portion in FIG. 17 is entered (No), the initial phase correction unit 1 corrects the frame phase based on the frame phase correction value (110), First, the multiplication unit 2 multiplies the initial value (1 + j0) of the tap coefficient and passes it through (112), and also multiplies the initial value (1 + j0) of the tap coefficient in the multiplier 31 in the equalizer 3 and passes it through. Waveform equalization (114), region determination is performed by the determiner 32 (116), an error between the waveform equalization signal and the determination result is obtained by the adder 33 (117), and the tap coefficient updater 34 taps from the obtained error. The coefficient is updated (118), and the process returns to process 100 to repeat waveform equalization and tap coefficient update for the next symbol.
[0033]
Next, the operation results of the first carrier offset compensation circuit shown in FIG. 1 will be described using the specific examples of FIGS. 4 is a diagram illustrating an example of a received signal in the first carrier offset compensation circuit, FIG. 5 is a diagram illustrating an example of an output signal of the initial phase correction unit 1 in the first carrier offset compensation circuit, and FIG. FIG. 4 is a diagram illustrating an example of an output signal of an equalizer 3 in the first carrier offset compensation circuit.
[0034]
As shown in FIG. 4, the received signal input to the initial phase correction unit 1 is modulated: 16QAM, carrier offset amount: 100 Hz, received signal rotation direction: counterclockwise, initial phase deviation: about −58 degrees. And
[0035]
First, the initial phase correction unit 1 detects a phase difference at the head of the frame from UW data inserted in the received frame, and outputs a signal in which the phase difference is corrected.
In the received signal shown in FIG. 4, the initial phase shift is about −58 degrees, so that the phase at the beginning of the frame can be adjusted by rotating and correcting by +58 degrees. 5, the initial phase is corrected by +58 degrees as compared with FIG. 4, and the rotation of the received signal remains.
[0036]
The signal whose initial phase has been corrected is input to the multiplier 2 and multiplied by the tap coefficient from the equalizer 3. Initially, the initial value of the tap coefficient is set to (1 + j0). As a result, the input signal is passed through as it is.
From the second time onward, since the tap coefficient one symbol before output from the equalizer 3 is multiplied, it is expected that the rotation corrected one symbol before will also occur in the next symbol. Therefore, the multiplication unit 2 corrects in advance.
[0037]
The signal output from the multiplier 2 is input to the equalizer 3, multiplied again by the tap coefficient of the initial value (1 + j0) by the multiplier 31, passed through, and subjected to region determination by the determiner 32, and by the adder 33. The determination result from the determination unit 32 is subtracted from the multiplication result of the multiplier 31 to calculate an error. The tap coefficient update unit 34 updates the tap coefficient based on the error, and the tap updated for each signal. The operation of outputting the coefficients to the multiplier 2 and the multiplier 31 is repeated.
[0038]
As a result of operating the circuit in this way, as shown in FIG. 6, phase rotation in a fixed direction is eliminated and correction is made to a position close to a stationary point on orthogonal coordinates, so that carrier offset compensation can be performed. I understand that.
[0039]
Next, another simulation result for obtaining the frequency characteristic of the error rate (BER) in the configuration of the first carrier offset compensation circuit shown in FIG. 1 will be described with reference to FIG. FIG. 7 is a graph showing an error rate (BER) vs. frequency characteristic of a simulation result in the first carrier offset compensation circuit configuration.
[0040]
As simulation conditions, the frame length is 1024 ms = 1024 symbols, the number of frames is 100 frames, the symbol rate is 1 Msps, the modulation method is 16 QAM, the SNR is 18 dB, and the carrier frequency is ± 2000 Hz.
As a specific simulation method, first, as described above, the determination of the phase rotation amount in the initial phase correction unit 1 is obtained by θ = arcTan (Qr / Ir) for each symbol, and the arithmetic average thereof is calculated as follows. The phase (initial phase) correction value is used.
[0041]
When the I-phase component of the received signal is Ir and the Q-phase component is Qr, the initial phase correction outputs I and Q in the initial phase correction unit 1 are
I = Ir × cos (θ) −Qr × sin (θ)
Q = Ir × sin (θ) + Qr × cos (θ)
It is.
[0042]
Substituting these initial phase correction outputs I and Q into variables Xi and Xq and setting tap coefficients as Wi and Wq, multiplication unit 2 outputs Yi and Yq are
Yi = Xi * Wi-Xq * Wq
Yq = Xi × Wq + Xq × Wi
It is.
[0043]
When the output of the determiner 32 is Yid and Yqd, the errors Ei and Eq output from the adder 33 are
Ei = Yi-Yid
Eq = Yq-Yqd
It is.
[0044]
Based on the LMS algorithm from these errors Ei and Eq, the tap coefficient change values dWi and dWq are obtained.
dWi = (Ei × Xi + Eq × Xq) × μ
dWq = (Eq × Xi−Ei × Xq) × μ
It is. Here, μ is a step size parameter.
[0045]
The updated tap numbers Wi and Wq finally output from the tap coefficient updater 34 are:
Wi = Wi-dWi
Wq = Wq-dWq
Then, the output of each unit is simulated while repeatedly updating the tap coefficient.
[0046]
FIG. 7 shows frequency versus error (BER) characteristics simulated with the configuration shown in FIG. 1, with the horizontal axis representing frequency and the vertical axis representing BER.
Compared with the simulation result under the same conditions in the conventional carrier offset compensation circuit shown in FIG. 19, for example, BER = 5 × 10 ^-3 BER = 5 × 10 10 in the conventional configuration of FIG. ^-3 The frequency that can be made below is limited to about ± 500 Hz, but in the configuration of FIG. 1 shown in FIG. 7, the frequency is ± 1000 Hz. It can be seen that the range can be expanded.
[0047]
Next, a digital radio receiver according to the second embodiment of the present invention that further improves the frequency characteristic of the error rate (BER) will be described with reference to FIG. FIG. 8 is a configuration block diagram of a carrier offset compensation circuit portion of the digital radio receiver according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected and demonstrated about the part which has the structure similar to FIG.
[0048]
The carrier offset compensation circuit portion (second carrier offset compensation circuit) of the digital radio receiver according to the second embodiment of the present invention has the same configuration as the first carrier offset compensation circuit as shown in FIG. As shown, an initial phase correction unit 1, a multiplication unit 2, and an equalizer 3 are provided, and an equalizer 4 that is a characteristic part of the second carrier offset compensation circuit is further provided.
[0049]
The configurations and operations of the initial phase correction unit 1, the multiplication unit 2, and the equalizer 3 that are the same as those of the first carrier offset compensation circuit are exactly the same, and thus description thereof is omitted.
The equalizer 4 determines the input signal and the region determination result of the input signal with respect to the carrier offset that cannot be sufficiently tracked by the equalizer 3 with respect to the output signal waveform-equalized by the equalizer 3. Is an equalizer that performs waveform equalization by adaptively updating tap coefficients based on the above.
Specifically, the equalizer 4 determines the area of the input signal, and multiplies the input signal by the tap coefficient while updating the tap coefficient to minimize the error based on the error between the determination result and the input signal. Thus, waveform equalization is performed.
As with the equalizer 3, the tap update algorithm uses the least mean square (LMS) algorithm, the number of taps is 1 TAP, the initial value of the tap coefficient is (1 + j0), and is reset every frame. An initial value is set.
[0050]
The internal configuration of the equalizer 4 is exactly the same as that of the equalizer 3 shown in FIG. 2, but the tap coefficient updated by the tap coefficient updater 34 inside the equalizer 4 is output as an equalizer. 4 is used only in the multiplier 31 inside the circuit 4 and is not output outside the equalizer 4.
[0051]
Next, the operation of the second carrier offset compensation circuit of the present invention will be described with reference to FIGS. 9 to 11 using output examples of simulation results. FIG. 9 is a diagram illustrating an example of an equalizer 3 output signal in the second carrier offset compensation circuit, and FIG. 10 is a diagram illustrating an example of an equalizer 4 output signal in the second carrier offset compensation circuit. FIG. 11 is a graph showing the frequency characteristic of the error rate (BER) in the second carrier offset compensation circuit. The simulation conditions are the same as those for the first carrier offset compensation circuit.
[0052]
The operation of the second carrier offset compensation circuit of the present invention is exactly the same as that of the first carrier offset compensation circuit from the initial phase correction unit 1 to the equalizer 3.
The output waveform from the equalizer 3 is tilted when the equalizer 3 cannot sufficiently follow the carrier offset frequency, so that a signal as shown in FIG. 9 is output. become.
As a result, the region determination is mistaken at the time of decoding, and the frequency-to-error (BER) characteristic has become a bowl shape as shown in FIG.
[0053]
Therefore, in the second carrier offset compensation circuit, the signal output from the equalizer 3 is input to the equalizer 4 and is multiplied by the tap coefficient of the initial value (1 + j0) in the multiplier 31 and passed through. The region is determined by the unit 32, the determination result from the determination unit 32 is subtracted from the multiplication result of the multiplier 31 by the adder 33, an error is calculated, and the tap coefficient update unit 34 updates the tap coefficient based on the error. The operation is repeated, and the tap coefficient updated for each signal is output to the multiplier 31.
Thereby, the inclination of the output from the equalizer 3 is compensated.
[0054]
As shown in FIG. 10, the result of operating the circuit in this way is compensated by correcting a slight inclination of the signal waveform, and is corrected to a point closer to the stationary point on the orthogonal coordinates. It can be seen that the offset compensation is performed with higher accuracy.
FIG. 11 shows frequency versus error (BER) characteristics simulated with the configuration shown in FIG. 8, with the horizontal axis representing frequency and the vertical axis representing BER. The first carrier offset compensation circuit shown in FIG. Compared to the above characteristics, the frequency range in which carrier offset compensation can be controlled is expanded to about ± 1200 Hz, and the frequency-to-error (BER) characteristics are horizontal over a wide range, which shows that the compensation accuracy is improved.
[0055]
Next, a digital radio receiver according to a third embodiment of the present invention that compensates for signal degradation such as waveform distortion in the propagation path will be described with reference to FIG. FIG. 12 is a configuration block diagram of a carrier offset compensation circuit portion of a digital radio receiver according to the third embodiment of the present invention. In addition, the same code | symbol is attached | subjected and demonstrated about the part which has the structure similar to FIG.
The carrier offset compensation circuit portion (third carrier offset compensation circuit) of the digital radio receiver according to the third embodiment of the present invention has the same configuration as the first carrier offset compensation circuit, as shown in FIG. As shown, an initial phase correction unit 1, a multiplication unit 2, and an equalizer 3 are provided, and an equalizer 5 that is a characteristic part of the third carrier offset compensation circuit is further provided.
In FIG. 12, the equalizer 5 is provided between the multiplier 2 and the equalizer 3, but may be provided between the initial phase correction unit 1 and the multiplier 2.
[0056]
The configurations and operations of the initial phase correction unit 1, the multiplication unit 2, and the equalizer 3 that are the same as those of the first carrier offset compensation circuit are exactly the same, and thus description thereof is omitted.
The equalizer 5 is provided for the purpose of compensating for signal degradation in the propagation path, compensating for degradation due to the frequency characteristics of the filter in the transceiver, and removing signal interference components such as signal symbol timing compensation. It is.
[0057]
The number of taps of the equalizer 5 is 10 TAP, the initial value of the tap coefficient is (1 + j0) at the center of the tap, the other is 0, and reset is not performed for each frame.
The tap coefficient of the equalizer 5 is updated by using the least mean square (LMS) algorithm in the same manner as the equalizer 3 from the error with the UW signal using the unique word (UW) which is a known signal in the frame. It is used to update the tap coefficient and perform waveform equalization.
[0058]
Here, a configuration example of the equalizer 5 will be described with reference to FIG. FIG. 13 is a block diagram showing a configuration example of the 10 TAP equalizer 5 in the third carrier offset compensation circuit of the present invention.
The 10 TAP equalizer 5 in the third carrier offset compensation circuit of the present invention includes a waveform equalization filter 51 and a tap coefficient updater 52.
[0059]
The tap coefficient updater 52 calculates an error from the input signal after waveform equalization and a reference sequence of a unique word (UW) that is a known signal, calculates a tap coefficient that minimizes this error, and outputs it. To do.
Here, as the tap update algorithm, a minimum mean square (LMS) algorithm that minimizes the mean square error based on the steepest descent method is used, and the number of taps is 10 TAP.
The waveform equalization filter 51 performs waveform equalization by multiplying the input signal by the tap coefficient output from the tap coefficient updater 52 and adds it to obtain an output signal.
[0060]
Here, the input signal before adaptation is X (n), the output signal after adaptation is Y (n), the step size parameter is μ, the error signal e (n) at the n-th iteration, and at the n-th iteration Assuming that the tap coefficient W (n) and the desired response (reference sequence) R (n), the operation in FIG.
[0061]
W (n + 1) = W (n) +2 μe (n) X ^* (N)
e (n) = R (n) -Y (n) = R (n) -W ^T (N) X (n)
[0062]
Next, the operation of the third carrier offset compensation circuit shown in FIG. 12 will be described using specific examples of FIGS. 14 is a diagram illustrating an example of a received signal in the third carrier offset compensation circuit, FIG. 15 is a diagram illustrating an example of an output signal from the initial phase correction unit 1 in the third carrier offset compensation circuit, and FIG. FIG. 17 is a diagram illustrating an example of an equalizer 5 output signal in the third carrier offset compensation circuit, and FIG. 17 is a diagram illustrating an example of an equalizer 3 output signal in the third carrier offset compensation circuit.
[0063]
Assume that the received signal input to the initial phase correction unit 1 has a received signal waveform including deterioration caused in a propagation path or the like, as shown in FIG.
First, the initial phase correction unit 1 detects the phase difference at the head of the frame from the UW data inserted in the received frame, and outputs a signal in which the phase difference is corrected (FIG. 15). Then, the tap coefficient of one symbol before output from the equalizer 3 is multiplied and input to the equalizer 5 for waveform equalization, and a signal waveform as shown in FIG. 16 is output. This is because the variation in phase and amplitude due to propagation path deterioration is compensated for from the rotation in a certain direction due to carrier offset + phase fluctuation due to propagation path deterioration shown in FIG. Only the rotation remains.
Note that the amount of phase rotation is approximately halved because of the effect of multiplying the tap coefficient one symbol before in the multiplier 2.
[0064]
Next, when this signal is input to the equalizer 3 and the carrier offset is compensated, as shown in FIG. 17, there is no phase rotation in a fixed direction, and the position is corrected to a position close to the stationary point on the orthogonal coordinates. Thus, it can be seen that the carrier offset compensation is performed.
In the configuration of FIG. 12, as in the configuration of FIG. 1, the simulation result of the frequency characteristic of the error rate (BER) becomes a bowl-shaped characteristic as shown in FIG. In order to expand the frequency range in which the offset compensation can be controlled and to obtain horizontal characteristics, the equalizer 3 can be obtained by combining the second carrier offset compensation circuit and adding the equalizer 4 after the equalizer 3. The output can be compensated more accurately, and a demodulated signal with a low error rate can be obtained.
[0065]
Next, a digital radio receiver according to a fourth embodiment of the present invention in which the circuit scale of the third carrier offset compensation circuit is reduced will be described with reference to FIG. FIG. 18 is a configuration block diagram of a carrier offset compensation circuit portion of a digital radio receiver according to the fourth embodiment of the present invention. In addition, the same code | symbol is attached | subjected and demonstrated about the part which has the structure similar to FIG.
The carrier offset compensation circuit portion (fourth carrier offset compensation circuit) of the digital radio receiver according to the fourth embodiment of the present invention has the same configuration as the third carrier offset compensation circuit, as shown in FIG. The initial phase determination unit 6 is provided instead of the initial phase correction unit 1 as a characteristic part of the fourth carrier offset compensation circuit, and includes an equalizer 5. Instead of this, an equalizer 5 'is provided.
In FIG. 18, the equalizer 5 ′ is provided between the multiplier 2 and the equalizer 3, but may be provided between the initial phase correction unit 1 and the multiplier 2.
[0066]
Since the configuration and operation of the multiplier 2 and the equalizer 3 that are the same as those of the third carrier offset compensation circuit are exactly the same, the description thereof is omitted.
The initial phase determination unit 6 detects a phase difference at the head of the frame from a known unique word in the received signal and outputs the phase difference as an initial phase offset correction value.
Specifically, as shown in FIG. 20, since a unique word (UW) (for example, 14 symbols) known between the transmitter and the receiver is incorporated and transmitted at the head of each frame, the symbol is transmitted for each symbol. Phase
θ = arcTan (Qr / Ir)
And a value obtained by arithmetically averaging the difference from the original phase of each symbol of UW is set as a frame phase (initial phase) offset correction value.
[0067]
The method for obtaining the symbol phase is not limited to the phase calculation by arcTan, and other real-time phase detection means may be used when performing real-time processing in actual hardware. Absent.
[0068]
Similarly to the equalizer 5 of the third carrier offset compensation circuit, the equalizer 5 ′ compensates for signal degradation in the propagation path, compensates for degradation due to the frequency characteristics of the filter in the transceiver, and compensates for signal symbol timing. The initial value of the tap coefficient is different.
[0069]
That is, the equalizer 5 ′ of the fourth carrier offset compensation circuit has a tap number of 10 TAP, and the initial value of the tap coefficient is the initial phase offset correction value input from the initial phase determination unit 6 at the tap center. Is set to 0, and reset is not performed for each frame.
[0070]
Then, the tap update of the equalizer 5 is performed by updating the tap using the least mean square (LMS) algorithm in the same manner as the equalizer 3 based on the error from the UW signal using the UW in the frame, thereby equalizing the waveform. Is to do.
As a characteristic part of the fourth embodiment, by inputting an initial phase offset correction value at the center of the tap, a signal can be output to the equalizer 3 in the subsequent stage while returning the initial phase.
[0071]
Next, the operation of the fourth carrier offset compensation circuit shown in FIG. 18 will be described.
In the fourth carrier offset compensation circuit of the present invention, the received signal is input to the initial phase determination unit 6, the phase difference at the head of the frame is detected from the UW data inserted in the received frame, and the initial phase offset correction is performed. A value is output, and the initial phase offset correction value is set as an initial value of the tap coefficient by the equalizer 5 '.
The multiplier 2 multiplies the received signal by the tap coefficient of one symbol before from the equalizer 3 and inputs it to the equalizer 5 'to perform waveform equalization, thereby performing initial phase correction and propagation path degradation. Phase and amplitude fluctuations are compensated for, and a signal waveform as shown in FIG. 16 is output.
The subsequent operation is the same as that of the third carrier offset compensation circuit.
[0072]
With the above processing, even if a signal is received at a position where the phase at the head of the frame is different every time due to the carrier offset, it is detected by the initial phase determination unit 6 but is detected by the equalizer 5 ′ according to the initial phase offset correction value. Thus, the initial phase can be instantaneously corrected, and the correction can be realized without providing the initial phase correction unit 1, so that the carrier offset compensation circuit can be reduced in scale to realize highly accurate carrier offset compensation.
[0073]
Next, as a digital radio receiver according to the fifth embodiment of the present invention, the above-mentioned second and third carrier offset compensation circuits suggested in the 64th paragraph are combined, and the baseband demodulation of the millimeter wave band FWA is performed. The digital wireless receiver applied to the unit will be described.
[0074]
FIG. 21 is a diagram illustrating a radio frame configuration of the digital radio receiver according to the fifth embodiment of the present invention. In order to perform TDD (time division division) communication, the radio frame is divided into an upper level and a lower level. The data in the radio frame is logically divided into 12 blocks, and is assigned to the upper and lower frames between 1 to 11 and 11 to 1 according to the setting of the TDD ratio considering transmission and reception traffic. A GT (guard time) of 18.96 μs is provided after the upper and lower frames, assuming a propagation delay of 4 km at the maximum.
[0075]
A control channel (DCCH: Down link Control Channel or UCCH: Up link Control CHannel) is provided at the head of the upper and lower frames. The control channel includes a leading AGC (Auto Gain Control) symbol followed by a UW (unique word). The AGC symbol is a simple known symbol string composed of 14 symbols, and is used for AGC control and initial phase correction. The UW is a concatenation of 8.5 PN (Pseudo Noise) codes of 15 symbols, and is used for frame synchronization, clock synchronization, AFC control, and equalizer training. The transmission rate is 6.75 M symbol / sec.
[0076]
FIG. 22 is a block diagram of the baseband demodulator of the digital radio receiver according to the fifth embodiment of the present invention. Explaining along the signal flow, the IF (intermediate frequency) signal centered at 13.5 MHz is controlled to an appropriate amplitude by AGC, then A / D conversion, IQ component separation, quadrature detection, and root roll The received complex baseband signal is regenerated by passing through a roll-off filter 7 having an off characteristic. Thereafter, the received complex baseband signal is adjusted in the initial phase at the head of the frame by the initial phase correction unit 1 ′ in order to improve the convergence characteristics of the equalizer, and then the distortion generated in the transmission line and in the apparatus in the equalizer 5 Component compensation is mainly performed, carrier offset compensation is performed in the equalizers 3 and 4, and then soft decision Viterbi decoding is performed in the region determination unit 8 to obtain decoded data. All decoded data is subjected to a transmission error check in the radio frame in the CRC calculation unit, and the radio frame data in which an error has occurred is discarded.
[0077]
The initial phase correction unit 1 ′ has substantially the same configuration and function as the initial phase correction unit 1 and the like of the first embodiment, but obtains a calculated value from the tap coefficient updater 52 for simplification of calculation. .
The equalizers 3 and 4 are 1-tap equalizers that operate at intervals of one symbol. Although not clearly shown in FIG. 2, the tracking mode operation using the symbol point determination result for the reference sequence is performed in the data portion, and the UW portion is operated in the training mode using the known UW as the reference sequence. This operation is common as an equalizer for wireless communication. As hardware, all of them are composed of FPGAs including calculation of filter coefficients.
The equalizer 5 is a linear equalizer with 10 taps using an LMS algorithm having a small calculation processing load similar to that of the third embodiment as shown in FIG. Such an equalizer is suitable for a case where multipath is not remarkable and the time variation of the line state is small as in FWA, and the main purpose is not to compensate for a delayed wave. Further, as is apparent from FIG. 13, it is an equalizer in the training mode and does not update the tap coefficient in the section other than UW, and simply operates as a filter. The step gain μ is 0.25. As hardware, a filter coefficient is calculated by a DSP corresponding to the tap coefficient updater 52, and the result is given as a coefficient input of a digital filter IC corresponding to the waveform equalization filter 51.
[0078]
The roll-off filter 7 has α = 0.3 and 63 taps.
The carrier synchronization unit 9 configures a PLL (Phase Locked Loop) using phase error information observed from the UW symbol position and controls a VCXO (Voltage Controlled Crystal Oscillator) 10 to realize AFC (Auto Frequency Control). . The VCXO10 is broad because the frequency variable range is set as wide as ± 160KHz considering the secular change of the oscillator used for the millimeter wave band circuit and the phase error tracking performance of the carrier synchronization unit 9 is emphasized. Although carrier offset can be removed by AFC, it is difficult to ensure short-term stability, and fluctuations of about ± 150 Hz occur. It is the equalizers 3 and 4 that compensate for this. In FIG. 22, the carrier synchronization unit 9 obtains the phase error information from the equalizer 3, but is not limited thereto, and may be obtained from the equalizer 5 or separately calculated.
The symbol synchronization unit performs PLL control based on the phase error information using the correlation value of the UW part, and reproduces the symbol timing with the VCXO 11 having a center frequency of 108 MHz. This clock is a source of a timing clock used in the demodulator. In 1024QAM, since the eye opening width is about 4 ns (2.7% in symbol period ratio), the clock jitter is 2 ns or less.
The frame synchronization AGC control system synchronization unit performs frame synchronization, AGC control, and system synchronization from the AGC symbol and UW. The obtained frame timing is supplied to each part of the apparatus such as the initial phase correction unit 1 and the equalizers 3, 4, and 5.
[0079]
In the following, verification by simulation or the like will be described as a process leading to the configuration of the present embodiment. The simulation conditions are the same as those of the above-described millimeter-band FWA baseband demodulator according to the present embodiment unless otherwise specified.
First, the effect of the carrier frequency offset when the equalization process is performed by the 10-tap equalizer 5 alone was verified by computer simulation (simulation 1). As simulation conditions, the input data is 16 frames, the initial phase is 0, the word length is not limited, and the SAW filter characteristics are included.
23 to 25 show the pre-equalization (equalizer 5 input signal) constellation, the equalization (equalizer 5 output signal) constellation, and the equalization error convergence characteristics when the frequency offset is 15 Hz, respectively. Show. As shown in FIG. 24, a slight inclination remains in the post-equalization constellation, and symbol points that cannot be distinguished from adjacent symbol points can be seen. In FIG. 25, it can be seen that the error does not converge but vibrates. Note that the equalized error power DUR (Desired to Undesired single power ratio) on the vertical axis in FIG. 25 is defined as the power ratio between the ideal constellation when demodulating the modulation signal and the vector error therefrom. This is an equivalent value to a modulation error ratio MER (Modulation Error Ratio), which is a measure for evaluating the quality of the modulation signal.
FIG. 26 shows DUR values for various frequency offset amounts. The DUR value in the figure is a DUR value averaged after convergence or in a vibration state. It was found that if there is even a slight phase rotation due to the frequency offset, the convergence characteristics are affected and vibration occurs. In the configuration of this simulation, in order to achieve 47 dB, which is the target value of the waveform equalization error, the frequency offset must be suppressed to about 1 Hz. As a trial, a simulation was performed by operating the equalizer 5 in the tracking mode in the data portion. However, the DUR was 32 dB with respect to the offset of 100 Hz, which is not enough. As a means for solving this, it is conceivable to improve the convergence characteristics by using a fast adaptive algorithm such as RLS (Recursive Least Square). However, RLS has a large calculation amount and a data transmission delay due to a processing delay occurs, which is not desirable. .
[0080]
Next, with the configuration as shown in FIG. 27 provided with the equalizer 3 in addition to the equalizer 5, the influence of the carrier frequency offset was verified by computer simulation (simulation 2). The equalizer 3 is expected to function as a phase rotator that compensates for the residual phase error. In this simulation, since the initial phase correction unit 7 is also included, 70 degrees is given as an initial phase error, the offset frequency is 32 Hz, and the signal width (word length limit) is 12 bits.
FIG. 28 to FIG. 31 show output signals from the roll-off filter 7, the initial phase correction unit 1, the equalizer 5, and the equalizer 3 as simulation results, respectively. As can be seen from the equalizer 3 output of FIG. 31, it can be seen that the frequency offset component has disappeared.
FIG. 32 shows the frequency versus BER characteristics in the range of the offset frequency of −300 to 300 Hz. As simulation conditions, SNR is 36 dB, word length is limited, and SAW filter characteristics are included. From FIG. 32, it can be seen that the offset frequency can be compensated in the range of ± 200 Hz, but this is insufficient, and a bowl-shaped characteristic similar to FIG. 7 appears within the compensation range.
[0081]
Next, the influence of the carrier frequency offset was verified by computer simulation with the configuration including the equalizers 5 and 3 and the multiplier 2 (Simulation 3). As a configuration, the multiplier of FIG. 12 is added to the configuration of FIG. By providing the multiplier 2 that pre-multiplies the input signal to the equalizer 5 by the phase correction value (the tap coefficient itself) calculated by the equalizer 3, the burden of the tap coefficient tracking operation of the equalizer 5 is reduced. Expected to reduce effect.
FIG. 33 shows the frequency versus BER characteristics in the range of the offset frequency of −600 to 600 Hz. The simulation conditions are the same as in simulation 2. From FIG. 32, it can be seen that the compensation range of the offset frequency is almost twice that of the simulation 2, but the bowl-shaped characteristic in which the BER deteriorates as the offset frequency increases remains. It shows that the phase error cannot be completely removed.
[0082]
Next, the influence of the carrier frequency offset was verified by computer simulation with the configuration including the equalizers 5, 3, 4 and the multiplier 2 (simulation 4). As a configuration, the equalizer 4 of FIG. 8 is added to the configuration of the simulation 3 and corresponds to the configuration adopted in the baseband demodulation unit of FIG. The equalizer 4 is a one-tap equalizer similar to the equalizer 3, and is expected to have an effect of removing the residual phase error of the equalizer 3 and improving the BER with a light operation.
FIG. 34 shows the frequency versus BER characteristics in the range of the offset frequency of −600 to 600 Hz. The simulation conditions are the same as in simulation 3. From FIG. 32, it was confirmed that the offset frequency compensation range is the same as that of the simulation 3, but a horizontal frequency versus BER characteristic is obtained instead of the bowl shape.
[0083]
Next, processing of the symbol synchronizer of the baseband demodulator of the digital radio receiver according to the fifth embodiment of the present invention will be described. In this embodiment, since TDD adaptively changes, if a phase error is detected from the symbol of the data portion, the phase synchronization unit needs to be controlled according to the TDD ratio, and the circuit configuration becomes complicated. Therefore, the symbol synchronization unit of the present embodiment detects a phase error using UW, which is information that does not change for each frame.
FIG. 35 is a diagram for explaining phase error detection by UW correlation. The timing at which the correlation value becomes maximum when ideal symbol synchronization is achieved is tp, the timing of the immediately preceding and subsequent samples is tp−1 and tp + 1, respectively, and the correlation values of the three timings are indicated by circles. When the phase of the internal clock controlled by the symbol synchronizer is advanced, the correlation value indicated by the square is shifted and the correlation value indicated by the triangle is obtained when the timing is reversed. Therefore, if the difference between the correlation values at tp−1 and tp + 1 is taken, the delay is positive and the advance is negative, and the phase error amount is obtained. Based on this, a signal for controlling the VCXO 11 can be calculated.
[0084]
Finally, in the digital wireless receiver of this embodiment, CNR vs. BER characteristics are shown in FIG. 36 as a result of a laboratory experiment using wireless hardware. The condition of the experiment of FIG. 36 is that the transmitter and the receiver are connected via a transmission line with an IF of 13.5 MHz, and the BER before error correction is obtained without using the equalizer 4. By adding the equalizer 3, the error floor of 1024QAM can be eliminated.
In the above description of the digital radio receiver according to the embodiment of the present invention, 16QAM and 1024QAM have been described as examples. However, the technology of the present invention can be applied to other phase modulation schemes (QPSK, etc.). .
[0085]
According to the digital radio receiver according to the embodiment of the present invention, the multiplier unit 2 is provided on the input side of the equalizer 3 (first equalizer) for compensating for the carrier offset so as to equalize the received signal. Since the tap coefficient one symbol before output from the unit 3 is multiplied, it is similar to performing carrier offset compensation while predicting a frequency offset to which rotation is applied in a certain direction, and quickly performing carrier offset compensation. Therefore, there is an effect that the range of the frequency offset that can be dealt with is widened to enable stable operation.
[0086]
Moreover, according to the digital radio receiver according to the embodiment of the present invention, the initial phase correction unit 1 detects the phase difference at the head of the frame from the unique word of the received signal, corrects the phase difference, Since the signal region determination error is avoided, the equalization error can be converged at high speed, so that it is possible to realize a stable operation immediately after the start of communication.
[0087]
According to the digital radio receiver according to the second embodiment of the present invention, the second equalization is further performed after the equalizer 3 (first equalizer) for compensating the carrier offset. Since the equalizer 4 which is an equalizer is provided, the equalizer 4 compensates for the carrier offset that cannot be followed by the equalizer 3 alone, thereby expanding the frequency range in which the carrier offset compensation control is possible. The BER characteristic can also be horizontal over a wide range, and there is an effect that the compensation accuracy can be improved and stable operation can be realized.
[0088]
Further, according to the digital radio receiver according to the third embodiment of the present invention, 10 tap equalization is a third equalizer that performs waveform equalization while updating tap coefficients using UW. Since the device 5 is provided, in addition to the carrier offset compensation, there is an effect that the interference component of the signal is removed to compensate for the deterioration of the propagation path and the like, thereby enabling a stable operation.
[0089]
Further, according to the digital radio receiver according to the fourth embodiment of the present invention, the initial phase determination unit 6 detects the phase difference at the head of the frame to obtain the initial phase offset correction value. Since the initial phase offset correction value is set to the initial value of the tap coefficient of the equalizer 5 'which is an equalizer and the waveform is equalized, the equalizer 5' not only compensates for the deterioration of the propagation path but also the initial phase. The initial phase correction can be realized without providing the initial phase correction unit 1, and the equalization is performed while reducing the circuit scale of the carrier offset compensation circuit and avoiding the first signal region determination error. Since error convergence can be performed at high speed, there is an effect that stable operation can be realized immediately after the start of communication.
[0090]
【The invention's effect】
According to the present invention, the multiplier multiplies the received signal by the tap coefficient one symbol before the first equalizer updates and outputs it as the input signal of the first equalizer. Since it is a digital radio receiver that outputs a decoded signal by performing waveform equalization while updating tap coefficients based on the input signal and its area determination result, the carrier predicts the frequency offset to which rotation is applied in a certain direction This is the same as performing offset compensation, and there is an effect that the range of the frequency offset that can be dealt with is widened to enable stable operation.
[0091]
According to the present invention, the second equalizer is provided on the output side of the first equalizer, and the second equalizer uses the output signal of the first equalizer and its region determination result. The digital wireless receiver according to claim 1, wherein the digital wireless receiver outputs the decoded signal by performing waveform equalization while updating the tap coefficient, so that the carrier offset that could not be tracked by the first equalizer alone is changed to the second value. Compensating with an equalizer expands the frequency range in which carrier offset compensation can be controlled, and the frequency-to-BER characteristic can also be horizontal over a wide range, improving the compensation accuracy and enabling stable operation. is there.
[0092]
According to the present invention, a third equalizer is provided on the input side of the multiplier or between the multiplier and the first equalizer, and is inserted into the received signal by the third equalizer. The digital radio receiver according to claim 1 or 2, wherein waveform equalization is performed while updating tap coefficients based on a known signal, so that in addition to carrier offset compensation, signal interference components are removed. Thus, it is possible to compensate for deterioration of the propagation path and the like to enable stable operation.
[0093]
According to the present invention, the initial phase correction unit determines the phase shift from the known signal inserted in the received signal to correct the initial phase, and the received signal whose initial phase is corrected is multiplied by the multiplier or the third unit. Since the digital wireless receiver according to claim 1 is used as an input to the equalizer, it is possible to avoid an error in determining the area of the first signal and to converge the equalization error at high speed. There is an effect that a stable operation can be realized immediately after the start.
[0094]
According to the present invention, the initial phase determination unit determines the phase shift from the known signal inserted in the received signal and outputs the initial phase offset value, and the third equalizer converts the initial phase offset value to the tap coefficient. 4. The digital wireless receiver according to claim 3, wherein the initial signal is set as an initial value of the first signal, so that the initial phase can be corrected without providing an initial phase correction unit, and the circuit scale of the carrier offset compensation circuit is reduced, and the first signal is corrected. Thus, the equalization error can be converged at a high speed while avoiding the region determination error, so that it is possible to realize a stable operation immediately after the start of communication.
[Brief description of the drawings]
FIG. 1 is a configuration block diagram of a carrier offset compensation circuit portion of a digital radio receiver according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating an internal configuration example of an equalizer according to the present invention.
FIG. 3 is a flowchart showing a flow of operation for each symbol in the first carrier offset compensation circuit of the present invention.
FIG. 4 is a diagram showing an example of a received signal in the first carrier offset compensation circuit of the present invention.
FIG. 5 is a diagram illustrating an example of an output signal of an initial phase correction unit in the first carrier offset compensation circuit of the present invention.
FIG. 6 is a diagram showing an example of an equalizer output signal in the first carrier offset compensation circuit of the present invention.
FIG. 7 is a graph showing an error rate (BER) vs. frequency characteristic of a simulation result in the first carrier offset compensation circuit configuration of the present invention.
FIG. 8 is a configuration block diagram of a carrier offset compensation circuit portion of a digital radio receiver according to a second embodiment of the present invention.
FIG. 9 is a diagram illustrating an example of an equalizer 3 output signal in the second carrier offset compensation circuit of the present invention.
FIG. 10 is a diagram showing an example of an output signal of an equalizer 4 in the second carrier offset compensation circuit of the present invention.
FIG. 11 is a graph showing frequency characteristics of error rate (BER) in the second carrier offset compensation circuit of the present invention.
FIG. 12 is a configuration block diagram of a carrier offset compensation circuit portion of a digital radio receiver according to a third embodiment of the present invention.
FIG. 13 is a block diagram showing a configuration example of a 10 TAP equalizer 5 in the third carrier offset compensation circuit of the present invention.
FIG. 14 is a diagram showing an example of a received signal in the third carrier offset compensation circuit of the present invention.
FIG. 15 is a diagram illustrating an example of an output signal of an initial phase correction unit in a third carrier offset compensation circuit of the present invention.
FIG. 16 is a diagram showing an example of an output signal of the equalizer 5 in the third carrier offset compensation circuit of the present invention.
FIG. 17 is a diagram illustrating an example of an equalizer 3 output signal in the third carrier offset compensation circuit of the present invention.
FIG. 18 is a configuration block diagram of a carrier offset compensation circuit portion of a digital radio receiver according to a fourth embodiment of the present invention.
FIG. 19 is a graph showing a simulation result of frequency versus error (BER) characteristics in a conventional carrier offset compensation circuit.
FIG. 20 shows an example of a frame configuration of a signal to be transmitted / received.
FIG. 21 is a radio frame configuration diagram of a digital radio receiver according to a fifth embodiment.
FIG. 22 is a block diagram of a baseband demodulation unit of a digital radio receiver according to a fifth embodiment.
FIG. 23 shows an input signal of the equalizer 5 in the simulation 1;
FIG. 24 shows an output signal of the equalizer 5 in the simulation 1;
FIG. 25 shows equalization error convergence characteristics of the equalizer 5 in simulation 1;
FIG. 26 is a D / U value with respect to the frequency billion set amount of the equalizer 5 in the simulation 1;
FIG. 27 is a block diagram assumed in simulation 2;
FIG. 28 is an output signal of the roll-off filter 7 in the simulation 2;
29 shows an output signal of the initial phase correction unit 1 in simulation 2. FIG.
30 shows an output signal of the equalizer 5 in the simulation 2. FIG.
FIG. 31 shows an output signal of the equalizer 3 in the simulation 2;
FIG. 32 shows frequency offset versus BER characteristics in simulation 2;
FIG. 33 shows frequency offset versus BER characteristics in simulation 3;
FIG. 34 shows frequency offset versus BER characteristics in simulation 4.
FIG. 35 is a diagram illustrating phase error detection using UW correlation in the fifth embodiment.
FIG. 36 shows CNR versus BER characteristics of the digital radio receiver according to the fifth embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Initial phase correction part, 2 ... Multiplication part, 3 ... Equalizer (1TAP), 4 ... Equalizer (1TAP), 5, 5 '... Equalizer (10TAP), 6 ... Initial phase determination part, 31 DESCRIPTION OF SYMBOLS ... Multiplier 32 ... Determinator 33 ... Adder 34 ... Tap coefficient updater 51 ... Waveform equalization filter 52 ... Tap coefficient updater 7 ... Roll-off filter 8 ... Area determination part 9 ... Carrier Synchronization part

Claims (4)

A digital radio receiver comprising: a complex multiplier that complex-multiplies a received signal by a tap coefficient; and a 1 TAP first equalizer that performs waveform equalization of a signal input from the complex multiplier and outputs a demodulated signal Because
The first equalizer is configured to minimize an error based on an error between a signal obtained by performing complex multiplication of a tap coefficient on an input signal from the complex multiplier and a region determination result of the signal. Performing waveform equalization by complex multiplying the input signal with the tap coefficient while updating the tap coefficient, and outputting a decoded signal,
The digital wireless receiver, wherein the complex multiplier performs complex multiplication on a received signal with a tap coefficient updated by the first equalizer to obtain an input signal of the first equalizer. On the output side of the first equalizer, the error is minimized so as to minimize an error based on an error between a signal obtained by complex-multiplying the output signal of the first equalizer by a tap coefficient and a region determination result of the signal. Provided is a 1 TAP second equalizer that performs waveform equalization by complexly multiplying the output signal of the first equalizer while updating the tap coefficient to output a decoded signal. The digital radio receiver according to claim 1. Waveform equalization by complexly multiplying the input signal with the tap coefficient while updating the tap coefficient to minimize the error based on the error between the signal obtained by multiplying the input signal by the tap coefficient and the known signal A third equalizer is provided, and the third equalizer is configured on the input side of the complex multiplier or between the complex multiplier and the first equalizer. The digital radio receiver according to claim 1 or 2. An initial phase correction unit that corrects an initial phase by complex-multiplying the reception signal with a phase error between a reception signal and a known signal is provided, and the reception signal whose initial phase is corrected is converted to the complex multiplier or the third 4. The digital radio receiver according to claim 1, wherein the digital radio receiver is used as an input of an encoder.

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