JP4408696B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device that needs to set a state of a word line voltage or a read reference voltage during a read operation.

  In a memory such as a DRAM or FLASH, it may be necessary to generate a high word line voltage during a read operation or to generate a read reference voltage for comparison with a differential amplifier circuit of a sense amplifier. When the generated voltage is required to be highly accurate in order to achieve high performance and high reliability with these memories, in order to compensate for the effects of manufacturing variations, laser fusing type and large current fusing type A fuse element is provided as a non-volatile element, and trimming processing of the fuse element is performed in an inspection process. In addition, these fuse elements are often used not only for read operations but also for memory operation status settings such as rewriting and function settings when there are product types.

  However, the fuse element is larger than the element area of the transistor mounted on the LSI, and has a demerit that the manufacturing cost is increased by increasing the trimming process, and trimming after the trimming process cannot be performed again.

  By the way, in an LSI equipped with a rewritable nonvolatile memory such as FLASH, trimming parameters such as state setting and function setting can be stored in the memory, so that trimming by rewriting can be performed again. The benefits of this are great. An increase in area in the case of a fuse element can also be suppressed. However, the state cannot be determined statically like a fuse element.

  When trimming parameters such as state settings and function settings stored in the memory are required during a read operation, there is a problem in reading them correctly. For example, in a product in which the word line voltage needs to be corrected by trimming by +0.5 V due to manufacturing variations of the word line voltage regulator, when reading the information “+0.5 V”, the word line voltage is increased by 0.5 V. The read operation must be performed in an incomplete state where there is a shortage. In other words, even if the reading speed is reduced, a product that cannot be stably trimmed can only be judged defective in the inspection process. In this case, even if the product has no defects in the rewrite characteristics of the memory cell or the voltage regulator itself to be trimmed, it is erroneously determined as defective.

  FIG. 12 shows a nonvolatile semiconductor that stores trimming parameters for word line voltage trimming processing in a memory area in a memory product that is required to generate a high-accuracy high-voltage word line voltage during a conventional read operation. It is a block diagram which shows the whole structure of a memory | storage device.

  In FIG. 12, reference numeral 1 denotes a memory cell array composed of a plurality of word lines, a plurality of bit lines, and electrically rewritable nonvolatile memory cells arranged in a matrix at their connection points, and 2 denotes a memory cell array 1. Trimming parameter area for storing trimming parameters, 3 is an address buffer, 4 is a row decoder, 5 is a row decoder for trimming parameter area, 6 is a column decoder, 7 is a sense amplifier, 8 is an input / output buffer, and 9 is for trimming parameters. The parameter holding circuit 10 generates a voltage to be applied to the word line of the memory cell array 1 and has a function of adjusting the voltage value by the voltage adjustment parameter 17, 11 a control circuit, 12 a row address, 13 Is the row address for the trimming parameter area, 14 Column address, 15 is a trimming parameter address assigned to the parameter holding circuit 9, 16 is a bidirectional data bus, 17 is a voltage adjustment parameter for the word line voltage regulator 10, and 18 is a voltage generated by the word line voltage regulator 10. Is a word line voltage power supply line, 19 is an initial setting signal input in synchronization with a detection signal or reset signal of a power-on detection circuit after the power is turned on or after a system reset is released, and 20 receives an initial setting signal 19 The trimming parameter address generated by the control circuit 11 during the trimming process, 21 is a word line voltage regulator activation signal for activating the word line voltage regulator 10, 22 is a sense amplifier activation signal for activating the sense amplifier 7, Is the trim read by the parameter holding circuit 9 Parameters latch signal for taking the grayed parameters from the data bus 16, 24 is an input-output control signal for performing output control of the output buffer 8 and external data.

  The address buffer 3 is connected such that a row address 12, a trimming parameter area row address 13, a column address 14, and a trimming parameter address 15 are output. The sense amplifier 7 is connected to the input / output buffer 8 and the parameter holding circuit 9 via a data bus 16. The trimming parameters held by the parameter holding circuit 9 are connected so as to be given to the word line voltage regulator 10 as voltage adjustment parameters 17. The word line voltage power supply line 18 for transmitting the potential generated by the word line voltage regulator 10 is connected to the word line through the row decoder 4 and the trimming parameter area row decoder 5 so as to be supplied to the word line. The control circuit 11 also receives a clock signal for memory operation, a mode signal for setting various modes such as reading and rewriting, and an initial setting signal 19.

  The operation of the conventional nonvolatile semiconductor memory device configured as described above will be described below with reference to FIG. 12 and FIG. 13 showing the internal flow during the trimming process.

  First, when the initial setting signal 19 is activated (S1 in FIG. 13) and input to the control circuit 11 after the power is turned on or after the system reset is released, all the latch circuits in the parameter holding circuit 9 are cleared and the word The line voltage regulator activation signal 21 is activated, and the word line voltage regulator 10 starts operating (S2 in FIG. 13). After the stabilization wait of about several microseconds (S3 in FIG. 13), a stable voltage is supplied from the word line voltage power supply line 18 to the row decoder 4 and the trimming parameter region row decoder 5 for the trimming parameter region. A word line and a bit line are selected according to the row address 13 and the column address 14. That is, the word line and the bit line corresponding to the memory cell storing the trimming parameter in the trimming parameter area 2 are selected. As a result, the sense amplifier activation signal 22 is activated, and the trimming parameters are output to the data bus 16 (S4 in FIG. 13). Then, the trimming parameters are latched in a predetermined latch circuit in the parameter holding circuit 9 according to the trimming parameter address 15 in synchronization with the parameter latch signal 23 (S5 in FIG. 13). Next, the latched trimming parameter is given to the word line voltage regulator 10 as the voltage adjustment parameter 17 (S6 in FIG. 13), and the trimming process is completed after waiting for stabilization of about several microseconds (S7 in FIG. 13).

  Next, an example of an inspection flow for confirming the trimming function in the inspection process will be described below with reference to FIG. In FIG. 14, the same inspection flow may be used not only in the related art but also in the nonvolatile semiconductor memory device of the present invention.

  First, an inspection pattern such as a checker is stored in the memory cell array 1 (S10 in FIG. 14), and a desired word line voltage is externally supplied from the tester to the word line voltage power supply line 18 for a product that has been determined to be non-defective in the previous inspection process The inspection pattern stored in the memory cell array 1 is read out (S12 in FIG. 14). If the test pattern does not match the expected value, a failure is determined (S13 in FIG. 14). If the test pattern matches, the read / rewrite test of the memory cell array 1 is determined to be good, and the process proceeds to the next test.

  Next, reset and reset release (S14 in FIG. 14) are entered, the initial setting signal 19 is activated, and all the latch circuits in the parameter holding circuit 9 are cleared. After the voltage of the word line voltage regulator 10 is generated and stabilized, the voltage value of the word line voltage power supply line 18 is monitored by a tester (S15 in FIG. 14). Thereby, a default voltage value without trimming is measured. Here, if the default voltage value is outside the trimming range, a failure is determined (S16 in FIG. 14), and if it is within the trimming range, a good determination is made. Next, different trimming parameters for each product are input to the parameter holding circuit 9 via the input / output buffer 8 in accordance with the voltage adjustment table held by the external tester (S17 in FIG. 14). After the voltage of the word line voltage regulator 10 is stabilized, the voltage value of the word line voltage power supply line 18 is monitored by a tester (S18 in FIG. 14). If the result of monitoring is outside the inspection standard, a failure is determined (S19 in FIG. 14), and if it is within the inspection standard, the function confirmation test of the word line voltage regulator 10 and the parameter holding circuit 9 is determined to be good and trimming parameters are trimmed. Store in the parameter area 2 (S20 in FIG. 14), and then proceed to the next test.

  Next, reset and reset release (S21 in FIG. 14) are entered, the initial setting signal 19 is activated, and all the latch circuits in the parameter holding circuit 9 are cleared. Then, the word line voltage trimming (S22 in FIG. 14) of the word line voltage from the memory whose internal operation has been described with reference to FIGS. 12 and 13 is performed, and the word line voltage power supply line 18 is stabilized after the voltage of the word line voltage regulator 10 is stabilized. Is monitored with a tester (S23 in FIG. 14). At this time, if it is outside the inspection standard, a failure is determined (S24 in FIG. 14), and if it is within the inspection standard, all the trimming functions are determined to be good, and the process proceeds to the next inspection step.

  The problem here is that the read / rewrite test of the memory cell array 1 is judged as good and the function check test of the word line voltage regulator 10 and the parameter holding circuit 9 is judged as good. The failure due to the trimming (S24 in FIG. 14) occurs due to the read failure caused by reading the trimming parameter with the word line voltage.

  Next, with reference to FIG. 15 showing the influence of the variation in the word line voltage on the threshold distribution of the memory cell, the reason why the reading failure occurs due to reading the trimming parameter with the default word line voltage before trimming. Will be explained. FIG. 15A shows a case where there is no variation in the default word line voltage and a good determination is made. FIG. 15B shows a case where there is a variation but a good determination is made, and FIG. 15C shows a case where there is a variation and a failure is judged.

  First, after the memory cell storing the trimming parameter is rewritten, the threshold width of the memory cell with the read reference voltage (Vref) 30 as the center is the “1” side threshold value 31 and the “0” side threshold value. It is a condition for correct reading to be secured to ΔVread of 32 or more.

  Here, regarding the threshold distribution 33 of the “1” data and the threshold distribution 34 of the “0” data, when the word line voltage varies by −ΔVwl, they are shifted as shown by 35 and 36, respectively, or the variation width. When (−ΔVwl) is large, it is greatly displaced like 37 and 38. Similarly, if it is varied by + ΔVwl, it will be shifted as 39 and 40, respectively, or if the variation width (+ ΔVwl) is large, it will be largely shifted as 41 and 42.

  At this time, the product of FIG. 15B in which the deviation width is small and does not fall between the “1” side threshold value 31 and the “0” side threshold value 32 can be read correctly. The product shown in FIG. 15C, which has a large shift width and interrupts between the “1” side threshold value 31 and the “0” side threshold value 32, is defective because correct reading cannot be performed.

  Further, it is necessary to generate a high-precision read reference voltage for comparison of the differential amplifier circuit of the sense amplifier 7, and even when trimming is performed, a defect occurs for the same reason as described above. . The reason why a read failure occurs due to reading of the trimming parameter with the default read reference voltage before trimming will be described with reference to FIG. 16 showing the influence of the variation of the read reference voltage on the threshold distribution of the memory cells. .

  16A shows a case where the default read reference voltage does not vary and is determined to be good. FIG. 16B shows a case where there is a variation but good determination is made, and FIG. 16C shows a variation. This is a case where a defect is determined.

  First, after rewriting the memory cell storing the trimming parameters as in FIG. 15A, the threshold width of the memory cell is set to the “1” side threshold value 31 with the read reference voltage (Vref) 30 as the center. In order to correctly read out, it is ensured that ΔVread or more between the “0” side boundary thresholds 32.

  Here, regarding the read reference voltage (Vref) 30, the “1” side boundary threshold value 31 and the “0” side boundary threshold value 32, if the read reference voltage varies by −ΔVref, 43, 44 and 45 respectively. When the deviation or the variation width (−ΔVref) is large, the deviations are large like 46, 47, and 48. Similarly, if there is a variation of + ΔVref, they will shift as 49, 50, 51, respectively, or if the variation width (+ ΔVref) is large, they will deviate greatly as 52, 53, 54.

  At this time, the shift width is small, and the threshold distribution 33 of “1” data and the threshold distribution 34 of “0” data are “1” side threshold 31 and “0” side threshold 32. The product shown in FIG. 16 (b) that has not interrupted during the period can be read correctly, but the deviation is large, and the interval between the “1” side threshold value 31 and the “0” side threshold value 32 is large. The product shown in FIG. 16 (c) that has been interrupted is defective because correct reading cannot be performed.

Alternatively, other than the above-described example, in a technique that stores trimming parameters in a conventional nonvolatile memory and performs stable trimming at the time of initial setting, the same data is stored in a plurality of memory cells on the same bit line. When storing and reading trimming parameters, multiple word lines are selected and analog majority decision is made to enable stable trimming (for example, refer to Patent Document 1), and writing / erasing of trimming parameters to memory cells In some cases, the threshold voltage difference is made larger than that of other memory cells so that the trimming parameters can be read stably (for example, see Patent Document 2).
Japanese Patent Laid-Open No. 2002-150789 (page 6-9, FIG. 1-3) Japanese Patent Laid-Open No. 2001-176290 (page 9, FIGS. 17-18)

  However, in the conventionally proposed technology, the same read and rewrite control can be performed using the decoder, sense amplifier, and rewrite control circuit having the same configuration in the memory area for storing the trimming parameters and the memory cell array body area. Even if the product has no problems in the rewrite characteristics of the memory cell or the voltage regulator itself to be trimmed, it may be erroneously determined to be defective. Alternatively, a circuit around the memory cell array dedicated to the memory area for storing the trimming parameters is required, which increases the circuit area, or requires special rewrite control, which is disadvantageous in terms of reliability and inspection costs. May occur.

  In view of these problems of the prior art, the present invention provides similar read and rewrite control using a decoder, sense amplifier, and rewrite control circuit having the same configuration in the memory area for storing trimming parameters and the memory cell array body area. In addition, it is an object of the present invention to provide a non-volatile semiconductor memory device with reduced product cost that is not erroneously determined to be defective in a product in which the rewrite characteristics of the memory cell and the voltage regulator to be trimmed are not defective. To do.

  In addition, optimal trimming is performed against fluctuations in the product environment such as power supply voltage and ambient temperature so that memory characteristics after trimming can be optimized.

  Further, it is possible to perform more stable and reliable trimming against unstable elements such as power supply fluctuations that may occur during trimming processing immediately after the power is turned on, and to improve the resistance against the unstable elements.

  In addition, in the case of a read error caused by an environmental change such as a power supply voltage drop, the stability of a system equipped with a memory can be improved.

  The present invention takes the following means in order to solve the above problems. Hereinafter, a plurality of types of component means will be described. Each of these means may be constituted by hardware or software, or a combination of hardware and software. You may comprise.

  As a first solving means, a non-volatile semiconductor memory device according to the present invention includes a non-volatile memory cell array, determination means, parameter changing means, parameter holding means, parameter selecting means, voltage regulator and control means, which are a plurality of components. I have. The voltage regulator may be a word line voltage regulator that generates a voltage to be applied to a word line of a memory cell array, or a read reference voltage regulator that generates a voltage to be applied to a sense amplifier as a read reference voltage for a selected memory cell. It may be.

  The memory cell array includes a trimming parameter area for storing trimming parameters and erroneous read confirmation data. The control means controls to read erroneous read confirmation data from the memory cell array in the initial stage. The determination means is configured to compare erroneous read confirmation data read from the memory cell array with an expected value, and output an activated determination signal when they match. Initially, the determination signal is inactive. The parameter changing means is configured to change the parameter stepwise when the determination signal of the determining means is inactive. This is the increment parameter. When the determination signal of the determination unit is inactive, the parameter selection unit selects the increment parameter by the parameter changing unit and outputs it as a voltage adjustment parameter. When the determination signal is activated, the parameter selection unit Is selected and output as a voltage adjustment parameter. Therefore, in the initial stage, the parameter selection means selects the increment parameter by the parameter changing means and supplies it to the voltage regulator as the voltage adjustment parameter. The voltage regulator adjusts the voltage value based on the received voltage adjustment parameter. In the case of a word line voltage regulator, the voltage applied to the word line of the memory cell array is adjusted. In the case of a read reference voltage regulator, the read reference voltage applied to the sense amplifier is adjusted. Based on the adjusted voltage value, the control unit controls reading of erroneous read confirmation data from the trimming parameter area of the memory cell array, and the determination unit compares the read erroneous read confirmation data with an expected value. As a result of the comparison, as long as they are inconsistent and the determination signal is inactive, the parameter changing means changes the parameter by one step (increment), and the parameter selecting means selects the parameter after the changing by one step to the voltage regulator. give. As a result, the voltage regulator outputs a voltage value of the next level, and reads the erroneous read confirmation data from the trimming parameter area of the memory cell array as described above. This loop control is repeated until the read error reading confirmation data matches the expected value. As a result, when the comparison between the erroneous read confirmation data and the expected value by the determination unit coincides, the determination unit outputs an activated determination signal. When the determination signal is activated, the control means reads the trimming parameters from the trimming parameter area of the memory cell array instead of reading the erroneous read confirmation data. The parameter holding means holds the trimming parameters read from the memory cell array. The parameter selection means selects the trimming parameter held in the parameter holding means and gives it to the voltage regulator in accordance with the activation of the determination signal. The voltage regulator adjusts the voltage value based on the trimming parameters read after the erroneous read confirmation data matches the expected value.

In short, the nonvolatile semiconductor memory device of the present invention is
A non-volatile memory cell array including a trimming parameter area for storing trimming parameters and erroneous read confirmation data;
A determination means for outputting an activated determination signal when the erroneous read confirmation data read from the memory cell array matches an expected value incorporated in advance as hardware ; and
Parameter changing means for stepwise changing the parameter when the determination signal of the determination means is inactive;
Parameter holding means for holding the trimming parameters read from the memory cell array;
When the determination signal of the determination means is inactive, the parameter of the parameter changing means is selected. When the determination signal is activated, the parameter of the parameter holding means is selected and output as a voltage adjustment parameter Means,
A voltage regulator that adjusts a voltage value according to the voltage adjustment parameter received from the parameter selection means;
The memory operation is initialized based on the input of the initial setting signal, the erroneous read confirmation data is read from the memory cell array, and after the determination means outputs the activated determination signal, the trimming is performed from the memory cell array. Control means for switching to parameter reading and for holding the trimming parameters read by the parameter holding means.

  According to this configuration, while the regulation voltage is adjusted step by step by the voltage regulator, the erroneous read confirmation data is read, and the trimming parameter is read and held when the data matches the expected value. I have to. This ensures stable and reliable trimming. As described above, a product that does not have a defect in the rewrite characteristics of the memory cell, the word line voltage regulator to be trimmed, the read reference voltage regulator itself, or the like can be prevented from being erroneously determined as defective, and can be correctly and correctly as expected. Will be judged.

  As a second solving means, the nonvolatile semiconductor memory device according to the present invention is the above first solving means, further comparing the read trimming parameter with the increment parameter by the parameter changing means, and comparing the comparison result. Comparing means for supplying to the control means is provided. The trimming parameter area in the memory cell array is configured to store a plurality of trimming parameters having different trimming voltage values as the trimming parameters. The control unit controls reading of the next trimming parameter from the trimming parameter area as long as the comparison result of the comparison unit does not match, and holds the trimming parameter when the comparison result matches in the parameter holding unit. The parameter selection means is configured to select the parameter of the parameter holding means and switch to a state of outputting as a voltage adjustment parameter when the comparison result of the comparison means matches. Yes.

  The effect | action by this structure is as follows. When the product environment such as the power supply voltage or the ambient temperature changes, even the trimming parameter read when the erroneous read confirmation data matches the expected value may become an inappropriate regulated voltage. In order to cope with this inconvenience, a plurality of trimming parameters are prepared by giving a range to the trimming voltage value, and the plurality of trimming parameters are stored in the trimming parameter area. Then, the next candidate trimming parameter is read out until the trimming parameter read from the trimming parameter area matches the increment parameter by the parameter changing means set for reading (or until the error is minimized). According to this, it is possible to select the optimal trimming parameters depending on the product environment such as the power supply voltage and the ambient temperature, and it is possible to optimize the memory characteristics after trimming.

  As a third solving means, in the nonvolatile semiconductor memory device according to the present invention, in the first solving means, the determination signal holding means for holding the determination signal by the determination means over a plurality of stages, and the determination signal are continuous. And a calculation means for calculating trimming parameters at a stage close to the center of the stages of the plurality of determination signals that are activated and held in the determination signal holding means when activated. Then, the control means causes the parameter holding means to hold the trimming parameter at a stage close to the center calculated by the calculating means, and after holding the trimming parameter, selects the parameter of the parameter holding means. It is configured to control.

  The effect | action by this structure is as follows. During the trimming process immediately after the power is turned on, unstable factors such as power fluctuations are likely to occur, and the comparison judgment between the erroneous read confirmation data and the expected value may be inaccurate. That is, even if the determination signal by the determination means is activated once, it is not always optimal. In the case of the next increment parameter, the determination signal may be activated. That is, there may be a plurality of increment parameters for activating the determination signal, and the reliability of the determination signal is poor. In order to cope with this inconvenience, when the determination signal by the determination means is activated continuously, a stage close to the center of the stages of the plurality of activated determination signals (average value) ) Is obtained, held, and given to the voltage regulator as a voltage adjustment parameter. Thereby, trimming parameters corresponding to more reliable increment parameters can be obtained, and stable and reliable trimming can be performed. Therefore, it is possible to improve the resistance against unstable elements such as power supply fluctuations that may occur during the trimming process immediately after the power is turned on.

  As a fourth solving means, the nonvolatile semiconductor memory device according to the present invention is the above first to third solving means, wherein the sense amplifier or the output buffer further has a function of holding read data, and a reread request is made from the outside. When the signal is input, the initial setting signal is activated and trimming is executed only when the determination signal is inactivated, and the held read data is output when the determination signal is activated.

  The effect | action by this structure is as follows. If an environmental change such as a drop in power supply voltage occurs, a read error may occur. In order to cope with this inconvenience, when a read error is found by parity check etc. both inside and outside the memory, it becomes possible to enter a re-trimming process by a re-read request, and reread after re-trimming. Correct read data can be obtained. Therefore, it is possible to improve the stability of the system in the case of a read error that is caused by an environmental change such as a power supply voltage drop.

  According to the present invention, the operation of comparing the erroneous read confirmation data with the expected value is repeated while the parameter is incremented by the parameter changing means, and the trimming parameter is read and held in the parameter holding means when the determination signal is activated. By determining the final trimming parameter, stable and reliable trimming can be performed. Therefore, it is avoided that a product having no defect in the rewrite characteristics of the memory cell, the word line voltage regulator to be trimmed, the read reference voltage regulator itself, or the like is erroneously determined as defective, and is correctly determined as expected. As a result, an excellent nonvolatile semiconductor memory device capable of reducing the product cost can be realized.

  In addition, a plurality of trimming voltage values with a range are prepared as trimming parameters, and the trimming parameters that match the voltage adjustment parameters at the stage where the determination signal is activated are held in the parameter holding means, so that the power supply voltage, the ambient temperature, etc. Therefore, it is possible to select an optimum trimming parameter with respect to the fluctuation of the product environment and to optimize the memory characteristics after trimming.

  In addition, the determination signal is continuously activated as a result of an unstable factor such as power supply fluctuation during the trimming process immediately after the power is turned on. Since the trimming parameter at the stage (average value) near the center of the stage of the determination signal is obtained, stable and reliable trimming can be performed. Therefore, it is possible to improve resistance to unstable elements such as power supply fluctuation that may occur during the trimming process immediately after the power is turned on.

  Further, when a read error occurs due to an environmental change such as a power supply voltage drop, re-trimming processing is performed by a re-read request, and correct read data can be obtained by re-reading after re-trimming. Therefore, it is possible to improve the stability of the system in the case of a read error that is caused by an environmental change such as a power supply voltage drop.

  Embodiments of a nonvolatile semiconductor memory device according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention.

  In FIG. 1, 1 is a memory cell array, 2 is a trimming parameter area, 3 is an address buffer, 4 is a row decoder, 5 is a row decoder for trimming parameter area, 6 is a column decoder, 7 is a sense amplifier, 8 is an input / output buffer, 9 is a parameter holding circuit, 10 is a word line voltage regulator, 11 is a control circuit, 12 is a row address, 13 is a trimming parameter area row address, 14 is a column address, 15 is a trimming parameter address, 16 is a data bus, 17 Is a voltage adjustment parameter, 18 is a word line voltage power line, 19 is an initial setting signal, 20 is a trimming parameter address, 21 is a word line voltage regulator activation signal, 22 is a sense amplifier activation signal, 23 is a parameter latch signal, 24 is an input / output control signal. Is the same as the configuration of the coming example.

  The address buffer 3 is connected so that a row address 12, a trimming parameter area row address 13, a column address 14, and a trimming parameter address 15 are output. The sense amplifier 7 includes an input / output buffer 8 and a parameter holding circuit. 9, the word line voltage power supply line 18 is connected to the word line at the time of reading through the row decoder 4 and the trimming parameter region row decoder 5, and the control circuit 11 A clock signal for operation, a mode signal for setting various modes such as reading and rewriting, and an initial setting signal 19 are input, and their connection relation is the same as that of the conventional example.

  As a new component, 60 is a determination circuit that is connected to the data bus 16 and compares the read data with the expected value to determine coincidence / non-coincidence, and 61 is a determination signal that is activated when the determination circuit 60 gives a coincidence determination result. , 62 is a parameter change circuit that changes the increment parameter used for voltage adjustment stepwise, 63 is an increment parameter that is output after the change by the parameter change circuit 62, and 64 is connected to the parameter holding circuit 9 and the parameter change circuit 62. A parameter selection circuit that selectively gives one of the parameters as the voltage adjustment parameter 17 to the word line voltage regulator 10 according to the determination signal 61, and 65 is an increment signal that causes the parameter change circuit 62 to increment the increment parameter 63 step by step. These are conventional examples It is a component no.

  The parameter selection circuit 64 selects one of the trimming parameter 57 held by the parameter holding circuit 9 and the increment parameter 63 generated by the parameter change circuit 62 according to the determination signal 61 from the determination circuit 60. The voltage adjustment parameter 17 is provided to the word line voltage regulator 10.

  Further, the determination signal 61 is input to the parameter changing circuit 62 to control the change of the increment parameter 63 and is connected to the control circuit 11 so as to perform control for switching the trimming parameter address 20.

  In the trimming parameter area 2, in addition to the trimming parameters similar to those in the conventional example, erroneous read confirmation data unique to the present invention is stored. The control circuit 11 initially controls the trimming parameter address 20 so as to read the erroneous read confirmation data from the trimming parameter area 2 and gives it to the address buffer 3, and the read erroneous read confirmation data matches the expected value. After that, the trimming parameter address 20 is controlled so as to read the trimming parameter from the trimming parameter area 2 and applied to the address buffer 3.

  The operation of the nonvolatile semiconductor memory device of the present embodiment configured as described above will be described below with reference to FIG. 1 and FIG. 2 showing the control flow during the trimming process.

  First, when the initial setting signal 19 is activated (S1 in FIG. 2) and input to the control circuit 11 after the power is turned on or after the system reset is released, all the latch circuits in the parameter holding circuit 9 are cleared, and the parameter The register circuit in the change circuit 62 is cleared and the increment parameter 63 is set to the default value. Next, the word line voltage regulator activation signal 21 is activated to start the operation of the word line voltage regulator 10 (S2 in FIG. 2), and the internal flow that is a feature of the present embodiment indicated by S10 in FIG. Proceed to Since the determination signal 61 is inactive, the word line voltage regulator 10 is trimmed according to the initialized increment parameter 63 selected as the voltage adjustment parameter 17 by the parameter selection circuit 64 (S11 in FIG. 2) ( S12 of FIG. Furthermore, after waiting for stabilization for about several microseconds (S13 in FIG. 2), a stable voltage is supplied from the word line voltage power supply line 18 to the row decoder 4 and the trimming parameter region row decoder 5. Then, a word line and a bit line are selected in accordance with the trimming parameter area row address 13 and the column address 14. That is, the word line and the bit line corresponding to the memory cell storing the erroneous read confirmation data in the trimming parameter area 2 are selected. As a result, when the sense amplifier activation signal 22 is activated, erroneous read confirmation data is output to the data bus 16 (S14 in FIG. 2). Then, the determination circuit 60 compares the erroneous read confirmation data with the expected value (S15 in FIG. 2). If the comparison results do not match (S16 in FIG. 2), the determination signal 61 remains inactive, so the parameter selection circuit 64 continues to select the increment parameter 63 as the voltage adjustment parameter 17, and the determination signal 61 In response, the control circuit 11 activates the increment signal 65, the parameter change circuit 62 increments the increment parameter 63 (S17 in FIG. 2), and trims the word line voltage regulator 10 again (S12 in FIG. 2).

  If the comparison results match (S18 in FIG. 2), the word line and the bit line are selected according to the row address 13 and the column address 14 for the trimming parameter area. That is, the word line and the bit line corresponding to the memory cell storing the trimming parameter in the trimming parameter area 2 are selected. As a result, the sense amplifier activation signal 22 is activated, and the trimming parameters are output to the data bus 16 (S4 in FIG. 2). Then, the trimming parameters are latched in a predetermined latch circuit in the parameter holding circuit 9 in accordance with the trimming parameter address 15 in synchronization with the parameter latch signal 23 (S5 in FIG. 2). The trimming parameter 57 latched in the parameter holding circuit 9 is given to the word line voltage regulator 10 as the voltage adjustment parameter 17 (S6 in FIG. 2), and trimming is performed after waiting for stabilization of about several microseconds (S7 in FIG. 2). Processing is completed.

  Next, the reason why stable and reliable trimming can be performed according to this embodiment will be described with reference to FIG. FIG. 3 illustrates the effect of stepped trimmed word line voltages on the threshold distribution of memory cells.

  3A to FIG. 3F, the word line voltage is increased stepwise by the voltage adjustment parameter 17 changed stepwise when the loop of S17 of FIG. 2 is executed. The threshold value distribution and the threshold value distribution of “0” data indicate a state in which the threshold value is gradually shifted to the higher side as indicated by lines 55 and 56, respectively. 3 is compared with the expected value at each stage (S15 in FIG. 2), and ΔVread between the “1” side threshold 31 and the “0” side threshold 32 is secured. Data can be read correctly only in stages, and erroneous read confirmation data matches the expected value (S18 in FIG. 2).

  Therefore, as long as it is a rewritable product, ΔVread is secured between the threshold distribution of the “1” data and the threshold distribution of the “0” data, so even if the word line voltage varies due to manufacturing factors, etc. However, by changing the word line voltage stepwise, it is possible to obtain a word line voltage that is read correctly, although it varies from product to product. At that stage, the trimming parameters are read out again (S4 in FIG. 2), whereby the correct trimming parameters are obtained.

  Therefore, products with no defects in the rewrite characteristics of the memory cells and the word line voltage regulator itself to be trimmed are avoided from being erroneously determined as defective, and are correctly determined as good as expected, reducing the product cost. it can.

(Embodiment 2)
FIG. 4 is a block diagram showing the overall configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. The second embodiment corresponds to a case where a read reference voltage regulator that needs to generate a highly accurate voltage is provided instead of the word line voltage regulator of the first embodiment.

  In FIG. 4, 66 is a read reference voltage regulator for applying a read reference voltage (Vref) 30 to the sense amplifier 7, 67 is a read reference voltage power line, and 68 is a read reference voltage regulator activation signal. The read reference voltage regulator 66 is connected to the comparison input terminal of the differential amplifier section of the sense amplifier 7 via the read reference voltage power line 67, and the read reference voltage regulator activation signal 67 is input from the control circuit 11 at the time of reading. Then, the generated read reference voltage (Vref) 30 is applied to the sense amplifier 7. The sense amplifier 7 sets a given read reference voltage (Vref) 30.

  The parameter selection circuit 64 selects one of the trimming parameter 57 held by the parameter holding circuit 9 and the increment parameter 63 generated by the parameter change circuit 62 according to the determination signal 61 from the determination circuit 60. The read reference voltage regulator 66 is provided as the voltage adjustment parameter 17.

  Other configurations and connection relationships are the same as those of the first embodiment.

  The operation of the nonvolatile semiconductor memory device of the present embodiment configured as described above is the same as that in the case of replacing the word line voltage regulator with the read reference voltage regulator in the operation described in the first embodiment.

  Next, the reason why stable and reliable trimming can be performed according to this embodiment will be described with reference to FIG. FIG. 5 shows the effect of a read reference voltage trimmed in stages on the threshold distribution of the memory cells.

  5A to 5F, the read reference voltage (Vref) 30 is increased stepwise by the voltage adjustment parameter 17 changed stepwise, and the “1” side boundary threshold value 31 and “0” are increased. This represents a state where the side boundary threshold value 32 is gradually shifted to the higher side. Correct reading is performed only at the stage of FIG. 5C in which ΔVread between the “1” side threshold value 31 and the “0” side threshold value 32 is ensured by comparison with the expected value at each stage. The erroneous read confirmation data matches the expected value. Therefore, as long as it is a rewritable product, ΔVread is secured between the threshold distribution of the “1” data and the threshold distribution of the “0” data, so even if the read reference voltage varies due to manufacturing factors, etc. However, by changing the read reference voltage stepwise, it is possible to obtain a read reference voltage that is read correctly, although it varies depending on the product. By reading out the trimming parameters anew at that stage, the correct trimming parameters can be obtained.

  Therefore, products that have no defects in the rewrite characteristics of the memory cells and the read reference voltage regulator itself to be trimmed are avoided from being erroneously determined as defective, and are correctly determined as expected, thereby reducing product cost. it can.

(Embodiment 3)
FIG. 6 is a block diagram showing the overall configuration of the nonvolatile semiconductor memory device according to the third embodiment of the present invention.

  The trimming parameter area 2 stores a plurality of trimming parameters in which the trimming voltage value has a range. Reference numeral 69 denotes a comparison circuit that compares the read data with the increment parameter 63 and outputs a match signal 70 that is activated if they match, and the parameter selection circuit 64 selectively selects parameters according to the match signal 70. The voltage adjustment parameter 17 is connected to the word line voltage regulator 10. Other configurations and connection relationships are the same as those of the first embodiment.

  The operation of the nonvolatile semiconductor memory device of this embodiment will be described below with reference to FIG. 6 and FIG. 7 showing the internal flow at the time of trimming processing.

  Up to S18 of the internal flow, which is a feature of the present embodiment shown in S20 of FIG. 7, is the same as the internal flow diagram 2 of the first embodiment. Here, it demonstrates from S18 of FIG.

  When the comparison result between the erroneous read confirmation data and the expected value coincides (S18 in FIG. 7), the word line and the bit line are selected according to the trimming parameter area row address 13 and the column address 14. That is, the word line and the bit line corresponding to the memory cell storing the first trimming parameter in the trimming parameter area 2 are selected. As a result, the sense amplifier activation signal 22 is activated to output trimming parameters to the data bus 16 (S21 in FIG. 7), and the comparator 69 compares the read trimming parameters with the increment parameters 63 (see FIG. 7). S22 of FIG. 7). If the comparison results do not match (S23 in FIG. 7), the control circuit 11 decodes the trimming parameter area row address 13 for the second trimming parameter (S24 in FIG. 7), and the trimming parameter is read out. (S21 in FIG. 7). If the comparison results match (S25 in FIG. 7), the parameter holding circuit 9 can be latched by the match signal 70, and the parameter is synchronized with the parameter latch signal 23 according to the trimming parameter address 15. The trimming parameter is latched in a predetermined latch circuit in the holding circuit 9 (S5 in FIG. 7). Then, the latched trimming parameter 57 is given to the word line voltage regulator 10 as the voltage adjustment parameter 17 (S6 in FIG. 7), and the trimming process is completed after waiting for stabilization of about several microseconds (S7 in FIG. 7). Therefore, since the optimum trimming parameters depending on the product environment such as the power supply voltage and the ambient temperature can be selected from the plurality of trimming values, the memory characteristics after trimming can be optimized.

(Embodiment 4)
FIG. 8 is a block diagram showing the overall configuration of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

  In FIG. 8, 72 is a determination signal holding circuit for storing the determination signal 61 for each stage, 73 is a plurality of determination signals held by the determination signal holding circuit 72, and 74 is a plurality of determination signals 73 that are calculated and activated. When the converted determination signal 61 is continuous, a calculation circuit for calculating a voltage adjustment parameter at a stage close to the average of the voltage adjustment parameters at the continuous stage, 75 is a voltage adjustment parameter calculated by the calculation circuit 74, and 76 is a parameter This is a signal for switching the voltage adjustment parameter selected by the parameter selection circuit 27 after the increment parameter is changed in all stages by the change circuit 62. These configurations are components that are not in the first embodiment, but other configurations and connection relationships are the same as those in the first embodiment.

  One embodiment of the arithmetic circuit 74 is shown in FIG. In FIG. 9, the input is an eight-step decision signal 73 held by the decision signal holding circuit 72, the output is a voltage adjustment parameter 75 in which the decision signal activated after the operation is converted into only one step, and further 100 to 102 are An array of 3-input ANDs that converts the activated signal to one stage if it is continuous for three stages, and converts it to no stage if it is continuous for two stages or one stage, 103 is activated An array of 2-input ANDs that converts the signal into two stages if the signal is continuous in two stages, 104 to 107 are 8-input OR circuits, 108 are 7-input OR circuits, 112 to 117 are transfer gates, and 120 to 124 are step-by-step determinations Signal.

  The operation of the arithmetic circuit according to this embodiment configured as described above will be described below with reference to FIG.

  The inputted eight-stage determination signal 73 is converted for each step in the AND array 100 to 103, and each AND is obtained by taking the AND of the NOR of the determination signal after conversion and the OR of the determination signal before conversion. Which of the transfer gates 112 to 117 is to be conducted is determined. That is, which conversion stage determination signal is to be transferred is determined. In other words, the determination signal before conversion is transferred only when all the determination signals after conversion are inactive and at least one of the determination signals before conversion is activated. Even when the determination signal 73 includes a plurality of activated determination signals, the output voltage adjustment parameter 75 is always limited to one. Since only the determination signals adjacent to the inactive determination signal among the continuous activated determination signals in the steps of the array 100 to 103 of the AND are inactivated and aggregated, a plurality of activated stages The voltage adjustment parameter at a stage close to the center of the can be calculated.

  The operation of the nonvolatile semiconductor memory device of the present embodiment configured as described above will be described below with reference to FIG. 8 and FIG. 10 showing the internal flow at the time of trimming processing.

  In the internal flow, which is a feature of the present embodiment shown in S30 of FIG. 10, up to S14 is the same as the internal flow diagram 2 of the first embodiment, and will be described from S31 of FIG.

  Regardless of whether the comparison result between the erroneous read confirmation data and the expected value does not match, the determination circuit 60 compares and determines the erroneous read confirmation data and the expected value (S31 in FIG. 10). If the preset maximum number has not been reached (S32 in FIG. 10), the determination signal 61 is stored in the determination signal holding circuit 72 (S33 in FIG. 10), and the parameter change circuit 62 changes the increment parameter. (S17 in FIG. 10), the word line voltage regulator 10 is trimmed again (S12 in FIG. 10). When the set maximum number of times is reached (S34 in FIG. 10), the final determination signal 61 is stored in the determination signal holding circuit 72 (S35 in FIG. 10), and the arithmetic circuit 74 is in a stage close to the average of the voltage adjustment parameters. The voltage adjustment parameter is calculated (S36 in FIG. 10). Further, the calculated voltage adjustment parameter 75 is latched in a predetermined latch circuit in the parameter holding circuit 9 in accordance with the trimming parameter address 15 in synchronization with the parameter latch signal 23 (S37 in FIG. 10). The voltage adjustment parameter of the holding circuit 9 is selected, and the latched trimming parameter 57 is given to the word line voltage regulator 10 as the voltage adjustment parameter 17 (S6 in FIG. 10) and waits for stabilization of about several microseconds (FIG. 10). After S7), the trimming process is completed. In other words, since the trimming parameters can be read with a word line voltage value that can be read reliably, stable and reliable trimming can be performed, and resistance to unstable factors such as power supply fluctuations that can occur during the trimming process immediately after power on is improved. Can be achieved.

(Embodiment 5)
FIG. 11 is a block diagram showing the overall configuration of the nonvolatile semiconductor memory device according to the fifth embodiment of the present invention.

  In FIG. 11, 77 and 78 are logic circuits configured so that the initial setting signal is activated only when the external reread request signal ERR is activated and the determination signal 61 is deactivated. Is a parity area for storing parity bits in the memory cell array, and the decision circuit 60 can check the parity. These configurations are components that are not in the first embodiment, but other configurations and connection relationships are the same as those in the first embodiment. The sense amplifier 7 has a function of holding read data.

  The operation of the nonvolatile semiconductor memory device of the present embodiment configured as described above will be described below with reference to FIG.

  When a parity bit is provided in order to improve the stability of the memory system during a normal read operation, the determination circuit 60 makes a determination every cycle. If a read error is found both in the memory and outside by parity check or the like, the re-read request signal ERR is externally input to activate the initial setting signal, and the re-read request signal ERR is Even if it is input, if the determination signal 61 is not deactivated and an internal error is not detected, the external output data is held as it is and is output when a re-reading request is received from the outside.

  Therefore, it is effective to perform trimming again in the case of a read error caused by an environmental change such as a power supply voltage drop. In other words, correct read data can be obtained by rereading after re-trimming, and stability of a system equipped with a memory can be improved.

  In this embodiment, the sense amplifier 7 has a read data holding function. However, the input / output buffer 8 may have a read data holding function instead of the sense amplifier 7.

  In the above description, the word line voltage regulator and the read reference voltage regulator are cited as examples of voltage regulators used during the read operation. However, if the trimming parameters are stored in the same word line, the word line voltage regulator is trimmed when the word line voltage regulator is trimmed. The effect that the influence of the voltage dispersion | variation for every can be suppressed more effectively is acquired. Similarly, if the trimming parameters are stored in the same bit line or in a memory area connected to the same differential amplifier in the sense amplifier, the read reference voltage regulator is trimmed, and the influence of variations in the read voltage that differ for each differential amplifier in the sense amplifier is affected. The effect that it can suppress more is acquired.

  The nonvolatile semiconductor memory device according to the present invention relates to an LSI equipped with a nonvolatile memory such as FLASH or FeRAM, and is useful for applications such as product cost reduction, performance improvement and function expansion by trimming.

1 is an overall configuration diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. Control flow diagram at the time of trimming processing in Embodiment 1 of the present invention Distribution diagram of memory cell threshold value in the first embodiment of the present invention Overall configuration diagram of nonvolatile semiconductor memory device according to Embodiment 2 of the present invention Memory cell threshold value distribution diagram in the second embodiment of the present invention Overall configuration diagram of nonvolatile semiconductor memory device according to Embodiment 3 of the present invention Control flow diagram at the time of trimming processing in Embodiment 3 of the present invention Overall configuration diagram of nonvolatile semiconductor memory device according to Embodiment 4 of the present invention Configuration diagram of arithmetic circuit in Embodiment 4 of the present invention Control flow diagram at the time of trimming processing in Embodiment 4 of the present invention Overall configuration diagram of nonvolatile semiconductor memory device according to Embodiment 5 of the present invention Overall configuration diagram of a nonvolatile semiconductor memory device in the prior art Control flow diagram during trimming process in the prior art Inspection flow chart for confirmation of trimming function in conventional technology The figure which shows the influence of the dispersion | variation in word line voltage with respect to threshold value distribution of a memory cell in a prior art The figure which shows the influence of the dispersion | variation in a read reference voltage with respect to threshold value distribution of a memory cell in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Trimming parameter area 3 Address buffer 4 Row decoder 5 Trimming parameter area row decoder 6 Column decoder 7 Sense amplifier 8 Input / output buffer 9 Parameter holding circuit 10 Word line voltage regulator 11 Control circuit 12 Row address 13 Trimming parameter area Row address 14 Column address 15 Trimming parameter address 16 Data bus 17 Voltage adjustment parameter 18 Word line voltage power supply line 19 Initial setting signal 20 Trimming parameter address 21 Word line voltage regulator activation signal 22 Sense amplifier activation signal 23 Parameter latch signal 24 I / O control signal 27 Parameter selection circuit 30 Read reference voltage (Vref)
31 “1” Boundary Threshold 32 “0” Boundary Threshold 33 “1” Data Threshold Distribution 34 “0” Data Threshold Distribution 60 Determination Circuit 61 Determination Signal 62 Parameter Change Circuit 63 Increment Parameters 64 Parameter selection circuit 65 Increment signal 66 Read reference voltage regulator 67 Read reference voltage power supply line 68 Read reference voltage regulator activation signal 69 Comparison circuit 70 Match signal 72 Judgment signal holding circuit 73 Multiple decision signals 74 Arithmetic circuit 75 Voltage adjustment Parameter 76 Voltage adjustment parameter switching signal 77, 78 Logic circuit 79 Parity area

Claims (10)

A non-volatile memory cell array including a trimming parameter area for storing trimming parameters and erroneous read confirmation data;
A determination means for outputting an activated determination signal when the erroneous read confirmation data read from the memory cell array matches an expected value incorporated in advance as hardware ; and
Parameter changing means for stepwise changing the parameter when the determination signal of the determination means is inactive;
Parameter holding means for holding the trimming parameters read from the memory cell array;
When the determination signal of the determination means is inactive, the parameter of the parameter changing means is selected. When the determination signal is activated, the parameter of the parameter holding means is selected and output as a voltage adjustment parameter Means,
A voltage regulator that adjusts a voltage value according to the voltage adjustment parameter received from the parameter selection means;
The memory operation is initialized based on the input of the initial setting signal, the erroneous read confirmation data is read from the memory cell array, and after the determination means outputs the activated determination signal, the trimming is performed from the memory cell array. A non-volatile semiconductor memory device comprising: control means for switching to parameter reading and for holding the trimming parameter read by the parameter holding means. Further, a comparison unit that compares the read trimming parameter with a parameter of the parameter changing unit and gives the comparison result to the control unit,
The trimming parameter area in the memory cell array is configured to store a plurality of trimming parameters having different trimming voltage values as the trimming parameters,
The control unit controls reading of the next trimming parameter from the trimming parameter area as long as the comparison result of the comparison unit does not match, and causes the parameter holding unit to hold the trimming parameter when the comparison result matches. Composed of
The said parameter selection means is comprised so that it may switch to the state which outputs as a voltage adjustment parameter after selecting the parameter of the said parameter holding means according to the comparison result of the said comparison means. Nonvolatile semiconductor memory device. Furthermore, determination signal holding means for holding the determination signal by the determination means over a plurality of stages;
Calculating means for calculating a trimming parameter at a stage close to the center of the stages of the plurality of determination signals that are activated and held in the determination signal holding means when the determination signals are continuously activated; Prepared,
The control unit controls the parameter holding unit to hold the trimming parameter at a stage close to the center calculated by the calculation unit, and then controls the parameter selection unit to select the parameter of the parameter holding unit. The nonvolatile semiconductor memory device according to claim 1, configured to The initial setting signal is configured to be activated only when the determination signal is inactivated when a reread request signal is input from the outside to the control means. The nonvolatile semiconductor memory device according to any one of the above. The sense amplifier has a function of holding read data, and when the re-read request signal is input from the outside to the control means, the read data held by the sense amplifier only when the determination signal is activated The nonvolatile semiconductor memory device according to claim 4, wherein the nonvolatile semiconductor memory device is configured so as to be output. The output buffer at the next stage of the sense amplifier has a function of outputting and holding read data externally, and only when the determination signal is activated when a reread request signal is input from the outside to the control means The nonvolatile semiconductor memory device according to claim 4, configured to output the read data held in an output buffer. 7. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage regulator is a word line voltage regulator that generates a voltage to be applied to a word line of the memory cell array. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage regulator is a read reference voltage regulator that generates a voltage to be applied to the sense amplifier as a read reference voltage of a selected memory cell. The nonvolatile semiconductor memory device according to claim 7, wherein the erroneous read confirmation data or the trimming parameter is configured to be stored in a memory area selected by the same word line in the trimming parameter area. The nonvolatile semiconductor memory device according to claim 8, wherein the erroneous read confirmation data or the trimming parameter is configured to be stored in a memory area read by the same differential amplifier in the sense amplifier.

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