JP4403991B2 - Information code reader and control method of information code reader - Google Patents

Description

  The present invention relates to an information code reading apparatus including an area sensor for optically reading an information code, and an FPGA for processing image data read through the area sensor, and a control method for the information code reading apparatus. .

In an information code reading apparatus that reads a two-dimensional code such as a barcode or a QR code (registered trademark), various specifications are required even though the number of production is not so large. For this reason, when a digital circuit that performs processing for capturing and decoding an image including an information code is configured by a custom IC such as a gate array, the development and fixed costs increase, leading to an increase in manufacturing cost. There are circumstances.
In addition, there is a situation in which an information code reader equipped with such a custom IC cannot flexibly cope with a specification change. In recent years, there has been an information code reading apparatus in which the digital circuit is realized by a field programmable gate array (hereinafter referred to as FPGA) in order to cope with high-mix low-volume production and reduce the risk of specification change. It has been put into practical use.

By the way, for a device configured to be portable, such as the information code reading device, low power consumption is required in order to extend the time during which the operation is possible with the limited capacity of the mounted battery. ing. While the FPGA has the above-described advantages, it has a disadvantage that the static current consumption is larger than that of a normal gate array. Some FPGAs allow a static current consumption range of, for example, 10 mA (typ) to 200 mA (max) in a very wide range.
For the reasons described above, an information code reader configured using an FPGA tends to shorten the operable time. Therefore, it is desirable to shorten the time for supplying the operation power to the FPGA as much as possible.

For example, Patent Document 1 describes that an information code reading apparatus configured using an FPGA has encountered such a situation in order to cope with the case where the logic of the FPGA is inadvertently rewritten due to noise or the like. When determined, a technique for re-execution of FPGA configuration is disclosed.
JP 2004-13300 A

Although the technique disclosed in Patent Document 1 is intended to solve the problem by paying attention to the problem peculiar to the FPGA, the problem derived from the characteristic that the static consumption current of the FPGA is large is completely considered. Not.
If the static consumption current of the FPGA is reduced, it is assumed that the power supply to the FPGA is stopped by, for example, an auto power off function when it is determined that the FPGA is not in use. However, the inventors of the present invention have considered that there is room for further improvement in dealing with the above problems.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an information code reading apparatus that can suppress an increase in power consumption caused by that as much as possible even when configured using an FPGA. And providing a control method of the information code reader.

According to the information code reading device of the first aspect, when the reading of the information code is started, the control means starts supplying power to the area sensor and the FPGA, and the indeterminate data discharging process in the area sensor and the configuration for the FPGA. The parallel processing is performed in parallel. Then, the start timing of the power supply to each is set so that the end timing of the exposure processing of the area sensor performed following the indefinite data discharge processing and the end timing of the configuration processing for the FPGA are substantially simultaneous.
That is, the area sensor and the FPGA are supplied with power when reading of the information code is started. In the initial state when the area sensor is turned on, indefinite data exists in the light receiving element, and it is necessary to perform a discharge process for discharging the indefinite data. On the other hand, the FPGA must perform configuration processing for defining internal logic when the power is turned on. Therefore, by performing them in parallel, reading of the information code can be started quickly after the power is turned on.

  In general, the time required for the indeterminate data ejection processing and the exposure processing of the area sensor is longer than the time required for the FPGA configuration processing. The FPGA may function from the stage where the exposure processing of the area sensor is completed and the image data can be captured. Therefore, if the power supply start timing is set so that the indefinite data discharge process, the exposure process, and the configuration process are completed almost simultaneously, the time for starting the power supply to the FPGA can be delayed. Therefore, power consumption can be suppressed by shortening the power supply time.

  According to the information code reading apparatus of the second aspect, the control unit predicts the time required for the indeterminate data discharge processing in the area sensor and the time required for the configuration processing for the FPGA, and based on these prediction results. Thus, the start timing of power supply to the area sensor and the FPGA is set. That is, the indefinite data discharge processing and the configuration processing time can be predicted according to the specifications of the area sensor and the FPGA, respectively. Further, the time required for the area sensor to perform the exposure process is also defined in the specification. Therefore, if the power supply start timing is set based on each predicted time, it is possible to accurately set the end timings of the processing of both the area sensor and the FPGA substantially simultaneously.

  According to the information code reading device of the third aspect, the second power supply interrupting means interrupts only the power supplied to the core part of the FPGA. That is, some FPGAs employ a structure in which the power supplied to the core unit and the power supplied to the peripheral interface unit are separated in order to reduce power consumption. In such an FPGA, when power supply is stopped, only supply of power supplied to the core unit is stopped, and power is continuously supplied to the peripheral interface unit. With such a configuration, it is possible to reliably prevent the current from inadvertently flowing to the FPGA side from the peripheral circuit side to which power is supplied, and thus it is possible to prevent an increase in power consumption.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 3 is a functional block diagram showing an electrical configuration of the information code reader. The optical head portion of the information code reading device 1 includes an LED 2 for irradiating the reading target area A with light, and an area sensor 4 that receives reflected light from the reading target area A through an imaging optical system such as an imaging lens 3. It consists of and.
The area sensor 4 includes a CCD (Charge Coupled Device) 5 formed by two-dimensionally arranging a plurality of light receiving elements 5, an amplification circuit 6 for amplifying the light reception signal output from the CCD 5, and the light reception signal amplified by the amplification circuit 6. It comprises an A / D converter 7 for A / D conversion. Then, when the area sensor 4 images the reading target area A based on a control signal given from a CPU (control means) 8, the light receiving signal corresponding to the imaging is converted into an electrical image signal, and an FPGA (Field Programmable). Gate Array) 9.

The FPGA 9 controls an image capturing process including an information code in a state where an information code pattern such as a QR code is positioned in the reading target area A. There are various methods for such image capture processing. For example, processing for recognizing whether the image signal from the area sensor 4 corresponds to the information code to be read, and the image signal is the above information. When it is recognized that it corresponds to the code, an image capturing process including a process of storing the image signal in the memory 10 and a decoding process of decoding the information code based on the image data stored in the memory 10 are performed.
In this case, the FPGA 9 is configured to output a capture completion signal and a decode completion signal to the CPU 8 when the image capture process and the decode process are completed. When the FPGA 9 is used, it is necessary to perform a configuration process for defining the function of the internal logic circuit block when the power is turned on.

The CPU 8 controls the information code reading device based on the control program stored in the other memory 11. Further, the memory 11 stores the configuration program (“Config. P.” in the figure) 12. When the CPU 8 reads the configuration program 12, it passes through a serial communication interface (not shown). To the FPGA 9 side. Then, the function of the logic circuit block in the FPGA 9 is defined by the data of the configuration program 12, and the FPGA 9 performs the intended operation. The control signals and data as described above are exchanged between the CPU 8 and the FPGA 9. The CPU 8 is given an operation signal from the operation switch 13.
The information code reader 1 has a battery power supply circuit 16 for supplying a power supply voltage from the battery. The battery power supply circuit 16 generates two types of power supply voltages (3.0 V and 1.8 V). The 1.8 V power supply is supplied for the internal power supply of the FPGA 9 as will be described in detail later. . A 3.0 V power supply is supplied to the I / O power supply of the FPGA 9 and other components.

FIG. 4 shows an internal block of the FPGA 9. The FPGA 9 includes a logic circuit block CLB (Configuration Logic Block) 15, a block RAM 16, a DLL (Delay Locked Loop) 17, an I / O logic (peripheral interface unit) 18, and the like. The DLL 17 is a circuit that multiplies or divides the frequency of a clock signal used internally, and the I / O logic 18 is an input / output logic or buffer that is a signal interface with the outside. These I / O logic 18 parts operate with a 3.0 V power supply, and the other core parts 19 (CLB 15, block RAM 16, DLL 17) operate with a 1.8 V power supply.
As shown in FIG. 3, the area sensor 4 and the I / O logic 18 portion of the FPGA 9 are respectively connected to 3.0 V, 1... Via power switches 20 and 21 (first and second power interrupting means). An 8V power supply is supplied. Opening and closing of the power switches 20 and 21 is controlled by the CPU 8.

  Next, the operation of the present embodiment will be described with reference to FIGS. FIG. 2 is a flowchart showing the control contents executed by the CPU 8 of the information code reading device 1 only in the part related to the gist of the present invention. FIG. 1 is a timing chart showing the operating state of each unit corresponding to the flowchart of FIG. Note that, as an initial state, the power switches 20 and 21 are OFF, and power is supplied to the area sensor 4 and the core portion 19 of the FPGA 9 even when power is supplied to the main body of the information code reader 1 (CPU 8 or the like). Not in supply.

When the user starts reading a bar code or a two-dimensional code by operating a trigger switch (not shown) for starting reading in the operation switch 13 (“start”), the CPU 8 first turns on the power switch 19. The power is turned on to supply power to the area sensor 4 (step S1). Then, the area sensor 4 starts a “data discharge” process as an initialization process. This “data ejection” is unstable immediately after the area sensor 4 is turned on, because unstable level data is generated in the light receiving element in the CCD 5 and is discharged to the outside first. It is a process for obtaining the received light data.
In this “data discharge” process, it is generally necessary to discharge data for at least two to three frames, and the area sensor 4 used in the present embodiment is designed to perform “data discharge” for two frames. To do. Then, for example, if the data output time of one frame is 33 ms, the data discharge time TDO is predicted to require 33 ms × 2 = 66 ms (discharge time prediction means).

  Further, as shown in FIG. 1, the area sensor 4 performs “exposure” for reading an image when the “data ejection” process is completed. When the “exposure” is completed, the image data obtained by the “exposure” is written into the memory 10 via the FPGA 9, that is, normal image data output processing is performed. When the “take-in” is completed, the FPGA 9 performs a “decode” process for reading the information code based on the image data written in the memory 10.

Refer to FIG. 2 again. The CPU 8 waits for the elapse of the standby time TW in step S2 following step S1, and the standby time TW here is determined as follows. That is, when the standby time TW elapses, the CPU 8 turns on the power switch 21 to supply power to the core unit 19 of the FPGA 9 (step S3), and starts the configuration process of the FPGA 9 (step S4).
Then, assuming that the time required for the configuration is TCF and the time required for “exposure” of the area sensor 4 is TEX,
TW = TDO + TEX-TCF
The waiting time TW is determined so that In other words, the FPGA 9 needs to function from the time when the “exposure” of the area sensor 4 is completed and “take-in” is started, so that the configuration processing of the FPGA 9 may be completed by that time. . Incidentally, the time TEX required for “exposure” of one frame is about 33 ms as in the case of “data ejection”. That is, (TDO + TEX) is predicted as 66 + 33 = 99 [ms].
Therefore, if the CPU 8 starts supplying power to the core unit 19 of the FPGA 9 after the elapse of the waiting time TW in step S2, the configuration process is completed and the "exposure" in the area sensor 4 is completed. Therefore, the start of power supply to the core portion 19 can be delayed as much as possible.

When the CPU 8 sequentially reads the configuration program 12 stored in the memory 11, the CPU 8 writes it in a buffer of a serial communication interface such as a UART (Universal Asynchronous Receiver Transmitter). The process is continued until there is no more data in the program 12 (step S5, “YES”). When all the data is transmitted to the FPGA 9 side, the CPU 8 monitors the “capture” and “decode” processing performed by the FPGA 9 side (steps S6 and S7).
When the FPGA 9 notifies the CPU 8 that the “decoding” is completed, for example, by generating an interrupt, the CPU 8 refers to the decoding result and turns off both the power switches 20 and 21 to thereby detect the area sensor. 4 and power supply to the core 19 of the FPGA 9 are stopped (step S8). Then, the reading process ends.

Here, as an example, when the FPGA 9 is a 100 k gate class device, the data capacity of the configuration program 12 is about 870 k bits, for example. If the communication speed in serial communication is 12 Mbps, the configuration time TCF is predicted to be about 73 ms (configuration time prediction means). Therefore, the waiting time TW is
TW = TDO + TEX-TCF = 66 + 33-73 = 26 [ms]
The power supply start timing setting means may be set.

As described above, according to this embodiment, the CPU 8 of the information code reader 1 starts supplying power to the area sensor 4 and the core unit 18 of the FPGA 9 when reading of the information code is started. Indefinite data discharge processing and configuration processing for the FPGA 9 are performed in parallel. Then, the start timing of the power supply to each is set so that the end timing of the exposure processing of the area sensor 4 performed following the indefinite data discharge processing and the end timing of the configuration processing are substantially the same.
That is, by performing the indefinite data discharge process and the configuration process in parallel, reading of the information code can be started quickly after the power is turned on. If the power supply start timing is set so that the indefinite data discharge process, the exposure process, and the configuration process are completed almost simultaneously, the time for starting the power supply to the FPGA 9 can be delayed. Therefore, power consumption can be suppressed by shortening the power supply time.

In addition, when the reading of the information code is completed, the CPU 8 stops the power supply to the area sensor 4 and the core unit 18 of the FPGA 9, so that the power supply time to the FPGA 9 can be further shortened and the power consumption can be suppressed. .
Further, the CPU 8 predicts the time TDO required for the indefinite data discharge process and the time TCF required for the configuration process, and based on these prediction results, determines the start timing of power supply to each of the area sensors 4 and FPGA 9. Since the setting is performed, it is possible to perform an accurate setting for making the end timings of both processes substantially the same.
In addition, since only the power supplied to the core portion 19 of the FPGA 9 is interrupted by the power switch 21, and the power is continuously supplied to the I / O logic 18, the CPU 8 to which power is supplied, etc. It is possible to reliably prevent the current from inadvertently flowing to the FPGA 9 side from the peripheral circuits, and to prevent an increase in power consumption.

(Second embodiment)
FIG. 5 shows a second embodiment of the present invention, and only parts different from the first embodiment will be described. FIG. 5 is a diagram corresponding to FIG. 1 of the first embodiment. In the second embodiment, when the CPU 8 performs the configuration process of the FPGA 9, the data of the configuration program 12 is transferred in parallel by 8 bits. In this case, the configuration time TCF is predicted to be 73/8 = 9.1 [ms] (configuration time prediction means). Therefore, as the waiting time TW,
TW = TDO + TEX-TCF = 66 + 33-9.1 = 89.9 [ms]
The power supply start timing setting means may be set.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
The setting of the power supply start timing for each of the area sensor 4 and the FPGA 9 does not necessarily need to be determined based on strict prediction of the indefinite data discharge processing time TDO and the configuration processing time TCF. In short, if the end time of the exposure processing time following the indeterminate data discharge processing on the area sensor 4 side and the end time of the configuration processing are substantially simultaneous, the determination may be made based on the approximate setting time. .
A configuration serial PROM may be used, and the configuration may be such that the configuration is performed directly from the serial PROM to the FPGA based on a serial clock output after power is supplied from the FPGA without the intervention of the CPU.
The FPGA is not necessarily limited to one in which the power supplied to the core unit and the I / O logic unit that is the peripheral interface unit is independent. Therefore, the power supplied to the entire FPGA may be interrupted collectively by the second power supply interrupting means.

2 is a timing chart showing the operation state of each part corresponding to the flowchart of FIG. 2 according to the first embodiment of the present invention. A flow chart showing only the control contents executed by the CPU of the information code reading device according to the gist of the present invention. Functional block diagram showing the electrical configuration of the information code reader The figure which shows the internal block of FPGA FIG. 1 equivalent view showing a second embodiment of the present invention.

Explanation of symbols

  In the drawings, 1 is an information code reader, 4 is an area sensor, 8 is a CPU (control means, ejection time predicting means, config time predicting means, power supply start timing setting means), 9 is an FPGA, and 18 is an I / O. Logic (peripheral interface unit), 19 is a core unit, and 20 and 21 are power switches (first and second power supply interrupting means).

Claims (6)

An area sensor for optically reading an information code;
An FPGA (Field Programmable Gate Array) that processes image data read through the area sensor;
First power interrupting means for interrupting power supplied to the area sensor;
A second power supply interrupting means for interrupting the power supplied to the FPGA;
When reading of the information code is started, supply of power to the area sensor and the FPGA is started by the first and second power supply interrupting means, and indefinite data discharge processing in the area sensor and configuration processing for the FPGA And in parallel,
Power supply to each of the area sensor and the FPGA so that the end timing of the exposure processing of the area sensor performed following the indefinite data discharge processing and the end timing of the configuration processing for the FPGA are substantially the same. And a control means for setting the start timing of the information code. The control means includes
A discharge time predicting means for predicting a time required for indefinite data discharge processing in the area sensor;
A configuration time prediction means for predicting the time required for the configuration processing for the FPGA;
2. The information code according to claim 1, further comprising power supply start timing setting means for setting a power supply start timing for each of the area sensor and the FPGA based on the time predicted by the prediction means. Reader. In the FPGA, the power supplied to the core part and the power supplied to the peripheral interface part are separated,
3. The information code reading device according to claim 1, wherein the second power supply interrupting means interrupts only the power supplied to the core unit. An information code reader control method comprising an area sensor for optically reading an information code and an FPGA (Field Programmable Gate Array) for processing image data read via the area sensor,
When reading of the information code is started, power supply to the area sensor and the FPGA is started, and indefinite data discharge processing in the area sensor and configuration processing for the FPGA are performed in parallel.
Power supply to each of the area sensor and the FPGA so that the end timing of the exposure processing of the area sensor performed following the indefinite data discharge processing and the end timing of the configuration processing for the FPGA are substantially the same. A control method for an information code reading device, characterized in that the start timing is set. Predicting the time required for indeterminate data discharge processing in the area sensor, and predicting the time required for configuration processing for the FPGA;
5. The method of controlling an information code reader according to claim 4, wherein a start timing of power supply to each of the area sensor and the FPGA is set based on each predicted time.   When the FPGA is configured such that a power supplied to the core unit and a power supplied to the peripheral interface unit are separated from each other, only the power supplied to the core unit is intermittently connected. Item 6. A method for controlling an information code reading device according to Item 4 or 5.

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