JP4403653B2 - Multipurpose software-defined wireless communication device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a communication apparatus, and more particularly, to a software-defined wireless communication apparatus that enables communication by replacing software.
[0002]
[Prior art]
Until now, wireless communication devices are usually configured to perform a fixed function with a hardware circuit or a circuit according to hardware, so as to be suitable for one application. Therefore, in order to perform a plurality of different communications, it is necessary to prepare a plurality of wireless communication apparatuses having respective functions.
[0003]
For example, a PHS mobile phone is required for a PHS mobile phone call, and a Do Co Mo mobile phone is required for DoCoMo (Do Communication Mobile) mobile communication provided by NTT.
[0004]
As a means of overcoming such inconvenience, the document J. Mitola, “The software radio architecture” IEEE Communications Magazine Vol. 33.5, pp26-38, May 1995 (hereinafter referred to as document 1) is included in the communication device. It has been proposed that a program (software) for performing a target process is downloaded and stored in a memory in a wireless communication apparatus, and the program is operated to perform a process according to the purpose.
[0005]
That is, according to the method proposed in Document 1, if there is one wireless communication device having a memory for storing a program to be downloaded, the target process is basically performed by downloading the target program. Is proposing to be possible.
[0006]
Certainly, the technology proposed in Document 1 is theoretically possible and highly feasible due to the recent development and practical application of electronic and communication technologies.
[0007]
[Problems to be solved by the invention]
However, a wide and practical wireless communication device cannot be manufactured simply by applying memory technology, electronic technology, and computer technology. For example, since such a wireless communication device performs data communication wirelessly using an antenna (antenna), the antenna must be capable of data communication and program download.
[0008]
Next, the signal transmitted and received by the antenna is a high-frequency signal of about several GHz, and the part where the program operates is a baseband signal. Therefore, it is economical and small in terms of manufacturing a practical wireless communication device. Therefore, a low power consumption frequency conversion circuit is required.
[0009]
In order to configure a wireless communication apparatus adaptable for various uses, it is necessary to make the scale of the wireless communication apparatus that downloads and operates the program very large. Then, the price of such a wireless communication device becomes very high, and it may be more economical to prepare a plurality of separate wireless communication devices.
[0010]
Furthermore, when the software-defined wireless communication device proposed in Document 1 is applied, there is a demand for enabling two or more processes at a time. However, Document 1 has neither disclosure nor suggestion to realize such a thing.
[0011]
Accordingly, an object of the present invention is to develop the software-defined wireless communication device proposed in Document 1, and to achieve a single wireless communication device that is small in size, low in power consumption and low in price so as to be suitable for carrying. Multi-purpose software-defined radio communication device capable of performing multi-purpose use, that is, multi-purpose software-defined radio receiver, multi-purpose software-defined radio transmitter, multi-purpose software-defined radio transmitter / receiver Is to provide.
[0012]
[Means for Solving the Problems]
  According to a first aspect of the present invention, at least two antennas;Provided corresponding to the at least two antennas,At least two receiving means, andat least2 antennas and aboveat leastA versatile software-defined radio receiving apparatus comprising switching means for selectively connecting between two receiving means,Of different strainsEach of the at least two receiving means converts the high frequency signal to a baseband signalDifferent systems forHas frequency conversion means and memory meansAnd the system is differentWith reconfigurable digital circuit means,For all of the at least two reconstructed digital circuit means,The control meansThe memory means in the at least two reconfigurable digital circuit meansCollaborative operation is possible even if divided and operatedA predetermined program is divided and loaded from shared memory means commonly connected to the at least two reconfigurable digital circuit means or via the antenna, and the at least twoReconstructed digitalA program stored in the memory means in the circuit means, While synchronizing the at least two reconfigurable digital circuit means, the processes are shared and operated in parallel so as to be coordinated.There is provided a multipurpose software-defined radio receiving apparatus that performs one task related to the predetermined program.
[0013]
Preferably, the reconfigurable digital circuit means comprises an FPGA (Field Programmable Gate Array) or a DSP (Digital Signal Processor).
[0014]
The frequency conversion means performs frequency conversion by an orthogonal demodulation method.
[0015]
  According to a second aspect of the invention, at least two antennas;Provided corresponding to the at least two antennas,At least two transmission means, andat least2 antennas and aboveat leastA versatile software-defined radio transmission apparatus comprising switching means for selectively connecting between two transmission means,Of different strainsEach of the at least two transmission means converts the baseband into a high frequency signalDifferent systems forHas frequency conversion means and memory meansAnd the system is differentWith reconfigurable digital circuit means,For all of the at least two reconstructed digital circuit means,The control meansThe memory means in the at least two reconfigurable digital circuit meansCollaborative operation is possible even if divided and operatedA predetermined program is divided and loaded from shared memory means commonly connected to the at least two reconfigurable digital circuit means or via the antenna, and the at least twoReconstructed digitalA program stored in the memory means in the circuit means, While synchronizing the at least two reconfigurable digital circuit means, the processes are shared and operated in parallel so as to be coordinated.There is provided a multipurpose software-defined wireless transmission device that performs one task related to the predetermined program.
[0016]
  According to a third aspect of the invention, at least two antennas;Provided corresponding to the at least two antennas,At least two transmission / reception means, andat least2 antennas and aboveat leastA versatile software-defined wireless communication device comprising switching means for selectively connecting between two transmission / reception means,Of different strainsEach of the at least two transmission / reception means converts the baseband into a high frequency signalDifferent systems forA frequency conversion means, a means for converting a high-frequency signal into a baseband signal, and a memory means.And the system is differentWith reconfigurable digital circuit means,For all of the at least two reconstructed digital circuit means,The control meansThe memory means in the at least two reconfigurable digital circuit meansCollaborative operation is possible even if divided and operatedA predetermined program is divided and loaded from shared memory means commonly connected to the at least two reconfigurable digital circuit means or via the antenna, and the at least twoReconstructed digitalA program stored in the memory means in the circuit means, While synchronizing the at least two reconfigurable digital circuit means, the processes are shared and operated in parallel so as to be coordinated.There is provided a multipurpose software-defined wireless transmission device that performs one task related to the predetermined program.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
With reference to FIG. 1, a multipurpose software-defined radio receiving apparatus as a first embodiment of the multipurpose software-defined radio communication apparatus of the present invention will be described.
[0018]
The multipurpose software-defined wireless receiver 1 illustrated in FIG. 1 includes two antennas 11 and 12, antenna switching means 21, two reception blocks 31, 32, mode switching means 51, and two systems. Direct frequency conversion circuits (DCC) 61 and 62, two analog / digital conversion blocks (A / DC) 71 and 72, and two reconfigurable digital circuits (RDC) Reconfiguable Digital Circuit) 81, 82, data connection means 91 for connecting these two reconfigurable digital circuits 81, 82 to each other so as to exchange data, and two reconfigurable digital circuits 81, 82 Shared memory device (SM) 92 and control means (CONT) 95 connected in common
[0019]
The antenna switching means 21 to which the antennas 11 and 12 are connected can output the output signals of the antennas 11 and 12 freely and selectively according to the control signal S951 output from the control means 95 as follows. It is configured as an array circuit. The terminals in Table 1 indicate the terminals of the antenna switching means 21.
[0020]
[Table 1]
Table 1
Control signal S951    Output of antenna 11    Output of antenna 12
0000 None None
0001 Terminal A None
0010 Without terminal B
0100 None Terminal A
1000 None Terminal B
1001 Terminal A Terminal B
0110 Terminal B Terminal A
[0021]
Each of the reception blocks 31 and 32 includes a band pass filter (BPF), a variable gain low noise high frequency amplifier circuit (LNA), and the like. Each of the reception blocks 31 and 32 may further include a variable filter (Funable Filter) in the subsequent stage of the band pass filter (BPF). The number of reception blocks 31 and 32 is the same as the number of direct frequency conversion circuits (DCC) 61 and 62. In this embodiment, since the direct frequency conversion circuits 61 and 62 are two systems, two reception blocks 31 and 32 are also provided.
The band-pass filter passes the original received signal from which the predetermined low-frequency component signal and the predetermined high-frequency component signal, which are noise components, are removed from the output signals of the output terminals A and B of the antenna switching means 21.
When the reception blocks 31 and 32 are provided with a variable filter, the variable filter is, for example, a frequency specified by the control unit 95 with respect to a signal that has passed through the bandpass filter, for example, under a condition specified by the control unit 95. Filter by characteristics.
[0022]
The variable gain low noise high frequency amplifier circuit (LNA) is capable of changing a high frequency signal that has passed through a bandpass filter (or a high frequency signal that has further passed through a variable filter), for example, a signal of several GHz, while removing low frequency noise. Gain control is performed to amplify a low level signal to a predetermined gain while adjusting the level of the received signal to an appropriate value.
[0023]
The mode switching means 51 to which the output signals of the reception blocks 31 and 32 are connected, like the antenna switching means 21, the output signals of the reception blocks 31 and 32 are shown in Table 2 below according to the control signal S952 of the control means 95. As shown, it is configured as an array circuit so that it can be selectively output freely. The terminals in Table 2 represent output terminals of the mode switching means 51.
[0024]
[Table 2]
Table 2
Control signal S952      Block 31      Block 32
0000 None None
0001 Terminal A None
0010 Without terminal B
0100 None Terminal A
1000 None Terminal B
1001 Terminal A Terminal B
0110 Terminal B Terminal A
[0025]
As described above, the control unit 95 controls the antenna switching unit 21 and the mode switching unit 51 to directly connect the signals received by the antennas 11 and 12 to circuits of arbitrary systems after the frequency conversion circuits 61 and 62. be able to.
[0026]
The first direct frequency conversion circuit 61, the first analog / digital conversion block 71, the first reconfigurable digital circuit 81, the data connection means 91, and the shared memory device 92 constitute the first system receiving circuit 101. is doing.
Similarly, the second direct frequency conversion circuit 62, the second analog / digital conversion block 72, the second reconfigurable digital circuit 82, the data connection means 91, and the shared memory device 92 are used as the second system receiving circuit. 102 is configured.
The data connection means 91 and the shared memory device 92 belong to the first receiving circuit 101 and the second receiving circuit 102 in common.
[0027]
The two direct frequency conversion circuits 61 and 62 have the same circuit configuration.
Similarly, the two analog / digital conversion blocks 71 and 72 have the same circuit configuration.
The two reconfigurable digital circuits 81 and 82 have exactly the same circuit configuration.
That is, the first-system reception circuit 101 and the second-system reception circuit 102 have exactly the same circuit configuration, that is, a dual circuit configuration, with the data connection means 91 and the shared memory device 92 as a common circuit.
[0028]
The direct frequency conversion circuits 61 and 62 directly convert a high frequency signal amplified by the variable gain low noise high frequency amplifier circuit in the reception blocks 31 and 32, for example, a high frequency signal of several GHz to a baseband signal, for example. Circuit (down converter). Direct frequency conversion circuits (DCC) 61 and 62 as down converters can convert, for example, a frequency signal corresponding to a frequency control signal from the control means 95, for example, a baseband signal.
As such direct frequency conversion circuits 61 and 62, a circuit disclosed in, for example, a patent application publication based on International Patent Cooperation Treaty (PCT), WO99233166, which utilizes quadrature demodulation, Japanese Patent Laid-Open No. 9-8699. It is desirable to use the circuit disclosed in Japanese Unexamined Patent Publication No. 11-317777 or the circuit disclosed in Japanese Patent Application Laid-Open No. 11-317777 from the viewpoint of miniaturization of the circuit.
[0029]
Analog / digital conversion blocks (A / DC) 71 and 72 convert, for example, received analog signals converted up to baseband into digital signals by direct frequency conversion circuits 61 and 62. Since three types of signals are output from the direct frequency conversion circuits (DCC, down converter) 61 and 62, the analog / digital conversion blocks 71 and 72 each have three antenna / digital conversion circuits. ing. That is, three antenna / digital conversion circuits are illustrated as one analog / digital conversion block.
[0030]
The reconfigurable digital circuits 81 and 82 are circuits having a memory capable of storing a program and a signal processing circuit.
As such digital circuits 81 and 82, for example, an FPGA (Field Programmable Gate Array) having a memory can be used by allowing a user to incorporate a program in the field (site) and enabling desired program processing. it can.
Alternatively, as the digital circuits 81 and 82, a high-speed signal processing device having a memory known as a DSP (digital signal processor) can be used.
[0031]
Both the FPGA and the DSP have a memory, and the loaded program can be operated by loading the program into the memory. Therefore, as will be described later, by downloading a desired program from the program supplier via the antennas 11 and 12 and storing it in the memory, the two reconfigurable digital circuits 81 and 82 operate the program. be able to.
[0032]
Alternatively, various programs are stored in the shared memory device 92, the desired program is read from the shared memory device 92, transferred to the FPGA or DSP memory, and stored there, and then two reconfigurable digital The circuit (RDC) 81 and 82 can operate the program.
[0033]
As described above, the FPGA or the DSP is a reconfigurable digital circuit (RDC) 81, 82 that is small, high-speed, flexible, has a proven track record in various fields, has high reliability, and is a low-cost circuit. There are advantages.
[0034]
The data connection means 91 is used for mutual data communication between the reconfigurable digital circuits (RDC) 81 and 82. As the data connection means 91, for example, when the digital circuits 81 and 82 are configured by a DSP, a circuit capable of directly reading / writing between the memories of the DSP, or a DSP communication means for connecting two DSPs by a high-speed data bus, etc. Realize with.
In the case where the DSPs of the digital circuits 81 and 82 are exchanged via the shared memory device 92, the shared memory device 92 can be handled as one type of the data connection means 91.
[0035]
The shared memory device 92 is a shared storage means accessible from both of the reconfigurable digital circuits 81 and 82.
As the shared memory device 92, as described above, in the case where various programs operable by the digital circuits 81 and 82 are stored, a small magnetic disk, a magneto-optical disk, a floppy disk, or the like is used. be able to. Alternatively, a nonvolatile semiconductor memory or the like can be used, or a bipolar semiconductor memory capable of high speed operation can be used. Of course, the shared memory device 92 may be a combination of these memories as appropriate.
[0036]
First operation example
A first operation mode of the versatile software-defined radio receiving apparatus 1 illustrated in FIG. 1 will be described with reference to FIG.
2 shows a first mode of operation of the versatile software-defined radio receiver 1 of FIG. 1, that is, digital circuits 81 and 82 capable of reconstructing two independent programs stored in the shared memory device 92. FIG. 6 is a flowchart showing processing operations in the case where two independent operations are performed in the multipurpose software-defined radio receiving apparatus 1 using these programs.
[0037]
Step 1: Load the program
When the user operates an operation button (not shown) to instruct to download two programs from a program supplier, for example, the shared memory device 92 via the control unit 95, the control unit 95 stores the program in the shared memory device 92. Among the plurality of programs, the corresponding program is transferred to respective memories of reconfigurable digital circuits (RDC) 81 and 82.
For example, when an FPGA is used as the reconfigurable digital circuits 81 and 82, the first and second programs transferred from the shared memory device 92 are stored in the FPGA memory.
[0038]
Step 2: Circuit setting
The control means 95 controls the antenna switching means 21 and the mode switching means 51 according to the user's designation, and establishes a circuit as follows.
[0039]
[Table 3]
Table 3
First circuit: a circuit in which an antenna 11, a first reception block (BPF, LNA) 31, and a first-system reception circuit 101 are connected.
Second circuit: a circuit in which the antenna 12, the second receiving block (BPF, LNA) 33, and the second receiving circuit 102 are connected.
[0040]
Step 3: Start independent operation
After the establishment of the circuit, the control means 95 operates the FPGAs constituting the reconfigurable digital circuits 81 and 82, and is loaded from the shared memory device 92 and stored in the memory. Run the second program.
[0041]
As a result, the established first circuit and second circuit can operate independently according to the first and second programs, respectively. That is, processing of signals received via the antennas 11 and 12, the reception blocks 31 and 32, the direct frequency conversion circuits 61 and 62, and the analog / digital conversion blocks 71 and 72 is performed independently by the two FPGAs 81 and 82. Can do.
[0042]
Second operation example
A second operation mode of the versatile software-defined radio receiving apparatus 1 illustrated in FIG. 1 will be described with reference to FIG.
FIG. 3 shows a second mode of operation of the multipurpose software-defined radio receiver 1 of FIG. 1, that is, a program stored in the shared memory device 92 is divided into reconfigurable digital circuits 81 and 82. FIG. 10 is a flowchart showing a processing operation in a case where one operation is performed in cooperation with digital circuits 81 and 82 capable of reconstructing one program that has been loaded and divided.
[0043]
Step 11: Load the program
When the user operates an operation button (not shown) to instruct to download one program from a program supplier, for example, the shared memory device 92 via the control unit 95, the control unit 95 stores the program in the shared memory device 92. One program is transferred in half to the respective memories of the reconfigurable digital circuits 81 and 82. The program is created so that it can operate in cooperation even if it is divided.
As the digital circuits 81 and 82, for example, when an FPGA is used, half of the program transferred from the shared memory device 92 is stored in the FPGA memory.
[0044]
Step 12: Circuit setting
The control means 95 controls the antenna switching means 21 and the mode switching means 51 according to the user's designation, and establishes the circuits shown in Table 2 as described above.
[0045]
Step 13: Start cooperative action
After the establishment of the circuit, the control means 95 operates the FPGA constituting the reconfigurable digital circuits (RDC) 81 and 82 and is loaded from the shared memory device 92 and stored in the memory. Run half a program.
A half-by-one program operates in parallel by sharing processing while synchronizing both of the two FPGAs via the data connection means 91.
As a result, the established first circuit and second circuit can operate independently according to the first and second programs, respectively. That is, processing of signals received via the antennas 11 and 12, the reception blocks 31 and 32, the direct frequency conversion circuits 61 and 62, and the analog / digital conversion blocks (ADC) 71 and 72 is shared by the two FPGAs 81 and 82. However, the process can proceed.
[0046]
For example, when the capacity of one program is large and the memory of one FPGA cannot be accommodated and divided, the processing is divided into two memories of two FPGAs and loaded. It is suitable for the case where it is shared.
[0047]
Alternatively, if the received data volume is enormous and processing time is too long for one FPGA, the same program is loaded into the FPGA memory, and the data received by the first circuit and the second circuit are paralleled. Therefore, it is suitable for reducing the processing time by dividing the process.
While the data processing is time-matched via the data connection means 91, the processing result data can be stored in, for example, the shared memory device 92 and shared by the two FPGAs.
[0048]
Third operation example
A third operation mode of the multipurpose software-defined radio receiving apparatus 1 illustrated in FIG. 1 will be described with reference to FIG.
FIG. 4 is a flowchart showing a third operation mode of the multipurpose software-defined radio receiving apparatus 1 of FIG. 1, that is, a processing operation in the case of performing space diversity reception processing using the antennas 11 and 12.
[0049]
Step 21: Load the program
When the user operates an operation button (not shown) to instruct to download a desired program from a program supplier, for example, the shared memory device 92 via the control unit 95, the control unit 95 One program for spatial diversity stored in the (SM) 92 is transferred to each memory of the reconfigurable digital circuits 81 and 82.
As the reconfigurable digital circuits (RDC) 81 and 82, for example, when an FPGA is used, the same program for spatial diversity transferred from the shared memory device 92 is stored in the FPGA memory.
[0050]
Step 22: Circuit setting
The control means 95 controls the antenna switching means 21 and the mode switching means 51 according to the user's designation, and establishes the circuits shown in Table 2 as described above.
[0051]
Step 23: Start semi-independent operation
After the establishment of the circuit, the control means 95 operates the FPGA constituting the reconfigurable digital circuits (RDC) 81 and 82 and is loaded from the shared memory device 92 and stored in the memory. Run the same program for space diversity independently.
As a result, the FPGA of the first circuit and the FPGA of the second circuit calculate the strengths of the signals received by their own circuits, and exchange the data of those strength signals via the data connection means 91. It is compared and judged whether the intensity of the signal is high.
Then, the FPGA of the first circuit and the FPGA of the second circuit perform reception signal processing using a circuit connected to the antenna having the higher signal strength.
[0052]
As described above, the multipurpose software stipulated radio receiving apparatus 1 having the circuit configuration of FIG. 1 exchanges programs that operate in the reconfigurable digital circuits 81 and 82 and multipurpose software stipulated radio receiving. Various processes can be performed by appropriately setting the circuit configuration in the apparatus 1.
In addition, since data can be exchanged between the reconfigurable digital circuits 81 and 82 via the data connection means 91 or the shared memory device 92, one task can be distributedly processed by the reconfigurable digital circuits 81 and 82. You can also.
[0053]
In the above, the case where the FPGA is used as the reconfigurable digital circuits 81 and 82 has been described, but the same applies to the case where the DSP is used.
[0054]
Other program loading methods
In the above-described embodiment, the case where the program to be loaded into the FPGA or DSP which is the reconfigurable digital circuit 81 or 82 is loaded from the shared memory device 92 has been described, but it is necessary from the program supplier via the antennas 11 and 12. Can also be downloaded and loaded into the FPGA or DSP memory.
The subsequent operation of the versatile software-defined radio receiving apparatus 1 is the same as described above.
[0055]
The multipurpose software-defined radio receiving apparatus 1 illustrated in FIG. 1 is not limited to two systems, and can be expanded to a plurality of systems of three or more. For example, if four systems are used, four types of processing can be performed independently, or one processing can be performed in four divisions using four reconfigurable digital circuits (RDCs).
[0056]
Second embodiment
With reference to FIG. 5, a multipurpose software-defined radio communication apparatus will be described as a second embodiment of the multipurpose software-defined radio communication apparatus of the present invention.
[0057]
The multipurpose software-defined wireless transmitter 1A illustrated in FIG. 5 includes two antennas 11 and 12, antenna switching means 21A, two transmission blocks 131 and 132, mode switching means 51A, and two direct frequencies. Conversion circuits (DCC: Direct frequency conversion circuit, upconverters) 161, 162, two digital / analog conversion blocks (DACs) 171, 172, two reconfigurable digital circuits (RDCs) 81A, 82A, a data connection means 91 for connecting these two reconfigurable digital circuits 81A and 82A to each other so as to exchange data and a common connection to the two reconfigurable digital circuits 81 and 82 Shared memory device (SM) 92 and control means (CON ) With a 95A.
[0058]
The multipurpose software stipulated radio transmitting apparatus 1A illustrated in FIG. 5 is an inverse circuit of the multipurpose software stipulated radio receiving apparatus 1 illustrated in FIG.
[0059]
The antennas 11 and 12 in FIG. 5 are the same as the antennas 11 and 12 in FIG.
Although the signal transmission direction is opposite, the antenna switching means 21A of FIG. 5 and the antenna switching means 21 of FIG. 1 are similar circuits, and perform signal selection similar to Table 1 above according to the operation of the control means 95A. be able to.
Each of the transmission blocks 131 and 132 has an inverse circuit configuration with respect to the reception blocks 31 and 32 illustrated in FIG. 1, and includes a variable gain low noise high frequency amplifier circuit (LNA), a band pass filter (BPF), and the like. Yes. The bandpass filter (BPF) and variable gain low noise high frequency amplifier circuit (LNA) in the transmission blocks 131 and 132 are the same as the bandpass filter (BPF) and variable gain in the reception blocks 31 and 32 described with reference to FIG. It is a circuit similar to a low noise high frequency amplifier circuit (LNA).
Although the signal transmission direction is reversed, the mode switching means 51A of FIG. 5 and the mode switching means 51 of FIG. 1 are similar circuits, and perform signal selection similar to Table 2 above according to the operation of the control means 95A. be able to.
[0060]
Direct frequency conversion circuits 161 and 162 in FIG. 5 convert a low frequency signal into a high frequency signal, whereas direct frequency conversion circuits 61 and 62 in FIG. 1 are down converters. It is different to be an up-converter. However, the direct frequency conversion circuits 161 and 162 can also have a circuit configuration using orthogonal transform, similar to the direct frequency conversion circuits 61 and 62. The direct frequency conversion circuits (DCC, up-converter) 161 and 162 can also perform frequency conversion according to the frequency control signal from the control means 95A.
[0061]
The digital / analog conversion blocks 171 and 172 in FIG. 5 are circuit blocks for converting a digital signal into an analog signal, which is the reverse of the analog / digital conversion blocks 71 and 72 in FIG. These digital / analog conversion blocks (DAC) 171 and 172 also indicate three digital / antenna conversion circuits. This is because three types of digital signals are output to the direct frequency conversion circuits (DCC, up-converter) 161 and 162, respectively.
[0062]
The reconfigurable digital circuits 81A and 81B shown in FIG. 5 can be configured using an FPGA, a DSP, etc., like the reconfigurable digital circuits 81 and 82 shown in FIG.
[0063]
The data connection means 91 and the shared memory device 92 are substantially the same in FIG. 1 and FIG.
[0064]
5 includes an antenna switching unit 21A, a mode switching unit 51A, two direct frequency conversion circuits (DCC, upconverter) 161 and 162, and two reconfigurable digital circuits (RDC) 81A, Control according to the transmission process is performed on 82A.
[0065]
Also in the multipurpose software-defined wireless transmission device 1A of FIG. 5, the reconfigurable digital circuits 181 and 182 are operated in their memories using the FPGA or DSP, and the program is read from the shared memory device 92. It can be read out and downloaded from the distributor via the antennas 11 and 12 and loaded into the memory of the FPGA or DSP for transmission processing.
[0066]
2 to 4 show an example of the reception process of the multipurpose software-defined radio receiving apparatus 1 of FIG. 1, the multipurpose software-defined radio transmitting apparatus 1A of FIG. The transmission process corresponding to the process illustrated in FIG. 4 can be performed.
[0067]
In particular, various types of signal transmission paths can be set by appropriately selecting the antenna switching means 21A and the mode switching means 51A under the control of the control means 95A.
[0068]
The digital data signal-processed by the reconfigurable digital circuits 81A and 82A are converted into analog signals by the DACs 171 and 172, respectively. The direct frequency conversion circuits 161 and 162, for example, convert baseband signals to high-frequency signals, A signal which has been amplified by a variable gain low noise high frequency amplifier circuit (LNA) in the transmission blocks 131 and 132 and passed through the band pass filter is transmitted from the antennas 11 and 12 via the antenna switching means 21A via the mode switching means 51A. Is done.
[0069]
Also in the multipurpose software-defined wireless transmission device 1A illustrated in FIG. 5, two kinds of processing can be performed simultaneously by loading desired programs into reconfigurable digital circuits (RDC) 81A and 82A, or 1 One process can be shared.
[0070]
Third embodiment
With reference to FIG. 6, a multipurpose software-defined radio communication apparatus will be described as a third embodiment of the multipurpose software-defined radio communication apparatus of the present invention.
[0071]
A multipurpose software-defined radio transmitting / receiving apparatus 1B illustrated in FIG. 6 includes a multipurpose software-defined radio receiving apparatus 1 illustrated in FIG. 1 and a multipurpose software-defined radio transmitting apparatus 1A illustrated in FIG. Are combined.
Since the multi-purpose software-defined wireless transceiver 1B of FIG. 6 is provided with two transmission / reception circuits, two types of transmission / reception can be performed simultaneously or at different times.
For this purpose, the transmission / reception and signal processing programs are loaded into the reconfigurable digital circuits 81B and 82B from the shared memory device 92 or wirelessly.
[0072]
As an example of performing such two types of transmission / reception, for example, PHS communication and ITS communication can be simultaneously performed by one multipurpose software-defined wireless transmission / reception device 1B illustrated in FIG. Alternatively, ITS communication and IP digital communication can be performed simultaneously.
[0073]
The above-described embodiments are merely examples of the present invention. Therefore, various modifications can be made in accordance with the idea of the present invention.
[0074]
【The invention's effect】
As described above, the versatile software-defined wireless communication device of the present invention can load various programs by loading a desired program into a reconfigurable digital circuit and appropriately driving antenna switching means, mode switching means, and the like. Can be performed simultaneously, independently, or in concert.
[0075]
The versatile software-defined wireless communication device of the present invention constitutes a digital circuit that can be reconstructed with an easy-to-use FPGA, DSP, etc., and uses a direct frequency conversion circuit with a small circuit scale, so it is small and lightweight. Can be manufactured at a low price.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a multipurpose software-defined radio receiving apparatus as a first embodiment of a multipurpose software-defined radio communication apparatus according to the present invention;
FIG. 2 is a flowchart showing the processing operation of the first form of the operation mode of the multipurpose software-defined radio receiving apparatus of FIG. 1;
FIG. 3 is a flowchart showing the processing operation of the second mode of the operation mode of the multipurpose software-defined radio receiving apparatus of FIG. 1;
4 is a flowchart showing a processing operation of a third form of the operation mode of the versatile software-defined radio receiving apparatus of FIG. 1; FIG.
FIG. 5 is a configuration diagram of a multipurpose software-defined radio transmission apparatus as a second embodiment of the multipurpose software-defined radio communication apparatus of the present invention.
FIG. 6 is a block diagram of a multipurpose software-defined radio transceiver apparatus as a third embodiment of the multipurpose software-defined radio communication apparatus of the present invention.
[Explanation of symbols]
1. Multipurpose software-defined type wireless receiver
1A ・ ・ Multi-use software-defined radio transmitter
1B ・ ・ Multi-use software-defined wireless transceiver
11, 12, ... Antenna
21, 21A, 21B .. Antenna switching means
31, 32 ... Reception block
51, 51A, 51B ·· Mode switching means
61, 62 .. Direct frequency conversion circuit (DCC, down converter)
71, 72 .. Analog / digital conversion block (A / DC)
81, 82 .. Reconfigurable digital circuit (RDC)
91 .. Data connection means
92 .. Shared memory device
95 .. Control means
131, 132 ... Transmission block
161, 162 .. Direct frequency conversion circuit
(DCC, upconverter)
171, 172 .. Digital / analog conversion block (DAC)

Claims (12)

At least two antennas;
Provided corresponding to the at least two antennas, and at least two receiving means of different systems ;
A versatile software defined type radio receiver device comprising a switching means for the selective connection between said at least two antennas and the at least two receiving means,
Each of the at least two receiving means of the different strains, and the frequency conversion means systems are different for converting a high-frequency signal into a baseband signal, have a memory unit, the system is composed of different reconfigurable digital circuit means and,
For all of the at least two reconstructed digital circuit means, the control means comprises:
Shared memory means commonly connected to the at least two reconfigurable digital circuit means for a predetermined program that can operate in cooperation with the memory means in the at least two reconfigurable digital circuit means. From or through the above antenna,
The program stored in said memory means in said at least two reconfigurable digital circuit means, by cooperative operation by operating in parallel to share the processing while attempted synchronization of the at least two reconfigurable digital circuit means To perform one task related to the predetermined program,
Multipurpose software-defined wireless receiver. The reconfigurable digital circuit means is composed of an FPGA (Field Programmable Gate Array).
The multipurpose software-defined wireless receiver according to claim 1. The reconfigurable digital circuit means comprises a DSP (digital signal processor);
The multipurpose software-defined wireless receiver according to claim 1. The multipurpose software-defined radio receiving apparatus according to claim 1, wherein the frequency converting means performs frequency conversion by an orthogonal demodulation method. At least two antennas;
Provided corresponding to the at least two antennas, and at least two transmission means of different systems ;
A versatile software defined wireless transmission device comprising a switching means for the selective connection between said at least two antennas and the at least two transmission means,
Each of the at least two transmission means of the different strains, and the frequency conversion means systems are different for converting the baseband frequency signal, have a memory unit, is composed of a reconfigurable digital circuit means strains differ cage,
For all of the at least two reconstructed digital circuit means, the control means comprises:
Shared memory means commonly connected to the at least two reconfigurable digital circuit means for a predetermined program that can operate in cooperation with the memory means in the at least two reconfigurable digital circuit means. From or through the above antenna,
The program stored in said memory means in said at least two reconfigurable digital circuit means, by cooperative operation by operating in parallel to share the processing while attempted synchronization of the at least two reconfigurable digital circuit means To perform one task related to the predetermined program,
Multipurpose software-defined wireless transmitter. The reconfigurable digital circuit means is composed of an FPGA (Field Programmable Gate Array).
The multipurpose software-defined wireless transmission device according to claim 5. The reconfigurable digital circuit means comprises a DSP (digital signal processor);
The multipurpose software-defined wireless transmission device according to claim 5. The multipurpose software-defined radio transmission apparatus according to claim 5, wherein the frequency conversion means performs frequency conversion by an orthogonal demodulation method. At least two antennas;
Provided corresponding to the at least two antennas, and at least two transmission / reception means of different systems ;
A versatile software defined wireless communication apparatus comprising a switching means for the selective connection between said at least two antennas and the at least two transmitting and receiving means,
Said each of the at least two transceiver means different strains, possess means for converting the frequency conversion means and the high-frequency signal system is different for converting the baseband frequency signal to a baseband signal, a memory means, strains Consisting of different reconfigurable digital circuit means ,
For all of the at least two reconstructed digital circuit means, the control means comprises:
Shared memory means commonly connected to the at least two reconfigurable digital circuit means for a predetermined program that can operate in cooperation with the memory means in the at least two reconfigurable digital circuit means. From or through the above antenna,
The program stored in said memory means in said at least two reconfigurable digital circuit means, by cooperative operation by operating in parallel to share the processing while attempted synchronization of the at least two reconfigurable digital circuit means To perform one task related to the predetermined program,
Multipurpose software-defined wireless transmitter. The reconfigurable digital circuit means is composed of an FPGA (Field Programmable Gate Array).
The multipurpose software-defined wireless communication apparatus according to claim 9. The reconfigurable digital circuit means comprises a DSP (digital signal processor);
The multipurpose software-defined wireless communication apparatus according to claim 9. The multipurpose software-defined radio communication device according to claim 9, wherein the frequency conversion means performs frequency conversion by an orthogonal demodulation method.

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