JP4397699B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to an error correction technique for a semiconductor integrated circuit and a memory included therein.

  It has a content addressable memory (abbreviated as “CAM”) and a random access memory (abbreviated as “RAM”) on the same substrate, and stores data and check bits (or encoded data) in the RAM. A technique is known in which error detection / correction is performed using the data read from the data and the check bit (or encoded data), and the CAM is refreshed using the RAM data (see, for example, Patent Document 1).

  In addition, the parity code generated from the input data is stored, and when the input data matches the CAM data, the parity code corresponding to that word is compared with the parity code generated from the input data, so that a soft error can be detected. A technique for detection is known (see, for example, Patent Document 2).

US Patent Application Publication No. 2003/0007408

US Pat. No. 6,067,656

  CAM is used for applications such as cache memory management. In applications such as cache memory management, a soft error occurs in the CAM and wrong data is read only when there is a mismatch, and when there is no match due to a soft error, it is processed as a miss and the lower memory Since the error is automatically repaired by re-reading from, there was no major inconvenience. For this reason, conventionally, only measures for preventing a mismatch are taken.

  However, when a CAM is used to classify packets in a router or a network switch of a network device that has started to use CAM in recent years, there is a serious inconvenience in packet processing due to a mismatch caused by a soft error. May occur. For example, it is necessary to pass only a specific IP address, and when a passable IP address is stored in the CAM, if it does not match due to a soft error of the CAM, a packet that should originally pass through cannot be passed. It will cause a failure. As a method for avoiding this, the error correction technique described in Patent Document 1 is not sufficient as an error detection method because the error detection of the CAM itself is not performed. Also, the soft error detection technique based on parity code comparison as described in Patent Document 2 is effective only when an error occurs in the CAM data and matches the input data. If this happens, error detection is not possible.

  An object of the present invention is to provide a technique for ensuring high reliability against soft errors.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, an error correction code generation circuit for generating an error correction code for entry data written in the CAM portion, and error detection and error correction based on the error correction code for read data from the CAM portion An error detection and correction circuit is provided.

  According to the above means, the error detection and correction circuit performs error detection and error correction on the read data from the CAM unit based on the error correction code. This error detection and error correction does not affect the performance of the CAM unit. If the error does not match the comparison data due to an error, the network failure can be avoided by setting the period from the error occurrence to the error detection to be equal to or less than the timeout period of a retransmission request such as TCP / IP. This achieves high reliability against soft errors.

  At this time, in the error detection and correction circuit, in order to prevent data destruction in the CAM unit, error detection and error correction based on the error correction code is performed at a timing excluding the data write cycle to the CAM unit. good.

  A RAM unit capable of storing the error correction code generated by the error correction code creating circuit may be provided, and the error detection and error correction may be performed based on the error correction code in the RAM unit.

  In the CAM unit, a second storage area for storing the error correction code is provided separately from the first storage area for storing the comparison data, and the error correction code stored in the second storage area is provided. The error detection and the error correction can be performed based on the above.

  A parity generation circuit for generating a parity bit to be added to data to be written in the CAM unit is also provided in order to prevent erroneous entry data from matching with each other even during a period from error occurrence to error correction. Can be provided.

  In order to notify the occurrence of an error, the error detection and correction circuit may output a signal indicating an error detection state.

  The CAM unit can adopt a cell structure that enables storage of ternary data.

  The CAM unit includes a dynamic cell having a charge storage capacity for data storage, and the error detection and correction circuit uses data read for refreshing the dynamic cell. Thus, the software can be configured to perform soft error detection and error correction based on the error correction code. At this time, it is possible to provide a selector capable of substituting the data corrected by the error detection and correction circuit for the write data to the dynamic cell at the time of refresh.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide a technique for ensuring high reliability against soft errors.

  FIG. 15 shows a router LSI which is an example of a semiconductor integrated circuit according to the present invention. The router LSI 200 includes a routing processor 201 that performs transfer processing of the packet according to destination address information included in the packet data in accordance with a predetermined program, and IP address information corresponding to the destination address transmitted from the routing processor 201 in a routing table. And a routing information output unit 220 for outputting routing information corresponding to the IP address information searched by the IP address search unit 210, and a known semiconductor integrated circuit. It is formed on one semiconductor substrate such as a single crystal silicon substrate by a circuit manufacturing technique. The routing processor 201 performs packet data transfer processing according to the routing information transmitted from the routing information output unit 220. The routing information output unit 220 is not particularly limited, but includes a RAM (random access memory) 221 in which routing information is stored in relation to an IP address, and a decoder 222 that decodes a search result in the IP address search unit 210. A direct peripheral circuit 223 for inputting / outputting data to / from the RAM 221 is included. Based on the decoding result of the decoder 222, the corresponding routing information is read from the RAM 221 and transmitted directly to the routing processor 201 via the peripheral circuit 223.

  FIG. 1 shows a configuration example of the IP address search unit 210.

  The IP address search unit 210 is not particularly limited, but includes an address buffer 1, a data input / output buffer 2, an address counter 3, a command decoder 4, selectors 5, 6, and 7, a CAM unit 8, and a RAM (random access memory). Section 9, ECC generation circuit 10, error detection and correction circuit 11, correction data latch 12, defective address latch 13, and priority encoder 14.

  The CAM unit 8 includes a plurality of memory cells arranged in an array, an address decoder for decoding an input address signal, and the like.

  The address buffer 1 is provided for capturing an address signal transmitted from the routing processor 201. The address signal transmitted from the routing processor 201 is transmitted to the selector 5 through the address buffer 1.

  The data input / output buffer 2 is provided for taking in data transmitted from the routing processor 201 and transmitting correction data transmitted from the error detection and correction circuit 11 to the routing processor 201. Data transmitted from the routing processor 201 is transmitted to the selector 6 via the data input / output buffer 2. The correction data transmitted from the error detection and correction circuit 11 can be transmitted to the routing processor 201 and the selector 6 via the data input / output buffer 2.

  The command decoder 4 has a function of decoding a command transmitted from the routing processor 201. The result of decoding by the command decoder 4 is transmitted to the address counter 3 and the selectors 5, 6 and 7.

  The address counter 3 generates an address signal for reading data based on the output signal of the command decoder 4. The generated address signal is transmitted to selectors 5 and 7.

  The selector 5 selectively sends the address signal transmitted from the address buffer 1, the defective address signal transmitted from the defective address latch 13, and the address signal transmitted from the address counter 3 to the subsequent CAM unit 8. introduce. The selection operation of the selector 5 is controlled by the output signal of the command decoder 4.

  The selector 6 selectively transmits the data transmitted via the data input / output buffer 2 and the output data of the correction data latch 12 to the ECC generation circuit 10. The selection operation of the selector 6 is controlled by the output signal of the command decoder 4.

  The selector 7 selectively sends the address signal transmitted from the address buffer 1, the defective address signal transmitted from the defective address latch 13, and the address signal transmitted from the address counter 3 to the subsequent RAM unit 9. introduce. The selection operation of the selector 7 is controlled by the output signal of the command decoder 4.

  The ECC generation circuit 10 creates an error correction code (ECC) for the entry data written to the CAM unit 8. The created error correction code is written in the RAM unit 9.

  The error detection and correction circuit 11 performs soft error detection and error correction of the entry data stored in the CAM unit 8 based on the error correction code stored in the RAM unit 9. This soft error detection and error correction are performed at a timing excluding the write cycle to the CAM unit 8. By the processing in the error detection and correction circuit 11, an ECC status signal, error correction data, and a defective address signal are output. The ECC status signal is transmitted to the routing processor 201. The error correction data is transmitted to the selector 6 through the correction data latch 12, and the defective address signal is transmitted to the selectors 5 and 7 through the defective address latch 13.

  The priority encoder 14 outputs match address information and a match status signal with the highest priority when a plurality of addresses match. The match address information and the match status signal are transmitted to the routing information output unit 220. The match status signal is also transmitted to the routing processor 201.

  FIG. 4 shows the operation timing of the main part in the configuration shown in FIG.

  When writing to the CAM unit 8 is instructed by a command supplied to the command decoder 4, data is written to the CAM unit 8 and the error correction code generated by the ECC generation circuit 10 is written to the RAM unit 9. It is.

  When data read from the CAM unit 8 is instructed by a command supplied to the command decoder 4, the data is read from the CAM unit 8 and transmitted to the routing processor 201 via the data input / output buffer 2. The

  When the data search of the CAM unit 8 is instructed by the command supplied to the command decoder 4, the comparison data transmitted via the data input / output buffer 2 and the selector 6 and the entry stored in the CAM unit 8 are stored. Comparison with the data is performed in the CAM unit 8. If there is an address with matching data in this comparison, the match status signal is enabled and the address information is output. When a plurality of addresses match, the priority encoder 14 selects the address information with the highest priority.

  When the command supplied to the command decoder 4 is not one of the above, for example, when the operation of the CAM unit 8 is unnecessary, or when the CAM is divided into a plurality of blocks and the operation of some CAMs is unnecessary. The stored data is read out from both the CAM unit 8 and the RAM unit 9, and error detection (ECC check) is performed in the error detection and correction circuit 11. If an error has occurred, the ECC status signal is set to an error state (eg, logical value “1”), and the error-corrected data and the defective address are stored in the corresponding latches 12 and 13, respectively. Here, the address signal for reading is automatically generated by the increment operation of the address counter 3. That is, the address counter 3 generates an address signal by adding 1 each time the above reading is performed. When the CAM unit 8 is a circuit that can be read simultaneously with the search, the time from the occurrence of the error to the error detection is shortened by reading the CAM unit 8 simultaneously with the search.

  When the error correction is instructed by the command supplied to the command decoder 4, the correction data is written to the corresponding address in the CAM unit 8. That is, the data held in the correction data latch 12 is transmitted to the CAM unit 8 via the selector 6, and the holding address of the defective address latch 13 is transmitted to the CAM unit 8 via the selector 5. Correction data is written to the address. At this time, an error correction code is generated again in the ECC generation circuit 10 and written in the RAM unit 9. A defective address stored in the defective address latch 13 is used as a write address to the RAM unit 9.

  In the example shown in FIG. 4, after data is written from addresses A0 to An, the data from Ds0 to Dsk + 3 is searched. At the time of writing, data Dw0 to Dwn are written to the CAM unit 8 and at the same time, error correction codes ecc0 to ecn are written to corresponding addresses of the RAM unit 9. At the time of retrieval, data is read from the CAM unit 8 and the RAM unit 9 simultaneously with the retrieval of the CAM unit 8, and error detection is performed. An error occurs at address k, and the ECC status signal is set to a logical value “1” in the next cycle, and a defective address is output. When the error correction command is input, the corrected data Dwk is written to the address k of the CAM unit 8 and the RAM unit 9. In this example, the ECC status signal is monitored by the routing processor 201 shown in FIG. 15, and when an error occurs, the search is temporarily suspended and an error correction command is issued. It is possible to detect the search idle time and correct the error without using the command, but by stopping the search and repairing the error, the time from error occurrence to correction can be shortened. it can. Also, by collecting error addresses with the controller, it is possible to grasp the error occurrence status, and by identifying whether the error is a random error or due to a device failure, it is possible to replace parts such as parts replacement. It is possible to cope with improvement in reliability. Further, error detection after error correction is performed from the address where the error has occurred, so that it is possible to confirm that the error is not a permanent error.

  FIG. 5 shows a configuration example for one of a plurality of CAM cells constituting the CAM unit 8.

  The CAM cell MC (0, 0) is called a ternary CAM having two static storage units, and includes a first word line WA, a second word line WB, a comparison match line MATCH, The data line DO, the second data line D1, the first comparison data line CD0, and the second comparison data line CD1 are arranged so as to intersect with each other, and at the intersections, the first storage unit DA, the second storage unit DB, A first comparison circuit 511 and a second comparison circuit 512 are arranged.

  The first storage unit DA includes a first inverter formed by connecting a p-channel MOS transistor ML0A and an n-channel MOS transistor MD0A in series, and a p-channel MOS transistor ML1A and an n-channel MOS transistor MD1A connected in series. And a second inverter formed in a loop. The source electrodes of the p-channel MOS transistors ML0A and ML1A are coupled to the high potential power source Vdd, and the source electrodes of the n-channel MOS transistors MD0A and MD1A are coupled to the low potential power source Vss. The first storage unit DA includes a first storage node 513 and a second storage node 514. The first storage node 513 is coupled to the first data line D0 via an n-channel MOS transistor MT0A that is a transfer MOS, and the second storage node 514 is connected via an n-channel MOS transistor MT1A that is a transfer MOS. Are coupled to the second data line D1. The gate electrodes of the n-channel MOS transistors MT0A and MT1A are coupled to the first word line WA. When the first word line WA is driven to a high level, the n-channel MOS transistors MT0A and MT1A are turned on, It is possible to read data from one storage unit DA and write data to the first storage unit DA.

  The second storage unit DB includes a first inverter formed by connecting a p-channel MOS transistor ML0B and an n-channel MOS transistor MD0B in series, and a p-channel MOS transistor ML1B and an n-channel MOS transistor MD1B connected in series. And a second inverter formed in a loop. The source electrodes of the p-channel MOS transistors ML0B and ML1B are coupled to the high potential power source Vdd, and the source electrodes of the n-channel MOS transistors MD0B and MD1B are coupled to the low potential power source Vss. The second storage unit DB includes a first storage node 515 and a second storage node 516. The first storage node 515 is coupled to the first data line D0 via an n-channel MOS transistor MT0B which is a transfer MOS, and the second storage node 516 is connected via an n-channel MOS transistor MT1B which is a transfer MOS. Are coupled to the second data line D1. The gate electrodes of the n-channel MOS transistors MT0B and MT1B are coupled to the second word line WB. When the second word line WB is driven to a high level, the n-channel MOS transistors MT0B and MT1B are turned on, It is possible to read data from the two storage units DB and write data to the second storage unit DB.

  The first comparison circuit 511 includes two n-channel MOS transistors MCA and MC0 connected in series. The drain electrode of n channel type MOS transistor MCA is coupled to comparison match line MATCH, and the gate electrode of n channel type MOS transistor MCA is coupled to first storage node 513 of first storage unit DA. The source electrode of the n-channel MOS transistor MC0 is coupled to the low potential side power supply Vss, and the gate electrode of the n-channel MOS transistor MC0 is coupled to the first comparison data line CD0.

  The second comparison circuit 512 includes two n-channel MOS transistors MCB and MC1 connected in series. The drain electrode of n-channel MOS transistor MCB is coupled to comparison match line MATCH, and the gate electrode of n-channel MOS transistor MCB is coupled to first storage node 515 of second storage unit DB. The source electrode of the n-channel MOS transistor MC1 is coupled to the low potential side power source Vss, and the gate electrode of the n-channel MOS transistor MC1 is coupled to the second comparison data line CD1.

  In the above configuration, when DA = “0” and DB = “1”, the stored data is “1”, and when DA = “1” & DB = “0”, the stored data is “0”, and DA = “ When 0 '& DB =' 0 ', this CAM cell is excluded from comparison.

  FIG. 7 shows an example of data arrangement in the CAM unit 8 when the CAM cell shown in FIG. 5 is adopted, and FIG. 8 shows an example of error correction data arrangement in the RAM unit 9 in that case. It is. By making the physical adjacent cells become another set of ECC, error detection and correction can be performed even when data of a plurality of cells are inverted by high energy particles such as cosmic rays. In the example shown in FIG. 8, the even bits and the odd bits are set in different sets. In this example, the data width is increased by creating an error correction code by combining two physically non-adjacent addresses, thereby reducing the number of bits required for the error correction code. In the case of data writing to the CAM unit 8, the error correction code can be created by reading the data of the address paired with the target address.

  According to the above example, the following operational effects can be obtained.

  (1) By performing error detection and correction simultaneously with the search of the CAM unit 8 or using a period when the CAM unit 8 is not used, the performance of the CAM unit 8 is not affected. In the period from the occurrence of an error to the detection of an error, the parity bit is also subject to comparison, so that mismatch can be prevented. In the case where the comparison data does not match due to an error, a network failure can be avoided by setting the period from the occurrence of the error to the detection of the error to be equal to or less than the timeout time of a retransmission request such as TCP / IP. Thereby, it is possible to ensure high reliability against soft errors without affecting the performance.

  (2) Due to the effect of (1) above, even in an LSI incorporating a large-capacity CAM with a miniaturized process, high reliability can be ensured for soft errors without degrading performance.

  (3) By detecting and correcting errors in a separate set of physical adjacent bits in the CAM unit 8, error detection and correction are possible even for multi-cell data inversion errors due to high-energy particles such as cosmic rays it can. As a result, it is possible to ensure high reliability against soft errors caused by high-energy particles such as cosmic rays.

  (4) Since only the error correction code is stored, the area of the circuit required for error correction can be reduced. In addition, an extra process such as adding a capacitor for countermeasures against soft errors is unnecessary.

  Next, another configuration example will be described.

  In the above example, the first storage unit MA and the second storage unit MB in the CAM cell are the static type, but can be the dynamic type. A configuration example of the memory cell MC (0, 0) in that case is shown in FIG. The configuration shown in FIG. 6 is greatly different from the configuration shown in FIG. 5 in that the first storage unit DA and the second storage unit DB are of a dynamic type.

  In FIG. 6, the first storage unit DA includes an n-channel MOS transistor MTA and a charge storage capacitor CA coupled thereto, and the second storage unit DB is coupled to the n-channel MOS transistor MTB. Charge storage capacitor CB. One end of the charge storage capacitor CA is coupled to the low potential side power supply Vss, and the other end is coupled to the data line D via the n-channel MOS transistor MTA. One end of the charge storage capacitor CB is coupled to the low potential side power supply Vss, and the other end is coupled to the data line D via the n-channel MOS transistor MTB. The gate electrode of the n-channel MOS transistor MTA is coupled to the word line WA, and the gate electrode of the n-channel MOS transistor MTB is coupled to the word line WB. When the word line WA is driven to the selected level, the n-channel MOS transistor MTA is turned on, so that the data transmitted via the data D can be written into the charge storage capacitor CA. Data stored in the charge storage capacitor CA can be read out to the data line D. When the word line WB is driven to the selection level, the n-channel MOS transistor MTB is turned on, so that the data transmitted via the data D can be written into the charge storage capacitor CB. Data stored in the charge storage capacitor CB can be read out to the data line D. In the first comparison circuit 511, n-channel MOS transistors MCA and MC0 are connected in series, the gate electrode of the n-channel MOS transistor MCA is coupled to the first comparison data line CD0, and the gate electrode of the n-channel MOS transistor MC0 is It is coupled to the storage node 517 of the first storage unit MA. In the second comparison circuit 512, n-channel MOS transistors MCB and MC1 are connected in series, the gate electrode of the n-channel MOS transistor MCB is coupled to the second comparison data line CD1, and the gate electrode of the n-channel MOS transistor MC1 is It is coupled to the storage node 518 of the second storage unit DB.

  When the CAM cell is a dynamic type, it is necessary to read and rewrite data within a certain time interval in order to prevent data destruction due to leakage current. Error detection can also be performed using this read data. 11 and 12 show a configuration example in that case. 13 shows the operation timing of the main part in the configuration shown in FIG. 11, and FIG. 14 shows the operation timing of the main part in the configuration shown in FIG.

  In the configuration shown in FIG. 11, a refresh counter 30 for refreshing dynamic cells is provided. When a refresh command is received by the command decoder 4, refresh is performed using the address of the refresh counter 30. Error detection is performed on the data read from the CAM unit 8 for refresh. Further, when an error is detected in the error detection and correction circuit 11, the ECC status is changed to the logical value “1” until the error correction is completed. Inform about the occurrence. Then, the data corrected by the error detection and correction circuit 11 is written to the error occurrence address in the CAM unit 8.

  Further, as in the configuration shown in FIG. 12, a selector 60 for selectively transmitting the output of the ECC generation circuit 10 and the output of the error detection and correction circuit 11 to the CAM unit 8 is provided, and rewriting at the time of refreshing is performed. The data to be performed may be replaced with corrected data. By performing error correction simultaneously with the refresh operation in this manner, higher reliability can be obtained for soft errors.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, as shown in FIG. 2, the error correction code generated by the ECC generation circuit 10 is stored in a predetermined area in the CAM unit 8, and error detection and correction is performed based on the error correction code read from the CAM unit 8. May be performed. In such a configuration, the RAM unit 9 and the selector 7 corresponding thereto in FIG. 1 are unnecessary.

  When the error correction code is stored in the RAM unit 9, a parity generation circuit 15 for generating a parity bit is provided as shown in FIG. 3, and the parity bit is included in the comparison data of the CAM unit 8, Even in the period from the occurrence of an error to the error correction, entry data in which an error has occurred can be prevented from being accidentally matched. This parity bit may be generated within the same chip as shown in FIG. 3, or may be generated outside the chip and included in a part of the data of the CAM unit 8.

  In the above example, the CAM unit 8 has two storage units. However, the present invention is not limited to this, and various configurations can be employed. For example, a ternary CAM cell can be composed of a data cell and a mask cell. FIG. 16 shows an example in which a ternary CAM cell is composed of a data cell and a mask cell. The first word line WD, the second word line WM, the comparison coincidence line MATCH and the first data line DO, the second data line D1, the first comparison data line CD0, and the second comparison data line CD1 are arranged so as to intersect. The first storage unit D, the second storage unit M, the first comparison circuit 521, and the second comparison circuit 522 are arranged at the intersections.

  The first storage unit D corresponding to the data cell includes a first inverter in which a p-channel MOS transistor ML0D and an n-channel MOS transistor MD0D are connected in series, a p-channel MOS transistor ML1D and an n-channel MOS transistor. A second inverter formed by connecting MD1D in series is coupled in a loop. The source electrodes of the p-channel MOS transistors ML0D and ML1D are coupled to the high potential side power supply Vdd, and the source electrodes of the n-channel MOS transistors MD0D and MD1D are coupled to the low potential side power supply Vss. The first storage unit D includes a first storage node 523 and a second storage node 524. The first storage node 523 is coupled to the first data line D0 via an n-channel MOS transistor MT0D which is a transfer MOS, and the second storage node 524 is connected via an n-channel MOS transistor MT1D which is a transfer MOS. Are coupled to the second data line D1. The gate electrodes of the n-channel MOS transistors MT0D and MT1D are coupled to the first word line WD. When the first word line WD is driven to a high level, the n-channel MOS transistors MT0D and MT1D are turned on, Data can be read from the first storage unit D and written to the first storage unit D.

  The second memory M corresponding to the mask cell includes a first inverter in which a p-channel MOS transistor ML0M and an n-channel MOS transistor MD0M are connected in series, a p-channel MOS transistor ML1M and an n-channel MOS transistor. A second inverter formed by connecting MD1M in series is coupled in a loop. The source electrodes of the p-channel MOS transistors ML0M and ML1M are coupled to the high potential power source Vdd, and the source electrodes of the n-channel MOS transistors MD0M and MD1M are coupled to the low potential power source Vss. The second storage unit M includes a first storage node 525 and a second storage node 526. The first storage node 525 is coupled to the first data line D0 via an n-channel MOS transistor MT0M which is a transfer MOS, and the second storage node 526 is connected via an n-channel MOS transistor MT1M which is a transfer MOS. Are coupled to the second data line D1. The gate electrodes of the n-channel MOS transistors MT0M and MT1M are coupled to the second word line WM. When the second word line WM is driven to a high level, the n-channel MOS transistors MT0M and MT1M are turned on. Data can be read from the second storage unit M and written to the second storage unit M.

  The first comparison circuit 521 includes three n-channel MOS transistors MCD0, MC0, MCM0 connected in series. The drain electrode of n-channel MOS transistor MCD0 is coupled to comparison match line MATCH, and the gate electrode of n-channel MOS transistor MCD0 is coupled to first storage node 523 of first storage unit D. The gate electrode of n channel type MOS transistor MC0 is coupled to first comparison data line CD0. The source electrode of the n-channel MOS transistor MCM0 is coupled to the low potential side power supply Vss, and the gate electrode of the n-channel MOS transistor MCM0 is coupled to the first storage node 525 of the second storage unit M.

  The second comparison circuit 522 includes three n-channel MOS transistors MCD1, MC1, and MCM1 connected in series. The drain electrode of n-channel MOS transistor MCD1 is coupled to comparison match line MATCH, and the gate electrode of n-channel MOS transistor MCD1 is coupled to first storage node 524 of first storage unit D. The gate electrode of n channel type MOS transistor MC1 is coupled to second comparison data line CD1. The source electrode of the n-channel MOS transistor MCM1 is coupled to the low potential side power supply Vss, and the gate electrode of the n-channel MOS transistor MCM1 is coupled to the first storage node 525 of the second storage unit M.

  In the above configuration, the storage data is stored in the first storage unit D, and the mask data is stored in the second storage unit. When the first storage node 525 of the second storage unit M is at a low potential, this CAM cell is excluded from comparison.

  An example of the arrangement of data and masks in the CAM cell array is shown in FIG. In FIG. 9, D corresponds to a data cell, and M corresponds to a mask cell. By making the physical adjacent cells a different set of ECCs, error detection and correction can be performed even when data of a plurality of cells are inverted by high energy particles such as cosmic rays. An example of the arrangement of the correction code in the RAM is shown in FIG. Also in this example, the even bits and the odd bits are set in different sets. Further, by generating a correction code by combining two addresses that are not physically adjacent to each other, the number of bits required for the correction code is reduced by increasing the data width.

  In FIG. 15, the routing processor 201 may be configured as a separate chip from the IP address search unit 210 and the routing information output unit 220.

  In the above description, the case where the invention made mainly by the inventor is applied to a router LSI, which is the field of use behind the invention, has been described. However, the present invention is not limited to this, and various semiconductor integrated circuits are used. Can be applied.

  The present invention can be applied on the condition that it includes at least a CAM portion capable of holding entry data.

FIG. 3 is a block diagram illustrating a configuration example of an IP address search unit in a router LSI which is an example of a semiconductor integrated circuit according to the present invention. It is a block diagram of another example of the configuration of the router LSI. It is a block diagram of another example of the configuration of the router LSI. It is an operation | movement timing diagram of the principal part in the structure shown by FIG. It is a circuit diagram of a configuration example of a main part in a CAM unit included in the router LSI. FIG. 10 is a circuit diagram illustrating another configuration example of a main part in a CAM unit included in the router LSI. FIG. 6 is an explanatory diagram of a data arrangement example in a CAM unit when the CAM cell shown in FIG. 5 is adopted. It is explanatory drawing of the example of arrangement | positioning of the error correction data to RAM part at the time of employ | adopting the CAM cell shown by FIG. FIG. 17 is an explanatory diagram of a data arrangement example in a CAM unit when the CAM cell shown in FIG. 16 is adopted. It is explanatory drawing of the example of arrangement | positioning of the error correction data to RAM part at the time of employ | adopting the CAM cell shown by FIG. It is a block diagram of another example of the configuration of the router LSI. It is a block diagram of another example of the configuration of the router LSI. FIG. 12 is an operation timing chart of main parts in the configuration shown in FIG. 11. FIG. 13 is an operation timing chart of main parts in the configuration shown in FIG. 12. It is a block diagram of an example of the overall configuration of the router LSI. FIG. 10 is a circuit diagram illustrating another configuration example of a main part in a CAM unit included in the router LSI.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Address input buffer 2 Data input / output buffer 3 Address counter 4 Command decoder 5-7, 60 Selector 8 CAM array 9 Correction code storage RAM array 10 ECC generation circuit 11 Error detection and correction circuit 12 Correction data latch 13 Defective address latch 14 Priority encoder 15 Parity generation circuit 30 Refresh counter

Claims (9)

A semiconductor integrated circuit that includes a CAM unit capable of storing entry data, compares the input comparison data with the entry data, and outputs the comparison result;
An error correction code creation circuit for creating an error correction code for entry data written in the CAM section;
A RAM unit capable of storing the error correction code generated by the error correction code creating circuit;
An error detection and correction circuit for detecting a software error in the entry data stored in the CAM unit and correcting the error based on the error correction code stored in the RAM unit ;
And a data transmission path for writing entry data error-corrected by the error detection and correction circuit to a corresponding address of the CAM unit .   2. The semiconductor integrated circuit according to claim 1, wherein the error detection and correction circuit performs error detection and error correction based on the error correction code at a timing excluding a data write cycle to the CAM unit. 2. The semiconductor integrated circuit according to claim 1 , further comprising a parity generation circuit for generating a parity bit to be added to data written to the CAM unit . 2. The semiconductor integrated circuit according to claim 1, wherein the error detection and correction circuit outputs a signal indicating the state upon error detection . The semiconductor integrated circuit according to claim 1, wherein the CAM unit includes a cell capable of storing ternary data, and the error detection and correction circuit performs error correction on the ternary data . The CAM unit includes a dynamic cell having a charge storage capacity for data storage, and the error detection and correction circuit uses data read for refreshing the dynamic cell. 2. The semiconductor integrated circuit according to claim 1, wherein soft error detection and error correction are performed on the data based on the error correction code . 7. The semiconductor integrated circuit according to claim 6, further comprising a selector capable of substituting data that has been error-corrected by the error detection and correction circuit for writing data to the dynamic cell at the time of refresh . 2. The semiconductor integrated circuit according to claim 1, wherein the adjacent bits in the CAM portion are different sets of error correction codes . 9. The semiconductor integrated circuit according to claim 8, wherein the same set of error correction codes includes a plurality of addresses in the CAM unit .

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