JP4394627B2 - Self-aligned pattern manufacturing method and semiconductor device using the same - Google Patents

Description

  The present invention relates to a self-aligned pattern manufacturing method and a semiconductor device using the same.

  A projection exposure apparatus used in a photolithography process in the manufacture of a conventional semiconductor device projects and exposes a pattern formed on a reticle onto a semiconductor wafer via a projection optical system. In such an exposure apparatus, since a plurality of layers of patterns are formed on the wafer in an overlapping manner, the pattern already formed on the wafer and the pattern on the reticle to be projected and transferred next can be positioned with high accuracy. It becomes important to match.

  Therefore, in order to realize highly accurate alignment, alignment marks (alignment marks) are formed on the wafer. This alignment mark is read and measured with high accuracy by an alignment sensor mounted on the exposure apparatus, thereby realizing high-accuracy alignment.

  As this alignment sensor, as described in Japanese Patent Laid-Open No. 2-272305 (Patent Document 1), a laser beam is irradiated to an alignment mark formed in a dot array on a wafer, and the alignment mark is diffracted. Alternatively, an LSA (Laser Step Alignment) method for detecting the mark position using scattered light, or a halogen lamp or the like as described in JP-A-4-65603 (Patent Document 2) is used as a light source. An FIA (Field Image Alignment) method in which image data of an alignment mark imaged by illuminating with light having a wide wavelength bandwidth is processed to measure the position of the alignment mark, or Japanese Patent Laid-Open No. 2-272305 (Patent Document 1) ) Use laser beams with the same frequency or slightly different frequencies on the diffraction grating-like alignment marks on the wafer. It was irradiated from a direction, by interfering two diffracted light generated, LIA (Laser Interferometric Alignment) for measuring the position of the alignment mark from the phase there is a method or the like. It is possible to perform highly accurate alignment (alignment) using these alignment methods.

JP-A-2-272305 JP-A-4-65603

However, since the pattern to be transferred onto the wafer has been increasingly miniaturized and highly integrated in recent years, alignment has become very important. However, the present situation is that it is not sufficient even if the sensor is used.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method that enables alignment in a self-aligning manner instead of measuring the position of an alignment mark formed on a wafer with high accuracy.

According to the present invention,
Different from the interlayer film on the surface of the interlayer film; and an interlayer film on a semiconductor substrate having a gate electrode or wiring on the surface, the step of depositing an interlayer film having a step corresponding to the pattern of the gate electrode or wiring step, the etching is performed so that the formed film, the film on one side wall of the step in which the surface is exposed interlayer film in the lower planar portion and the upper flat portion of the step is left; type of film forming step interlayer film And forming a resist film on the entire surface of the remaining film, and opening the resist film on the lower flat portion of the step or on the lower flat portion and the upper flat portion so that the edge of the opening is positioned on the remaining film. And a step of forming a pattern in a self-aligning manner on the gate electrode or the wiring by utilizing the opening of the resist film and the remaining film obtained (second method) Production method) It is provided.

According to the present invention, the step of depositing an interlayer film on a semiconductor substrate having a gate electrode or wiring on the surface and forming an interlayer film having a step corresponding to the pattern of the gate electrode or wiring; Forming a film of a different kind from the interlayer film on the surface of the film; forming a resist film on the entire surface of the formed film, and positioning the resist film on a film in which the edge of the opening is formed on the side wall of the step A step of opening on the lower flat portion of the step or on the lower flat portion and the upper flat portion ; using the opening of the resist film obtained, a film formed on the surface of the interlayer film is formed on the lower flat portion of the step or Etching so that the film is left on the side wall of the step while the surface is exposed to the lower flat part and the upper flat part; and the gate electrode or the wiring is formed using the resist film opening and the remaining film. Self-aligned pattern Method for producing a self-aligned pattern characterized by comprising the step of (third manufacturing method) is provided.

According to the present invention, a semiconductor device manufactured using either the second or third manufacturing method of the self-aligned pattern is provided.

According to the method of the present invention, it is possible to manufacture a self-aligned pattern without measuring an alignment mark (alignment mark) with high accuracy.
If this self-aligned pattern manufacturing method is used, a semiconductor device can be more easily manufactured. Further, according to this method, the semiconductor element can be miniaturized and highly integrated without depending on the detection accuracy of the alignment mark (alignment mark) and / or the resolution limit of photolithography.

  A first method for producing a self-aligned pattern according to the present invention includes a step of forming a film of a different type from the base on the surface of the base having a step; while the surface of the base is exposed on the flat portion of the step. And a step of etching so that a film remains on the side wall portion of the step; and a step of forming a pattern in a self-aligned manner on the base using the remaining film.

In the present invention, on the surface having a step, a surface connecting the upper flat portion and the lower flat portion is referred to as a “(step difference) side wall portion” or a “(step difference) inclined portion”. The inclination angle of the side wall part suitable for the present invention is 30 to 90 degrees, but the method of the present invention can also be applied to a surface having a step of the side wall part whose inclination angle is smaller than 30 degrees. The “inclination angle” is an angle θ (0 degree <θ ≦ 90 degrees) formed by the side wall portion and a plane parallel to the upper plane and / or the lower plane.
It should be noted that in the present invention, a “plane” is not intended to be a completely flat plane.

  In the present invention, the surface of the base may be a surface made of one type of material or a surface made of a plurality of types of materials. The surface of the base is preferably made of one kind of material, particularly preferably the surface of an interlayer film or an insulating film deposited on the semiconductor element.

  In the present invention, the type of film different from the base formed on the base surface is composed of a material that functions as a mask when a self-aligned pattern is formed on the base surface in a later step. For example, when the pattern is formed on the surface of the base by etching, the type of film different from the base is made of a material having a sufficiently low selectivity relative to the material constituting the base surface under the base surface etching conditions. The Thus, for example, when the underlying surface is composed of a silicon oxide film, the film formed on the underlying surface can be composed of a silicon nitride film or a polysilicon film.

In a preferred embodiment, the film formed on the base surface is formed so that the film thickness in the direction perpendicular to the surface is substantially uniform. As a result, the film thickness in the direction perpendicular to the flat part of the step (this direction is usually the same as the etching direction in the step of etching the film later) is thicker on the side wall part of the step than the flat part of the step. . For this reason, if the film formed on the step flat portion and the film formed on the step side wall portion are etched in the direction perpendicular to the flat portion under the same conditions, the film is removed at the step flat portion and the surface of the base is exposed. However, a film remains on the step side wall portion (hereinafter, this remaining film is also referred to as a “side wall film”).
For the film formation on the surface of the base, a CVD method with good step coverage (for example, low pressure chemical vapor deposition (LP-CVD method)) is preferably used.

  The thickness of the film to be formed is such that the width in the horizontal direction (upper plane portion-lower plane portion direction) of the film formed through the etching process is larger than the alignment accuracy in the resist film forming process. It must be a film thickness. Therefore, the film thickness to be formed needs to be thicker if the slope of the step slope is steep (as the slope angle is closer to 90 degrees), and if the slope is gentle (the slope angle is 0 degree). The closer you are) it may be thinner.

  The thickness of the film to be formed also affects the thickness of the film formed in a sidewall shape through the etching process, but as will be described later, the thickness of the remaining sidewall film is increased by a separate process. can do. Therefore, the thickness of the film to be formed does not necessarily have to be determined in consideration of whether or not the thickness of the remaining sidewall film can function as a mask in the process of forming a self-aligned pattern on the surface of the base. .

In order to etch the formed film so that the surface of the base is exposed on the flat portion of the step while the film remains on the side wall of the step, preferably anisotropic etching (e.g., RIE (Reactive Ion Etching)) is performed. Use. The sidewall-like film remaining after the etching step is naturally formed on the step side wall portion and thus in a self-aligned manner with the step.
The formed film only needs to be etched so that the film remains on at least a part of the side wall of the step, and it is not always necessary to etch so that the film remains on the side wall of all the steps existing on the base surface. Absent. For example, etching may be performed so that the film remains on the side wall portion of a desired partial step, and in this case, a self-aligned pattern is finally manufactured only for the desired partial step. Further, the film may remain only on a part of the desired side wall of the step, and in this case, a self-aligned pattern is finally manufactured in a desired direction with respect to the step.

  After this etching step, if the remaining sidewall-like film is thin due to the inclination angle of the sidewall being loose, etc., the remaining sidewall-like film is formed before the step of forming the self-aligned pattern on the base. In addition, a film thickness that can function as a mask may be formed by selectively depositing a film. Further, the deposited film may be the same type of film as the remaining film, or may be a different type of film. When the pattern is formed on the base by etching, the different types of films are preferably made of a material having a sufficiently low selectivity compared to the material constituting the base under the base surface etching conditions. Examples of a method for selectively depositing the same type of film on the remaining sidewall film include an epitaxial growth method using a liquid phase or a gas phase. As a method of selectively depositing different types of films on the remaining sidewall film, for example, when the remaining film is polysilicon, a silicide film can be selectively formed on the polysilicon. Salicide technology. By increasing the film thickness of the remaining sidewall-like film, it becomes easy to form a self-aligned pattern on the base using this sidewall-like film.

  The second method for producing a self-aligned pattern according to the present invention includes a step of forming a film of a different type from the base on the surface of the base having a step; while the surface of the base is exposed on the flat portion of the step. Etching so that the film remains on the side wall of the step; forming a resist film on the entire surface of the base and the remaining film, and opening the resist film so that the edge of the opening is located on the remaining film And a step of forming a pattern in a self-aligned manner on the base using the opening of the resist film obtained and the remaining film.

  In this method, the resist film only needs to be opened so as to be positioned on the sidewall-like film where the edge of the opening remains, and it is not necessary to position the resist film with high accuracy using an alignment mark or the like.

  As described in the description of the first manufacturing method, the film thickness of the remaining sidewall film can be increased after the etching step. Therefore, the second method of the present invention is a film formed on the base surface. With respect to the film thickness (in the direction perpendicular to the flat part of the step), the difference between the flat part of the step and the inclined part is small, and the thickness of the sidewall film remaining on the inclined part after the etching process becomes thin. It can also be carried out on a surface having a step with a gentle slope. When the tilt angle is gentle (the tilt angle is 0 degree, for example, 30 degrees), there is an advantage that a larger margin can be secured against the alignment shift in the step of opening the resist film.

  Since the edge of the opening of the resist film is positioned on the remaining sidewall film, the portion of the edge does not affect the position of the edge of the pattern formed on the base. Instead, the position of the edge of the remaining sidewall film determines the position of the edge of the pattern formed on the base. Since the position of the side wall-like film is formed in a self-aligned manner as described above, the pattern formed on the base has the side wall-like film where the edge of the opening is located in the inclined portion. Will be self-aligned with respect to the step, and even if an alignment shift occurs at the opening of the resist film, as long as the edge of the opening is located on the predetermined sidewall-like film, the pattern formed on the base The effect of deviation is not affected.

  It is not necessary for the entire edge of the opening to be located on the sidewall film. At least part of the edge of the opening remains so that the resist film opens at the base surface exposed part of the desired step plane part (s) and does not open at the base surface exposed part of the other step flat part. It suffices if it is located on the sidewall-like film. For example, when the opening is circular, some arcs may be located on the sidewall film, and when the opening is polygonal, some sides may be located on the sidewall film. Good. In this case, a self-aligned pattern is formed on the base with respect to the side wall portion on which the sidewall-like film is formed with part of the edge of the opening formed thereon (therefore, the upper plane or the lower plane connected thereto).

  One opening may be opened only on one desired step plane portion (for example, an upper step plane portion or a lower step plane portion), or a plurality of desired step plane portions (upper step planes) that are adjacent via an inclined portion. Part and lower flat part). In the latter case, a plurality of patterns can be formed with a single resist film. For example, the contact hole pattern for the gate electrode and the contact hole pattern for the active region (source region or drain region) adjacent to the gate electrode can be formed with one resist film.

  Since the edge of the opening of the resist film is transferred to the inclined surface on the sidewall-like film, shape degradation or the like may occur due to the halation (reflection from the base) effect during photolithography. Therefore, in order to prevent the shape deterioration, it is preferable to use a known antireflection film such as an inorganic or organic film during photolithography.

  Other points are as described for the first method.

The self-aligned pattern produced by the method of the present invention is not limited to a specific one as long as it can be produced on the underlying surface using the resist film and the remaining film. The self-aligned pattern is, for example, an etching pattern or an ion implantation pattern that is produced using a resist film and the remaining sidewall film as a mask.
When the surface of the base has a step corresponding to a lower layer pattern (for example, a gate electrode pattern, an active region pattern, or a metal wiring pattern) like an interlayer film deposited on a semiconductor element, for example, The pattern produced by the method will self-align with the underlying pattern.

  A third method for producing a self-aligned pattern according to the present invention includes a step of forming a film of a different type from the base on the surface of the base having a step; forming a resist film on the entire surface of the formed film, A step of opening so that the edge of the opening is positioned on the film formed on the side wall of the step; using the opening of the obtained resist film, the film formed on the surface of the base is applied to the flat portion of the step Etching so that the film remains on the side wall of the step while exposing the surface of the step; and forming a pattern in a self-aligned manner on the base using the opening of the resist film and the remaining film It is characterized by having.

In the third method, the order of the resist film formation / opening step and the etching step of the film formed on the underlying surface is the reverse of the first method.
In the resist film formation and opening process of the third method, the resist film is opened so that the edge of the opening is located on the film formed on the side wall of the step. In order to eliminate the need for highly accurate positioning using alignment marks or the like at this time, the film thickness of the film formed on the surface of the base is set in the horizontal direction (the direction of the upper flat part-the lower flat part) after film deposition. Any film thickness may be used as long as the width is larger than the alignment accuracy in the process.

Since the edge of the opening of the resist film is located on the film formed on the side wall portion of the step, the corresponding portion of the edge does not affect the position of the edge of the pattern formed on the base, and instead is etched later. The position of the edge of the sidewall film remaining after the process determines the position of the edge of the pattern formed on the base. The position of the sidewall-like film is formed in the step slope part, and thus in a self-aligned manner with the step, so that the edge of the opening is formed in the predetermined step side wall part even if the alignment shift occurs at the time of opening the resist film As long as the pattern is positioned on the formed film, the pattern formed on the base is self-aligned with the step without being affected by the shift.
The other points are as described for the first method.

  When the order of the resist film formation / opening process and the etching process of the film formed on the underlying surface is reversed, for example, when the process of forming a pattern in a self-aligned manner on the underlying surface is the etching process of the underlying surface, the film It is possible to perform the two etching processes of the etching process and the base etching process continuously only by changing the etching conditions, and the time and / or cost required for manufacturing can be reduced, such as eliminating the labor required for replacing the equipment. Can be reduced.

  The (first to third) methods of the present invention can be used, for example, on the surface of an interlayer film deposited on a semiconductor element. The step on the surface may occur corresponding to a specific semiconductor element (for example, a gate electrode or a metal wiring). At this time, the step on the surface is caused by a difference between the surface (planar portion) of the interlayer film deposited on the specific semiconductor element and the surface (planar portion) of the interlayer film deposited on another portion. In this case, a self-aligned pattern (for example, a contact hole) for the specific semiconductor element is formed by the method of the present invention.

  The method of the present invention can also be used on the surface of an insulating film deposited after the formation of the trench and having a step on the surface corresponding to the trench. At this time, the step is caused by a difference between the surface (planar portion) of the insulating film deposited on the trench and the surface (planar portion) of the insulating film deposited on another portion. In this case, the surface of the surface can be processed in a self-aligned manner with respect to the trench (for example, a region other than the trench is etched) by the method of the present invention.

  The step on the base surface and / or the remaining sidewall film may be planarized and / or removed after a self-aligned pattern is formed on the surface of the base, or after subsequent necessary steps. For the planarization, a CMP (Chemical Mechanical Polishing) process can be used.

  In the pattern production method of the present invention, the size of the pattern produced on the underlying surface does not depend on the resist film opening size at all by positioning all the edges of the resist film opening on the sidewall film. It is possible to determine the distance between the sidewall-like films where the edge of the opening of the resist film exists (interval on the base surface).

  In the manufacture of a semiconductor device, the distance between sidewall-like films is affected by the size and / or spacing of semiconductor elements (for example, gate electrodes) and / or the inclination angle of the side wall portion of the surface step generated during interlayer film deposition. Therefore, by adjusting these, the size of the pattern formed on the surface of the interlayer film (for example, the opening size of the contact hole) can be adjusted.

  Therefore, it is possible to produce a pattern having a size less than the resolution limit of photolithography. For this reason, for example, in the manufacture of a semiconductor device, the semiconductor element can be manufactured with a size or interval smaller than the resolution limit of photolithography, and thus the semiconductor element can be further miniaturized / integrated.

Hereinafter, a method of manufacturing a self-aligned pattern according to the present invention will be described in detail with reference to FIGS. Each example shows an example applied to the manufacture of a semiconductor device as one aspect of the method of manufacturing a self-aligned pattern of the present invention.
Each embodiment is merely an example for explaining the present invention, and the present invention is not limited to the embodiment.

<Example 1>
In this example, the contact pattern was formed in a self-aligned manner on the active region adjacent to the gate electrode by the second self-aligned pattern manufacturing method of the present invention.
First, as shown in FIG. 1A, silicon oxide formed by a bias high-density plasma CVD (HDP-CVD) method through steps necessary for manufacturing a semiconductor device such as forming a gate electrode 102 on a semiconductor substrate 101. A silicon nitride film 104 was formed on the film (interlayer film) 103 by low pressure chemical vapor deposition (LP-CVD). Here, the surface of the interlayer film 103 has a step, and the convex portion (step flat portion and inclined portion) is formed in a self-aligned manner corresponding to the gate electrode, and the inclination angle of the inclined portion is 50 degrees. Since the silicon nitride film 104 is deposited by the CVD method with good step coverage, it is formed with a substantially uniform film thickness in the direction perpendicular to the surface of the interlayer film 103, and the film thickness in the direction perpendicular to the semiconductor substrate 101 is The inclined part is thicker than the flat part.

  Next, as shown in FIG. 1B, the silicon nitride film 104 is etched back by anisotropic etching by RIE (Reactive Ion Etching). Etching back was performed until the silicon nitride film 104 on the flat portion of the step (surface parallel to the semiconductor substrate 101) was removed and the interlayer film 103 was exposed. As described above, since the film thickness in the etching direction is different between the flat part of the step and the side wall part, by performing anisotropic etching, when the silicon nitride film 104 is removed on the flat part of the step. The sidewall-like film remains on the step inclined portion (side wall portion). That is, a lower exposed portion 107 in which the silicon oxide film 103 is exposed without forming the silicon nitride film 104 is formed in the lower step planar portion, and the silicon nitride film 104 is not present in the upper step planar portion. An upper exposed portion 108 where the oxide film 103 is exposed is formed.

  Next, as shown in FIG. 1C, a resist film 105 is formed by a photoresist process. The resist film 105 is formed so that the edge (edge) of the opening is located on the sidewall-like film 104 so as to be exposed without covering the lower exposed part 107 but covering the upper exposed part 108.

  Next, as shown in FIG. 1D, the interlayer film 103 is selectively etched using the sidewall film of the resist film 105 and the silicon nitride film 104 as a mask to form a contact pattern 106. At this time, the pattern edge of the contact pattern 106 is determined by the edge of the sidewall-like film of the silicon nitride film 104. Since the edge of the sidewall film is determined by the position of the step on the surface of the interlayer film 103 corresponding to the gate electrode 102, the position of the contact pattern 106 is adjusted in a self-aligned manner with respect to the gate electrode. The electrode 102 is formed in a self-aligned manner at a desired position between the electrodes 102 without being in contact therewith. Thus, the contact pattern 106 is produced as a self-aligned pattern.

In the present embodiment (FIG. 1), the case where the inclination angle of the stepped portion (inclined portion) is about 50 degrees has been described, but of course the inclination angle is not limited to 50 degrees in the method of the present invention.
The closer the tilt angle is to the vertical (90 degrees) side, the thicker the silicon nitride film (in the etching direction) formed on the tilted part is than the film formed on the flat part. The film thickness of the sidewall film after the nitride film etch-back also increases. This facilitates the etching back of the silicon nitride film and the production of a self-aligned pattern on the underlying surface (for example, contact etching).
On the other hand, as the tilt angle is set to the vertical (90 degrees) side, the length of the tilted region in the horizontal direction (the direction of the upper plane portion-the lower plane portion) is shortened, and the alignment margin when forming the resist film opening is increased. Will be reduced. However, this problem can be solved by increasing the film thickness (in the direction perpendicular to the surface) of the film formed on the surface of the base as described above.
In fact, it was confirmed that the method of the present invention can be carried out with sufficiently good results on a surface having a step having an inclination angle of about 30 degrees to about 90 degrees.

< Reference Example 2>
In this embodiment, to form a self-aligned manner contact pattern on Gate electrodes.
In the same manner as in Example 1, a gate electrode 202, an interlayer film 203, and a silicon nitride film side wall film 204 were formed on a semiconductor substrate 201 (FIGS. 2A and 2B).

Next, as shown in FIG. 2C, a resist film 205 is formed so as to cover the lower exposed portion 207 but leave the upper exposed portion 208 exposed. At this time, the edge (edge) of the opening of the resist film 205 is positioned on the sidewall film 204.
Next, as shown in FIG. 2D, the interlayer film 203 is selectively etched using the sidewall film of the resist film 205 and the silicon nitride film 204 as a mask to form a contact pattern 206. Also in this embodiment, since the pattern edge of the contact pattern 206 is determined by the edge of the sidewall film of the silicon nitride film 204, the contact pattern 206 is self-aligned with the gate electrode as in the first embodiment. The position is adjusted and formed on the gate electrode 202 in a self-aligning manner.

<Example 3>
In this example, the contact pattern was formed in a self-aligned manner on the gate electrode and on the active region adjacent to the gate electrode by the second self-aligned pattern manufacturing method of the present invention.
In the same manner as in Example 1, a gate electrode 302, an interlayer film 303, and a silicon nitride film side wall film 304 were formed on a semiconductor substrate 301 (FIGS. 3A and 3B).

Next, as shown in FIG. 3C, the upper portions of the step upper and lower step plane portions corresponding to the gate electrode and the activation region are opened including the upper portion of the sidewall-like film 304 therebetween. Then, a resist film 305 is formed. At this time, the edge (edge) of the opening of the resist film 305 is positioned on the sidewall film 304.
Next, the interlayer film 303 was selectively etched using the resist film 305 and the silicon nitride film 304 as a mask to form a contact pattern 306 (FIG. 3D). Also in this embodiment, since the pattern edge of the contact pattern 306 is determined by the edge of the sidewall-like film of the silicon nitride film 304, the contact pattern 306 is adjacent to the gate electrode and the same as in the first and second embodiments. It is formed in a self-aligned manner with respect to the active region.

<Example 4>
In this embodiment, a contact pattern is formed in a self-aligned manner on an active region adjacent to a gate electrode by the third self-aligned pattern manufacturing method of the present invention.
Similarly to Example 1, a gate electrode 402, an interlayer film 403, and a silicon nitride film 404 were formed on a semiconductor substrate 401 (FIG. 4A).

Subsequently, as shown in FIG. 4B, a resist film 405 is formed so that the lower part of the step is opened and the edge (edge) of the opening is located on the step inclined part (side wall part) of the silicon nitride film 404. .
Next, the silicon nitride film 404 in the opening of the resist film 405 was etched back by anisotropic etching by RIE until the silicon nitride film 404 was removed at the plane portion below the step and the surface of the interlayer film 403 was exposed. At this time, the silicon nitride film 404 formed on the step inclined portion (side wall portion) in the opening of the resist film 405 has a thickness in the etching direction larger than that of the step flat portion as described above. It remains (FIG. 4 (c)).

Next, the interlayer film 403 was selectively etched using the sidewall film of the resist film 405 and the silicon nitride film 404 as a mask to form a contact pattern 406 (FIG. 4D).
Also in this embodiment, as in the above embodiment, the pattern edge of the contact pattern 406 is determined by the edge of the sidewall film of the silicon nitride film 404, and the edge of the sidewall film is the interlayer corresponding to the gate electrode 402. Since the position of the step on the surface of the film 403 is determined, the position of the contact pattern 406 is adjusted in a self-aligned manner with respect to the gate electrode, and is formed in a desired position without contacting the gate electrode 402. The

< Reference Example 5>
This example forms a self-aligned manner contact pattern on Gate electrodes.
5A, a gate electrode 502, an interlayer film 503, and a silicon nitride film 504 are formed on a semiconductor substrate 501 in the same manner as in the first embodiment.

Subsequently, as shown in FIG. 5B, a resist film 505 is formed so that the upper part of the step is opened and the edge (edge) of the opening is located on the step inclined part (side wall part) of the silicon nitride film 504. .
Next, the silicon nitride film 504 in the opening of the resist film 505 was etched back until the surface of the interlayer film 503 was exposed by removing the silicon nitride film 504 in the upper flat portion of the step by anisotropic etching using RIE. At this time, the silicon nitride film 504 formed on the step inclined portion (side wall portion) in the opening of the resist film 505 has a thickness in the etching direction larger than that of the step flat portion as described above. It remains (FIG. 5 (c)).

Next, the interlayer film 503 was selectively etched using the sidewall film of the resist film 505 and the silicon nitride film 504 as a mask to form a contact pattern 506 (FIG. 5D).
Also in this embodiment, since the pattern edge of the contact pattern 506 is determined by the edge of the sidewall film of the silicon nitride film 504, the contact pattern 506 is self-aligned with the gate electrode as in the above embodiment. The position is adjusted and formed on the gate electrode 502 in a self-aligning manner.

<Example 6>
In this example, the contact pattern was formed in a self-aligned manner on the gate electrode and on the active region adjacent to the gate electrode by the third self-aligned pattern manufacturing method of the present invention.
6A, the gate electrode 602, the interlayer film 603, and the silicon nitride film 604 are formed on the semiconductor substrate 601 as in the first embodiment.

Subsequently, as shown in FIG. 6B, the resist film 605 has an upper portion of the step upper and lower step portions corresponding to the gate electrode and the activation region including an upper portion of the sidewall film therebetween. The resist film 605 is formed so that the opening edge is positioned on the sidewall film 604.
Next, the silicon nitride film 604 in the opening of the resist film 605 is etched back until the surface of the interlayer film 603 is exposed by removing the silicon nitride film 604 in the upper and lower steps by anisotropic etching using RIE. did. At this time, the silicon nitride film 604 formed in the step inclined portion (side wall portion) in the opening of the resist film 605 remains as a sidewall-like film because the film thickness in the etching direction is thicker than the step flat portion. (FIG. 6 (c)).

Next, a contact pattern 606 is formed by selectively etching the interlayer film 603 on the upper and lower steps of the step using the sidewall film of the resist film 605 and the silicon nitride film 604 as a mask (FIG. 6D). ).
Also in this embodiment, since the pattern edge of the contact pattern 606 is determined by the edge of the side wall film of the silicon nitride film 604, the contact pattern 606 includes the gate electrode and the active region adjacent thereto, as in the above embodiment. Is formed in a self-aligned manner.

<Example 7>
In this embodiment, as shown in FIG. 7, the contact hole is formed in a self-aligned manner with respect to the gate electrode 702 existing only on one side of the contact hole to be formed. Except for the formation of the resist film 705, the same procedure as in Example 1 is performed. The resist film 705 opens at the lower flat part of the step where the contact hole is to be formed, does not open at the upper flat part of the step above the gate electrode 702, and at least a part of the edge of the opening exists on the gate electrode 702 side The silicon nitride film is formed so as to be positioned on the sidewall film 704. As a result, the contact hole 706 is formed in a self-aligned manner with respect to the gate electrode 702 existing only on one side. Such a method can be used at the end of the array.

<Example 8>
In this embodiment, as shown in FIG. 8, a self-aligned contact pattern 806 and a contact pattern 809 that does not require self-alignment (not self-aligned) are produced at the same time. While the self-aligned contact pattern 806 needs to be fabricated in a self-aligned manner on the narrow gate electrode 802, the contact pattern 809 is fabricated in a relatively wide active region (i.e., has a high tolerance for misalignment) ) So it is not necessary to be self-aligned.
Until the resist film 805 is formed, the same procedure as in the first embodiment is performed.

The resist film 805 is formed on the silicon nitride film 804 in which the edge of the opening for the self-aligned contact pattern 806 is formed on the inclined portion (side wall portion) of the step on the surface of the interlayer film 803 formed corresponding to the gate electrode 802. It forms so that it may be located in. At this time, the edge of the opening for the contact pattern 809 need not be located on the silicon nitride film 804.
Next, in the opening for the self-aligned contact pattern 806, the sidewall film of the resist film 805 and the silicon nitride film 804 is used as a mask, and in the opening for the contact pattern 809, only the resist film 805 is used as a mask. 803 is selectively etched to form contact patterns 806 and 809 simultaneously. At this time, an etching condition is selected such that etching stops on the surface of the gate electrode 802 and the surface of the semiconductor substrate 801.

Since the pattern edge of the contact pattern 809 is determined by the edge of the resist film 805, it is affected by the misalignment of the resist film 805 and is not positioned in a self-aligning manner. On the other hand, since the pattern edge of the contact pattern 806 is determined by the edge of the sidewall film of the silicon nitride film 804, the position of the contact pattern 806 is adjusted in a self-aligned manner with respect to the gate electrode, and the contact pattern 806 is formed on the gate electrode 802. It is formed in a self-aligning manner.
In this manner, the self-aligned contact pattern 806 and the contact pattern 809 that is not self-aligned are manufactured at the same time.

<Example 9>
This embodiment shows an example in which a self-aligned contact pattern is produced in a semiconductor device having a wiring pattern.
The semiconductor device illustrated in FIG. 9 includes a cell array structure including memory elements as examples of memory elements.

More specifically, in this semiconductor device, a P-type well region is formed on the surface portion of the semiconductor substrate (not shown). An element isolation region 911 is formed in this P-type well region. In the surface portion of the semiconductor substrate, a region where the element isolation region 911 is not formed becomes an active region.
The word lines 912 extend in the horizontal direction in FIG. 9 and are formed side by side in the vertical direction. The word lines 912 are narrower when adjacent word lines pass over the same element isolation region 911, and each of the word lines 912 is perpendicular to the direction in which the word lines extend (lateral direction in FIG. 9) (FIG. 9). When passing over the element isolation regions 911 adjacent to each other in the middle (vertical direction), the meandering is made wider. By meandering the word lines 912 in this manner, the element isolation regions 911 having a smaller size can be efficiently arranged, and thus the size of the memory cell array (in the vertical direction in FIG. 9) is reduced.

A gate insulating film is formed between the word line 912 and each active region (not shown). A sidewall having a memory effect is formed on the sidewall of the word line 912 (not shown). In the active regions on both sides not covered by the word line 912, an N-type diffusion region 913 is formed as a source / drain diffusion region on the surface of the P-type well region.
That is, in this semiconductor device, a memory element which is one field effect transistor includes a word line 912 (gate electrode) and N-type diffusion regions (source region or drain region) 913 formed on both sides of the word line 912. Contains.

  Further, the bit lines 914 extend in the vertical direction of FIG. 9 and are arranged in the horizontal direction of FIG. Bit line 914 is electrically connected to N-type diffusion region (source region or drain region) 913 through contact hole 906. The contact hole 906 is formed on the N-type diffusion region 913 where the interval between the word lines 912 is wide.

In such a semiconductor device, the contact hole 906 is formed by the method of the present invention so as to be self-aligned with each semiconductor element without performing a highly accurate photolithography alignment process.
Briefly described, a suitable position for making the contact hole 906 is circled from both sides by two adjacent word lines 912 due to the meandering word lines 912. In other words, a suitable position for manufacturing the contact hole 906 is near the center of the circular region 915 (concave) surrounded by two adjacent word lines 912 (convex). This circular region 915 is emphasized due to the proximity effect or the like in the manufacturing process of the semiconductor device before the contact hole 906 is formed.

  Therefore, by adjusting the film forming conditions of the interlayer oxide film deposited after the formation of the word line 912 and the film forming process in the method of the present invention, only the vicinity of the center of the circular region 915 is opened. A sidewall-like film can be left on. Therefore, the contact hole 906 is formed near the center of the circular region 915.

  In this way, since the structure can be formed in a self-aligned manner at a desired position by adjusting the process with a very high accuracy such as the film forming process thickness, it is substantially more effective than the alignment by the photolithography process. Target alignment accuracy can be improved. In addition, those detailed conditions can be formed in a self-aligned manner by adjusting the highly accurate process such as the film forming process film thickness even when the pattern shape, process conditions, etc. are changed. Regardless of the device and the manufacturing factory, it can be implemented by appropriate adjustment.

As shown in Examples 1 to 9, a self-aligned pattern could be produced using a step on the surface.
In the first to ninth embodiments, the formation of the contact hole between the element on the surface of the semiconductor substrate and the metal wiring on the upper layer is described. However, in order to form the contact hole connecting the metal wiring and the metal wiring on the upper layer, the element The self-aligned fabrication method of the present invention can be carried out and has the same effect in order to remove the oxide film in the region other than the trench (projection region) after the oxide film is buried after the isolation trench etch.
Further, in the above embodiment, only the preparation of the contact hole has been described, but the contact plug, the metal wiring, etc. are easily manufactured by a known technique. If the surface step or the side wall of the silicon nitride film adversely affects the subsequent process, perform CMP (chemical mechanical polishing) after filling the contact plug with tungsten or after forming the contact plug. It is preferable to make it flat.

It is a figure explaining the method of Example 1. FIG. It is a figure explaining the method of the reference example 2. FIG. FIG. 6 is a diagram for explaining a method of Example 3. It is a figure explaining the method of Example 4. FIG. It is a figure explaining the method of the reference example 5. FIG. It is a figure explaining the method of Example 6. FIG. FIG. 10 is a diagram for explaining a method of Example 7. It is a figure explaining the method of Example 8. FIG. 10 is a schematic top view of a semiconductor device manufactured by a method of Example 9. FIG.

Explanation of symbols

101, 201, 301, 401, 501, 601, 701, 801 Semiconductor substrate
102, 202, 302, 402, 502, 602, 702, 802 Gate electrode
103, 203, 303, 403, 503, 603, 703, 803 Silicon oxide film
104, 204, 304, 404, 504, 604, 704, 804 Silicon nitride film
105, 205, 305, 405, 505, 605, 705, 805 Resist film
106, 206, 306, 406, 506, 606, 706, 806, 906 Self-aligned contact holes
107, 207, 307, 407, 507, 607, 707, 807
108, 208, 308, 408, 508, 608, 708, 808
809 Contact holes that do not require self-alignment
911 element isolation region
912 word line
913 N-type diffusion region (source / drain diffusion region)
914 bit line
915 Circular area surrounded by two adjacent word lines

Claims (6)

Depositing an interlayer film on a semiconductor substrate having a gate electrode or wiring on the surface, and forming an interlayer film having a step corresponding to the pattern of the gate electrode or wiring;
Forming a film of a different type from the interlayer film on the surface of the interlayer film ;
Etching the formed film so that the surface of the interlayer film is exposed on the lower flat part and the upper flat part of the step while the film remains on the side wall of at least a part of the step;
A resist film is formed on the entire surface of the interlayer film and the remaining film, and the resist film is opened on the lower flat part of the step or on the lower flat part and the upper flat part so that the edge of the opening is located on the remaining film. And a step of forming a pattern in a self-aligning manner on the gate electrode or wiring by using an opening of the resist film obtained and a remaining film, and a method for producing a self-aligning pattern. Depositing an interlayer film on a semiconductor substrate having a gate electrode or wiring on the surface, and forming an interlayer film having a step corresponding to the pattern of the gate electrode or wiring;
Forming a film of a different type from the interlayer film on the surface of the interlayer film ;
A resist film is formed on the entire surface of the formed film, and the resist film is formed on the lower flat portion of the step or on the lower flat portion and the upper flat portion so that the edge of the opening is positioned on the film formed on the side wall portion of the step. step of opening in,
By utilizing the opening of the resulting resist film, the film formed on the surface of the interlayer film, the lower flat portion of the step or the lower planar portion and one at the step side wall portion of the surface of the interlayer film in the upper flat portion is exposed And a step of forming a pattern in a self-aligning manner on the gate electrode or the wiring by utilizing the opening of the resist film and the remaining film. Manufacturing method. The method according to claim 1 or 2 self alignment pattern is the pattern of the contact hole. The method according to any one of claims 1 to 3 , wherein the inclination angle of the side wall portion is within a range of 30 degrees to 90 degrees. The interlayer film is a silicon oxide film, a method according to any one of claims 1 to 4 film formed on the surface of the interlayer film is a silicon nitride film or a polysilicon film. The semiconductor device manufactured using a method according to any one of claims 1-5.

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