JP4390554B2 - Code judging method and code judging device - Google Patents

Description

  The present invention relates to a code determination method and a code determination device, and more particularly to a code determination method and a code determination device for determining a code according to a pulse width in a predetermined cycle.

  The radio timepiece receives a standard radio wave that is a standard of time and frequency, detects the standard time, and adjusts the display time of the timepiece. This radio timepiece is currently used for a wall clock or a wristwatch.

  FIG. 9 shows a block diagram of the radio timepiece.

  The radio timepiece 100 mainly includes a receiving unit 111, a time measuring unit 112, and a display unit 113 (see Patent Document 1).

  The reception unit 111 includes an antenna 121 and a reception circuit 122, and detects a standard radio wave received by the antenna 121 by the reception circuit 122. The detection signal detected by the receiving unit 111 is supplied to the time measuring unit 112.

  The timer unit 112 includes a vibrator 131 and a timer circuit 132. The vibrator 131 oscillates at a predetermined frequency and supplies the oscillation output to the timer circuit 132. The clock circuit 132 divides the oscillation output from the vibrator 131 to generate a time step timing, and performs the time step. The time information being advanced by the time measuring circuit 132 is supplied to the display unit 113.

  The display unit 113 includes a driver 141 and a display 142. The driver 141 generates a drive signal for driving the display 142 based on the time information supplied from the time measuring circuit 132. The display 142 includes, for example, a VFD (vacuum fluoresce display), an LCD (liquid crystal display), and the like, and is driven according to a drive signal supplied from the driver 141 to display time.

[Standard radio wave]
In Japan, a standard radio wave JJY is transmitted from a predetermined transmitting station in order to inform the domestic and foreign countries of the standard of time and frequency, and Japan Standard Time (JST) based on Coordinated Universal Time (UTC). The standard radio wave JJY is obtained by superimposing a time code on a carrier wave having a frequency of 40 kHz or 60 kHz. The radio timepiece 100 acquires the standard time by detecting the time code from the standard radio wave.

The time code superimposed on the standard radio wave will be described.
FIG. 10 is a diagram for explaining a code included in one second of a standard radio wave.

  The time code is configured such that one cycle is 60 seconds and one pulse signal is included in one second. Codes such as position markers “P”, symbols “0”, “1”, etc. are represented according to the pulse width. The position marker “P” is represented by a pulse having a pulse width of 0.2 s ± 5 ms as shown in FIG. Further, the code “0” is represented by a pulse having a pulse width of 0.8 s ± 5 ms as shown in FIG. Further, the symbol “1” is represented by a pulse having a pulse width of 0.5 s ± 5 ms as shown in FIG.

JP 2002-14183 A

  However, since the standard radio wave to be received by the radio timepiece has a long wavelength, it is easily affected by noise and the like. Therefore, when detecting codes such as “P”, “0”, “1”, etc., which constitute time information, there are many erroneous detections, and even when reception is performed, there are problems such as correction at different times. there were.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a code determination method and a code determination apparatus that can accurately and efficiently determine a code.

The present invention provides an input signal when determining that it is any one of first to third codes or an error according to a ratio between the first logic and the second logic in a predetermined period of the input signal. a plurality of bit divided by a predetermined period divided into blocks to the first to fourth blocks, to determine the logic of each block based on the logic of the bits included in each block to the first to every fourth block The code of the input signal is determined based on the determined logic of the first to fourth blocks, and the logic of the first block is high level and the logic of the second block is low level. Yes, when the logic of the third block is low level or error, the first code is determined .

  Further, the present invention is characterized in that the logic of a block is determined based on the logic of a predetermined bit selected in advance among a plurality of bits.

Furthermore, the present invention is characterized in that the code is determined based on the logic of a predetermined block selected in advance among the first to fourth blocks.

  Furthermore, the present invention is characterized by determining whether or not to code-code an input signal based on the number of inversions between the first logic and the second logic of the input signal.

According to the present invention, a plurality of bits obtained by dividing an input signal by a predetermined period are divided into a predetermined number of blocks, and the logic of each block is determined based on the logic of bits included in each block for each predetermined number of blocks. And determining the code of the input signal based on the determined logic of the predetermined number of blocks, the logic of the first block is high level, the logic of the second block is low level, When the logic of the third block is at a low level or an error, the determination of the first code makes it possible to perform the code determination even if the third block has an error. Can determine the code.

  Further, by determining the logic of a block based on the logic of a predetermined bit selected in advance among a plurality of bits, it is possible to exclude a bit that is likely to be noised from the determination, so that a code can be determined with high accuracy.

  Furthermore, by determining the code based on the logic of a predetermined block selected in advance among a predetermined number of blocks, blocks that are susceptible to noise can be excluded from the code determination, so that the code can be determined with high accuracy.

  Further, by removing the input signal from the code determination based on the number of inversions between the first logic and the second logic of the input signal, it is possible to remove the input signal that is noisy and difficult to determine the code. Therefore, unnecessary code determination is not required, code determination can be performed efficiently, and erroneous determination can be reduced.

〔System configuration〕
FIG. 1 shows a block diagram of an embodiment of the present invention.

  The timing device 1 of the present embodiment is a timing device mounted on an automobile, for example, and includes a receiving unit 11, a timing unit 12, and a display unit 13. The receiving unit 11 includes an antenna 21, an amplifier circuit 22, a filter 23, and a detection circuit 24. The antenna 21 receives radio waves and converts them into electrical signals. The electrical signal converted by the antenna 21 is supplied to the amplifier circuit 22.

  The amplifier circuit 22 amplifies the electric signal supplied from the antenna 21 and supplies the amplified signal to the filter 23. The filter 23 passes the signal in the frequency band including the standard radio wave from the signal amplified by the amplifier circuit 22. The signal that has passed through the filter 23 is supplied to the detection circuit 24. The detection circuit 24 detects a signal corresponding to the standard radio wave from the signal that has passed through the filter 23. The detection signal detected by the detection circuit 24 is supplied to the timer unit 12.

  The timer unit 12 includes a timer circuit 31, a memory 32, and an oscillator circuit 33. The timing circuit 31 is supplied with a detection signal from the receiving unit 11 and is connected to the memory 32 and the oscillation circuit 33 and to terminals Tacc and Tb.

  FIG. 2 shows a functional block diagram of the time measuring circuit 31.

  The timing circuit 31 includes a waveform shaping unit 311, a code determination unit 312, an information extraction unit 313, a correction unit 314, and a timing time information generation unit 315.

  The waveform shaping unit 311 shapes the detection signal supplied from the receiving unit 11 into a pulse shape. The pulse signal shaped by the waveform shaping unit 311 is supplied to the code determination unit 312.

  The code determination unit 312 constitutes a main part of the present invention, and is configured by a CPU or logic. The code determination unit 312 includes a high level and a low level during a predetermined period of 1 second of the pulse signal supplied from the waveform shaping unit 311. The code “P”, “0”, “1” is determined according to the ratio of the error, and the error “E” is determined. The code determined by the code determination unit 312 is supplied to the information extraction unit 313. The operation of the code determination unit 312 will be described later.

  The information extraction unit 313 extracts standard time information based on the code supplied from the code determination unit 312. The processing of the code determination unit 312 will be described later. The standard time information extracted by the information extraction unit 313 is supplied to the correction unit 314.

  The correction unit 314 stores the standard time information supplied from the information extraction unit 313 in the memory 32, determines normality of the standard time information extracted from the plurality of standard time information stored in the memory 32, and determines the standard time When the information is normally received, the standard time information is supplied to the time information generating unit 315, and the time information generated by the time information generating unit 315 is corrected to the standard time information.

  An oscillation output is supplied from the oscillation circuit 33 to the clock time information generation unit 315. The timekeeping time information generation unit 315 counts the oscillation output from the oscillation circuit 33, advances the timekeeping time information, and can correct the timekeeping time information to standard time information in accordance with an instruction from the correction unit 314. Has been. The clock time information generated by the clock time information generation unit 315 is supplied to the display unit 13.

  The display unit 13 includes a driver circuit 41 and a display 42. The driver circuit 41 is supplied with time measurement time information from the time measurement circuit 31. The driver circuit 41 generates a drive signal for driving the display 42 based on the time count information supplied from the time count circuit 31. The display 42 is composed of a VFD (vacuum fluoresce display), an LCD (liquid crystal display), and the like, is driven according to a drive signal supplied from the driver circuit 41, and displays the time measured according to the time measured information.

[Operation of Code Determination Unit 312]
Next, the operation of the code determination unit 312 constituting the time measuring circuit 31 will be described.

  FIG. 3 shows a process flowchart of the code determination unit 312.

  In step S1-1, the code determination unit 312 divides the pulse signal from the waveform shaping unit 311 into 32 parts every second. In the subsequent processing, the code determination unit 312 handles the state of each divided period as 1-bit information.

  In step S1-2, the code determination unit 312 determines whether all the 32-bit states are at a high level. The code determination unit 312 determines that the standard radio wave is not in a receiving state when all 32 bits are at the high level in step S1-2, and therefore determines that there is an error in step S1-3.

  In addition, when at least one bit out of 32 bits is at a low level in step S1-2, the code determination unit 312 determines whether or not the number of falling times is four or more in step S1-4. If the number of falling times is 4 or more, the code determination unit 312 determines that there is a lot of noise and cannot be used for code determination, and determines an error in step S1-3.

  Further, if the number of falling times is less than 4 in step S1-4, the code determining unit 312 determines that the code can be determined, and in step S1-5, the 32-bit information is converted into the A block and B The block is divided into four blocks, block, C block, and D block. At this time, among the 32 bits, the 1st to 7th bits are divided into A blocks, the 8th to 16th bits are divided into B blocks, the 17th to 25th bits are divided into C blocks, and the 26th to 32nd bits are divided into D blocks. Is done.

  The code determination unit 312 performs the A block value determination process in step S1-6. The A block value determination process is a process of determining the block value of the A block from the state of each of the first to seventh bits. In addition, the code determination unit 312 executes a B block value determination process in step S1-7. The B block value determination process is a process of determining the block value of the B block from the state of each of the 8th to 16th bits.

  The code determination unit 312 executes C block value determination processing in step S1-8. The C block determination process is a process of determining the block value of the C block from the state of each of the 8th to 25th bits. In addition, the code determination unit 312 performs a D block determination process in step S1-9. The D block determination process is a process of determining the block value of the D block from the state of each of the 26th to 32nd bits.

  Next, in step S1-10, the code determination unit 312 determines a code from the logical values of the A block, B block, C block, and D block.

[A block value judgment processing]
Next, the A block value determination process in step S1-6 will be described.

  FIG. 4 shows a process flowchart of the A block value determination process.

  In the A block value determination process, the code determination unit 312 first extracts bit values of the second to sixth bits from the first to seventh bits constituting the A block in step S2-1. Note that the first bit and the eighth bit are easily affected by noise and the like, and the bit value is unstable, so they are excluded from the determination of the A block value.

  Next, the code determination unit 312 determines whether or not 3 bits or more of the second to sixth bits are at a high level in step S2-2. If the code determination unit 312 determines that at least three of the second to sixth bits are high in step S2-2, the code determination unit 312 determines that the block value of the A block is low in step S2-3. . If the code determination unit 312 determines in step S2-2 that the high-level bit of the second to sixth bits is 2 bits or less, the code determination unit 312 sets the A block value to the high level in step S2-4. judge.

  As described above, the block value of the A block is determined to be high level or low level.

[B block value determination processing]
Next, the B block value determination process in step S1-7 will be described.

  FIG. 5 shows a process flowchart of the B block value determination process.

  In the B block value determination process, the code determination unit 312 first extracts the 8th to 16th bit values constituting the B block in step S3-1. Next, in step S3-2, the code determination unit 312 determines whether or not 7 bits or more of the 8th to 16th bits are at a high level.

  When the code determination unit 312 determines in step S3-2 that 7 or more bits among the 8th to 16th bits are at a high level, the code determination unit 312 determines that the block value of the B block is at a low level in step S3-3. . If the code determination unit 312 determines in step S3-2 that 6 bits or less of the 8th to 16th bits are at a high level, the code determination unit 312 determines that the 8th to 16th bits in step S3-4. It is determined whether or not 3 bits or more and 6 bits or less are at a high level.

  If the code determination unit 312 determines in step S3-4 that 3 bits or more and 6 bits or less of the 8th to 16th bits are at a high level, the influence of noise or the like is large and the determination is difficult. In step S3-5, the block value of the B block is determined as an error. If the code determination unit 312 determines in step S3-4 that the high-level bits among the 8th to 16th bits are 3 bits or less, the code determination unit 312 increases the block value of the B block in step S3-6. Judge the level.

  As described above, the block value of the B block is determined to be high level or low level.

[C block value determination processing]
Next, the C block value determination process in step S1-8 will be described.

  FIG. 6 shows a process flowchart of the C block value determination process.

  In the C block value determination process, the code determination unit 312 first extracts the bit values of the 17th to 25th bits constituting the C block in step S4-1. Next, in step S4-2, the code determination unit 312 determines whether or not 7 bits or more of the 17th to 25th bits are at a high level.

  If the code determination unit 312 determines in step S4-2 that 7 or more bits of the 17th to 25th bits are at a high level, the code block 312 sets the block value of the C block to a low level in step S4-3. judge. If the code determination unit 312 determines in step S3-2 that 6 bits or less of the 17th to 25th bits are high level, the code determination unit 312 receives the 17th to 25th bits in step S4-4. It is determined whether or not 3 bits or more and 6 bits or less are at a high level.

  If the code determination unit 312 determines in step S4-4 that bits of 3 bits or more and 6 bits or less of the 17th to 25th bits are at a high level, the influence of noise or the like is large and the determination is difficult. In step S4-5, the block value of the C block is determined as an error. If the code determination unit 312 determines in step S4-4 that the high-level bits of the 17th to 25th bits are 3 bits or less, the code determination unit 312 increases the block value of the C block in step S4-6. Judge the level.

  As described above, the block value of the C block is determined to be high level or low level.

[D block value determination processing]
Next, the D block value determination process in step S1-9 will be described.

  FIG. 7 shows a process flowchart of the D block value determination process.

  In the A block value determination process, the code determination unit 312 first extracts the 26th to 32nd bit bit values constituting the D block in step S5-1.

  Next, the code determination unit 312 determines whether or not 3 bits or more of the 26th to 32nd bits are at a high level in step S5-2. If it is determined in step S5-2 that 3 or more of the 26th to 32nd bits are high level, the code determination unit 312 determines that the block value of the D block is low level in step S5-3. If the code determination unit 312 determines in step S5-2 that the high-level bit among the 26th to 32nd bits is 2 bits or less, the code determination unit 312 sets the D block value to the high level in step S5-4. judge.

  As described above, the block value of the D block is determined to be high level or low level.

[Code judgment processing]
Next, the code determination process in step S1-10 will be described.

  FIG. 8 shows a process flowchart of the code determination process.

  In the code determination process, the code determination unit 312 first captures the block value VA of the A block, the block value VB of the B block, and the block value VC of the C block in step S6-1. Next, in step S6-2, the code determination unit 312 determines that the block value VA of the A block is high level (H), that is, (VA = H), and the block value VB of B block is low level (L). That is, it is determined whether (VB = L) and the block value VC of the C block is low level (L) or error (E), that is, (VC = LorE).

  If the code determination unit 312 determines in step S6-2 that (VA = H) & (VB = L) & (VC = LorE), the code for that period is “P” in step S6-3. ". If the code determination unit 312 determines that (VA = H) & (VB = L) & (VC = LorE) is not satisfied in step S6-2, the block of the A block is determined in step S6-4. The value VA is low level (L), that is, (VA = L), the block value VB of the B block is low level (L), that is, (VB = L), and the block value VC of the C block is high. It is determined whether the level (H), that is, (VC = H).

  If the code determination unit 312 determines in step S6-4 that (VA = L) & (VB = L) & (VC = H), the code for that period is “1” in step S6-5. It is determined that If the code determination unit 312 determines in step S6-4 that (VA = L) & (VB = L) & (VC = H), the block value VA of the A block is determined in step S6-6. Is at the low level (L), that is, (VA = L), the block value VB of the B block is at the low level (L), that is, (VB = L), and the block value VC of the C block is at the high level ( H), that is, whether or not (VC = L) is determined.

  If it is determined in step S6-6 that (VA = L) & (VB = L) & (VC = L), the code determination unit 312 determines in step S6-7 that the code for that period is “0”. . The code determination unit 312 determines that the influence of noise is large and the code cannot be determined unless (VA = L) & (VB = L) & (VC = L) in step S6-6. The code of the period is determined as error “E”.

  As described above, the code determination unit 312 determines the code for one second as one of “P”, “0”, “1”, and “E”.

  The code determination unit 312 determines the block value of the D block by the D block value determination process in step S1-9, but the block value of the D block is used for the code determination in the code determination process of step S1-10. Not. This is because the D block is the 26th to 32nd bits, and this part is not involved in the code determination. Therefore, it is easily affected by noise, and there is a probability that an error will occur if the block value of the D block is included. This is because the code cannot be determined.

〔effect〕
According to the present embodiment, the pulse signal from the waveform shaping unit 311 is divided into 32 bits from the pulse signal for 1 second in step S1-1, and the 32 bits divided in step S1-5 are divided into blocks A to D. The blocks are divided into four blocks. In steps S1-6 to S1-9, the logic of each block is determined based on the bit logic for each of the A to D blocks. In step S1-10, based on the logic of the A to D blocks. By determining the code of the pulse signal, the noise can be rounded into the block, so that the influence of the noise can be reduced, and therefore the code can be determined with high accuracy.

  Further, according to the present embodiment, for example, in step S1-6, out of the 1st to 7th bits constituting the A block, the 2nd to 7th bits of the 1st to 7th bits excluding the logic of the 1st bit that is susceptible to noise are excluded. By determining the logic of the A block based on the logic, it is possible to exclude the logic of the first bit that is likely to be noisy from the determination, so that the code can be determined with high accuracy.

  Furthermore, according to the present embodiment, in step S1-10, the influence of noise is excluded by excluding the D block having a large noise influence and a small contribution to the code judgment from the code judgment among the A to D blocks. Is difficult to receive, so the code can be determined with high accuracy.

  Furthermore, according to the present embodiment, in step S1-3, it is determined that an error has occurred and the code determination is not performed when the logic inversion number of the input pulse signal from the waveform shaping unit 311 is four or more. Therefore, before the code determination in steps S1-5 to S1-10, since it is possible to remove an input signal that is noisy and difficult to determine the code, unnecessary code determination can be omitted, and code determination can be performed efficiently. In addition, erroneous determination can be reduced.

[Others]
Note that the timer circuit 31 may be configured by a microcomputer or the like, and may execute the above operation by a program, or the logic may be configured to execute the above operation.

It is a block block diagram of one Example of this invention. 3 is a functional block diagram of a time measuring circuit 31. FIG. 5 is a processing flowchart of a code determination unit 312. It is a processing flowchart of A block value determination processing. It is a process flowchart of a B block value determination process. It is a processing flowchart of C block value determination processing. It is a processing flowchart of D block value determination processing. It is a process flowchart of a code | cord | chord determination process. It is a block block diagram of a radio timepiece. It is a figure for demonstrating the code | cord | chord contained in 1 second of a standard radio wave.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Time measuring device 11 Receiving part 21 Antenna, 22 Amplifier circuit, 23 Filter, 24 Detection circuit 12 Time measuring part 31 Time measuring circuit 311 Waveform shaping part, 312 Code determination part, 313 Information extraction part 314 Correction part, 315 Timekeeping time information generation part 32 Memory, 33 Oscillator circuit 13 Display unit 41 Driver circuit, 42 Display

Claims (8)

In determining the code judging method that first logic and is one any rate first to third according to the code or the error between the second logic during a predetermined period of the input signal,
A block dividing procedure for dividing a plurality of bits obtained by dividing the input signal into predetermined periods into first to fourth blocks;
A block logic determination procedure for determining a high level, a low level, and an error as the logic of each block based on the logic of the bits included in each block for each of the first to fourth blocks;
It said block possess and determining code judging procedure code of the input signal based on the logic of the logic determination procedure in the determined first to fourth blocks,
In the code determination procedure, when the logic of the first block is high level, the logic of the second block is low level, and the logic of the third block is low level or error, A code determination method, wherein the first code is determined . The code determination method according to claim 1, wherein the block logic determination procedure determines the logic of the block based on a logic of a predetermined bit selected in advance among the plurality of bits. The code determination method according to claim 1 , wherein the code determination procedure determines the code based on a logic of a predetermined block selected in advance among the first to fourth blocks. An error determination procedure for determining whether or not to code-code the input signal based on the number of inversions between the first logic and the second logic of the input signal. The code determination method according to any one of claims 1 to 3. In the code determination device that determines any one of the first to third codes or an error according to a ratio between the first logic and the second logic in a predetermined period of the input signal,
Block dividing means for dividing a plurality of bits obtained by dividing the input signal into predetermined periods into first to fourth blocks;
Block logic determination means for determining the logic of each block based on the logic of the bits included in each block for each of the first to fourth blocks;
Possess and determining code judging unit code of the input signal based on the logic of the block logic is determined by determination means that said first to fourth blocks,
When the logic of the first block is high level, the logic of the second block is low level, and the logic of the third block is low level or error, A code determination device that determines the first code . 6. The code judging device according to claim 5, wherein the block logic judging means judges the logic of the block based on a logic of a predetermined bit selected in advance among the plurality of bits. It said code determination means code judging apparatus according to claim 5 or 6, wherein determining the code based on the logic of the preselected predetermined block among the first to fourth blocks. An error determination means for determining whether or not to code-code the input signal based on the number of inversions between the first logic and the second logic of the input signal. code judging apparatus according to any one claim 5 to 7.

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